diff --git a/software/conf/project_oracle.atstart b/software/conf/project_oractle_config.atstart similarity index 90% rename from software/conf/project_oracle.atstart rename to software/conf/project_oractle_config.atstart index 1db4532..71e239f 100644 --- a/software/conf/project_oracle.atstart +++ b/software/conf/project_oractle_config.atstart @@ -2,27 +2,27 @@ format_version: '2' name: My Project versions: api: '1.0' - backend: 1.7.301 + backend: 1.7.303 commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 content: unknown content_pack_name: unknown format: '2' - frontend: 1.7.301 - packs_version_avr8: 1.0.1408 + frontend: 1.7.303 + packs_version_avr8: 1.0.1410 packs_version_qtouch: unknown - packs_version_sam: 1.0.1373 - version_backend: 1.7.301 + packs_version_sam: 1.0.1554 + version_backend: 1.7.303 version_frontend: '' board: - identifier: CustomBoard - device: SAME54P20A-AF + identifier: SAME54XplainedPro + device: SAME54P20A-AU details: null application: null middlewares: {} drivers: CMCC: user_label: CMCC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC functionality: System api: HAL:HPL:CMCC configuration: @@ -38,7 +38,7 @@ drivers: domain_group: null DMAC: user_label: DMAC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC functionality: System api: HAL:HPL:DMAC configuration: @@ -574,7 +574,7 @@ drivers: domain_group: null EXTERNAL_IRQ_0: user_label: EXTERNAL_IRQ_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ functionality: External_IRQ api: HAL:Driver:Ext_IRQ configuration: @@ -697,7 +697,7 @@ drivers: eic_gclk_selection: Generic clock generator 0 GCLK: user_label: GCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK functionality: System api: HAL:HPL:GCLK configuration: @@ -711,7 +711,7 @@ drivers: enable_gclk_gen_1__externalclock: 1000000 enable_gclk_gen_2: false enable_gclk_gen_2__externalclock: 1000000 - enable_gclk_gen_3: true + enable_gclk_gen_3: false enable_gclk_gen_3__externalclock: 1000000 enable_gclk_gen_4: false enable_gclk_gen_4__externalclock: 1000000 @@ -750,7 +750,7 @@ drivers: gclk_arch_gen_2_oe: false gclk_arch_gen_2_oov: false gclk_arch_gen_2_runstdby: false - gclk_arch_gen_3_enable: true + gclk_arch_gen_3_enable: false gclk_arch_gen_3_idc: false gclk_arch_gen_3_oe: false gclk_arch_gen_3_oov: false @@ -827,7 +827,7 @@ drivers: domain_group: null MCLK: user_label: MCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK functionality: System api: HAL:HPL:MCLK configuration: @@ -850,7 +850,7 @@ drivers: configuration: {} OSC32KCTRL: user_label: OSC32KCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL functionality: System api: HAL:HPL:OSC32KCTRL configuration: @@ -878,7 +878,7 @@ drivers: domain_group: null OSCCTRL: user_label: OSCCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL functionality: System api: HAL:HPL:OSCCTRL configuration: @@ -959,7 +959,7 @@ drivers: domain_group: null PORT: user_label: PORT - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::PORT::driver_config_definition::PORT::HAL:HPL:PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT functionality: System api: HAL:HPL:PORT configuration: @@ -1019,26 +1019,9 @@ drivers: variant: null clocks: domain_group: null - QUAD_SPI_0: - user_label: QUAD_SPI_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.Sync - functionality: Quad_SPI - api: HAL:Driver:QSPI_Sync - configuration: - qspi_advanced: false - qspi_baud_rate: 375000 - qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following - edge of SPCK. - qspi_cpol: The inactive state value of SPCK is logic level zero. - qspi_dlybs: 0 - qspi_dlycs: 0 - optional_signals: [] - variant: null - clocks: - domain_group: null RAMECC: user_label: RAMECC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC functionality: System api: HAL:HPL:RAMECC configuration: {} @@ -1046,67 +1029,11 @@ drivers: variant: null clocks: domain_group: null - TIMER_0: - user_label: TIMER_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::RTC::driver_config_definition::Timer::HAL:Driver:Timer - functionality: Timer - api: HAL:Driver:Timer - configuration: - rtc_arch_comp_val: 32 - rtc_arch_init_reset: true - rtc_arch_prescaler: OFF(Peripheral clock divided by 1) - rtc_cmpeo0: false - rtc_cmpeo1: false - rtc_event_control: false - rtc_ovfeo: false - rtc_pereo0: false - rtc_pereo1: false - rtc_pereo2: false - rtc_pereo3: false - rtc_pereo4: false - rtc_pereo5: false - rtc_pereo6: false - rtc_pereo7: false - rtc_tamper_active_layer_frequency_prescalar: DIV2 CLK_RTC_OUT is CLK_RTC /2 - rtc_tamper_debounce_frequency_prescalar: DIV2 CLK_RTC_DEB is CLK_RTC /2 - rtc_tamper_input_action_0: OFF(Disabled) - rtc_tamper_input_action_1: OFF(Disabled) - rtc_tamper_input_action_2: OFF(Disabled) - rtc_tamper_input_action_3: OFF(Disabled) - rtc_tamper_input_action_4: OFF(Disabled) - rtc_tampereo: false - rtc_tampevei: false - tamper_debounce_enable_0: false - tamper_debounce_enable_1: false - tamper_debounce_enable_2: false - tamper_debounce_enable_3: false - tamper_debounce_enable_4: false - tamper_input_0_settings: false - tamper_input_1_settings: false - tamper_input_2_settings: false - tamper_input_3_settings: false - tamper_input_4_settings: false - tamper_level_0: false - tamper_level_1: false - tamper_level_2: false - tamper_level_3: false - tamper_level_4: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: RTC - input: RTC source - external: false - external_frequency: 0 - configuration: - rtc_clk_selection: RTC source USART_0: user_label: USART_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SERCOM0::driver_config_definition::UART::HAL:Driver:USART.Sync + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async functionality: USART - api: HAL:Driver:USART_Sync + api: HAL:Driver:USART_Async configuration: usart_advanced: false usart_arch_clock_mode: USART with internal clock @@ -1121,7 +1048,7 @@ drivers: usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) usart_arch_sampr: 16x arithmetic usart_arch_sfde: false - usart_baud_rate: 9600 + usart_baud_rate: 115200 usart_character_size: 8 bits usart_parity: No parity usart_rx_enable: true @@ -1131,11 +1058,11 @@ drivers: variant: specification: TXPO=0, RXPO=1, CMODE=0 required_signals: - - name: SERCOM0/PAD/0 - pad: PA04 + - name: SERCOM2/PAD/0 + pad: PB25 label: TX - - name: SERCOM0/PAD/1 - pad: PA05 + - name: SERCOM2/PAD/1 + pad: PB24 label: RX clocks: domain_group: @@ -1153,7 +1080,7 @@ drivers: slow_gclk_selection: Generic clock generator 3 I2C_0: user_label: I2C_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM3::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync functionality: I2C api: HAL:Driver:I2C_Master_Sync configuration: @@ -1171,11 +1098,11 @@ drivers: variant: specification: SDA=0, SCL=1 required_signals: - - name: SERCOM1/PAD/0 - pad: PA16 + - name: SERCOM3/PAD/0 + pad: PA22 label: SDA - - name: SERCOM1/PAD/1 - pad: PA17 + - name: SERCOM3/PAD/1 + pad: PA23 label: SCL clocks: domain_group: @@ -1191,20 +1118,9 @@ drivers: configuration: core_gclk_selection: Generic clock generator 0 slow_gclk_selection: Generic clock generator 3 - DELAY_0: - user_label: DELAY_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay - functionality: Delay - api: HAL:Driver:Delay - configuration: - systick_arch_tickint: false - optional_signals: [] - variant: null - clocks: - domain_group: null - TIMER_1: - user_label: TIMER_1 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::TC0::driver_config_definition::Timer::HAL:Driver:Timer + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer functionality: Timer api: HAL:Driver:Timer configuration: @@ -1234,28 +1150,28 @@ drivers: configuration: tc_gclk_selection: Generic clock generator 0 pads: - PA04: - name: PA04 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA04 - mode: Peripheral IO - user_label: PA04 - configuration: null - PA05: - name: PA05 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA05 - mode: Peripheral IO - user_label: PA05 - configuration: null - PA16: - name: PA16 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA16 + PA22: + name: PA22 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA22 mode: I2C - user_label: PA16 + user_label: PA22 configuration: null - PA17: - name: PA17 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA17 + PA23: + name: PA23 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA23 mode: I2C - user_label: PA17 + user_label: PA23 + configuration: null + PB24: + name: PB24 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 + mode: Peripheral IO + user_label: PB24 + configuration: null + PB25: + name: PB25 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 + mode: Peripheral IO + user_label: PB25 configuration: null toolchain_options: [] diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/.vs/same54_gfx_4_19_20/v14/.atsuo b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/.vs/same54_gfx_4_19_20/v14/.atsuo deleted file mode 100644 index b7e3428..0000000 Binary files a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/.vs/same54_gfx_4_19_20/v14/.atsuo and /dev/null differ diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/atmel_start_config.atstart b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/atmel_start_config.atstart deleted file mode 100644 index c851f8f..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/atmel_start_config.atstart +++ /dev/null @@ -1,1002 +0,0 @@ -format_version: '2' -name: My Project -versions: - api: '1.0' - backend: 1.7.303 - commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 - content: unknown - content_pack_name: unknown - format: '2' - frontend: 1.7.303 - packs_version_avr8: 1.0.1410 - packs_version_qtouch: unknown - packs_version_sam: 1.0.1554 - version_backend: 1.7.303 - version_frontend: '' -board: - identifier: SAME54XplainedPro - device: SAME54P20A-AU -details: null -application: null -middlewares: {} -drivers: - CMCC: - user_label: CMCC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC - functionality: System - api: HAL:HPL:CMCC - configuration: - cache_size: 4 KB - cmcc_advanced_configuration: false - cmcc_clock_gating_disable: false - cmcc_data_cache_disable: false - cmcc_enable: false - cmcc_inst_cache_disable: false - optional_signals: [] - variant: null - clocks: - domain_group: null - DMAC: - user_label: DMAC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC - functionality: System - api: HAL:HPL:DMAC - configuration: - dmac_beatsize_0: 8-bit bus transfer - dmac_beatsize_1: 8-bit bus transfer - dmac_beatsize_10: 8-bit bus transfer - dmac_beatsize_11: 8-bit bus transfer - dmac_beatsize_12: 8-bit bus transfer - dmac_beatsize_13: 8-bit bus transfer - dmac_beatsize_14: 8-bit bus transfer - dmac_beatsize_15: 8-bit bus transfer - dmac_beatsize_16: 8-bit bus transfer - dmac_beatsize_17: 8-bit bus transfer - dmac_beatsize_18: 8-bit bus transfer - dmac_beatsize_19: 8-bit bus transfer - dmac_beatsize_2: 8-bit bus transfer - dmac_beatsize_20: 8-bit bus transfer - dmac_beatsize_21: 8-bit bus transfer - dmac_beatsize_22: 8-bit bus transfer - dmac_beatsize_23: 8-bit bus transfer - dmac_beatsize_24: 8-bit bus transfer - dmac_beatsize_25: 8-bit bus transfer - dmac_beatsize_26: 8-bit bus transfer - dmac_beatsize_27: 8-bit bus transfer - dmac_beatsize_28: 8-bit bus transfer - dmac_beatsize_29: 8-bit bus transfer - dmac_beatsize_3: 8-bit bus transfer - dmac_beatsize_30: 8-bit bus transfer - dmac_beatsize_31: 8-bit bus transfer - dmac_beatsize_4: 8-bit bus transfer - dmac_beatsize_5: 8-bit bus transfer - dmac_beatsize_6: 8-bit bus transfer - dmac_beatsize_7: 8-bit bus transfer - dmac_beatsize_8: 8-bit bus transfer - dmac_beatsize_9: 8-bit bus transfer - dmac_blockact_0: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_1: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_10: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_11: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_12: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_13: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_14: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_15: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_16: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_17: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_18: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_19: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_2: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_20: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_21: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_22: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_23: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_24: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_25: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_26: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_27: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_28: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_29: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_3: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_30: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_31: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_4: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_5: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_6: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_7: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_8: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_9: Channel will be disabled if it is the last block transfer in - the transaction - dmac_channel_0_settings: false - dmac_channel_10_settings: false - dmac_channel_11_settings: false - dmac_channel_12_settings: false - dmac_channel_13_settings: false - dmac_channel_14_settings: false - dmac_channel_15_settings: false - dmac_channel_16_settings: false - dmac_channel_17_settings: false - dmac_channel_18_settings: false - dmac_channel_19_settings: false - dmac_channel_1_settings: false - dmac_channel_20_settings: false - dmac_channel_21_settings: false - dmac_channel_22_settings: false - dmac_channel_23_settings: false - dmac_channel_24_settings: false - dmac_channel_25_settings: false - dmac_channel_26_settings: false - dmac_channel_27_settings: false - dmac_channel_28_settings: false - dmac_channel_29_settings: false - dmac_channel_2_settings: false - dmac_channel_30_settings: false - dmac_channel_31_settings: false - dmac_channel_3_settings: false - dmac_channel_4_settings: false - dmac_channel_5_settings: false - dmac_channel_6_settings: false - dmac_channel_7_settings: false - dmac_channel_8_settings: false - dmac_channel_9_settings: false - dmac_dbgrun: false - dmac_dstinc_0: false - dmac_dstinc_1: false - dmac_dstinc_10: false - dmac_dstinc_11: false - dmac_dstinc_12: false - dmac_dstinc_13: false - dmac_dstinc_14: false - dmac_dstinc_15: false - dmac_dstinc_16: false - dmac_dstinc_17: false - dmac_dstinc_18: false - dmac_dstinc_19: false - dmac_dstinc_2: false - dmac_dstinc_20: false - dmac_dstinc_21: false - dmac_dstinc_22: false - dmac_dstinc_23: false - dmac_dstinc_24: false - dmac_dstinc_25: false - dmac_dstinc_26: false - dmac_dstinc_27: false - dmac_dstinc_28: false - dmac_dstinc_29: false - dmac_dstinc_3: false - dmac_dstinc_30: false - dmac_dstinc_31: false - dmac_dstinc_4: false - dmac_dstinc_5: false - dmac_dstinc_6: false - dmac_dstinc_7: false - dmac_dstinc_8: false - dmac_dstinc_9: false - dmac_enable: false - dmac_evact_0: No action - dmac_evact_1: No action - dmac_evact_10: No action - dmac_evact_11: No action - dmac_evact_12: No action - dmac_evact_13: No action - dmac_evact_14: No action - dmac_evact_15: No action - dmac_evact_16: No action - dmac_evact_17: No action - dmac_evact_18: No action - dmac_evact_19: No action - dmac_evact_2: No action - dmac_evact_20: No action - dmac_evact_21: No action - dmac_evact_22: No action - dmac_evact_23: No action - dmac_evact_24: No action - dmac_evact_25: No action - dmac_evact_26: No action - dmac_evact_27: No action - dmac_evact_28: No action - dmac_evact_29: No action - dmac_evact_3: No action - dmac_evact_30: No action - dmac_evact_31: No action - dmac_evact_4: No action - dmac_evact_5: No action - dmac_evact_6: No action - dmac_evact_7: No action - dmac_evact_8: No action - dmac_evact_9: No action - dmac_evie_0: false - dmac_evie_1: false - dmac_evie_10: false - dmac_evie_11: false - dmac_evie_12: false - dmac_evie_13: false - dmac_evie_14: false - dmac_evie_15: false - dmac_evie_16: false - dmac_evie_17: false - dmac_evie_18: false - dmac_evie_19: false - dmac_evie_2: false - dmac_evie_20: false - dmac_evie_21: false - dmac_evie_22: false - dmac_evie_23: false - dmac_evie_24: false - dmac_evie_25: false - dmac_evie_26: false - dmac_evie_27: false - dmac_evie_28: false - dmac_evie_29: false - dmac_evie_3: false - dmac_evie_30: false - dmac_evie_31: false - dmac_evie_4: false - dmac_evie_5: false - dmac_evie_6: false - dmac_evie_7: false - dmac_evie_8: false - dmac_evie_9: false - dmac_evoe_0: false - dmac_evoe_1: false - dmac_evoe_10: false - dmac_evoe_11: false - dmac_evoe_12: false - dmac_evoe_13: false - dmac_evoe_14: false - dmac_evoe_15: false - dmac_evoe_16: false - dmac_evoe_17: false - dmac_evoe_18: false - dmac_evoe_19: false - dmac_evoe_2: false - dmac_evoe_20: false - dmac_evoe_21: false - dmac_evoe_22: false - dmac_evoe_23: false - dmac_evoe_24: false - dmac_evoe_25: false - dmac_evoe_26: false - dmac_evoe_27: false - dmac_evoe_28: false - dmac_evoe_29: false - dmac_evoe_3: false - dmac_evoe_30: false - dmac_evoe_31: false - dmac_evoe_4: false - dmac_evoe_5: false - dmac_evoe_6: false - dmac_evoe_7: false - dmac_evoe_8: false - dmac_evoe_9: false - dmac_evosel_0: Event generation disabled - dmac_evosel_1: Event generation disabled - dmac_evosel_10: Event generation disabled - dmac_evosel_11: Event generation disabled - dmac_evosel_12: Event generation disabled - dmac_evosel_13: Event generation disabled - dmac_evosel_14: Event generation disabled - dmac_evosel_15: Event generation disabled - dmac_evosel_16: Event generation disabled - dmac_evosel_17: Event generation disabled - dmac_evosel_18: Event generation disabled - dmac_evosel_19: Event generation disabled - dmac_evosel_2: Event generation disabled - dmac_evosel_20: Event generation disabled - dmac_evosel_21: Event generation disabled - dmac_evosel_22: Event generation disabled - dmac_evosel_23: Event generation disabled - dmac_evosel_24: Event generation disabled - dmac_evosel_25: Event generation disabled - dmac_evosel_26: Event generation disabled - dmac_evosel_27: Event generation disabled - dmac_evosel_28: Event generation disabled - dmac_evosel_29: Event generation disabled - dmac_evosel_3: Event generation disabled - dmac_evosel_30: Event generation disabled - dmac_evosel_31: Event generation disabled - dmac_evosel_4: Event generation disabled - dmac_evosel_5: Event generation disabled - dmac_evosel_6: Event generation disabled - dmac_evosel_7: Event generation disabled - dmac_evosel_8: Event generation disabled - dmac_evosel_9: Event generation disabled - dmac_lvl_0: Channel priority 0 - dmac_lvl_1: Channel priority 0 - dmac_lvl_10: Channel priority 0 - dmac_lvl_11: Channel priority 0 - dmac_lvl_12: Channel priority 0 - dmac_lvl_13: Channel priority 0 - dmac_lvl_14: Channel priority 0 - dmac_lvl_15: Channel priority 0 - dmac_lvl_16: Channel priority 0 - dmac_lvl_17: Channel priority 0 - dmac_lvl_18: Channel priority 0 - dmac_lvl_19: Channel priority 0 - dmac_lvl_2: Channel priority 0 - dmac_lvl_20: Channel priority 0 - dmac_lvl_21: Channel priority 0 - dmac_lvl_22: Channel priority 0 - dmac_lvl_23: Channel priority 0 - dmac_lvl_24: Channel priority 0 - dmac_lvl_25: Channel priority 0 - dmac_lvl_26: Channel priority 0 - dmac_lvl_27: Channel priority 0 - dmac_lvl_28: Channel priority 0 - dmac_lvl_29: Channel priority 0 - dmac_lvl_3: Channel priority 0 - dmac_lvl_30: Channel priority 0 - dmac_lvl_31: Channel priority 0 - dmac_lvl_4: Channel priority 0 - dmac_lvl_5: Channel priority 0 - dmac_lvl_6: Channel priority 0 - dmac_lvl_7: Channel priority 0 - dmac_lvl_8: Channel priority 0 - dmac_lvl_9: Channel priority 0 - dmac_lvlen0: true - dmac_lvlen1: true - dmac_lvlen2: true - dmac_lvlen3: true - dmac_lvlpri0: 0 - dmac_lvlpri1: 0 - dmac_lvlpri2: 0 - dmac_lvlpri3: 0 - dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 - dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 - dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 - dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 - dmac_runstdby_0: false - dmac_runstdby_1: false - dmac_runstdby_10: false - dmac_runstdby_11: false - dmac_runstdby_12: false - dmac_runstdby_13: false - dmac_runstdby_14: false - dmac_runstdby_15: false - dmac_runstdby_16: false - dmac_runstdby_17: false - dmac_runstdby_18: false - dmac_runstdby_19: false - dmac_runstdby_2: false - dmac_runstdby_20: false - dmac_runstdby_21: false - dmac_runstdby_22: false - dmac_runstdby_23: false - dmac_runstdby_24: false - dmac_runstdby_25: false - dmac_runstdby_26: false - dmac_runstdby_27: false - dmac_runstdby_28: false - dmac_runstdby_29: false - dmac_runstdby_3: false - dmac_runstdby_30: false - dmac_runstdby_31: false - dmac_runstdby_4: false - dmac_runstdby_5: false - dmac_runstdby_6: false - dmac_runstdby_7: false - dmac_runstdby_8: false - dmac_runstdby_9: false - dmac_srcinc_0: false - dmac_srcinc_1: false - dmac_srcinc_10: false - dmac_srcinc_11: false - dmac_srcinc_12: false - dmac_srcinc_13: false - dmac_srcinc_14: false - dmac_srcinc_15: false - dmac_srcinc_16: false - dmac_srcinc_17: false - dmac_srcinc_18: false - dmac_srcinc_19: false - dmac_srcinc_2: false - dmac_srcinc_20: false - dmac_srcinc_21: false - dmac_srcinc_22: false - dmac_srcinc_23: false - dmac_srcinc_24: false - dmac_srcinc_25: false - dmac_srcinc_26: false - dmac_srcinc_27: false - dmac_srcinc_28: false - dmac_srcinc_29: false - dmac_srcinc_3: false - dmac_srcinc_30: false - dmac_srcinc_31: false - dmac_srcinc_4: false - dmac_srcinc_5: false - dmac_srcinc_6: false - dmac_srcinc_7: false - dmac_srcinc_8: false - dmac_srcinc_9: false - dmac_stepsel_0: Step size settings apply to the destination address - dmac_stepsel_1: Step size settings apply to the destination address - dmac_stepsel_10: Step size settings apply to the destination address - dmac_stepsel_11: Step size settings apply to the destination address - dmac_stepsel_12: Step size settings apply to the destination address - dmac_stepsel_13: Step size settings apply to the destination address - dmac_stepsel_14: Step size settings apply to the destination address - dmac_stepsel_15: Step size settings apply to the destination address - dmac_stepsel_16: Step size settings apply to the destination address - dmac_stepsel_17: Step size settings apply to the destination address - dmac_stepsel_18: Step size settings apply to the destination address - dmac_stepsel_19: Step size settings apply to the destination address - dmac_stepsel_2: Step size settings apply to the destination address - dmac_stepsel_20: Step size settings apply to the destination address - dmac_stepsel_21: Step size settings apply to the destination address - dmac_stepsel_22: Step size settings apply to the destination address - dmac_stepsel_23: Step size settings apply to the destination address - dmac_stepsel_24: Step size settings apply to the destination address - dmac_stepsel_25: Step size settings apply to the destination address - dmac_stepsel_26: Step size settings apply to the destination address - dmac_stepsel_27: Step size settings apply to the destination address - dmac_stepsel_28: Step size settings apply to the destination address - dmac_stepsel_29: Step size settings apply to the destination address - dmac_stepsel_3: Step size settings apply to the destination address - dmac_stepsel_30: Step size settings apply to the destination address - dmac_stepsel_31: Step size settings apply to the destination address - dmac_stepsel_4: Step size settings apply to the destination address - dmac_stepsel_5: Step size settings apply to the destination address - dmac_stepsel_6: Step size settings apply to the destination address - dmac_stepsel_7: Step size settings apply to the destination address - dmac_stepsel_8: Step size settings apply to the destination address - dmac_stepsel_9: Step size settings apply to the destination address - dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_trifsrc_0: Only software/event triggers - dmac_trifsrc_1: Only software/event triggers - dmac_trifsrc_10: Only software/event triggers - dmac_trifsrc_11: Only software/event triggers - dmac_trifsrc_12: Only software/event triggers - dmac_trifsrc_13: Only software/event triggers - dmac_trifsrc_14: Only software/event triggers - dmac_trifsrc_15: Only software/event triggers - dmac_trifsrc_16: Only software/event triggers - dmac_trifsrc_17: Only software/event triggers - dmac_trifsrc_18: Only software/event triggers - dmac_trifsrc_19: Only software/event triggers - dmac_trifsrc_2: Only software/event triggers - dmac_trifsrc_20: Only software/event triggers - dmac_trifsrc_21: Only software/event triggers - dmac_trifsrc_22: Only software/event triggers - dmac_trifsrc_23: Only software/event triggers - dmac_trifsrc_24: Only software/event triggers - dmac_trifsrc_25: Only software/event triggers - dmac_trifsrc_26: Only software/event triggers - dmac_trifsrc_27: Only software/event triggers - dmac_trifsrc_28: Only software/event triggers - dmac_trifsrc_29: Only software/event triggers - dmac_trifsrc_3: Only software/event triggers - dmac_trifsrc_30: Only software/event triggers - dmac_trifsrc_31: Only software/event triggers - dmac_trifsrc_4: Only software/event triggers - dmac_trifsrc_5: Only software/event triggers - dmac_trifsrc_6: Only software/event triggers - dmac_trifsrc_7: Only software/event triggers - dmac_trifsrc_8: Only software/event triggers - dmac_trifsrc_9: Only software/event triggers - dmac_trigact_0: One trigger required for each block transfer - dmac_trigact_1: One trigger required for each block transfer - dmac_trigact_10: One trigger required for each block transfer - dmac_trigact_11: One trigger required for each block transfer - dmac_trigact_12: One trigger required for each block transfer - dmac_trigact_13: One trigger required for each block transfer - dmac_trigact_14: One trigger required for each block transfer - dmac_trigact_15: One trigger required for each block transfer - dmac_trigact_16: One trigger required for each block transfer - dmac_trigact_17: One trigger required for each block transfer - dmac_trigact_18: One trigger required for each block transfer - dmac_trigact_19: One trigger required for each block transfer - dmac_trigact_2: One trigger required for each block transfer - dmac_trigact_20: One trigger required for each block transfer - dmac_trigact_21: One trigger required for each block transfer - dmac_trigact_22: One trigger required for each block transfer - dmac_trigact_23: One trigger required for each block transfer - dmac_trigact_24: One trigger required for each block transfer - dmac_trigact_25: One trigger required for each block transfer - dmac_trigact_26: One trigger required for each block transfer - dmac_trigact_27: One trigger required for each block transfer - dmac_trigact_28: One trigger required for each block transfer - dmac_trigact_29: One trigger required for each block transfer - dmac_trigact_3: One trigger required for each block transfer - dmac_trigact_30: One trigger required for each block transfer - dmac_trigact_31: One trigger required for each block transfer - dmac_trigact_4: One trigger required for each block transfer - dmac_trigact_5: One trigger required for each block transfer - dmac_trigact_6: One trigger required for each block transfer - dmac_trigact_7: One trigger required for each block transfer - dmac_trigact_8: One trigger required for each block transfer - dmac_trigact_9: One trigger required for each block transfer - optional_signals: [] - variant: null - clocks: - domain_group: null - GCLK: - user_label: GCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK - functionality: System - api: HAL:HPL:GCLK - configuration: - enable_gclk_gen_0: true - enable_gclk_gen_0__externalclock: 1000000 - enable_gclk_gen_1: false - enable_gclk_gen_10: false - enable_gclk_gen_10__externalclock: 1000000 - enable_gclk_gen_11: false - enable_gclk_gen_11__externalclock: 1000000 - enable_gclk_gen_1__externalclock: 1000000 - enable_gclk_gen_2: false - enable_gclk_gen_2__externalclock: 1000000 - enable_gclk_gen_3: false - enable_gclk_gen_3__externalclock: 1000000 - enable_gclk_gen_4: false - enable_gclk_gen_4__externalclock: 1000000 - enable_gclk_gen_5: false - enable_gclk_gen_5__externalclock: 1000000 - enable_gclk_gen_6: false - enable_gclk_gen_6__externalclock: 1000000 - enable_gclk_gen_7: false - enable_gclk_gen_7__externalclock: 1000000 - enable_gclk_gen_8: false - enable_gclk_gen_8__externalclock: 1000000 - enable_gclk_gen_9: false - enable_gclk_gen_9__externalclock: 1000000 - gclk_arch_gen_0_enable: true - gclk_arch_gen_0_idc: false - gclk_arch_gen_0_oe: false - gclk_arch_gen_0_oov: false - gclk_arch_gen_0_runstdby: false - gclk_arch_gen_10_enable: false - gclk_arch_gen_10_idc: false - gclk_arch_gen_10_oe: false - gclk_arch_gen_10_oov: false - gclk_arch_gen_10_runstdby: false - gclk_arch_gen_11_enable: false - gclk_arch_gen_11_idc: false - gclk_arch_gen_11_oe: false - gclk_arch_gen_11_oov: false - gclk_arch_gen_11_runstdby: false - gclk_arch_gen_1_enable: false - gclk_arch_gen_1_idc: false - gclk_arch_gen_1_oe: false - gclk_arch_gen_1_oov: false - gclk_arch_gen_1_runstdby: false - gclk_arch_gen_2_enable: false - gclk_arch_gen_2_idc: false - gclk_arch_gen_2_oe: false - gclk_arch_gen_2_oov: false - gclk_arch_gen_2_runstdby: false - gclk_arch_gen_3_enable: false - gclk_arch_gen_3_idc: false - gclk_arch_gen_3_oe: false - gclk_arch_gen_3_oov: false - gclk_arch_gen_3_runstdby: false - gclk_arch_gen_4_enable: false - gclk_arch_gen_4_idc: false - gclk_arch_gen_4_oe: false - gclk_arch_gen_4_oov: false - gclk_arch_gen_4_runstdby: false - gclk_arch_gen_5_enable: false - gclk_arch_gen_5_idc: false - gclk_arch_gen_5_oe: false - gclk_arch_gen_5_oov: false - gclk_arch_gen_5_runstdby: false - gclk_arch_gen_6_enable: false - gclk_arch_gen_6_idc: false - gclk_arch_gen_6_oe: false - gclk_arch_gen_6_oov: false - gclk_arch_gen_6_runstdby: false - gclk_arch_gen_7_enable: false - gclk_arch_gen_7_idc: false - gclk_arch_gen_7_oe: false - gclk_arch_gen_7_oov: false - gclk_arch_gen_7_runstdby: false - gclk_arch_gen_8_enable: false - gclk_arch_gen_8_idc: false - gclk_arch_gen_8_oe: false - gclk_arch_gen_8_oov: false - gclk_arch_gen_8_runstdby: false - gclk_arch_gen_9_enable: false - gclk_arch_gen_9_idc: false - gclk_arch_gen_9_oe: false - gclk_arch_gen_9_oov: false - gclk_arch_gen_9_runstdby: false - gclk_gen_0_div: 1 - gclk_gen_0_div_sel: false - gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) - gclk_gen_10_div: 1 - gclk_gen_10_div_sel: false - gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_11_div: 1 - gclk_gen_11_div_sel: false - gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_1_div: 1 - gclk_gen_1_div_sel: false - gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) - gclk_gen_2_div: 1 - gclk_gen_2_div_sel: true - gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_3_div: 1 - gclk_gen_3_div_sel: false - gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) - gclk_gen_4_div: 1 - gclk_gen_4_div_sel: false - gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_5_div: 1 - gclk_gen_5_div_sel: false - gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_6_div: 1 - gclk_gen_6_div_sel: false - gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_7_div: 1 - gclk_gen_7_div_sel: false - gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_8_div: 1 - gclk_gen_8_div_sel: false - gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_9_div: 1 - gclk_gen_9_div_sel: false - gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - optional_signals: [] - variant: null - clocks: - domain_group: null - MCLK: - user_label: MCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK - functionality: System - api: HAL:HPL:MCLK - configuration: - cpu_clock_source: Generic clock generator 0 - cpu_div: '1' - enable_cpu_clock: true - mclk_arch_bupdiv: Divide by 8 - mclk_arch_hsdiv: Divide by 1 - mclk_arch_lpdiv: Divide by 4 - nvm_wait_states: '5' - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: CPU - input: CPU - external: false - external_frequency: 0 - configuration: {} - OSC32KCTRL: - user_label: OSC32KCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL - functionality: System - api: HAL:HPL:OSC32KCTRL - configuration: - enable_osculp32k: true - enable_rtc_source: false - enable_xosc32k: true - osculp32k_calib: 0 - osculp32k_calib_enable: false - rtc_1khz_selection: false - rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) - xosc32k_arch_cfden: false - xosc32k_arch_cfdeo: false - xosc32k_arch_cgm: Standard mode - xosc32k_arch_en1k: false - xosc32k_arch_en32k: true - xosc32k_arch_enable: true - xosc32k_arch_ondemand: true - xosc32k_arch_runstdby: false - xosc32k_arch_startup: 1000092us - xosc32k_arch_swben: false - xosc32k_arch_xtalen: true - optional_signals: [] - variant: null - clocks: - domain_group: null - OSCCTRL: - user_label: OSCCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL - functionality: System - api: HAL:HPL:OSCCTRL - configuration: - dfll_arch_bplckc: false - dfll_arch_calibration: false - dfll_arch_ccdis: false - dfll_arch_coarse: 31 - dfll_arch_cstep: 1 - dfll_arch_enable: false - dfll_arch_fine: 128 - dfll_arch_fstep: 1 - dfll_arch_llaw: false - dfll_arch_ondemand: false - dfll_arch_qldis: false - dfll_arch_runstdby: false - dfll_arch_stable: false - dfll_arch_usbcrm: false - dfll_arch_waitlock: true - dfll_mode: Open Loop Mode - dfll_mul: 0 - dfll_ref_clock: Generic clock generator 3 - enable_dfll: false - enable_fdpll0: true - enable_fdpll1: false - enable_xosc0: false - enable_xosc1: false - fdpll0_arch_dcoen: false - fdpll0_arch_enable: true - fdpll0_arch_filter: 0 - fdpll0_arch_lbypass: true - fdpll0_arch_ltime: No time-out, automatic lock - fdpll0_arch_ondemand: false - fdpll0_arch_refclk: XOSC32K clock reference - fdpll0_arch_runstdby: false - fdpll0_arch_wuf: false - fdpll0_clock_dcofilter: 0 - fdpll0_clock_div: 0 - fdpll0_ldr: 3661 - fdpll0_ldrfrac: 1 - fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - fdpll1_arch_dcoen: false - fdpll1_arch_enable: false - fdpll1_arch_filter: 0 - fdpll1_arch_lbypass: false - fdpll1_arch_ltime: No time-out, automatic lock - fdpll1_arch_ondemand: false - fdpll1_arch_refclk: XOSC32K clock reference - fdpll1_arch_runstdby: false - fdpll1_arch_wuf: false - fdpll1_clock_dcofilter: 0 - fdpll1_clock_div: 0 - fdpll1_ldr: 1463 - fdpll1_ldrfrac: 13 - fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - xosc0_arch_cfden: false - xosc0_arch_enable: false - xosc0_arch_enalc: false - xosc0_arch_lowbufgain: false - xosc0_arch_ondemand: false - xosc0_arch_runstdby: false - xosc0_arch_startup: 31us - xosc0_arch_swben: false - xosc0_arch_xtalen: false - xosc0_frequency: 12000000 - xosc1_arch_cfden: false - xosc1_arch_enable: false - xosc1_arch_enalc: false - xosc1_arch_lowbufgain: false - xosc1_arch_ondemand: false - xosc1_arch_runstdby: false - xosc1_arch_startup: 31us - xosc1_arch_swben: false - xosc1_arch_xtalen: true - xosc1_frequency: 12000000 - optional_signals: [] - variant: null - clocks: - domain_group: null - PORT: - user_label: PORT - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT - functionality: System - api: HAL:HPL:PORT - configuration: - enable_port_input_event_0: false - enable_port_input_event_1: false - enable_port_input_event_2: false - enable_port_input_event_3: false - porta_event_action_0: Output register of pin will be set to level of event - porta_event_action_1: Output register of pin will be set to level of event - porta_event_action_2: Output register of pin will be set to level of event - porta_event_action_3: Output register of pin will be set to level of event - porta_event_pin_identifier_0: 0 - porta_event_pin_identifier_1: 0 - porta_event_pin_identifier_2: 0 - porta_event_pin_identifier_3: 0 - porta_input_event_enable_0: false - porta_input_event_enable_1: false - porta_input_event_enable_2: false - porta_input_event_enable_3: false - portb_event_action_0: Output register of pin will be set to level of event - portb_event_action_1: Output register of pin will be set to level of event - portb_event_action_2: Output register of pin will be set to level of event - portb_event_action_3: Output register of pin will be set to level of event - portb_event_pin_identifier_0: 0 - portb_event_pin_identifier_1: 0 - portb_event_pin_identifier_2: 0 - portb_event_pin_identifier_3: 0 - portb_input_event_enable_0: false - portb_input_event_enable_1: false - portb_input_event_enable_2: false - portb_input_event_enable_3: false - portc_event_action_0: Output register of pin will be set to level of event - portc_event_action_1: Output register of pin will be set to level of event - portc_event_action_2: Output register of pin will be set to level of event - portc_event_action_3: Output register of pin will be set to level of event - portc_event_pin_identifier_0: 0 - portc_event_pin_identifier_1: 0 - portc_event_pin_identifier_2: 0 - portc_event_pin_identifier_3: 0 - portc_input_event_enable_0: false - portc_input_event_enable_1: false - portc_input_event_enable_2: false - portc_input_event_enable_3: false - portd_event_action_0: Output register of pin will be set to level of event - portd_event_action_1: Output register of pin will be set to level of event - portd_event_action_2: Output register of pin will be set to level of event - portd_event_action_3: Output register of pin will be set to level of event - portd_event_pin_identifier_0: 0 - portd_event_pin_identifier_1: 0 - portd_event_pin_identifier_2: 0 - portd_event_pin_identifier_3: 0 - portd_input_event_enable_0: false - portd_input_event_enable_1: false - portd_input_event_enable_2: false - portd_input_event_enable_3: false - optional_signals: [] - variant: null - clocks: - domain_group: null - RAMECC: - user_label: RAMECC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC - functionality: System - api: HAL:HPL:RAMECC - configuration: {} - optional_signals: [] - variant: null - clocks: - domain_group: null - USART_0: - user_label: USART_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM0::driver_config_definition::UART::HAL:Driver:USART.Sync - functionality: USART - api: HAL:Driver:USART_Sync - configuration: - usart_advanced: false - usart_arch_clock_mode: USART with internal clock - usart_arch_cloden: false - usart_arch_dbgstop: Keep running - usart_arch_dord: LSB is transmitted first - usart_arch_enc: No encoding - usart_arch_fractional: 0 - usart_arch_ibon: false - usart_arch_lin_slave_enable: Disable - usart_arch_runstdby: false - usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) - usart_arch_sampr: 16x arithmetic - usart_arch_sfde: false - usart_baud_rate: 9600 - usart_character_size: 8 bits - usart_parity: No parity - usart_rx_enable: true - usart_stop_bit: One stop bit - usart_tx_enable: true - optional_signals: [] - variant: - specification: TXPO=0, RXPO=1, CMODE=0 - required_signals: - - name: SERCOM0/PAD/0 - pad: PA04 - label: TX - - name: SERCOM0/PAD/1 - pad: PA05 - label: RX - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - external: false - external_frequency: 0 - - name: Slow - input: Generic clock generator 3 - external: false - external_frequency: 0 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - TIMER_0: - user_label: TIMER_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer - functionality: Timer - api: HAL:Driver:Timer - configuration: - tc_arch_dbgrun: false - tc_arch_evact: Event action disabled - tc_arch_mceo0: false - tc_arch_mceo1: false - tc_arch_ondemand: false - tc_arch_ovfeo: false - tc_arch_presync: Reload or reset counter on next GCLK - tc_arch_runstdby: false - tc_arch_tcei: false - tc_arch_tcinv: false - timer_advanced_configuration: false - timer_event_control: false - timer_prescaler: Divide by 8 - timer_tick: 1000 - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: TC - input: Generic clock generator 0 - external: false - external_frequency: 0 - configuration: - tc_gclk_selection: Generic clock generator 0 -pads: - PA04: - name: PA04 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA04 - mode: Peripheral IO - user_label: PA04 - configuration: null - PA05: - name: PA05 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA05 - mode: Peripheral IO - user_label: PA05 - configuration: null -toolchain_options: [] diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_sercom_config.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_sercom_config.h deleted file mode 100644 index 2f63e8e..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_sercom_config.h +++ /dev/null @@ -1,278 +0,0 @@ -/* Auto-generated config file hpl_sercom_config.h */ -#ifndef HPL_SERCOM_CONFIG_H -#define HPL_SERCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -#ifndef CONF_SERCOM_0_USART_ENABLE -#define CONF_SERCOM_0_USART_ENABLE 1 -#endif - -// Basic Configuration - -// Receive buffer enable -// Enable input buffer in SERCOM module -// usart_rx_enable -#ifndef CONF_SERCOM_0_USART_RXEN -#define CONF_SERCOM_0_USART_RXEN 1 -#endif - -// Transmitt buffer enable -// Enable output buffer in SERCOM module -// usart_tx_enable -#ifndef CONF_SERCOM_0_USART_TXEN -#define CONF_SERCOM_0_USART_TXEN 1 -#endif - -// Frame parity -// <0x0=>No parity -// <0x1=>Even parity -// <0x2=>Odd parity -// Parity bit mode for USART frame -// usart_parity -#ifndef CONF_SERCOM_0_USART_PARITY -#define CONF_SERCOM_0_USART_PARITY 0x0 -#endif - -// Character Size -// <0x0=>8 bits -// <0x1=>9 bits -// <0x5=>5 bits -// <0x6=>6 bits -// <0x7=>7 bits -// Data character size in USART frame -// usart_character_size -#ifndef CONF_SERCOM_0_USART_CHSIZE -#define CONF_SERCOM_0_USART_CHSIZE 0x0 -#endif - -// Stop Bit -// <0=>One stop bit -// <1=>Two stop bits -// Number of stop bits in USART frame -// usart_stop_bit -#ifndef CONF_SERCOM_0_USART_SBMODE -#define CONF_SERCOM_0_USART_SBMODE 0 -#endif - -// Baud rate <1-6250000> -// USART baud rate setting -// usart_baud_rate -#ifndef CONF_SERCOM_0_USART_BAUD -#define CONF_SERCOM_0_USART_BAUD 9600 -#endif - -// - -// Advanced configuration -// usart_advanced -#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG -#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0 -#endif - -// Run in stand-by -// Keep the module running in standby sleep mode -// usart_arch_runstdby -#ifndef CONF_SERCOM_0_USART_RUNSTDBY -#define CONF_SERCOM_0_USART_RUNSTDBY 0 -#endif - -// Immediate Buffer Overflow Notification -// Controls when the BUFOVF status bit is asserted -// usart_arch_ibon -#ifndef CONF_SERCOM_0_USART_IBON -#define CONF_SERCOM_0_USART_IBON 0 -#endif - -// Start of Frame Detection Enable -// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) -// usart_arch_sfde -#ifndef CONF_SERCOM_0_USART_SFDE -#define CONF_SERCOM_0_USART_SFDE 0 -#endif - -// Collision Detection Enable -// Collision detection enable -// usart_arch_cloden -#ifndef CONF_SERCOM_0_USART_CLODEN -#define CONF_SERCOM_0_USART_CLODEN 0 -#endif - -// Operating Mode -// <0x0=>USART with external clock -// <0x1=>USART with internal clock -// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. -// usart_arch_clock_mode -#ifndef CONF_SERCOM_0_USART_MODE -#define CONF_SERCOM_0_USART_MODE 0x1 -#endif - -// Sample Rate -// <0x0=>16x arithmetic -// <0x1=>16x fractional -// <0x2=>8x arithmetic -// <0x3=>8x fractional -// <0x4=>3x arithmetic -// How many over-sampling bits used when sampling data state -// usart_arch_sampr -#ifndef CONF_SERCOM_0_USART_SAMPR -#define CONF_SERCOM_0_USART_SAMPR 0x0 -#endif - -// Sample Adjustment -// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) -// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) -// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) -// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) -// Adjust which samples to use for data sampling in asynchronous mode -// usart_arch_sampa -#ifndef CONF_SERCOM_0_USART_SAMPA -#define CONF_SERCOM_0_USART_SAMPA 0x0 -#endif - -// Fractional Part <0-7> -// Fractional part of the baud rate if baud rate generator is in fractional mode -// usart_arch_fractional -#ifndef CONF_SERCOM_0_USART_FRACTIONAL -#define CONF_SERCOM_0_USART_FRACTIONAL 0x0 -#endif - -// Data Order -// <0=>MSB is transmitted first -// <1=>LSB is transmitted first -// Data order of the data bits in the frame -// usart_arch_dord -#ifndef CONF_SERCOM_0_USART_DORD -#define CONF_SERCOM_0_USART_DORD 1 -#endif - -// Does not do anything in UART mode -#define CONF_SERCOM_0_USART_CPOL 0 - -// Encoding Format -// <0=>No encoding -// <1=>IrDA encoded -// usart_arch_enc -#ifndef CONF_SERCOM_0_USART_ENC -#define CONF_SERCOM_0_USART_ENC 0 -#endif - -// LIN Slave Enable -// Break Character Detection and Auto-Baud/LIN Slave Enable. -// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). -// <0=>Disable -// <1=>Enable -// usart_arch_lin_slave_enable -#ifndef CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE -#define CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// usart_arch_dbgstop -#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE -#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_0_USART_INACK -#define CONF_SERCOM_0_USART_INACK 0x0 -#endif - -#ifndef CONF_SERCOM_0_USART_DSNACK -#define CONF_SERCOM_0_USART_DSNACK 0x0 -#endif - -#ifndef CONF_SERCOM_0_USART_MAXITER -#define CONF_SERCOM_0_USART_MAXITER 0x7 -#endif - -#ifndef CONF_SERCOM_0_USART_GTIME -#define CONF_SERCOM_0_USART_GTIME 0x2 -#endif - -#define CONF_SERCOM_0_USART_RXINV 0x0 -#define CONF_SERCOM_0_USART_TXINV 0x0 - -#ifndef CONF_SERCOM_0_USART_CMODE -#define CONF_SERCOM_0_USART_CMODE 0 -#endif - -#ifndef CONF_SERCOM_0_USART_RXPO -#define CONF_SERCOM_0_USART_RXPO 1 /* RX is on PIN_PA05 */ -#endif - -#ifndef CONF_SERCOM_0_USART_TXPO -#define CONF_SERCOM_0_USART_TXPO 0 /* TX is on PIN_PA04 */ -#endif - -/* Set correct parity settings in register interface based on PARITY setting */ -#if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 1 -#if CONF_SERCOM_0_USART_PARITY == 0 -#define CONF_SERCOM_0_USART_PMODE 0 -#define CONF_SERCOM_0_USART_FORM 4 -#else -#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 -#define CONF_SERCOM_0_USART_FORM 5 -#endif -#else /* #if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 0 */ -#if CONF_SERCOM_0_USART_PARITY == 0 -#define CONF_SERCOM_0_USART_PMODE 0 -#define CONF_SERCOM_0_USART_FORM 0 -#else -#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 -#define CONF_SERCOM_0_USART_FORM 1 -#endif -#endif - -// Calculate BAUD register value in UART mode -#if CONF_SERCOM_0_USART_SAMPR == 0 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_0_USART_SAMPR == 1 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_0_USART_SAMPR == 2 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_0_USART_SAMPR == 3 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_0_USART_SAMPR == 4 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#endif - -// <<< end of configuration section >>> - -#endif // HPL_SERCOM_CONFIG_H diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/peripheral_clk_config.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/peripheral_clk_config.h deleted file mode 100644 index 82e94e0..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/peripheral_clk_config.h +++ /dev/null @@ -1,137 +0,0 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 119997440 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM0_CORE_SRC -#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM0_SLOW_SRC -#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY - * \brief SERCOM0's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY -#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 119997440 -#endif - -/** - * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY - * \brief SERCOM0's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 -#endif - -// TC Clock Source -// tc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for TC. -#ifndef CONF_GCLK_TC0_SRC -#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_TC0_FREQUENCY - * \brief TC0's Clock frequency - */ -#ifndef CONF_GCLK_TC0_FREQUENCY -#define CONF_GCLK_TC0_FREQUENCY 119997440 -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/components/display/p_ssd1963.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/components/display/p_ssd1963.c deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/components/display/p_ssd1963.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/components/display/p_ssd1963.h deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/driver_init.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/driver_init.c deleted file mode 100644 index 3e032d0..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/driver_init.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_init.h" -#include -#include -#include - -struct timer_descriptor TIMER_0; - -struct usart_sync_descriptor USART_0; - -void USART_0_PORT_init(void) -{ - - gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0); - - gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1); -} - -void USART_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); -} - -void USART_0_init(void) -{ - USART_0_CLOCK_init(); - usart_sync_init(&USART_0, SERCOM0, (void *)NULL); - USART_0_PORT_init(); -} - -/** - * \brief Timer initialization function - * - * Enables Timer peripheral, clocks and initializes Timer driver - */ -static void TIMER_0_init(void) -{ - hri_mclk_set_APBAMASK_TC0_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - timer_init(&TIMER_0, TC0, _tc_get_timer()); -} - -void system_init(void) -{ - init_mcu(); - - USART_0_init(); - - TIMER_0_init(); -} diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_gpio.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_gpio.c deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_gpio.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_gpio.h deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_tcc.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_tcc.c deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_tcc.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_tcc.h deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_usart.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_usart.c deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_usart.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/drivers/p_usart.h deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/examples/driver_examples.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/examples/driver_examples.c deleted file mode 100644 index 113c648..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/examples/driver_examples.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_examples.h" -#include "driver_init.h" -#include "utils.h" - -/** - * Example of using USART_0 to write "Hello World" using the IO abstraction. - */ -void USART_0_example(void) -{ - struct io_descriptor *io; - usart_sync_get_io_descriptor(&USART_0, &io); - usart_sync_enable(&USART_0); - - io_write(io, (uint8_t *)"Hello World!", 12); -} - -static struct timer_task TIMER_0_task1, TIMER_0_task2; - -/** - * Example of using TIMER_0. - */ -static void TIMER_0_task1_cb(const struct timer_task *const timer_task) -{ -} - -static void TIMER_0_task2_cb(const struct timer_task *const timer_task) -{ -} - -void TIMER_0_example(void) -{ - TIMER_0_task1.interval = 100; - TIMER_0_task1.cb = TIMER_0_task1_cb; - TIMER_0_task1.mode = TIMER_TASK_REPEAT; - TIMER_0_task2.interval = 200; - TIMER_0_task2.cb = TIMER_0_task2_cb; - TIMER_0_task2.mode = TIMER_TASK_REPEAT; - - timer_add_task(&TIMER_0, &TIMER_0_task1); - timer_add_task(&TIMER_0, &TIMER_0_task2); - timer_start(&TIMER_0); -} diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/documentation/usart_sync.rst b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/documentation/usart_sync.rst deleted file mode 100644 index 15e4b13..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/documentation/usart_sync.rst +++ /dev/null @@ -1,58 +0,0 @@ -The USART Synchronous Driver -============================ - -The universal synchronous and asynchronous receiver and transmitter -(USART) is usually used to transfer data from one device to the other. - -User can set action for flow control pins by function usart_set_flow_control, -if the flow control is enabled. All the available states are defined in union -usart_flow_control_state. - -Note that user can set state of flow control pins only if automatic support of -the flow control is not supported by the hardware. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * UART or USRT communication mode - * Character size - * Data order - * Flow control -* Data transfer: transmission, reception - -Applications ------------- - -They are commonly used in a terminal application or low-speed communication -between devices. - -Dependencies ------------- - -USART capable hardware. - -Concurrency ------------ - -Write buffer should not be changed while data is being sent. - - -Limitations ------------ - -* The driver does not support 9-bit character size. -* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. - And the SCK pin can't be set directly. Application can use a GCLK output PIN - to generate SCK. For example to communicate with a SMARTCARD with ISO7816 - (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be - config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_usart_sync.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_usart_sync.h deleted file mode 100644 index 1ef22fc..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_usart_sync.h +++ /dev/null @@ -1,247 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SYNC_USART_H_INCLUDED -#define _HAL_SYNC_USART_H_INCLUDED - -#include "hal_io.h" -#include - -/** - * \addtogroup doc_driver_hal_usart_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Synchronous USART descriptor - */ -struct usart_sync_descriptor { - struct io_descriptor io; - struct _usart_sync_device device; -}; - -/** - * \brief Initialize USART interface - * - * This function initializes the given I/O descriptor to be used - * as USART interface descriptor. - * It checks if the given hardware is not initialized and - * if the given hardware is permitted to be initialized. - * - * \param[out] descr A USART descriptor which is used to communicate via USART - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to as set of functions pointers - * - * \return Initialization status. - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); - -/** - * \brief Deinitialize USART interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and - * if the given hardware is permitted to be deinitialized. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return De-initialization status. - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); - -/** - * \brief Enable USART interface - * - * Enables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Enabling status. - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); - -/** - * \brief Disable USART interface - * - * Disables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Disabling status. - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve I/O descriptor - * - * This function retrieves the I/O descriptor of the given USART descriptor. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] io An I/O descriptor to retrieve - * - * \return The status of the I/O descriptor retrieving. - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); - -/** - * \brief Specify action for flow control pins - * - * This function sets the action (or state) for the flow control pins - * if the flow control is enabled. - * It sets the state of flow control pins only if the automatic support of - * the flow control is not supported by the hardware. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] state A state to set the flow control pins - * - * \return The status of flow control action setup. - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state); - -/** - * \brief Set USART baud rate - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] baud_rate A baud rate to set - * - * \return The status of baud rate setting. - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); - -/** - * \brief Set USART data order - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] data_order A data order to set - * - * \return The status of data order setting. - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); - -/** - * \brief Set USART mode - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] mode A mode to set - * - * \return The status of mode setting. - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); - -/** - * \brief Set USART parity - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] parity A parity to set - * - * \return The status of parity setting. - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); - -/** - * \brief Set USART stop bits - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] stop_bits Stop bits to set - * - * \return The status of stop bits setting. - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); - -/** - * \brief Set USART character size - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] size A character size to set - * - * \return The status of character size setting. - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins - * if the flow control is enabled. - * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case - * if the flow control is done by the hardware - * and the pins state cannot be read out. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] state The state of flow control pins - * - * \return The status of flow control state reading. - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state); - -/** - * \brief Check if the USART transmitter is empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART TX empty checking. - * \retval 0 The USART transmitter is not empty - * \retval 1 The USART transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Check if the USART receiver is not empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART RX empty checking. - * \retval 1 The USART receiver is not empty - * \retval 0 The USART receiver is empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usart_sync_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_usart_sync.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_usart_sync.c deleted file mode 100644 index ab99c1d..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_usart_sync.c +++ /dev/null @@ -1,276 +0,0 @@ -/** - * \file - * - * \brief I/O USART related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_usart_sync.h" -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief Initialize usart interface - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) -{ - int32_t init_status; - ASSERT(descr && hw); - init_status = _usart_sync_init(&descr->device, hw); - if (init_status) { - return init_status; - } - - descr->io.read = usart_sync_read; - descr->io.write = usart_sync_write; - - return ERR_NONE; -} - -/** - * \brief Uninitialize usart interface - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_deinit(&descr->device); - - descr->io.read = NULL; - descr->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Enable usart interface - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Disable usart interface - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) -{ - ASSERT(descr && io); - - *io = &descr->io; - return ERR_NONE; -} - -/** - * \brief Specify action for flow control pins - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state) -{ - ASSERT(descr); - _usart_sync_set_flow_control_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Set usart baud rate - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) -{ - ASSERT(descr); - _usart_sync_set_baud_rate(&descr->device, baud_rate); - - return ERR_NONE; -} - -/** - * \brief Set usart data order - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) -{ - ASSERT(descr); - _usart_sync_set_data_order(&descr->device, data_order); - - return ERR_NONE; -} - -/** - * \brief Set usart mode - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) -{ - ASSERT(descr); - _usart_sync_set_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set usart parity - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) -{ - ASSERT(descr); - _usart_sync_set_parity(&descr->device, parity); - - return ERR_NONE; -} - -/** - * \brief Set usart stop bits - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) -{ - ASSERT(descr); - _usart_sync_set_stop_bits(&descr->device, stop_bits); - - return ERR_NONE; -} - -/** - * \brief Set usart character size - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) -{ - ASSERT(descr); - _usart_sync_set_character_size(&descr->device, size); - - return ERR_NONE; -} - -/** - * \brief Retrieve the state of flow control pins - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state) -{ - ASSERT(descr && state); - *state = _usart_sync_get_flow_control_state(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Check if the usart transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_ready_to_send(&descr->device); -} - -/** - * \brief Check if the usart receiver is not empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_byte_received(&descr->device); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t usart_sync_get_version(void) -{ - return DRIVER_VERSION; -} - -/* - * \internal Write the given data to usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf Data to write to usart - * \param[in] length The number of bytes to write - * - * \return The number of bytes written. - */ -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - while (!_usart_sync_is_ready_to_send(&descr->device)) - ; - do { - _usart_sync_write_byte(&descr->device, buf[offset]); - while (!_usart_sync_is_ready_to_send(&descr->device)) - ; - } while (++offset < length); - while (!_usart_sync_is_transmit_done(&descr->device)) - ; - return (int32_t)offset; -} - -/* - * \internal Read data from usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - do { - while (!_usart_sync_is_byte_received(&descr->device)) - ; - buf[offset] = _usart_sync_read_byte(&descr->device); - } while (++offset < length); - - return (int32_t)offset; -} diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/main.c b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/main.c deleted file mode 100644 index e69de29..0000000 diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/project.h b/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/project.h deleted file mode 100644 index 50c2bf8..0000000 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/project.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * project.h - * - * Created: 4/19/2020 6:56:39 PM - * Author: Penguin - */ diff --git a/software/firmware/project_oracle_base/AtmelStart.env_conf b/software/firmware/project_oracle_base/AtmelStart.env_conf deleted file mode 100644 index 2033451..0000000 --- a/software/firmware/project_oracle_base/AtmelStart.env_conf +++ /dev/null @@ -1,6 +0,0 @@ - - - - - - diff --git a/software/firmware/project_oracle_base/AtmelStart.gpdsc b/software/firmware/project_oracle_base/AtmelStart.gpdsc deleted file mode 100644 index 42d67f1..0000000 --- a/software/firmware/project_oracle_base/AtmelStart.gpdsc +++ /dev/null @@ -1,233 +0,0 @@ - - Atmel - My Project - Project generated by Atmel Start - http://start.atmel.com/ - - Initial version - - - Configuration Files generated by Atmel Start - - - - Atmel Start - - - - - - - - - -
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Overview
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CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

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  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
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  • System exception names to interface to system exceptions without having compatibility issues.
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  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
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  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
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  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
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  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
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The following sections provide details about the CMSIS-Core (Cortex-M):

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CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

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Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

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File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
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-Processor Support

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CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

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-Cortex-M Reference Manuals

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The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

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The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

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-Armv8-M Architecture

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Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

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The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

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-Tested and Verified Toolchains

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The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

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  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
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  • Arm: Arm Compiler 6.9
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  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
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  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
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  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
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- - - - diff --git a/software/firmware/project_oracle_base/armcc/Makefile b/software/firmware/project_oracle_base/armcc/Makefile deleted file mode 100644 index a23b21d..0000000 --- a/software/firmware/project_oracle_base/armcc/Makefile +++ /dev/null @@ -1,243 +0,0 @@ - -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -ifdef SystemRoot - SHELL = cmd.exe - MK_DIR = mkdir -else - ifeq ($(shell uname), Linux) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW32) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW64) - MK_DIR = mkdir -p - endif -endif - -# List the subdirectories for creating object files -SUB_DIRS += \ - \ -hpl/pm \ -hpl/tc \ -hpl/osc32kctrl \ -hpl/ramecc \ -hpl/dmac \ -hal/src \ -armcc/arm_addon/armcc \ -hpl/mclk \ -hpl/qspi \ -hpl/eic \ -hpl/sercom \ -examples \ -hpl/gclk \ -hpl/oscctrl \ -hal/utils/src \ -hpl/rtc \ -armcc/arm_addon/armcc/arm \ -hpl/systick \ -hpl/core \ -hpl/cmcc - -# List the object files -OBJS += \ -hal/src/hal_io.o \ -hpl/qspi/hpl_qspi.o \ -armcc/arm_addon/armcc/system_same54.o \ -hpl/eic/hpl_eic.o \ -hpl/core/hpl_core_m4.o \ -hpl/systick/hpl_systick.o \ -hal/src/hal_timer.o \ -hal/src/hal_i2c_m_sync.o \ -hal/src/hal_delay.o \ -hpl/pm/hpl_pm.o \ -hpl/core/hpl_init.o \ -hpl/ramecc/hpl_ramecc.o \ -hal/utils/src/utils_list.o \ -hal/utils/src/utils_assert.o \ -hpl/dmac/hpl_dmac.o \ -hpl/oscctrl/hpl_oscctrl.o \ -hal/src/hal_usart_sync.o \ -hpl/mclk/hpl_mclk.o \ -hpl/sercom/hpl_sercom.o \ -hpl/gclk/hpl_gclk.o \ -hal/src/hal_init.o \ -main.o \ -hpl/osc32kctrl/hpl_osc32kctrl.o \ -hpl/rtc/hpl_rtc.o \ -examples/driver_examples.o \ -driver_init.o \ -hal/src/hal_ext_irq.o \ -hal/src/hal_atomic.o \ -hal/src/hal_gpio.o \ -hal/src/hal_qspi_sync.o \ -hal/utils/src/utils_event.o \ -hal/src/hal_sleep.o \ -hal/src/hal_cache.o \ -atmel_start.o \ -hpl/tc/hpl_tc.o \ -hpl/cmcc/hpl_cmcc.o \ -armcc/arm_addon/armcc/arm/startup_same54.o - -OBJS_AS_ARGS += \ -"hal/src/hal_io.o" \ -"hpl/qspi/hpl_qspi.o" \ -"armcc/arm_addon/armcc/system_same54.o" \ -"hpl/eic/hpl_eic.o" \ -"hpl/core/hpl_core_m4.o" \ -"hpl/systick/hpl_systick.o" \ -"hal/src/hal_timer.o" \ -"hal/src/hal_i2c_m_sync.o" \ -"hal/src/hal_delay.o" \ -"hpl/pm/hpl_pm.o" \ -"hpl/core/hpl_init.o" \ -"hpl/ramecc/hpl_ramecc.o" \ -"hal/utils/src/utils_list.o" \ -"hal/utils/src/utils_assert.o" \ -"hpl/dmac/hpl_dmac.o" \ -"hpl/oscctrl/hpl_oscctrl.o" \ -"hal/src/hal_usart_sync.o" \ -"hpl/mclk/hpl_mclk.o" \ -"hpl/sercom/hpl_sercom.o" \ -"hpl/gclk/hpl_gclk.o" \ -"hal/src/hal_init.o" \ -"main.o" \ -"hpl/osc32kctrl/hpl_osc32kctrl.o" \ -"hpl/rtc/hpl_rtc.o" \ -"examples/driver_examples.o" \ -"driver_init.o" \ -"hal/src/hal_ext_irq.o" \ -"hal/src/hal_atomic.o" \ -"hal/src/hal_gpio.o" \ -"hal/src/hal_qspi_sync.o" \ -"hal/utils/src/utils_event.o" \ -"hal/src/hal_sleep.o" \ -"hal/src/hal_cache.o" \ -"atmel_start.o" \ -"hpl/tc/hpl_tc.o" \ -"hpl/cmcc/hpl_cmcc.o" \ -"armcc/arm_addon/armcc/arm/startup_same54.o" - -# List the dependency files -DEPS := $(OBJS:%.o=%.d) - -DEPS_AS_ARGS += \ -"hal/utils/src/utils_event.d" \ -"hal/src/hal_io.d" \ -"armcc/arm_addon/armcc/system_same54.d" \ -"hpl/ramecc/hpl_ramecc.d" \ -"hpl/qspi/hpl_qspi.d" \ -"hpl/core/hpl_core_m4.d" \ -"hpl/eic/hpl_eic.d" \ -"hal/src/hal_i2c_m_sync.d" \ -"hal/src/hal_timer.d" \ -"hal/utils/src/utils_list.d" \ -"hpl/cmcc/hpl_cmcc.d" \ -"hpl/dmac/hpl_dmac.d" \ -"hal/utils/src/utils_assert.d" \ -"hal/src/hal_delay.d" \ -"hpl/core/hpl_init.d" \ -"hpl/pm/hpl_pm.d" \ -"hpl/gclk/hpl_gclk.d" \ -"hpl/sercom/hpl_sercom.d" \ -"hal/src/hal_init.d" \ -"hal/src/hal_usart_sync.d" \ -"hpl/mclk/hpl_mclk.d" \ -"driver_init.d" \ -"hpl/systick/hpl_systick.d" \ -"hpl/osc32kctrl/hpl_osc32kctrl.d" \ -"main.d" \ -"examples/driver_examples.d" \ -"hpl/rtc/hpl_rtc.d" \ -"hal/src/hal_qspi_sync.d" \ -"hal/src/hal_cache.d" \ -"hal/src/hal_sleep.d" \ -"hal/src/hal_ext_irq.d" \ -"hal/src/hal_gpio.d" \ -"hal/src/hal_atomic.d" \ -"hpl/tc/hpl_tc.d" \ -"hpl/oscctrl/hpl_oscctrl.d" \ -"armcc/arm_addon/armcc/arm/startup_same54.d" \ -"atmel_start.d" - -OUTPUT_FILE_NAME :=AtmelStart -QUOTE := " -OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf -OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf - -vpath %.c ../ -vpath %.s ../ -vpath %.S ../ - -# All Target -all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) - -# Linker target - -$(OUTPUT_FILE_PATH): $(OBJS) - @echo Building target: $@ - @echo Invoking: ARMCC Linker - $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ ---strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ ---info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ --o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \ -$(OBJS_AS_ARGS) - - @echo Finished building target: $@ - -# Compiler target(s) - - - - -%.o: %.c - @echo Building file: $< - @echo ARMCC Compiler - $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/qspi" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ ---depend "$@" -o "$@" "$<" - - @echo Finished building: $< - -%.o: %.s - @echo Building file: $< - @echo ARMCC Assembler - $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAME54P20A__ SETA 1" \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/qspi" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ ---depend "$(@:%.o=%.d)" -o "$@" "$<" - - @echo Finished building: $< - -%.o: %.S - @echo Building file: $< - @echo ARMCC Preprocessing Assembler - $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/qspi" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ ---depend "$@" -o "$@" "$<" - - @echo Finished building: $< - -# Detect changes in the dependent files and recompile the respective object files. -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(DEPS)),) --include $(DEPS) -endif -endif - -$(SUB_DIRS): - $(MK_DIR) "$@" - -clean: - rm -f $(OBJS_AS_ARGS) - rm -f $(OUTPUT_FILE_PATH) - rm -f $(DEPS_AS_ARGS) - rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/software/firmware/project_oracle_base/armcc/arm_addon/armcc/arm/startup_same54.s b/software/firmware/project_oracle_base/armcc/arm_addon/armcc/arm/startup_same54.s deleted file mode 100644 index 3e17c25..0000000 --- a/software/firmware/project_oracle_base/armcc/arm_addon/armcc/arm/startup_same54.s +++ /dev/null @@ -1,588 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAME54.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Atmel SAME54 Device Series -; * @version V1.0.0 -; * @date 16. January 2017 -; * -; * @note -; * Copyright (C) 2017 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD MCLK_Handler ; 1 Main Clock - DCD OSCCTRL_0_Handler ; 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 - DCD OSCCTRL_1_Handler ; 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 - DCD OSCCTRL_2_Handler ; 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY - DCD OSCCTRL_3_Handler ; 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 - DCD OSCCTRL_4_Handler ; 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 - DCD OSC32KCTRL_Handler ; 7 32kHz Oscillators Control - DCD SUPC_0_Handler ; 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY - DCD SUPC_1_Handler ; 9 SUPC_BOD12DET, SUPC_BOD33DET - DCD WDT_Handler ; 10 Watchdog Timer - DCD RTC_Handler ; 11 Real-Time Counter - DCD EIC_0_Handler ; 12 EIC_EXTINT_0 - DCD EIC_1_Handler ; 13 EIC_EXTINT_1 - DCD EIC_2_Handler ; 14 EIC_EXTINT_2 - DCD EIC_3_Handler ; 15 EIC_EXTINT_3 - DCD EIC_4_Handler ; 16 EIC_EXTINT_4 - DCD EIC_5_Handler ; 17 EIC_EXTINT_5 - DCD EIC_6_Handler ; 18 EIC_EXTINT_6 - DCD EIC_7_Handler ; 19 EIC_EXTINT_7 - DCD EIC_8_Handler ; 20 EIC_EXTINT_8 - DCD EIC_9_Handler ; 21 EIC_EXTINT_9 - DCD EIC_10_Handler ; 22 EIC_EXTINT_10 - DCD EIC_11_Handler ; 23 EIC_EXTINT_11 - DCD EIC_12_Handler ; 24 EIC_EXTINT_12 - DCD EIC_13_Handler ; 25 EIC_EXTINT_13 - DCD EIC_14_Handler ; 26 EIC_EXTINT_14 - DCD EIC_15_Handler ; 27 EIC_EXTINT_15 - DCD FREQM_Handler ; 28 Frequency Meter - DCD NVMCTRL_0_Handler ; 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 - DCD NVMCTRL_1_Handler ; 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 - DCD DMAC_0_Handler ; 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 - DCD DMAC_1_Handler ; 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 - DCD DMAC_2_Handler ; 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 - DCD DMAC_3_Handler ; 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 - DCD DMAC_4_Handler ; 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 - DCD EVSYS_0_Handler ; 36 EVSYS_EVD_0, EVSYS_OVR_0 - DCD EVSYS_1_Handler ; 37 EVSYS_EVD_1, EVSYS_OVR_1 - DCD EVSYS_2_Handler ; 38 EVSYS_EVD_2, EVSYS_OVR_2 - DCD EVSYS_3_Handler ; 39 EVSYS_EVD_3, EVSYS_OVR_3 - DCD EVSYS_4_Handler ; 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 - DCD PAC_Handler ; 41 Peripheral Access Controller - DCD TAL_0_Handler ; 42 TAL_BRK - DCD TAL_1_Handler ; 43 TAL_IPS_0, TAL_IPS_1 - DCD 0 ; 44 Reserved - DCD RAMECC_Handler ; 45 RAM ECC - DCD SERCOM0_0_Handler ; 46 SERCOM0_0 - DCD SERCOM0_1_Handler ; 47 SERCOM0_1 - DCD SERCOM0_2_Handler ; 48 SERCOM0_2 - DCD SERCOM0_3_Handler ; 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 - DCD SERCOM1_0_Handler ; 50 SERCOM1_0 - DCD SERCOM1_1_Handler ; 51 SERCOM1_1 - DCD SERCOM1_2_Handler ; 52 SERCOM1_2 - DCD SERCOM1_3_Handler ; 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 - DCD SERCOM2_0_Handler ; 54 SERCOM2_0 - DCD SERCOM2_1_Handler ; 55 SERCOM2_1 - DCD SERCOM2_2_Handler ; 56 SERCOM2_2 - DCD SERCOM2_3_Handler ; 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 - DCD SERCOM3_0_Handler ; 58 SERCOM3_0 - DCD SERCOM3_1_Handler ; 59 SERCOM3_1 - DCD SERCOM3_2_Handler ; 60 SERCOM3_2 - DCD SERCOM3_3_Handler ; 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 - DCD SERCOM4_0_Handler ; 62 SERCOM4_0 - DCD SERCOM4_1_Handler ; 63 SERCOM4_1 - DCD SERCOM4_2_Handler ; 64 SERCOM4_2 - DCD SERCOM4_3_Handler ; 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 - DCD SERCOM5_0_Handler ; 66 SERCOM5_0 - DCD SERCOM5_1_Handler ; 67 SERCOM5_1 - DCD SERCOM5_2_Handler ; 68 SERCOM5_2 - DCD SERCOM5_3_Handler ; 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 - DCD SERCOM6_0_Handler ; 70 SERCOM6_0 - DCD SERCOM6_1_Handler ; 71 SERCOM6_1 - DCD SERCOM6_2_Handler ; 72 SERCOM6_2 - DCD SERCOM6_3_Handler ; 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 - DCD SERCOM7_0_Handler ; 74 SERCOM7_0 - DCD SERCOM7_1_Handler ; 75 SERCOM7_1 - DCD SERCOM7_2_Handler ; 76 SERCOM7_2 - DCD SERCOM7_3_Handler ; 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 - DCD CAN0_Handler ; 78 Control Area Network 0 - DCD CAN1_Handler ; 79 Control Area Network 1 - DCD USB_0_Handler ; 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP - DCD USB_1_Handler ; 81 USB_SOF_HSOF - DCD USB_2_Handler ; 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 - DCD USB_3_Handler ; 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 - DCD GMAC_Handler ; 84 Ethernet MAC - DCD TCC0_0_Handler ; 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A - DCD TCC0_1_Handler ; 86 TCC0_MC_0 - DCD TCC0_2_Handler ; 87 TCC0_MC_1 - DCD TCC0_3_Handler ; 88 TCC0_MC_2 - DCD TCC0_4_Handler ; 89 TCC0_MC_3 - DCD TCC0_5_Handler ; 90 TCC0_MC_4 - DCD TCC0_6_Handler ; 91 TCC0_MC_5 - DCD TCC1_0_Handler ; 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A - DCD TCC1_1_Handler ; 93 TCC1_MC_0 - DCD TCC1_2_Handler ; 94 TCC1_MC_1 - DCD TCC1_3_Handler ; 95 TCC1_MC_2 - DCD TCC1_4_Handler ; 96 TCC1_MC_3 - DCD TCC2_0_Handler ; 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A - DCD TCC2_1_Handler ; 98 TCC2_MC_0 - DCD TCC2_2_Handler ; 99 TCC2_MC_1 - DCD TCC2_3_Handler ; 100 TCC2_MC_2 - DCD TCC3_0_Handler ; 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A - DCD TCC3_1_Handler ; 102 TCC3_MC_0 - DCD TCC3_2_Handler ; 103 TCC3_MC_1 - DCD TCC4_0_Handler ; 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A - DCD TCC4_1_Handler ; 105 TCC4_MC_0 - DCD TCC4_2_Handler ; 106 TCC4_MC_1 - DCD TC0_Handler ; 107 Basic Timer Counter 0 - DCD TC1_Handler ; 108 Basic Timer Counter 1 - DCD TC2_Handler ; 109 Basic Timer Counter 2 - DCD TC3_Handler ; 110 Basic Timer Counter 3 - DCD TC4_Handler ; 111 Basic Timer Counter 4 - DCD TC5_Handler ; 112 Basic Timer Counter 5 - DCD TC6_Handler ; 113 Basic Timer Counter 6 - DCD TC7_Handler ; 114 Basic Timer Counter 7 - DCD PDEC_0_Handler ; 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A - DCD PDEC_1_Handler ; 116 PDEC_MC_0 - DCD PDEC_2_Handler ; 117 PDEC_MC_1 - DCD ADC0_0_Handler ; 118 ADC0_OVERRUN, ADC0_WINMON - DCD ADC0_1_Handler ; 119 ADC0_RESRDY - DCD ADC1_0_Handler ; 120 ADC1_OVERRUN, ADC1_WINMON - DCD ADC1_1_Handler ; 121 ADC1_RESRDY - DCD AC_Handler ; 122 Analog Comparators - DCD DAC_0_Handler ; 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 - DCD DAC_1_Handler ; 124 DAC_EMPTY_0 - DCD DAC_2_Handler ; 125 DAC_EMPTY_1 - DCD DAC_3_Handler ; 126 DAC_RESRDY_0 - DCD DAC_4_Handler ; 127 DAC_RESRDY_1 - DCD I2S_Handler ; 128 Inter-IC Sound Interface - DCD PCC_Handler ; 129 Parallel Capture Controller - DCD AES_Handler ; 130 Advanced Encryption Standard - DCD TRNG_Handler ; 131 True Random Generator - DCD ICM_Handler ; 132 Integrity Check Monitor - DCD PUKCC_Handler ; 133 PUblic-Key Cryptography Controller - DCD QSPI_Handler ; 134 Quad SPI interface - DCD SDHC0_Handler ; 135 SD/MMC Host Controller 0 - DCD SDHC1_Handler ; 136 SD/MMC Host Controller 1 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT MCLK_Handler [WEAK] - EXPORT OSCCTRL_0_Handler [WEAK] - EXPORT OSCCTRL_1_Handler [WEAK] - EXPORT OSCCTRL_2_Handler [WEAK] - EXPORT OSCCTRL_3_Handler [WEAK] - EXPORT OSCCTRL_4_Handler [WEAK] - EXPORT OSC32KCTRL_Handler [WEAK] - EXPORT SUPC_0_Handler [WEAK] - EXPORT SUPC_1_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_0_Handler [WEAK] - EXPORT EIC_1_Handler [WEAK] - EXPORT EIC_2_Handler [WEAK] - EXPORT EIC_3_Handler [WEAK] - EXPORT EIC_4_Handler [WEAK] - EXPORT EIC_5_Handler [WEAK] - EXPORT EIC_6_Handler [WEAK] - EXPORT EIC_7_Handler [WEAK] - EXPORT EIC_8_Handler [WEAK] - EXPORT EIC_9_Handler [WEAK] - EXPORT EIC_10_Handler [WEAK] - EXPORT EIC_11_Handler [WEAK] - EXPORT EIC_12_Handler [WEAK] - EXPORT EIC_13_Handler [WEAK] - EXPORT EIC_14_Handler [WEAK] - EXPORT EIC_15_Handler [WEAK] - EXPORT FREQM_Handler [WEAK] - EXPORT NVMCTRL_0_Handler [WEAK] - EXPORT NVMCTRL_1_Handler [WEAK] - EXPORT DMAC_0_Handler [WEAK] - EXPORT DMAC_1_Handler [WEAK] - EXPORT DMAC_2_Handler [WEAK] - EXPORT DMAC_3_Handler [WEAK] - EXPORT DMAC_4_Handler [WEAK] - EXPORT EVSYS_0_Handler [WEAK] - EXPORT EVSYS_1_Handler [WEAK] - EXPORT EVSYS_2_Handler [WEAK] - EXPORT EVSYS_3_Handler [WEAK] - EXPORT EVSYS_4_Handler [WEAK] - EXPORT PAC_Handler [WEAK] - EXPORT TAL_0_Handler [WEAK] - EXPORT TAL_1_Handler [WEAK] - EXPORT RAMECC_Handler [WEAK] - EXPORT SERCOM0_0_Handler [WEAK] - EXPORT SERCOM0_1_Handler [WEAK] - EXPORT SERCOM0_2_Handler [WEAK] - EXPORT SERCOM0_3_Handler [WEAK] - EXPORT SERCOM1_0_Handler [WEAK] - EXPORT SERCOM1_1_Handler [WEAK] - EXPORT SERCOM1_2_Handler [WEAK] - EXPORT SERCOM1_3_Handler [WEAK] - EXPORT SERCOM2_0_Handler [WEAK] - EXPORT SERCOM2_1_Handler [WEAK] - EXPORT SERCOM2_2_Handler [WEAK] - EXPORT SERCOM2_3_Handler [WEAK] - EXPORT SERCOM3_0_Handler [WEAK] - EXPORT SERCOM3_1_Handler [WEAK] - EXPORT SERCOM3_2_Handler [WEAK] - EXPORT SERCOM3_3_Handler [WEAK] - EXPORT SERCOM4_0_Handler [WEAK] - EXPORT SERCOM4_1_Handler [WEAK] - EXPORT SERCOM4_2_Handler [WEAK] - EXPORT SERCOM4_3_Handler [WEAK] - EXPORT SERCOM5_0_Handler [WEAK] - EXPORT SERCOM5_1_Handler [WEAK] - EXPORT SERCOM5_2_Handler [WEAK] - EXPORT SERCOM5_3_Handler [WEAK] - EXPORT SERCOM6_0_Handler [WEAK] - EXPORT SERCOM6_1_Handler [WEAK] - EXPORT SERCOM6_2_Handler [WEAK] - EXPORT SERCOM6_3_Handler [WEAK] - EXPORT SERCOM7_0_Handler [WEAK] - EXPORT SERCOM7_1_Handler [WEAK] - EXPORT SERCOM7_2_Handler [WEAK] - EXPORT SERCOM7_3_Handler [WEAK] - EXPORT CAN0_Handler [WEAK] - EXPORT CAN1_Handler [WEAK] - EXPORT USB_0_Handler [WEAK] - EXPORT USB_1_Handler [WEAK] - EXPORT USB_2_Handler [WEAK] - EXPORT USB_3_Handler [WEAK] - EXPORT GMAC_Handler [WEAK] - EXPORT TCC0_0_Handler [WEAK] - EXPORT TCC0_1_Handler [WEAK] - EXPORT TCC0_2_Handler [WEAK] - EXPORT TCC0_3_Handler [WEAK] - EXPORT TCC0_4_Handler [WEAK] - EXPORT TCC0_5_Handler [WEAK] - EXPORT TCC0_6_Handler [WEAK] - EXPORT TCC1_0_Handler [WEAK] - EXPORT TCC1_1_Handler [WEAK] - EXPORT TCC1_2_Handler [WEAK] - EXPORT TCC1_3_Handler [WEAK] - EXPORT TCC1_4_Handler [WEAK] - EXPORT TCC2_0_Handler [WEAK] - EXPORT TCC2_1_Handler [WEAK] - EXPORT TCC2_2_Handler [WEAK] - EXPORT TCC2_3_Handler [WEAK] - EXPORT TCC3_0_Handler [WEAK] - EXPORT TCC3_1_Handler [WEAK] - EXPORT TCC3_2_Handler [WEAK] - EXPORT TCC4_0_Handler [WEAK] - EXPORT TCC4_1_Handler [WEAK] - EXPORT TCC4_2_Handler [WEAK] - EXPORT TC0_Handler [WEAK] - EXPORT TC1_Handler [WEAK] - EXPORT TC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT PDEC_0_Handler [WEAK] - EXPORT PDEC_1_Handler [WEAK] - EXPORT PDEC_2_Handler [WEAK] - EXPORT ADC0_0_Handler [WEAK] - EXPORT ADC0_1_Handler [WEAK] - EXPORT ADC1_0_Handler [WEAK] - EXPORT ADC1_1_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_0_Handler [WEAK] - EXPORT DAC_1_Handler [WEAK] - EXPORT DAC_2_Handler [WEAK] - EXPORT DAC_3_Handler [WEAK] - EXPORT DAC_4_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT PCC_Handler [WEAK] - EXPORT AES_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - EXPORT ICM_Handler [WEAK] - EXPORT PUKCC_Handler [WEAK] - EXPORT QSPI_Handler [WEAK] - EXPORT SDHC0_Handler [WEAK] - EXPORT SDHC1_Handler [WEAK] - -PM_Handler -MCLK_Handler -OSCCTRL_0_Handler -OSCCTRL_1_Handler -OSCCTRL_2_Handler -OSCCTRL_3_Handler -OSCCTRL_4_Handler -OSC32KCTRL_Handler -SUPC_0_Handler -SUPC_1_Handler -WDT_Handler -RTC_Handler -EIC_0_Handler -EIC_1_Handler -EIC_2_Handler -EIC_3_Handler -EIC_4_Handler -EIC_5_Handler -EIC_6_Handler -EIC_7_Handler -EIC_8_Handler -EIC_9_Handler -EIC_10_Handler -EIC_11_Handler -EIC_12_Handler -EIC_13_Handler -EIC_14_Handler -EIC_15_Handler -FREQM_Handler -NVMCTRL_0_Handler -NVMCTRL_1_Handler -DMAC_0_Handler -DMAC_1_Handler -DMAC_2_Handler -DMAC_3_Handler -DMAC_4_Handler -EVSYS_0_Handler -EVSYS_1_Handler -EVSYS_2_Handler -EVSYS_3_Handler -EVSYS_4_Handler -PAC_Handler -TAL_0_Handler -TAL_1_Handler -RAMECC_Handler -SERCOM0_0_Handler -SERCOM0_1_Handler -SERCOM0_2_Handler -SERCOM0_3_Handler -SERCOM1_0_Handler -SERCOM1_1_Handler -SERCOM1_2_Handler -SERCOM1_3_Handler -SERCOM2_0_Handler -SERCOM2_1_Handler -SERCOM2_2_Handler -SERCOM2_3_Handler -SERCOM3_0_Handler -SERCOM3_1_Handler -SERCOM3_2_Handler -SERCOM3_3_Handler -SERCOM4_0_Handler -SERCOM4_1_Handler -SERCOM4_2_Handler -SERCOM4_3_Handler -SERCOM5_0_Handler -SERCOM5_1_Handler -SERCOM5_2_Handler -SERCOM5_3_Handler -SERCOM6_0_Handler -SERCOM6_1_Handler -SERCOM6_2_Handler -SERCOM6_3_Handler -SERCOM7_0_Handler -SERCOM7_1_Handler -SERCOM7_2_Handler -SERCOM7_3_Handler -CAN0_Handler -CAN1_Handler -USB_0_Handler -USB_1_Handler -USB_2_Handler -USB_3_Handler -GMAC_Handler -TCC0_0_Handler -TCC0_1_Handler -TCC0_2_Handler -TCC0_3_Handler -TCC0_4_Handler -TCC0_5_Handler -TCC0_6_Handler -TCC1_0_Handler -TCC1_1_Handler -TCC1_2_Handler -TCC1_3_Handler -TCC1_4_Handler -TCC2_0_Handler -TCC2_1_Handler -TCC2_2_Handler -TCC2_3_Handler -TCC3_0_Handler -TCC3_1_Handler -TCC3_2_Handler -TCC4_0_Handler -TCC4_1_Handler -TCC4_2_Handler -TC0_Handler -TC1_Handler -TC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -PDEC_0_Handler -PDEC_1_Handler -PDEC_2_Handler -ADC0_0_Handler -ADC0_1_Handler -ADC1_0_Handler -ADC1_1_Handler -AC_Handler -DAC_0_Handler -DAC_1_Handler -DAC_2_Handler -DAC_3_Handler -DAC_4_Handler -I2S_Handler -PCC_Handler -AES_Handler -TRNG_Handler -ICM_Handler -PUKCC_Handler -QSPI_Handler -SDHC0_Handler -SDHC1_Handler - B . - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/software/firmware/project_oracle_base/armcc/arm_addon/armcc/system_same54.c b/software/firmware/project_oracle_base/armcc/arm_addon/armcc/system_same54.c deleted file mode 100644 index 95d3036..0000000 --- a/software/firmware/project_oracle_base/armcc/arm_addon/armcc/system_same54.c +++ /dev/null @@ -1,70 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "same54.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ -#if __FPU_USED - /* Enable FPU */ - SCB->CPACR |= (0xFu << 20); - __DSB(); - __ISB(); -#endif - - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/software/firmware/project_oracle_base/atmel_start.c b/software/firmware/project_oracle_base/atmel_start.c deleted file mode 100644 index 79f252a..0000000 --- a/software/firmware/project_oracle_base/atmel_start.c +++ /dev/null @@ -1,9 +0,0 @@ -#include - -/** - * Initializes MCU, drivers and middleware in the project - **/ -void atmel_start_init(void) -{ - system_init(); -} diff --git a/software/firmware/project_oracle_base/atmel_start.h b/software/firmware/project_oracle_base/atmel_start.h deleted file mode 100644 index 0de62f5..0000000 --- a/software/firmware/project_oracle_base/atmel_start.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef ATMEL_START_H_INCLUDED -#define ATMEL_START_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include "driver_init.h" - -/** - * Initializes MCU, drivers and middleware in the project - **/ -void atmel_start_init(void); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/software/firmware/project_oracle_base/atmel_start_pins.h b/software/firmware/project_oracle_base/atmel_start_pins.h deleted file mode 100644 index e490668..0000000 --- a/software/firmware/project_oracle_base/atmel_start_pins.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef ATMEL_START_PINS_H_INCLUDED -#define ATMEL_START_PINS_H_INCLUDED - -#include - -// SAME54 has 14 pin functions - -#define GPIO_PIN_FUNCTION_A 0 -#define GPIO_PIN_FUNCTION_B 1 -#define GPIO_PIN_FUNCTION_C 2 -#define GPIO_PIN_FUNCTION_D 3 -#define GPIO_PIN_FUNCTION_E 4 -#define GPIO_PIN_FUNCTION_F 5 -#define GPIO_PIN_FUNCTION_G 6 -#define GPIO_PIN_FUNCTION_H 7 -#define GPIO_PIN_FUNCTION_I 8 -#define GPIO_PIN_FUNCTION_J 9 -#define GPIO_PIN_FUNCTION_K 10 -#define GPIO_PIN_FUNCTION_L 11 -#define GPIO_PIN_FUNCTION_M 12 -#define GPIO_PIN_FUNCTION_N 13 - -#define PA04 GPIO(GPIO_PORTA, 4) -#define PA05 GPIO(GPIO_PORTA, 5) -#define PA16 GPIO(GPIO_PORTA, 16) -#define PA17 GPIO(GPIO_PORTA, 17) - -#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/software/firmware/project_oracle_base/config/hpl_cmcc_config.h b/software/firmware/project_oracle_base/config/hpl_cmcc_config.h deleted file mode 100644 index 8590736..0000000 --- a/software/firmware/project_oracle_base/config/hpl_cmcc_config.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Auto-generated config file hpl_cmcc_config.h */ -#ifndef HPL_CMCC_CONFIG_H -#define HPL_CMCC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic Configuration - -// Cache enable -// Defines the cache should be enabled or not. -// cmcc_enable -#ifndef CONF_CMCC_ENABLE -#define CONF_CMCC_ENABLE 0x0 -#endif - -// Cache Size -// Defines the cache memory size to be configured. -// <0x0=>1 KB -// <0x1=>2 KB -// <0x2=>4 KB -// cache_size -#ifndef CONF_CMCC_CACHE_SIZE -#define CONF_CMCC_CACHE_SIZE 0x2 -#endif - -// Advanced Configuration -// cmcc_advanced_configuration -// Data cache disable -// Defines the data cache should be disabled or not. -// cmcc_data_cache_disable -#ifndef CONF_CMCC_DATA_CACHE_DISABLE -#define CONF_CMCC_DATA_CACHE_DISABLE 0x0 -#endif - -// Instruction cache disable -// Defines the Instruction cache should be disabled or not. -// cmcc_inst_cache_disable -#ifndef CONF_CMCC_INST_CACHE_DISABLE -#define CONF_CMCC_INST_CACHE_DISABLE 0x0 -#endif - -// Clock Gating disable -// Defines the clock gating should be disabled or not. -// cmcc_clock_gating_disable -#ifndef CONF_CMCC_CLK_GATING_DISABLE -#define CONF_CMCC_CLK_GATING_DISABLE 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_CMCC_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_dmac_config.h b/software/firmware/project_oracle_base/config/hpl_dmac_config.h deleted file mode 100644 index 90499fc..0000000 --- a/software/firmware/project_oracle_base/config/hpl_dmac_config.h +++ /dev/null @@ -1,7277 +0,0 @@ -/* Auto-generated config file hpl_dmac_config.h */ -#ifndef HPL_DMAC_CONFIG_H -#define HPL_DMAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// DMAC enable -// Indicates whether dmac is enabled or not -// dmac_enable -#ifndef CONF_DMAC_ENABLE -#define CONF_DMAC_ENABLE 0 -#endif - -// Priority Level 0 -// Indicates whether Priority Level 0 is enabled or not -// dmac_lvlen0 -#ifndef CONF_DMAC_LVLEN0 -#define CONF_DMAC_LVLEN0 1 -#endif - -// Level 0 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 0 -// <1=> Round-robin arbitration scheme for channel with priority 0 -// Defines Level 0 Arbitration for DMA channels -// dmac_rrlvlen0 -#ifndef CONF_DMAC_RRLVLEN0 -#define CONF_DMAC_RRLVLEN0 0 -#endif - -// Level 0 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri0 -#ifndef CONF_DMAC_LVLPRI0 -#define CONF_DMAC_LVLPRI0 0 -#endif -// Priority Level 1 -// Indicates whether Priority Level 1 is enabled or not -// dmac_lvlen1 -#ifndef CONF_DMAC_LVLEN1 -#define CONF_DMAC_LVLEN1 1 -#endif - -// Level 1 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 1 -// <1=> Round-robin arbitration scheme for channel with priority 1 -// Defines Level 1 Arbitration for DMA channels -// dmac_rrlvlen1 -#ifndef CONF_DMAC_RRLVLEN1 -#define CONF_DMAC_RRLVLEN1 0 -#endif - -// Level 1 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri1 -#ifndef CONF_DMAC_LVLPRI1 -#define CONF_DMAC_LVLPRI1 0 -#endif -// Priority Level 2 -// Indicates whether Priority Level 2 is enabled or not -// dmac_lvlen2 -#ifndef CONF_DMAC_LVLEN2 -#define CONF_DMAC_LVLEN2 1 -#endif - -// Level 2 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 2 -// <1=> Round-robin arbitration scheme for channel with priority 2 -// Defines Level 2 Arbitration for DMA channels -// dmac_rrlvlen2 -#ifndef CONF_DMAC_RRLVLEN2 -#define CONF_DMAC_RRLVLEN2 0 -#endif - -// Level 2 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri2 -#ifndef CONF_DMAC_LVLPRI2 -#define CONF_DMAC_LVLPRI2 0 -#endif -// Priority Level 3 -// Indicates whether Priority Level 3 is enabled or not -// dmac_lvlen3 -#ifndef CONF_DMAC_LVLEN3 -#define CONF_DMAC_LVLEN3 1 -#endif - -// Level 3 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 3 -// <1=> Round-robin arbitration scheme for channel with priority 3 -// Defines Level 3 Arbitration for DMA channels -// dmac_rrlvlen3 -#ifndef CONF_DMAC_RRLVLEN3 -#define CONF_DMAC_RRLVLEN3 0 -#endif - -// Level 3 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri3 -#ifndef CONF_DMAC_LVLPRI3 -#define CONF_DMAC_LVLPRI3 0 -#endif -// Debug Run -// Indicates whether Debug Run is enabled or not -// dmac_dbgrun -#ifndef CONF_DMAC_DBGRUN -#define CONF_DMAC_DBGRUN 0 -#endif - -// Channel 0 settings -// dmac_channel_0_settings -#ifndef CONF_DMAC_CHANNEL_0_SETTINGS -#define CONF_DMAC_CHANNEL_0_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 0 is running in standby mode or not -// dmac_runstdby_0 -#ifndef CONF_DMAC_RUNSTDBY_0 -#define CONF_DMAC_RUNSTDBY_0 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_0 -#ifndef CONF_DMAC_TRIGACT_0 -#define CONF_DMAC_TRIGACT_0 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_0 -#ifndef CONF_DMAC_TRIGSRC_0 -#define CONF_DMAC_TRIGSRC_0 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_0 -#ifndef CONF_DMAC_LVL_0 -#define CONF_DMAC_LVL_0 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_0 -#ifndef CONF_DMAC_EVOE_0 -#define CONF_DMAC_EVOE_0 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_0 -#ifndef CONF_DMAC_EVIE_0 -#define CONF_DMAC_EVIE_0 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_0 -#ifndef CONF_DMAC_EVACT_0 -#define CONF_DMAC_EVACT_0 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_0 -#ifndef CONF_DMAC_STEPSIZE_0 -#define CONF_DMAC_STEPSIZE_0 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_0 -#ifndef CONF_DMAC_STEPSEL_0 -#define CONF_DMAC_STEPSEL_0 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_0 -#ifndef CONF_DMAC_SRCINC_0 -#define CONF_DMAC_SRCINC_0 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_0 -#ifndef CONF_DMAC_DSTINC_0 -#define CONF_DMAC_DSTINC_0 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_0 -#ifndef CONF_DMAC_BEATSIZE_0 -#define CONF_DMAC_BEATSIZE_0 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_0 -#ifndef CONF_DMAC_BLOCKACT_0 -#define CONF_DMAC_BLOCKACT_0 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_0 -#ifndef CONF_DMAC_EVOSEL_0 -#define CONF_DMAC_EVOSEL_0 0 -#endif -// - -// Channel 1 settings -// dmac_channel_1_settings -#ifndef CONF_DMAC_CHANNEL_1_SETTINGS -#define CONF_DMAC_CHANNEL_1_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 1 is running in standby mode or not -// dmac_runstdby_1 -#ifndef CONF_DMAC_RUNSTDBY_1 -#define CONF_DMAC_RUNSTDBY_1 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_1 -#ifndef CONF_DMAC_TRIGACT_1 -#define CONF_DMAC_TRIGACT_1 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_1 -#ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_1 -#ifndef CONF_DMAC_LVL_1 -#define CONF_DMAC_LVL_1 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_1 -#ifndef CONF_DMAC_EVOE_1 -#define CONF_DMAC_EVOE_1 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_1 -#ifndef CONF_DMAC_EVIE_1 -#define CONF_DMAC_EVIE_1 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_1 -#ifndef CONF_DMAC_EVACT_1 -#define CONF_DMAC_EVACT_1 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_1 -#ifndef CONF_DMAC_STEPSIZE_1 -#define CONF_DMAC_STEPSIZE_1 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_1 -#ifndef CONF_DMAC_STEPSEL_1 -#define CONF_DMAC_STEPSEL_1 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_1 -#ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_1 -#ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_1 -#ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_1 -#ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_1 -#ifndef CONF_DMAC_EVOSEL_1 -#define CONF_DMAC_EVOSEL_1 0 -#endif -// - -// Channel 2 settings -// dmac_channel_2_settings -#ifndef CONF_DMAC_CHANNEL_2_SETTINGS -#define CONF_DMAC_CHANNEL_2_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 2 is running in standby mode or not -// dmac_runstdby_2 -#ifndef CONF_DMAC_RUNSTDBY_2 -#define CONF_DMAC_RUNSTDBY_2 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_2 -#ifndef CONF_DMAC_TRIGACT_2 -#define CONF_DMAC_TRIGACT_2 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_2 -#ifndef CONF_DMAC_TRIGSRC_2 -#define CONF_DMAC_TRIGSRC_2 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_2 -#ifndef CONF_DMAC_LVL_2 -#define CONF_DMAC_LVL_2 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_2 -#ifndef CONF_DMAC_EVOE_2 -#define CONF_DMAC_EVOE_2 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_2 -#ifndef CONF_DMAC_EVIE_2 -#define CONF_DMAC_EVIE_2 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_2 -#ifndef CONF_DMAC_EVACT_2 -#define CONF_DMAC_EVACT_2 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_2 -#ifndef CONF_DMAC_STEPSIZE_2 -#define CONF_DMAC_STEPSIZE_2 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_2 -#ifndef CONF_DMAC_STEPSEL_2 -#define CONF_DMAC_STEPSEL_2 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_2 -#ifndef CONF_DMAC_SRCINC_2 -#define CONF_DMAC_SRCINC_2 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_2 -#ifndef CONF_DMAC_DSTINC_2 -#define CONF_DMAC_DSTINC_2 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_2 -#ifndef CONF_DMAC_BEATSIZE_2 -#define CONF_DMAC_BEATSIZE_2 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_2 -#ifndef CONF_DMAC_BLOCKACT_2 -#define CONF_DMAC_BLOCKACT_2 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_2 -#ifndef CONF_DMAC_EVOSEL_2 -#define CONF_DMAC_EVOSEL_2 0 -#endif -// - -// Channel 3 settings -// dmac_channel_3_settings -#ifndef CONF_DMAC_CHANNEL_3_SETTINGS -#define CONF_DMAC_CHANNEL_3_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 3 is running in standby mode or not -// dmac_runstdby_3 -#ifndef CONF_DMAC_RUNSTDBY_3 -#define CONF_DMAC_RUNSTDBY_3 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_3 -#ifndef CONF_DMAC_TRIGACT_3 -#define CONF_DMAC_TRIGACT_3 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_3 -#ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_3 -#ifndef CONF_DMAC_LVL_3 -#define CONF_DMAC_LVL_3 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_3 -#ifndef CONF_DMAC_EVOE_3 -#define CONF_DMAC_EVOE_3 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_3 -#ifndef CONF_DMAC_EVIE_3 -#define CONF_DMAC_EVIE_3 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_3 -#ifndef CONF_DMAC_EVACT_3 -#define CONF_DMAC_EVACT_3 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_3 -#ifndef CONF_DMAC_STEPSIZE_3 -#define CONF_DMAC_STEPSIZE_3 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_3 -#ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_3 -#ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_3 -#ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_3 -#ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_3 -#ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_3 -#ifndef CONF_DMAC_EVOSEL_3 -#define CONF_DMAC_EVOSEL_3 0 -#endif -// - -// Channel 4 settings -// dmac_channel_4_settings -#ifndef CONF_DMAC_CHANNEL_4_SETTINGS -#define CONF_DMAC_CHANNEL_4_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 4 is running in standby mode or not -// dmac_runstdby_4 -#ifndef CONF_DMAC_RUNSTDBY_4 -#define CONF_DMAC_RUNSTDBY_4 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_4 -#ifndef CONF_DMAC_TRIGACT_4 -#define CONF_DMAC_TRIGACT_4 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_4 -#ifndef CONF_DMAC_TRIGSRC_4 -#define CONF_DMAC_TRIGSRC_4 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_4 -#ifndef CONF_DMAC_LVL_4 -#define CONF_DMAC_LVL_4 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_4 -#ifndef CONF_DMAC_EVOE_4 -#define CONF_DMAC_EVOE_4 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_4 -#ifndef CONF_DMAC_EVIE_4 -#define CONF_DMAC_EVIE_4 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_4 -#ifndef CONF_DMAC_EVACT_4 -#define CONF_DMAC_EVACT_4 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_4 -#ifndef CONF_DMAC_STEPSIZE_4 -#define CONF_DMAC_STEPSIZE_4 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_4 -#ifndef CONF_DMAC_STEPSEL_4 -#define CONF_DMAC_STEPSEL_4 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_4 -#ifndef CONF_DMAC_SRCINC_4 -#define CONF_DMAC_SRCINC_4 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_4 -#ifndef CONF_DMAC_DSTINC_4 -#define CONF_DMAC_DSTINC_4 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_4 -#ifndef CONF_DMAC_BEATSIZE_4 -#define CONF_DMAC_BEATSIZE_4 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_4 -#ifndef CONF_DMAC_BLOCKACT_4 -#define CONF_DMAC_BLOCKACT_4 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_4 -#ifndef CONF_DMAC_EVOSEL_4 -#define CONF_DMAC_EVOSEL_4 0 -#endif -// - -// Channel 5 settings -// dmac_channel_5_settings -#ifndef CONF_DMAC_CHANNEL_5_SETTINGS -#define CONF_DMAC_CHANNEL_5_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 5 is running in standby mode or not -// dmac_runstdby_5 -#ifndef CONF_DMAC_RUNSTDBY_5 -#define CONF_DMAC_RUNSTDBY_5 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_5 -#ifndef CONF_DMAC_TRIGACT_5 -#define CONF_DMAC_TRIGACT_5 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_5 -#ifndef CONF_DMAC_TRIGSRC_5 -#define CONF_DMAC_TRIGSRC_5 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_5 -#ifndef CONF_DMAC_LVL_5 -#define CONF_DMAC_LVL_5 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_5 -#ifndef CONF_DMAC_EVOE_5 -#define CONF_DMAC_EVOE_5 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_5 -#ifndef CONF_DMAC_EVIE_5 -#define CONF_DMAC_EVIE_5 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_5 -#ifndef CONF_DMAC_EVACT_5 -#define CONF_DMAC_EVACT_5 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_5 -#ifndef CONF_DMAC_STEPSIZE_5 -#define CONF_DMAC_STEPSIZE_5 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_5 -#ifndef CONF_DMAC_STEPSEL_5 -#define CONF_DMAC_STEPSEL_5 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_5 -#ifndef CONF_DMAC_SRCINC_5 -#define CONF_DMAC_SRCINC_5 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_5 -#ifndef CONF_DMAC_DSTINC_5 -#define CONF_DMAC_DSTINC_5 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_5 -#ifndef CONF_DMAC_BEATSIZE_5 -#define CONF_DMAC_BEATSIZE_5 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_5 -#ifndef CONF_DMAC_BLOCKACT_5 -#define CONF_DMAC_BLOCKACT_5 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_5 -#ifndef CONF_DMAC_EVOSEL_5 -#define CONF_DMAC_EVOSEL_5 0 -#endif -// - -// Channel 6 settings -// dmac_channel_6_settings -#ifndef CONF_DMAC_CHANNEL_6_SETTINGS -#define CONF_DMAC_CHANNEL_6_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 6 is running in standby mode or not -// dmac_runstdby_6 -#ifndef CONF_DMAC_RUNSTDBY_6 -#define CONF_DMAC_RUNSTDBY_6 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_6 -#ifndef CONF_DMAC_TRIGACT_6 -#define CONF_DMAC_TRIGACT_6 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_6 -#ifndef CONF_DMAC_TRIGSRC_6 -#define CONF_DMAC_TRIGSRC_6 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_6 -#ifndef CONF_DMAC_LVL_6 -#define CONF_DMAC_LVL_6 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_6 -#ifndef CONF_DMAC_EVOE_6 -#define CONF_DMAC_EVOE_6 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_6 -#ifndef CONF_DMAC_EVIE_6 -#define CONF_DMAC_EVIE_6 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_6 -#ifndef CONF_DMAC_EVACT_6 -#define CONF_DMAC_EVACT_6 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_6 -#ifndef CONF_DMAC_STEPSIZE_6 -#define CONF_DMAC_STEPSIZE_6 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_6 -#ifndef CONF_DMAC_STEPSEL_6 -#define CONF_DMAC_STEPSEL_6 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_6 -#ifndef CONF_DMAC_SRCINC_6 -#define CONF_DMAC_SRCINC_6 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_6 -#ifndef CONF_DMAC_DSTINC_6 -#define CONF_DMAC_DSTINC_6 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_6 -#ifndef CONF_DMAC_BEATSIZE_6 -#define CONF_DMAC_BEATSIZE_6 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_6 -#ifndef CONF_DMAC_BLOCKACT_6 -#define CONF_DMAC_BLOCKACT_6 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_6 -#ifndef CONF_DMAC_EVOSEL_6 -#define CONF_DMAC_EVOSEL_6 0 -#endif -// - -// Channel 7 settings -// dmac_channel_7_settings -#ifndef CONF_DMAC_CHANNEL_7_SETTINGS -#define CONF_DMAC_CHANNEL_7_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 7 is running in standby mode or not -// dmac_runstdby_7 -#ifndef CONF_DMAC_RUNSTDBY_7 -#define CONF_DMAC_RUNSTDBY_7 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_7 -#ifndef CONF_DMAC_TRIGACT_7 -#define CONF_DMAC_TRIGACT_7 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_7 -#ifndef CONF_DMAC_TRIGSRC_7 -#define CONF_DMAC_TRIGSRC_7 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_7 -#ifndef CONF_DMAC_LVL_7 -#define CONF_DMAC_LVL_7 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_7 -#ifndef CONF_DMAC_EVOE_7 -#define CONF_DMAC_EVOE_7 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_7 -#ifndef CONF_DMAC_EVIE_7 -#define CONF_DMAC_EVIE_7 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_7 -#ifndef CONF_DMAC_EVACT_7 -#define CONF_DMAC_EVACT_7 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_7 -#ifndef CONF_DMAC_STEPSIZE_7 -#define CONF_DMAC_STEPSIZE_7 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_7 -#ifndef CONF_DMAC_STEPSEL_7 -#define CONF_DMAC_STEPSEL_7 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_7 -#ifndef CONF_DMAC_SRCINC_7 -#define CONF_DMAC_SRCINC_7 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_7 -#ifndef CONF_DMAC_DSTINC_7 -#define CONF_DMAC_DSTINC_7 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_7 -#ifndef CONF_DMAC_BEATSIZE_7 -#define CONF_DMAC_BEATSIZE_7 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_7 -#ifndef CONF_DMAC_BLOCKACT_7 -#define CONF_DMAC_BLOCKACT_7 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_7 -#ifndef CONF_DMAC_EVOSEL_7 -#define CONF_DMAC_EVOSEL_7 0 -#endif -// - -// Channel 8 settings -// dmac_channel_8_settings -#ifndef CONF_DMAC_CHANNEL_8_SETTINGS -#define CONF_DMAC_CHANNEL_8_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 8 is running in standby mode or not -// dmac_runstdby_8 -#ifndef CONF_DMAC_RUNSTDBY_8 -#define CONF_DMAC_RUNSTDBY_8 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_8 -#ifndef CONF_DMAC_TRIGACT_8 -#define CONF_DMAC_TRIGACT_8 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_8 -#ifndef CONF_DMAC_TRIGSRC_8 -#define CONF_DMAC_TRIGSRC_8 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_8 -#ifndef CONF_DMAC_LVL_8 -#define CONF_DMAC_LVL_8 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_8 -#ifndef CONF_DMAC_EVOE_8 -#define CONF_DMAC_EVOE_8 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_8 -#ifndef CONF_DMAC_EVIE_8 -#define CONF_DMAC_EVIE_8 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_8 -#ifndef CONF_DMAC_EVACT_8 -#define CONF_DMAC_EVACT_8 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_8 -#ifndef CONF_DMAC_STEPSIZE_8 -#define CONF_DMAC_STEPSIZE_8 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_8 -#ifndef CONF_DMAC_STEPSEL_8 -#define CONF_DMAC_STEPSEL_8 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_8 -#ifndef CONF_DMAC_SRCINC_8 -#define CONF_DMAC_SRCINC_8 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_8 -#ifndef CONF_DMAC_DSTINC_8 -#define CONF_DMAC_DSTINC_8 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_8 -#ifndef CONF_DMAC_BEATSIZE_8 -#define CONF_DMAC_BEATSIZE_8 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_8 -#ifndef CONF_DMAC_BLOCKACT_8 -#define CONF_DMAC_BLOCKACT_8 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_8 -#ifndef CONF_DMAC_EVOSEL_8 -#define CONF_DMAC_EVOSEL_8 0 -#endif -// - -// Channel 9 settings -// dmac_channel_9_settings -#ifndef CONF_DMAC_CHANNEL_9_SETTINGS -#define CONF_DMAC_CHANNEL_9_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 9 is running in standby mode or not -// dmac_runstdby_9 -#ifndef CONF_DMAC_RUNSTDBY_9 -#define CONF_DMAC_RUNSTDBY_9 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_9 -#ifndef CONF_DMAC_TRIGACT_9 -#define CONF_DMAC_TRIGACT_9 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_9 -#ifndef CONF_DMAC_TRIGSRC_9 -#define CONF_DMAC_TRIGSRC_9 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_9 -#ifndef CONF_DMAC_LVL_9 -#define CONF_DMAC_LVL_9 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_9 -#ifndef CONF_DMAC_EVOE_9 -#define CONF_DMAC_EVOE_9 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_9 -#ifndef CONF_DMAC_EVIE_9 -#define CONF_DMAC_EVIE_9 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_9 -#ifndef CONF_DMAC_EVACT_9 -#define CONF_DMAC_EVACT_9 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_9 -#ifndef CONF_DMAC_STEPSIZE_9 -#define CONF_DMAC_STEPSIZE_9 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_9 -#ifndef CONF_DMAC_STEPSEL_9 -#define CONF_DMAC_STEPSEL_9 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_9 -#ifndef CONF_DMAC_SRCINC_9 -#define CONF_DMAC_SRCINC_9 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_9 -#ifndef CONF_DMAC_DSTINC_9 -#define CONF_DMAC_DSTINC_9 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_9 -#ifndef CONF_DMAC_BEATSIZE_9 -#define CONF_DMAC_BEATSIZE_9 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_9 -#ifndef CONF_DMAC_BLOCKACT_9 -#define CONF_DMAC_BLOCKACT_9 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_9 -#ifndef CONF_DMAC_EVOSEL_9 -#define CONF_DMAC_EVOSEL_9 0 -#endif -// - -// Channel 10 settings -// dmac_channel_10_settings -#ifndef CONF_DMAC_CHANNEL_10_SETTINGS -#define CONF_DMAC_CHANNEL_10_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 10 is running in standby mode or not -// dmac_runstdby_10 -#ifndef CONF_DMAC_RUNSTDBY_10 -#define CONF_DMAC_RUNSTDBY_10 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_10 -#ifndef CONF_DMAC_TRIGACT_10 -#define CONF_DMAC_TRIGACT_10 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_10 -#ifndef CONF_DMAC_TRIGSRC_10 -#define CONF_DMAC_TRIGSRC_10 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_10 -#ifndef CONF_DMAC_LVL_10 -#define CONF_DMAC_LVL_10 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_10 -#ifndef CONF_DMAC_EVOE_10 -#define CONF_DMAC_EVOE_10 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_10 -#ifndef CONF_DMAC_EVIE_10 -#define CONF_DMAC_EVIE_10 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_10 -#ifndef CONF_DMAC_EVACT_10 -#define CONF_DMAC_EVACT_10 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_10 -#ifndef CONF_DMAC_STEPSIZE_10 -#define CONF_DMAC_STEPSIZE_10 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_10 -#ifndef CONF_DMAC_STEPSEL_10 -#define CONF_DMAC_STEPSEL_10 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_10 -#ifndef CONF_DMAC_SRCINC_10 -#define CONF_DMAC_SRCINC_10 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_10 -#ifndef CONF_DMAC_DSTINC_10 -#define CONF_DMAC_DSTINC_10 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_10 -#ifndef CONF_DMAC_BEATSIZE_10 -#define CONF_DMAC_BEATSIZE_10 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_10 -#ifndef CONF_DMAC_BLOCKACT_10 -#define CONF_DMAC_BLOCKACT_10 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_10 -#ifndef CONF_DMAC_EVOSEL_10 -#define CONF_DMAC_EVOSEL_10 0 -#endif -// - -// Channel 11 settings -// dmac_channel_11_settings -#ifndef CONF_DMAC_CHANNEL_11_SETTINGS -#define CONF_DMAC_CHANNEL_11_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 11 is running in standby mode or not -// dmac_runstdby_11 -#ifndef CONF_DMAC_RUNSTDBY_11 -#define CONF_DMAC_RUNSTDBY_11 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_11 -#ifndef CONF_DMAC_TRIGACT_11 -#define CONF_DMAC_TRIGACT_11 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_11 -#ifndef CONF_DMAC_TRIGSRC_11 -#define CONF_DMAC_TRIGSRC_11 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_11 -#ifndef CONF_DMAC_LVL_11 -#define CONF_DMAC_LVL_11 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_11 -#ifndef CONF_DMAC_EVOE_11 -#define CONF_DMAC_EVOE_11 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_11 -#ifndef CONF_DMAC_EVIE_11 -#define CONF_DMAC_EVIE_11 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_11 -#ifndef CONF_DMAC_EVACT_11 -#define CONF_DMAC_EVACT_11 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_11 -#ifndef CONF_DMAC_STEPSIZE_11 -#define CONF_DMAC_STEPSIZE_11 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_11 -#ifndef CONF_DMAC_STEPSEL_11 -#define CONF_DMAC_STEPSEL_11 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_11 -#ifndef CONF_DMAC_SRCINC_11 -#define CONF_DMAC_SRCINC_11 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_11 -#ifndef CONF_DMAC_DSTINC_11 -#define CONF_DMAC_DSTINC_11 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_11 -#ifndef CONF_DMAC_BEATSIZE_11 -#define CONF_DMAC_BEATSIZE_11 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_11 -#ifndef CONF_DMAC_BLOCKACT_11 -#define CONF_DMAC_BLOCKACT_11 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_11 -#ifndef CONF_DMAC_EVOSEL_11 -#define CONF_DMAC_EVOSEL_11 0 -#endif -// - -// Channel 12 settings -// dmac_channel_12_settings -#ifndef CONF_DMAC_CHANNEL_12_SETTINGS -#define CONF_DMAC_CHANNEL_12_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 12 is running in standby mode or not -// dmac_runstdby_12 -#ifndef CONF_DMAC_RUNSTDBY_12 -#define CONF_DMAC_RUNSTDBY_12 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_12 -#ifndef CONF_DMAC_TRIGACT_12 -#define CONF_DMAC_TRIGACT_12 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_12 -#ifndef CONF_DMAC_TRIGSRC_12 -#define CONF_DMAC_TRIGSRC_12 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_12 -#ifndef CONF_DMAC_LVL_12 -#define CONF_DMAC_LVL_12 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_12 -#ifndef CONF_DMAC_EVOE_12 -#define CONF_DMAC_EVOE_12 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_12 -#ifndef CONF_DMAC_EVIE_12 -#define CONF_DMAC_EVIE_12 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_12 -#ifndef CONF_DMAC_EVACT_12 -#define CONF_DMAC_EVACT_12 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_12 -#ifndef CONF_DMAC_STEPSIZE_12 -#define CONF_DMAC_STEPSIZE_12 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_12 -#ifndef CONF_DMAC_STEPSEL_12 -#define CONF_DMAC_STEPSEL_12 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_12 -#ifndef CONF_DMAC_SRCINC_12 -#define CONF_DMAC_SRCINC_12 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_12 -#ifndef CONF_DMAC_DSTINC_12 -#define CONF_DMAC_DSTINC_12 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_12 -#ifndef CONF_DMAC_BEATSIZE_12 -#define CONF_DMAC_BEATSIZE_12 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_12 -#ifndef CONF_DMAC_BLOCKACT_12 -#define CONF_DMAC_BLOCKACT_12 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_12 -#ifndef CONF_DMAC_EVOSEL_12 -#define CONF_DMAC_EVOSEL_12 0 -#endif -// - -// Channel 13 settings -// dmac_channel_13_settings -#ifndef CONF_DMAC_CHANNEL_13_SETTINGS -#define CONF_DMAC_CHANNEL_13_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 13 is running in standby mode or not -// dmac_runstdby_13 -#ifndef CONF_DMAC_RUNSTDBY_13 -#define CONF_DMAC_RUNSTDBY_13 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_13 -#ifndef CONF_DMAC_TRIGACT_13 -#define CONF_DMAC_TRIGACT_13 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_13 -#ifndef CONF_DMAC_TRIGSRC_13 -#define CONF_DMAC_TRIGSRC_13 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_13 -#ifndef CONF_DMAC_LVL_13 -#define CONF_DMAC_LVL_13 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_13 -#ifndef CONF_DMAC_EVOE_13 -#define CONF_DMAC_EVOE_13 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_13 -#ifndef CONF_DMAC_EVIE_13 -#define CONF_DMAC_EVIE_13 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_13 -#ifndef CONF_DMAC_EVACT_13 -#define CONF_DMAC_EVACT_13 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_13 -#ifndef CONF_DMAC_STEPSIZE_13 -#define CONF_DMAC_STEPSIZE_13 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_13 -#ifndef CONF_DMAC_STEPSEL_13 -#define CONF_DMAC_STEPSEL_13 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_13 -#ifndef CONF_DMAC_SRCINC_13 -#define CONF_DMAC_SRCINC_13 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_13 -#ifndef CONF_DMAC_DSTINC_13 -#define CONF_DMAC_DSTINC_13 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_13 -#ifndef CONF_DMAC_BEATSIZE_13 -#define CONF_DMAC_BEATSIZE_13 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_13 -#ifndef CONF_DMAC_BLOCKACT_13 -#define CONF_DMAC_BLOCKACT_13 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_13 -#ifndef CONF_DMAC_EVOSEL_13 -#define CONF_DMAC_EVOSEL_13 0 -#endif -// - -// Channel 14 settings -// dmac_channel_14_settings -#ifndef CONF_DMAC_CHANNEL_14_SETTINGS -#define CONF_DMAC_CHANNEL_14_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 14 is running in standby mode or not -// dmac_runstdby_14 -#ifndef CONF_DMAC_RUNSTDBY_14 -#define CONF_DMAC_RUNSTDBY_14 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_14 -#ifndef CONF_DMAC_TRIGACT_14 -#define CONF_DMAC_TRIGACT_14 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_14 -#ifndef CONF_DMAC_TRIGSRC_14 -#define CONF_DMAC_TRIGSRC_14 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_14 -#ifndef CONF_DMAC_LVL_14 -#define CONF_DMAC_LVL_14 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_14 -#ifndef CONF_DMAC_EVOE_14 -#define CONF_DMAC_EVOE_14 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_14 -#ifndef CONF_DMAC_EVIE_14 -#define CONF_DMAC_EVIE_14 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_14 -#ifndef CONF_DMAC_EVACT_14 -#define CONF_DMAC_EVACT_14 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_14 -#ifndef CONF_DMAC_STEPSIZE_14 -#define CONF_DMAC_STEPSIZE_14 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_14 -#ifndef CONF_DMAC_STEPSEL_14 -#define CONF_DMAC_STEPSEL_14 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_14 -#ifndef CONF_DMAC_SRCINC_14 -#define CONF_DMAC_SRCINC_14 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_14 -#ifndef CONF_DMAC_DSTINC_14 -#define CONF_DMAC_DSTINC_14 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_14 -#ifndef CONF_DMAC_BEATSIZE_14 -#define CONF_DMAC_BEATSIZE_14 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_14 -#ifndef CONF_DMAC_BLOCKACT_14 -#define CONF_DMAC_BLOCKACT_14 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_14 -#ifndef CONF_DMAC_EVOSEL_14 -#define CONF_DMAC_EVOSEL_14 0 -#endif -// - -// Channel 15 settings -// dmac_channel_15_settings -#ifndef CONF_DMAC_CHANNEL_15_SETTINGS -#define CONF_DMAC_CHANNEL_15_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 15 is running in standby mode or not -// dmac_runstdby_15 -#ifndef CONF_DMAC_RUNSTDBY_15 -#define CONF_DMAC_RUNSTDBY_15 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_15 -#ifndef CONF_DMAC_TRIGACT_15 -#define CONF_DMAC_TRIGACT_15 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_15 -#ifndef CONF_DMAC_TRIGSRC_15 -#define CONF_DMAC_TRIGSRC_15 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_15 -#ifndef CONF_DMAC_LVL_15 -#define CONF_DMAC_LVL_15 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_15 -#ifndef CONF_DMAC_EVOE_15 -#define CONF_DMAC_EVOE_15 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_15 -#ifndef CONF_DMAC_EVIE_15 -#define CONF_DMAC_EVIE_15 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_15 -#ifndef CONF_DMAC_EVACT_15 -#define CONF_DMAC_EVACT_15 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_15 -#ifndef CONF_DMAC_STEPSIZE_15 -#define CONF_DMAC_STEPSIZE_15 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_15 -#ifndef CONF_DMAC_STEPSEL_15 -#define CONF_DMAC_STEPSEL_15 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_15 -#ifndef CONF_DMAC_SRCINC_15 -#define CONF_DMAC_SRCINC_15 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_15 -#ifndef CONF_DMAC_DSTINC_15 -#define CONF_DMAC_DSTINC_15 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_15 -#ifndef CONF_DMAC_BEATSIZE_15 -#define CONF_DMAC_BEATSIZE_15 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_15 -#ifndef CONF_DMAC_BLOCKACT_15 -#define CONF_DMAC_BLOCKACT_15 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_15 -#ifndef CONF_DMAC_EVOSEL_15 -#define CONF_DMAC_EVOSEL_15 0 -#endif -// - -// Channel 16 settings -// dmac_channel_16_settings -#ifndef CONF_DMAC_CHANNEL_16_SETTINGS -#define CONF_DMAC_CHANNEL_16_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 16 is running in standby mode or not -// dmac_runstdby_16 -#ifndef CONF_DMAC_RUNSTDBY_16 -#define CONF_DMAC_RUNSTDBY_16 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_16 -#ifndef CONF_DMAC_TRIGACT_16 -#define CONF_DMAC_TRIGACT_16 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_16 -#ifndef CONF_DMAC_TRIGSRC_16 -#define CONF_DMAC_TRIGSRC_16 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_16 -#ifndef CONF_DMAC_LVL_16 -#define CONF_DMAC_LVL_16 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_16 -#ifndef CONF_DMAC_EVOE_16 -#define CONF_DMAC_EVOE_16 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_16 -#ifndef CONF_DMAC_EVIE_16 -#define CONF_DMAC_EVIE_16 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_16 -#ifndef CONF_DMAC_EVACT_16 -#define CONF_DMAC_EVACT_16 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_16 -#ifndef CONF_DMAC_STEPSIZE_16 -#define CONF_DMAC_STEPSIZE_16 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_16 -#ifndef CONF_DMAC_STEPSEL_16 -#define CONF_DMAC_STEPSEL_16 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_16 -#ifndef CONF_DMAC_SRCINC_16 -#define CONF_DMAC_SRCINC_16 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_16 -#ifndef CONF_DMAC_DSTINC_16 -#define CONF_DMAC_DSTINC_16 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_16 -#ifndef CONF_DMAC_BEATSIZE_16 -#define CONF_DMAC_BEATSIZE_16 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_16 -#ifndef CONF_DMAC_BLOCKACT_16 -#define CONF_DMAC_BLOCKACT_16 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_16 -#ifndef CONF_DMAC_EVOSEL_16 -#define CONF_DMAC_EVOSEL_16 0 -#endif -// - -// Channel 17 settings -// dmac_channel_17_settings -#ifndef CONF_DMAC_CHANNEL_17_SETTINGS -#define CONF_DMAC_CHANNEL_17_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 17 is running in standby mode or not -// dmac_runstdby_17 -#ifndef CONF_DMAC_RUNSTDBY_17 -#define CONF_DMAC_RUNSTDBY_17 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_17 -#ifndef CONF_DMAC_TRIGACT_17 -#define CONF_DMAC_TRIGACT_17 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_17 -#ifndef CONF_DMAC_TRIGSRC_17 -#define CONF_DMAC_TRIGSRC_17 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_17 -#ifndef CONF_DMAC_LVL_17 -#define CONF_DMAC_LVL_17 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_17 -#ifndef CONF_DMAC_EVOE_17 -#define CONF_DMAC_EVOE_17 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_17 -#ifndef CONF_DMAC_EVIE_17 -#define CONF_DMAC_EVIE_17 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_17 -#ifndef CONF_DMAC_EVACT_17 -#define CONF_DMAC_EVACT_17 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_17 -#ifndef CONF_DMAC_STEPSIZE_17 -#define CONF_DMAC_STEPSIZE_17 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_17 -#ifndef CONF_DMAC_STEPSEL_17 -#define CONF_DMAC_STEPSEL_17 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_17 -#ifndef CONF_DMAC_SRCINC_17 -#define CONF_DMAC_SRCINC_17 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_17 -#ifndef CONF_DMAC_DSTINC_17 -#define CONF_DMAC_DSTINC_17 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_17 -#ifndef CONF_DMAC_BEATSIZE_17 -#define CONF_DMAC_BEATSIZE_17 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_17 -#ifndef CONF_DMAC_BLOCKACT_17 -#define CONF_DMAC_BLOCKACT_17 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_17 -#ifndef CONF_DMAC_EVOSEL_17 -#define CONF_DMAC_EVOSEL_17 0 -#endif -// - -// Channel 18 settings -// dmac_channel_18_settings -#ifndef CONF_DMAC_CHANNEL_18_SETTINGS -#define CONF_DMAC_CHANNEL_18_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 18 is running in standby mode or not -// dmac_runstdby_18 -#ifndef CONF_DMAC_RUNSTDBY_18 -#define CONF_DMAC_RUNSTDBY_18 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_18 -#ifndef CONF_DMAC_TRIGACT_18 -#define CONF_DMAC_TRIGACT_18 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_18 -#ifndef CONF_DMAC_TRIGSRC_18 -#define CONF_DMAC_TRIGSRC_18 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_18 -#ifndef CONF_DMAC_LVL_18 -#define CONF_DMAC_LVL_18 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_18 -#ifndef CONF_DMAC_EVOE_18 -#define CONF_DMAC_EVOE_18 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_18 -#ifndef CONF_DMAC_EVIE_18 -#define CONF_DMAC_EVIE_18 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_18 -#ifndef CONF_DMAC_EVACT_18 -#define CONF_DMAC_EVACT_18 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_18 -#ifndef CONF_DMAC_STEPSIZE_18 -#define CONF_DMAC_STEPSIZE_18 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_18 -#ifndef CONF_DMAC_STEPSEL_18 -#define CONF_DMAC_STEPSEL_18 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_18 -#ifndef CONF_DMAC_SRCINC_18 -#define CONF_DMAC_SRCINC_18 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_18 -#ifndef CONF_DMAC_DSTINC_18 -#define CONF_DMAC_DSTINC_18 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_18 -#ifndef CONF_DMAC_BEATSIZE_18 -#define CONF_DMAC_BEATSIZE_18 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_18 -#ifndef CONF_DMAC_BLOCKACT_18 -#define CONF_DMAC_BLOCKACT_18 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_18 -#ifndef CONF_DMAC_EVOSEL_18 -#define CONF_DMAC_EVOSEL_18 0 -#endif -// - -// Channel 19 settings -// dmac_channel_19_settings -#ifndef CONF_DMAC_CHANNEL_19_SETTINGS -#define CONF_DMAC_CHANNEL_19_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 19 is running in standby mode or not -// dmac_runstdby_19 -#ifndef CONF_DMAC_RUNSTDBY_19 -#define CONF_DMAC_RUNSTDBY_19 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_19 -#ifndef CONF_DMAC_TRIGACT_19 -#define CONF_DMAC_TRIGACT_19 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_19 -#ifndef CONF_DMAC_TRIGSRC_19 -#define CONF_DMAC_TRIGSRC_19 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_19 -#ifndef CONF_DMAC_LVL_19 -#define CONF_DMAC_LVL_19 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_19 -#ifndef CONF_DMAC_EVOE_19 -#define CONF_DMAC_EVOE_19 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_19 -#ifndef CONF_DMAC_EVIE_19 -#define CONF_DMAC_EVIE_19 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_19 -#ifndef CONF_DMAC_EVACT_19 -#define CONF_DMAC_EVACT_19 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_19 -#ifndef CONF_DMAC_STEPSIZE_19 -#define CONF_DMAC_STEPSIZE_19 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_19 -#ifndef CONF_DMAC_STEPSEL_19 -#define CONF_DMAC_STEPSEL_19 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_19 -#ifndef CONF_DMAC_SRCINC_19 -#define CONF_DMAC_SRCINC_19 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_19 -#ifndef CONF_DMAC_DSTINC_19 -#define CONF_DMAC_DSTINC_19 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_19 -#ifndef CONF_DMAC_BEATSIZE_19 -#define CONF_DMAC_BEATSIZE_19 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_19 -#ifndef CONF_DMAC_BLOCKACT_19 -#define CONF_DMAC_BLOCKACT_19 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_19 -#ifndef CONF_DMAC_EVOSEL_19 -#define CONF_DMAC_EVOSEL_19 0 -#endif -// - -// Channel 20 settings -// dmac_channel_20_settings -#ifndef CONF_DMAC_CHANNEL_20_SETTINGS -#define CONF_DMAC_CHANNEL_20_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 20 is running in standby mode or not -// dmac_runstdby_20 -#ifndef CONF_DMAC_RUNSTDBY_20 -#define CONF_DMAC_RUNSTDBY_20 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_20 -#ifndef CONF_DMAC_TRIGACT_20 -#define CONF_DMAC_TRIGACT_20 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_20 -#ifndef CONF_DMAC_TRIGSRC_20 -#define CONF_DMAC_TRIGSRC_20 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_20 -#ifndef CONF_DMAC_LVL_20 -#define CONF_DMAC_LVL_20 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_20 -#ifndef CONF_DMAC_EVOE_20 -#define CONF_DMAC_EVOE_20 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_20 -#ifndef CONF_DMAC_EVIE_20 -#define CONF_DMAC_EVIE_20 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_20 -#ifndef CONF_DMAC_EVACT_20 -#define CONF_DMAC_EVACT_20 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_20 -#ifndef CONF_DMAC_STEPSIZE_20 -#define CONF_DMAC_STEPSIZE_20 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_20 -#ifndef CONF_DMAC_STEPSEL_20 -#define CONF_DMAC_STEPSEL_20 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_20 -#ifndef CONF_DMAC_SRCINC_20 -#define CONF_DMAC_SRCINC_20 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_20 -#ifndef CONF_DMAC_DSTINC_20 -#define CONF_DMAC_DSTINC_20 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_20 -#ifndef CONF_DMAC_BEATSIZE_20 -#define CONF_DMAC_BEATSIZE_20 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_20 -#ifndef CONF_DMAC_BLOCKACT_20 -#define CONF_DMAC_BLOCKACT_20 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_20 -#ifndef CONF_DMAC_EVOSEL_20 -#define CONF_DMAC_EVOSEL_20 0 -#endif -// - -// Channel 21 settings -// dmac_channel_21_settings -#ifndef CONF_DMAC_CHANNEL_21_SETTINGS -#define CONF_DMAC_CHANNEL_21_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 21 is running in standby mode or not -// dmac_runstdby_21 -#ifndef CONF_DMAC_RUNSTDBY_21 -#define CONF_DMAC_RUNSTDBY_21 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_21 -#ifndef CONF_DMAC_TRIGACT_21 -#define CONF_DMAC_TRIGACT_21 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_21 -#ifndef CONF_DMAC_TRIGSRC_21 -#define CONF_DMAC_TRIGSRC_21 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_21 -#ifndef CONF_DMAC_LVL_21 -#define CONF_DMAC_LVL_21 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_21 -#ifndef CONF_DMAC_EVOE_21 -#define CONF_DMAC_EVOE_21 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_21 -#ifndef CONF_DMAC_EVIE_21 -#define CONF_DMAC_EVIE_21 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_21 -#ifndef CONF_DMAC_EVACT_21 -#define CONF_DMAC_EVACT_21 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_21 -#ifndef CONF_DMAC_STEPSIZE_21 -#define CONF_DMAC_STEPSIZE_21 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_21 -#ifndef CONF_DMAC_STEPSEL_21 -#define CONF_DMAC_STEPSEL_21 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_21 -#ifndef CONF_DMAC_SRCINC_21 -#define CONF_DMAC_SRCINC_21 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_21 -#ifndef CONF_DMAC_DSTINC_21 -#define CONF_DMAC_DSTINC_21 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_21 -#ifndef CONF_DMAC_BEATSIZE_21 -#define CONF_DMAC_BEATSIZE_21 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_21 -#ifndef CONF_DMAC_BLOCKACT_21 -#define CONF_DMAC_BLOCKACT_21 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_21 -#ifndef CONF_DMAC_EVOSEL_21 -#define CONF_DMAC_EVOSEL_21 0 -#endif -// - -// Channel 22 settings -// dmac_channel_22_settings -#ifndef CONF_DMAC_CHANNEL_22_SETTINGS -#define CONF_DMAC_CHANNEL_22_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 22 is running in standby mode or not -// dmac_runstdby_22 -#ifndef CONF_DMAC_RUNSTDBY_22 -#define CONF_DMAC_RUNSTDBY_22 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_22 -#ifndef CONF_DMAC_TRIGACT_22 -#define CONF_DMAC_TRIGACT_22 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_22 -#ifndef CONF_DMAC_TRIGSRC_22 -#define CONF_DMAC_TRIGSRC_22 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_22 -#ifndef CONF_DMAC_LVL_22 -#define CONF_DMAC_LVL_22 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_22 -#ifndef CONF_DMAC_EVOE_22 -#define CONF_DMAC_EVOE_22 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_22 -#ifndef CONF_DMAC_EVIE_22 -#define CONF_DMAC_EVIE_22 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_22 -#ifndef CONF_DMAC_EVACT_22 -#define CONF_DMAC_EVACT_22 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_22 -#ifndef CONF_DMAC_STEPSIZE_22 -#define CONF_DMAC_STEPSIZE_22 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_22 -#ifndef CONF_DMAC_STEPSEL_22 -#define CONF_DMAC_STEPSEL_22 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_22 -#ifndef CONF_DMAC_SRCINC_22 -#define CONF_DMAC_SRCINC_22 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_22 -#ifndef CONF_DMAC_DSTINC_22 -#define CONF_DMAC_DSTINC_22 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_22 -#ifndef CONF_DMAC_BEATSIZE_22 -#define CONF_DMAC_BEATSIZE_22 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_22 -#ifndef CONF_DMAC_BLOCKACT_22 -#define CONF_DMAC_BLOCKACT_22 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_22 -#ifndef CONF_DMAC_EVOSEL_22 -#define CONF_DMAC_EVOSEL_22 0 -#endif -// - -// Channel 23 settings -// dmac_channel_23_settings -#ifndef CONF_DMAC_CHANNEL_23_SETTINGS -#define CONF_DMAC_CHANNEL_23_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 23 is running in standby mode or not -// dmac_runstdby_23 -#ifndef CONF_DMAC_RUNSTDBY_23 -#define CONF_DMAC_RUNSTDBY_23 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_23 -#ifndef CONF_DMAC_TRIGACT_23 -#define CONF_DMAC_TRIGACT_23 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_23 -#ifndef CONF_DMAC_TRIGSRC_23 -#define CONF_DMAC_TRIGSRC_23 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_23 -#ifndef CONF_DMAC_LVL_23 -#define CONF_DMAC_LVL_23 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_23 -#ifndef CONF_DMAC_EVOE_23 -#define CONF_DMAC_EVOE_23 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_23 -#ifndef CONF_DMAC_EVIE_23 -#define CONF_DMAC_EVIE_23 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_23 -#ifndef CONF_DMAC_EVACT_23 -#define CONF_DMAC_EVACT_23 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_23 -#ifndef CONF_DMAC_STEPSIZE_23 -#define CONF_DMAC_STEPSIZE_23 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_23 -#ifndef CONF_DMAC_STEPSEL_23 -#define CONF_DMAC_STEPSEL_23 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_23 -#ifndef CONF_DMAC_SRCINC_23 -#define CONF_DMAC_SRCINC_23 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_23 -#ifndef CONF_DMAC_DSTINC_23 -#define CONF_DMAC_DSTINC_23 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_23 -#ifndef CONF_DMAC_BEATSIZE_23 -#define CONF_DMAC_BEATSIZE_23 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_23 -#ifndef CONF_DMAC_BLOCKACT_23 -#define CONF_DMAC_BLOCKACT_23 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_23 -#ifndef CONF_DMAC_EVOSEL_23 -#define CONF_DMAC_EVOSEL_23 0 -#endif -// - -// Channel 24 settings -// dmac_channel_24_settings -#ifndef CONF_DMAC_CHANNEL_24_SETTINGS -#define CONF_DMAC_CHANNEL_24_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 24 is running in standby mode or not -// dmac_runstdby_24 -#ifndef CONF_DMAC_RUNSTDBY_24 -#define CONF_DMAC_RUNSTDBY_24 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_24 -#ifndef CONF_DMAC_TRIGACT_24 -#define CONF_DMAC_TRIGACT_24 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_24 -#ifndef CONF_DMAC_TRIGSRC_24 -#define CONF_DMAC_TRIGSRC_24 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_24 -#ifndef CONF_DMAC_LVL_24 -#define CONF_DMAC_LVL_24 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_24 -#ifndef CONF_DMAC_EVOE_24 -#define CONF_DMAC_EVOE_24 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_24 -#ifndef CONF_DMAC_EVIE_24 -#define CONF_DMAC_EVIE_24 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_24 -#ifndef CONF_DMAC_EVACT_24 -#define CONF_DMAC_EVACT_24 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_24 -#ifndef CONF_DMAC_STEPSIZE_24 -#define CONF_DMAC_STEPSIZE_24 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_24 -#ifndef CONF_DMAC_STEPSEL_24 -#define CONF_DMAC_STEPSEL_24 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_24 -#ifndef CONF_DMAC_SRCINC_24 -#define CONF_DMAC_SRCINC_24 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_24 -#ifndef CONF_DMAC_DSTINC_24 -#define CONF_DMAC_DSTINC_24 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_24 -#ifndef CONF_DMAC_BEATSIZE_24 -#define CONF_DMAC_BEATSIZE_24 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_24 -#ifndef CONF_DMAC_BLOCKACT_24 -#define CONF_DMAC_BLOCKACT_24 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_24 -#ifndef CONF_DMAC_EVOSEL_24 -#define CONF_DMAC_EVOSEL_24 0 -#endif -// - -// Channel 25 settings -// dmac_channel_25_settings -#ifndef CONF_DMAC_CHANNEL_25_SETTINGS -#define CONF_DMAC_CHANNEL_25_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 25 is running in standby mode or not -// dmac_runstdby_25 -#ifndef CONF_DMAC_RUNSTDBY_25 -#define CONF_DMAC_RUNSTDBY_25 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_25 -#ifndef CONF_DMAC_TRIGACT_25 -#define CONF_DMAC_TRIGACT_25 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_25 -#ifndef CONF_DMAC_TRIGSRC_25 -#define CONF_DMAC_TRIGSRC_25 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_25 -#ifndef CONF_DMAC_LVL_25 -#define CONF_DMAC_LVL_25 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_25 -#ifndef CONF_DMAC_EVOE_25 -#define CONF_DMAC_EVOE_25 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_25 -#ifndef CONF_DMAC_EVIE_25 -#define CONF_DMAC_EVIE_25 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_25 -#ifndef CONF_DMAC_EVACT_25 -#define CONF_DMAC_EVACT_25 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_25 -#ifndef CONF_DMAC_STEPSIZE_25 -#define CONF_DMAC_STEPSIZE_25 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_25 -#ifndef CONF_DMAC_STEPSEL_25 -#define CONF_DMAC_STEPSEL_25 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_25 -#ifndef CONF_DMAC_SRCINC_25 -#define CONF_DMAC_SRCINC_25 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_25 -#ifndef CONF_DMAC_DSTINC_25 -#define CONF_DMAC_DSTINC_25 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_25 -#ifndef CONF_DMAC_BEATSIZE_25 -#define CONF_DMAC_BEATSIZE_25 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_25 -#ifndef CONF_DMAC_BLOCKACT_25 -#define CONF_DMAC_BLOCKACT_25 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_25 -#ifndef CONF_DMAC_EVOSEL_25 -#define CONF_DMAC_EVOSEL_25 0 -#endif -// - -// Channel 26 settings -// dmac_channel_26_settings -#ifndef CONF_DMAC_CHANNEL_26_SETTINGS -#define CONF_DMAC_CHANNEL_26_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 26 is running in standby mode or not -// dmac_runstdby_26 -#ifndef CONF_DMAC_RUNSTDBY_26 -#define CONF_DMAC_RUNSTDBY_26 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_26 -#ifndef CONF_DMAC_TRIGACT_26 -#define CONF_DMAC_TRIGACT_26 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_26 -#ifndef CONF_DMAC_TRIGSRC_26 -#define CONF_DMAC_TRIGSRC_26 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_26 -#ifndef CONF_DMAC_LVL_26 -#define CONF_DMAC_LVL_26 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_26 -#ifndef CONF_DMAC_EVOE_26 -#define CONF_DMAC_EVOE_26 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_26 -#ifndef CONF_DMAC_EVIE_26 -#define CONF_DMAC_EVIE_26 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_26 -#ifndef CONF_DMAC_EVACT_26 -#define CONF_DMAC_EVACT_26 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_26 -#ifndef CONF_DMAC_STEPSIZE_26 -#define CONF_DMAC_STEPSIZE_26 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_26 -#ifndef CONF_DMAC_STEPSEL_26 -#define CONF_DMAC_STEPSEL_26 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_26 -#ifndef CONF_DMAC_SRCINC_26 -#define CONF_DMAC_SRCINC_26 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_26 -#ifndef CONF_DMAC_DSTINC_26 -#define CONF_DMAC_DSTINC_26 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_26 -#ifndef CONF_DMAC_BEATSIZE_26 -#define CONF_DMAC_BEATSIZE_26 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_26 -#ifndef CONF_DMAC_BLOCKACT_26 -#define CONF_DMAC_BLOCKACT_26 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_26 -#ifndef CONF_DMAC_EVOSEL_26 -#define CONF_DMAC_EVOSEL_26 0 -#endif -// - -// Channel 27 settings -// dmac_channel_27_settings -#ifndef CONF_DMAC_CHANNEL_27_SETTINGS -#define CONF_DMAC_CHANNEL_27_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 27 is running in standby mode or not -// dmac_runstdby_27 -#ifndef CONF_DMAC_RUNSTDBY_27 -#define CONF_DMAC_RUNSTDBY_27 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_27 -#ifndef CONF_DMAC_TRIGACT_27 -#define CONF_DMAC_TRIGACT_27 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_27 -#ifndef CONF_DMAC_TRIGSRC_27 -#define CONF_DMAC_TRIGSRC_27 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_27 -#ifndef CONF_DMAC_LVL_27 -#define CONF_DMAC_LVL_27 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_27 -#ifndef CONF_DMAC_EVOE_27 -#define CONF_DMAC_EVOE_27 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_27 -#ifndef CONF_DMAC_EVIE_27 -#define CONF_DMAC_EVIE_27 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_27 -#ifndef CONF_DMAC_EVACT_27 -#define CONF_DMAC_EVACT_27 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_27 -#ifndef CONF_DMAC_STEPSIZE_27 -#define CONF_DMAC_STEPSIZE_27 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_27 -#ifndef CONF_DMAC_STEPSEL_27 -#define CONF_DMAC_STEPSEL_27 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_27 -#ifndef CONF_DMAC_SRCINC_27 -#define CONF_DMAC_SRCINC_27 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_27 -#ifndef CONF_DMAC_DSTINC_27 -#define CONF_DMAC_DSTINC_27 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_27 -#ifndef CONF_DMAC_BEATSIZE_27 -#define CONF_DMAC_BEATSIZE_27 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_27 -#ifndef CONF_DMAC_BLOCKACT_27 -#define CONF_DMAC_BLOCKACT_27 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_27 -#ifndef CONF_DMAC_EVOSEL_27 -#define CONF_DMAC_EVOSEL_27 0 -#endif -// - -// Channel 28 settings -// dmac_channel_28_settings -#ifndef CONF_DMAC_CHANNEL_28_SETTINGS -#define CONF_DMAC_CHANNEL_28_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 28 is running in standby mode or not -// dmac_runstdby_28 -#ifndef CONF_DMAC_RUNSTDBY_28 -#define CONF_DMAC_RUNSTDBY_28 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_28 -#ifndef CONF_DMAC_TRIGACT_28 -#define CONF_DMAC_TRIGACT_28 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_28 -#ifndef CONF_DMAC_TRIGSRC_28 -#define CONF_DMAC_TRIGSRC_28 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_28 -#ifndef CONF_DMAC_LVL_28 -#define CONF_DMAC_LVL_28 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_28 -#ifndef CONF_DMAC_EVOE_28 -#define CONF_DMAC_EVOE_28 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_28 -#ifndef CONF_DMAC_EVIE_28 -#define CONF_DMAC_EVIE_28 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_28 -#ifndef CONF_DMAC_EVACT_28 -#define CONF_DMAC_EVACT_28 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_28 -#ifndef CONF_DMAC_STEPSIZE_28 -#define CONF_DMAC_STEPSIZE_28 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_28 -#ifndef CONF_DMAC_STEPSEL_28 -#define CONF_DMAC_STEPSEL_28 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_28 -#ifndef CONF_DMAC_SRCINC_28 -#define CONF_DMAC_SRCINC_28 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_28 -#ifndef CONF_DMAC_DSTINC_28 -#define CONF_DMAC_DSTINC_28 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_28 -#ifndef CONF_DMAC_BEATSIZE_28 -#define CONF_DMAC_BEATSIZE_28 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_28 -#ifndef CONF_DMAC_BLOCKACT_28 -#define CONF_DMAC_BLOCKACT_28 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_28 -#ifndef CONF_DMAC_EVOSEL_28 -#define CONF_DMAC_EVOSEL_28 0 -#endif -// - -// Channel 29 settings -// dmac_channel_29_settings -#ifndef CONF_DMAC_CHANNEL_29_SETTINGS -#define CONF_DMAC_CHANNEL_29_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 29 is running in standby mode or not -// dmac_runstdby_29 -#ifndef CONF_DMAC_RUNSTDBY_29 -#define CONF_DMAC_RUNSTDBY_29 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_29 -#ifndef CONF_DMAC_TRIGACT_29 -#define CONF_DMAC_TRIGACT_29 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_29 -#ifndef CONF_DMAC_TRIGSRC_29 -#define CONF_DMAC_TRIGSRC_29 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_29 -#ifndef CONF_DMAC_LVL_29 -#define CONF_DMAC_LVL_29 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_29 -#ifndef CONF_DMAC_EVOE_29 -#define CONF_DMAC_EVOE_29 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_29 -#ifndef CONF_DMAC_EVIE_29 -#define CONF_DMAC_EVIE_29 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_29 -#ifndef CONF_DMAC_EVACT_29 -#define CONF_DMAC_EVACT_29 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_29 -#ifndef CONF_DMAC_STEPSIZE_29 -#define CONF_DMAC_STEPSIZE_29 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_29 -#ifndef CONF_DMAC_STEPSEL_29 -#define CONF_DMAC_STEPSEL_29 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_29 -#ifndef CONF_DMAC_SRCINC_29 -#define CONF_DMAC_SRCINC_29 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_29 -#ifndef CONF_DMAC_DSTINC_29 -#define CONF_DMAC_DSTINC_29 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_29 -#ifndef CONF_DMAC_BEATSIZE_29 -#define CONF_DMAC_BEATSIZE_29 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_29 -#ifndef CONF_DMAC_BLOCKACT_29 -#define CONF_DMAC_BLOCKACT_29 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_29 -#ifndef CONF_DMAC_EVOSEL_29 -#define CONF_DMAC_EVOSEL_29 0 -#endif -// - -// Channel 30 settings -// dmac_channel_30_settings -#ifndef CONF_DMAC_CHANNEL_30_SETTINGS -#define CONF_DMAC_CHANNEL_30_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 30 is running in standby mode or not -// dmac_runstdby_30 -#ifndef CONF_DMAC_RUNSTDBY_30 -#define CONF_DMAC_RUNSTDBY_30 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_30 -#ifndef CONF_DMAC_TRIGACT_30 -#define CONF_DMAC_TRIGACT_30 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_30 -#ifndef CONF_DMAC_TRIGSRC_30 -#define CONF_DMAC_TRIGSRC_30 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_30 -#ifndef CONF_DMAC_LVL_30 -#define CONF_DMAC_LVL_30 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_30 -#ifndef CONF_DMAC_EVOE_30 -#define CONF_DMAC_EVOE_30 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_30 -#ifndef CONF_DMAC_EVIE_30 -#define CONF_DMAC_EVIE_30 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_30 -#ifndef CONF_DMAC_EVACT_30 -#define CONF_DMAC_EVACT_30 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_30 -#ifndef CONF_DMAC_STEPSIZE_30 -#define CONF_DMAC_STEPSIZE_30 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_30 -#ifndef CONF_DMAC_STEPSEL_30 -#define CONF_DMAC_STEPSEL_30 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_30 -#ifndef CONF_DMAC_SRCINC_30 -#define CONF_DMAC_SRCINC_30 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_30 -#ifndef CONF_DMAC_DSTINC_30 -#define CONF_DMAC_DSTINC_30 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_30 -#ifndef CONF_DMAC_BEATSIZE_30 -#define CONF_DMAC_BEATSIZE_30 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_30 -#ifndef CONF_DMAC_BLOCKACT_30 -#define CONF_DMAC_BLOCKACT_30 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_30 -#ifndef CONF_DMAC_EVOSEL_30 -#define CONF_DMAC_EVOSEL_30 0 -#endif -// - -// Channel 31 settings -// dmac_channel_31_settings -#ifndef CONF_DMAC_CHANNEL_31_SETTINGS -#define CONF_DMAC_CHANNEL_31_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 31 is running in standby mode or not -// dmac_runstdby_31 -#ifndef CONF_DMAC_RUNSTDBY_31 -#define CONF_DMAC_RUNSTDBY_31 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_31 -#ifndef CONF_DMAC_TRIGACT_31 -#define CONF_DMAC_TRIGACT_31 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_31 -#ifndef CONF_DMAC_TRIGSRC_31 -#define CONF_DMAC_TRIGSRC_31 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_31 -#ifndef CONF_DMAC_LVL_31 -#define CONF_DMAC_LVL_31 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_31 -#ifndef CONF_DMAC_EVOE_31 -#define CONF_DMAC_EVOE_31 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_31 -#ifndef CONF_DMAC_EVIE_31 -#define CONF_DMAC_EVIE_31 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_31 -#ifndef CONF_DMAC_EVACT_31 -#define CONF_DMAC_EVACT_31 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_31 -#ifndef CONF_DMAC_STEPSIZE_31 -#define CONF_DMAC_STEPSIZE_31 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_31 -#ifndef CONF_DMAC_STEPSEL_31 -#define CONF_DMAC_STEPSEL_31 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_31 -#ifndef CONF_DMAC_SRCINC_31 -#define CONF_DMAC_SRCINC_31 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_31 -#ifndef CONF_DMAC_DSTINC_31 -#define CONF_DMAC_DSTINC_31 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_31 -#ifndef CONF_DMAC_BEATSIZE_31 -#define CONF_DMAC_BEATSIZE_31 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_31 -#ifndef CONF_DMAC_BLOCKACT_31 -#define CONF_DMAC_BLOCKACT_31 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_31 -#ifndef CONF_DMAC_EVOSEL_31 -#define CONF_DMAC_EVOSEL_31 0 -#endif -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_DMAC_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_gclk_config.h b/software/firmware/project_oracle_base/config/hpl_gclk_config.h deleted file mode 100644 index 72f4373..0000000 --- a/software/firmware/project_oracle_base/config/hpl_gclk_config.h +++ /dev/null @@ -1,920 +0,0 @@ -/* Auto-generated config file hpl_gclk_config.h */ -#ifndef HPL_GCLK_CONFIG_H -#define HPL_GCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Generic clock generator 0 configuration -// Indicates whether generic clock 0 configuration is enabled or not -// enable_gclk_gen_0 -#ifndef CONF_GCLK_GENERATOR_0_CONFIG -#define CONF_GCLK_GENERATOR_0_CONFIG 1 -#endif - -// Generic Clock Generator Control -// Generic clock generator 0 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 0 -// gclk_gen_0_oscillator -#ifndef CONF_GCLK_GEN_0_SOURCE -#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_0_runstdby -#ifndef CONF_GCLK_GEN_0_RUNSTDBY -#define CONF_GCLK_GEN_0_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel -#ifndef CONF_GCLK_GEN_0_DIVSEL -#define CONF_GCLK_GEN_0_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_0_oe -#ifndef CONF_GCLK_GEN_0_OE -#define CONF_GCLK_GEN_0_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_0_oov -#ifndef CONF_GCLK_GEN_0_OOV -#define CONF_GCLK_GEN_0_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_0_idc -#ifndef CONF_GCLK_GEN_0_IDC -#define CONF_GCLK_GEN_0_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_0_enable -#ifndef CONF_GCLK_GEN_0_GENEN -#define CONF_GCLK_GEN_0_GENEN 1 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> -// gclk_gen_0_div -#ifndef CONF_GCLK_GEN_0_DIV -#define CONF_GCLK_GEN_0_DIV 1 -#endif -// -// - -// Generic clock generator 1 configuration -// Indicates whether generic clock 1 configuration is enabled or not -// enable_gclk_gen_1 -#ifndef CONF_GCLK_GENERATOR_1_CONFIG -#define CONF_GCLK_GENERATOR_1_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 1 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 1 -// gclk_gen_1_oscillator -#ifndef CONF_GCLK_GEN_1_SOURCE -#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_1_runstdby -#ifndef CONF_GCLK_GEN_1_RUNSTDBY -#define CONF_GCLK_GEN_1_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel -#ifndef CONF_GCLK_GEN_1_DIVSEL -#define CONF_GCLK_GEN_1_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_1_oe -#ifndef CONF_GCLK_GEN_1_OE -#define CONF_GCLK_GEN_1_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_1_oov -#ifndef CONF_GCLK_GEN_1_OOV -#define CONF_GCLK_GEN_1_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_1_idc -#ifndef CONF_GCLK_GEN_1_IDC -#define CONF_GCLK_GEN_1_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_1_enable -#ifndef CONF_GCLK_GEN_1_GENEN -#define CONF_GCLK_GEN_1_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> -// gclk_gen_1_div -#ifndef CONF_GCLK_GEN_1_DIV -#define CONF_GCLK_GEN_1_DIV 1 -#endif -// -// - -// Generic clock generator 2 configuration -// Indicates whether generic clock 2 configuration is enabled or not -// enable_gclk_gen_2 -#ifndef CONF_GCLK_GENERATOR_2_CONFIG -#define CONF_GCLK_GENERATOR_2_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 2 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 2 -// gclk_gen_2_oscillator -#ifndef CONF_GCLK_GEN_2_SOURCE -#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_2_runstdby -#ifndef CONF_GCLK_GEN_2_RUNSTDBY -#define CONF_GCLK_GEN_2_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel -#ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 1 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_2_oe -#ifndef CONF_GCLK_GEN_2_OE -#define CONF_GCLK_GEN_2_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_2_oov -#ifndef CONF_GCLK_GEN_2_OOV -#define CONF_GCLK_GEN_2_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_2_idc -#ifndef CONF_GCLK_GEN_2_IDC -#define CONF_GCLK_GEN_2_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_2_enable -#ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> -// gclk_gen_2_div -#ifndef CONF_GCLK_GEN_2_DIV -#define CONF_GCLK_GEN_2_DIV 1 -#endif -// -// - -// Generic clock generator 3 configuration -// Indicates whether generic clock 3 configuration is enabled or not -// enable_gclk_gen_3 -#ifndef CONF_GCLK_GENERATOR_3_CONFIG -#define CONF_GCLK_GENERATOR_3_CONFIG 1 -#endif - -// Generic Clock Generator Control -// Generic clock generator 3 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 3 -// gclk_gen_3_oscillator -#ifndef CONF_GCLK_GEN_3_SOURCE -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_3_runstdby -#ifndef CONF_GCLK_GEN_3_RUNSTDBY -#define CONF_GCLK_GEN_3_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel -#ifndef CONF_GCLK_GEN_3_DIVSEL -#define CONF_GCLK_GEN_3_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_3_oe -#ifndef CONF_GCLK_GEN_3_OE -#define CONF_GCLK_GEN_3_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_3_oov -#ifndef CONF_GCLK_GEN_3_OOV -#define CONF_GCLK_GEN_3_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_3_idc -#ifndef CONF_GCLK_GEN_3_IDC -#define CONF_GCLK_GEN_3_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_3_enable -#ifndef CONF_GCLK_GEN_3_GENEN -#define CONF_GCLK_GEN_3_GENEN 1 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> -// gclk_gen_3_div -#ifndef CONF_GCLK_GEN_3_DIV -#define CONF_GCLK_GEN_3_DIV 1 -#endif -// -// - -// Generic clock generator 4 configuration -// Indicates whether generic clock 4 configuration is enabled or not -// enable_gclk_gen_4 -#ifndef CONF_GCLK_GENERATOR_4_CONFIG -#define CONF_GCLK_GENERATOR_4_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 4 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 4 -// gclk_gen_4_oscillator -#ifndef CONF_GCLK_GEN_4_SOURCE -#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_4_runstdby -#ifndef CONF_GCLK_GEN_4_RUNSTDBY -#define CONF_GCLK_GEN_4_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel -#ifndef CONF_GCLK_GEN_4_DIVSEL -#define CONF_GCLK_GEN_4_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_4_oe -#ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_4_oov -#ifndef CONF_GCLK_GEN_4_OOV -#define CONF_GCLK_GEN_4_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_4_idc -#ifndef CONF_GCLK_GEN_4_IDC -#define CONF_GCLK_GEN_4_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_4_enable -#ifndef CONF_GCLK_GEN_4_GENEN -#define CONF_GCLK_GEN_4_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> -// gclk_gen_4_div -#ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 -#endif -// -// - -// Generic clock generator 5 configuration -// Indicates whether generic clock 5 configuration is enabled or not -// enable_gclk_gen_5 -#ifndef CONF_GCLK_GENERATOR_5_CONFIG -#define CONF_GCLK_GENERATOR_5_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 5 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 5 -// gclk_gen_5_oscillator -#ifndef CONF_GCLK_GEN_5_SOURCE -#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_5_runstdby -#ifndef CONF_GCLK_GEN_5_RUNSTDBY -#define CONF_GCLK_GEN_5_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_5_div_sel -#ifndef CONF_GCLK_GEN_5_DIVSEL -#define CONF_GCLK_GEN_5_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_5_oe -#ifndef CONF_GCLK_GEN_5_OE -#define CONF_GCLK_GEN_5_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_5_oov -#ifndef CONF_GCLK_GEN_5_OOV -#define CONF_GCLK_GEN_5_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_5_idc -#ifndef CONF_GCLK_GEN_5_IDC -#define CONF_GCLK_GEN_5_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_5_enable -#ifndef CONF_GCLK_GEN_5_GENEN -#define CONF_GCLK_GEN_5_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 5 division <0x0000-0xFFFF> -// gclk_gen_5_div -#ifndef CONF_GCLK_GEN_5_DIV -#define CONF_GCLK_GEN_5_DIV 1 -#endif -// -// - -// Generic clock generator 6 configuration -// Indicates whether generic clock 6 configuration is enabled or not -// enable_gclk_gen_6 -#ifndef CONF_GCLK_GENERATOR_6_CONFIG -#define CONF_GCLK_GENERATOR_6_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 6 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 6 -// gclk_gen_6_oscillator -#ifndef CONF_GCLK_GEN_6_SOURCE -#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_6_runstdby -#ifndef CONF_GCLK_GEN_6_RUNSTDBY -#define CONF_GCLK_GEN_6_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_6_div_sel -#ifndef CONF_GCLK_GEN_6_DIVSEL -#define CONF_GCLK_GEN_6_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_6_oe -#ifndef CONF_GCLK_GEN_6_OE -#define CONF_GCLK_GEN_6_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_6_oov -#ifndef CONF_GCLK_GEN_6_OOV -#define CONF_GCLK_GEN_6_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_6_idc -#ifndef CONF_GCLK_GEN_6_IDC -#define CONF_GCLK_GEN_6_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_6_enable -#ifndef CONF_GCLK_GEN_6_GENEN -#define CONF_GCLK_GEN_6_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 6 division <0x0000-0xFFFF> -// gclk_gen_6_div -#ifndef CONF_GCLK_GEN_6_DIV -#define CONF_GCLK_GEN_6_DIV 1 -#endif -// -// - -// Generic clock generator 7 configuration -// Indicates whether generic clock 7 configuration is enabled or not -// enable_gclk_gen_7 -#ifndef CONF_GCLK_GENERATOR_7_CONFIG -#define CONF_GCLK_GENERATOR_7_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 7 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 7 -// gclk_gen_7_oscillator -#ifndef CONF_GCLK_GEN_7_SOURCE -#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_7_runstdby -#ifndef CONF_GCLK_GEN_7_RUNSTDBY -#define CONF_GCLK_GEN_7_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_7_div_sel -#ifndef CONF_GCLK_GEN_7_DIVSEL -#define CONF_GCLK_GEN_7_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_7_oe -#ifndef CONF_GCLK_GEN_7_OE -#define CONF_GCLK_GEN_7_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_7_oov -#ifndef CONF_GCLK_GEN_7_OOV -#define CONF_GCLK_GEN_7_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_7_idc -#ifndef CONF_GCLK_GEN_7_IDC -#define CONF_GCLK_GEN_7_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_7_enable -#ifndef CONF_GCLK_GEN_7_GENEN -#define CONF_GCLK_GEN_7_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 7 division <0x0000-0xFFFF> -// gclk_gen_7_div -#ifndef CONF_GCLK_GEN_7_DIV -#define CONF_GCLK_GEN_7_DIV 1 -#endif -// -// - -// Generic clock generator 8 configuration -// Indicates whether generic clock 8 configuration is enabled or not -// enable_gclk_gen_8 -#ifndef CONF_GCLK_GENERATOR_8_CONFIG -#define CONF_GCLK_GENERATOR_8_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 8 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 8 -// gclk_gen_8_oscillator -#ifndef CONF_GCLK_GEN_8_SOURCE -#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_8_runstdby -#ifndef CONF_GCLK_GEN_8_RUNSTDBY -#define CONF_GCLK_GEN_8_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_8_div_sel -#ifndef CONF_GCLK_GEN_8_DIVSEL -#define CONF_GCLK_GEN_8_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_8_oe -#ifndef CONF_GCLK_GEN_8_OE -#define CONF_GCLK_GEN_8_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_8_oov -#ifndef CONF_GCLK_GEN_8_OOV -#define CONF_GCLK_GEN_8_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_8_idc -#ifndef CONF_GCLK_GEN_8_IDC -#define CONF_GCLK_GEN_8_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_8_enable -#ifndef CONF_GCLK_GEN_8_GENEN -#define CONF_GCLK_GEN_8_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 8 division <0x0000-0xFFFF> -// gclk_gen_8_div -#ifndef CONF_GCLK_GEN_8_DIV -#define CONF_GCLK_GEN_8_DIV 1 -#endif -// -// - -// Generic clock generator 9 configuration -// Indicates whether generic clock 9 configuration is enabled or not -// enable_gclk_gen_9 -#ifndef CONF_GCLK_GENERATOR_9_CONFIG -#define CONF_GCLK_GENERATOR_9_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 9 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 9 -// gclk_gen_9_oscillator -#ifndef CONF_GCLK_GEN_9_SOURCE -#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_9_runstdby -#ifndef CONF_GCLK_GEN_9_RUNSTDBY -#define CONF_GCLK_GEN_9_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_9_div_sel -#ifndef CONF_GCLK_GEN_9_DIVSEL -#define CONF_GCLK_GEN_9_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_9_oe -#ifndef CONF_GCLK_GEN_9_OE -#define CONF_GCLK_GEN_9_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_9_oov -#ifndef CONF_GCLK_GEN_9_OOV -#define CONF_GCLK_GEN_9_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_9_idc -#ifndef CONF_GCLK_GEN_9_IDC -#define CONF_GCLK_GEN_9_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_9_enable -#ifndef CONF_GCLK_GEN_9_GENEN -#define CONF_GCLK_GEN_9_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 9 division <0x0000-0xFFFF> -// gclk_gen_9_div -#ifndef CONF_GCLK_GEN_9_DIV -#define CONF_GCLK_GEN_9_DIV 1 -#endif -// -// - -// Generic clock generator 10 configuration -// Indicates whether generic clock 10 configuration is enabled or not -// enable_gclk_gen_10 -#ifndef CONF_GCLK_GENERATOR_10_CONFIG -#define CONF_GCLK_GENERATOR_10_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 10 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 10 -// gclk_gen_10_oscillator -#ifndef CONF_GCLK_GEN_10_SOURCE -#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_10_runstdby -#ifndef CONF_GCLK_GEN_10_RUNSTDBY -#define CONF_GCLK_GEN_10_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_10_div_sel -#ifndef CONF_GCLK_GEN_10_DIVSEL -#define CONF_GCLK_GEN_10_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_10_oe -#ifndef CONF_GCLK_GEN_10_OE -#define CONF_GCLK_GEN_10_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_10_oov -#ifndef CONF_GCLK_GEN_10_OOV -#define CONF_GCLK_GEN_10_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_10_idc -#ifndef CONF_GCLK_GEN_10_IDC -#define CONF_GCLK_GEN_10_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_10_enable -#ifndef CONF_GCLK_GEN_10_GENEN -#define CONF_GCLK_GEN_10_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 10 division <0x0000-0xFFFF> -// gclk_gen_10_div -#ifndef CONF_GCLK_GEN_10_DIV -#define CONF_GCLK_GEN_10_DIV 1 -#endif -// -// - -// Generic clock generator 11 configuration -// Indicates whether generic clock 11 configuration is enabled or not -// enable_gclk_gen_11 -#ifndef CONF_GCLK_GENERATOR_11_CONFIG -#define CONF_GCLK_GENERATOR_11_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 11 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 11 -// gclk_gen_11_oscillator -#ifndef CONF_GCLK_GEN_11_SOURCE -#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_11_runstdby -#ifndef CONF_GCLK_GEN_11_RUNSTDBY -#define CONF_GCLK_GEN_11_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_11_div_sel -#ifndef CONF_GCLK_GEN_11_DIVSEL -#define CONF_GCLK_GEN_11_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_11_oe -#ifndef CONF_GCLK_GEN_11_OE -#define CONF_GCLK_GEN_11_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_11_oov -#ifndef CONF_GCLK_GEN_11_OOV -#define CONF_GCLK_GEN_11_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_11_idc -#ifndef CONF_GCLK_GEN_11_IDC -#define CONF_GCLK_GEN_11_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_11_enable -#ifndef CONF_GCLK_GEN_11_GENEN -#define CONF_GCLK_GEN_11_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 11 division <0x0000-0xFFFF> -// gclk_gen_11_div -#ifndef CONF_GCLK_GEN_11_DIV -#define CONF_GCLK_GEN_11_DIV 1 -#endif -// -// - -// <<< end of configuration section >>> - -#endif // HPL_GCLK_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_mclk_config.h b/software/firmware/project_oracle_base/config/hpl_mclk_config.h deleted file mode 100644 index 4089d83..0000000 --- a/software/firmware/project_oracle_base/config/hpl_mclk_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/* Auto-generated config file hpl_mclk_config.h */ -#ifndef HPL_MCLK_CONFIG_H -#define HPL_MCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// System Configuration -// Indicates whether configuration for system is enabled or not -// enable_cpu_clock -#ifndef CONF_SYSTEM_CONFIG -#define CONF_SYSTEM_CONFIG 1 -#endif - -// Basic settings -// CPU Clock source -// Generic clock generator 0 -// This defines the clock source for the CPU -// cpu_clock_source -#ifndef CONF_CPU_SRC -#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// CPU Clock Division Factor -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// Prescalar for CPU clock -// cpu_div -#ifndef CONF_MCLK_CPUDIV -#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val -#endif -// Low Power Clock Division -// Divide by 1 -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 32 -// Divide by 64 -// Divide by 128 -// mclk_arch_lpdiv -#ifndef CONF_MCLK_LPDIV -#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val -#endif - -// Backup Clock Division -// Divide by 1 -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 32 -// Divide by 64 -// Divide by 128 -// mclk_arch_bupdiv -#ifndef CONF_MCLK_BUPDIV -#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val -#endif -// High-Speed Clock Division -// Divide by 1 -// mclk_arch_hsdiv -#ifndef CONF_MCLK_HSDIV -#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val -#endif -// - -// NVM Settings -// NVM Wait States -// These bits select the number of wait states for a read operation. -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// nvm_wait_states -#ifndef CONF_NVM_WAIT_STATE -#define CONF_NVM_WAIT_STATE 5 -#endif - -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_MCLK_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_osc32kctrl_config.h b/software/firmware/project_oracle_base/config/hpl_osc32kctrl_config.h deleted file mode 100644 index 1126a13..0000000 --- a/software/firmware/project_oracle_base/config/hpl_osc32kctrl_config.h +++ /dev/null @@ -1,165 +0,0 @@ -/* Auto-generated config file hpl_osc32kctrl_config.h */ -#ifndef HPL_OSC32KCTRL_CONFIG_H -#define HPL_OSC32KCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// RTC Source configuration -// enable_rtc_source -#ifndef CONF_RTCCTRL_CONFIG -#define CONF_RTCCTRL_CONFIG 0 -#endif - -// RTC source control -// RTC Clock Source Selection -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// This defines the clock source for RTC -// rtc_source_oscillator -#ifndef CONF_RTCCTRL_SRC -#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K -#endif - -// Use 1 kHz output -// rtc_1khz_selection -#ifndef CONF_RTCCTRL_1KHZ - -#define CONF_RTCCTRL_1KHZ 0 - -#endif - -#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) -#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) -#else -#error unexpected CONF_RTCCTRL_SRC -#endif - -// -// - -// 32kHz External Crystal Oscillator Configuration -// Indicates whether configuration for External 32K Osc is enabled or not -// enable_xosc32k -#ifndef CONF_XOSC32K_CONFIG -#define CONF_XOSC32K_CONFIG 1 -#endif - -// 32kHz External Crystal Oscillator Control -// Oscillator enable -// Indicates whether 32kHz External Crystal Oscillator is enabled or not -// xosc32k_arch_enable -#ifndef CONF_XOSC32K_ENABLE -#define CONF_XOSC32K_ENABLE 1 -#endif - -// Start-Up Time -// <0x0=>62592us -// <0x1=>125092us -// <0x2=>500092us -// <0x3=>1000092us -// <0x4=>2000092us -// <0x5=>4000092us -// <0x6=>8000092us -// xosc32k_arch_startup -#ifndef CONF_XOSC32K_STARTUP -#define CONF_XOSC32K_STARTUP 0x3 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc32k_arch_ondemand -#ifndef CONF_XOSC32K_ONDEMAND -#define CONF_XOSC32K_ONDEMAND 1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc32k_arch_runstdby -#ifndef CONF_XOSC32K_RUNSTDBY -#define CONF_XOSC32K_RUNSTDBY 0 -#endif - -// 1kHz Output Enable -// Indicates whether 1kHz Output is enabled or not -// xosc32k_arch_en1k -#ifndef CONF_XOSC32K_EN1K -#define CONF_XOSC32K_EN1K 0 -#endif - -// 32kHz Output Enable -// Indicates whether 32kHz Output is enabled or not -// xosc32k_arch_en32k -#ifndef CONF_XOSC32K_EN32K -#define CONF_XOSC32K_EN32K 1 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc32k_arch_swben -#ifndef CONF_XOSC32K_SWBEN -#define CONF_XOSC32K_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc32k_arch_cfden -#ifndef CONF_XOSC32K_CFDEN -#define CONF_XOSC32K_CFDEN 0 -#endif - -// Clock Failure Detector Event Out -// Indicates whether Clock Failure Detector Event Out is enabled or not -// xosc32k_arch_cfdeo -#ifndef CONF_XOSC32K_CFDEO -#define CONF_XOSC32K_CFDEO 0 -#endif - -// Crystal connected to XIN32/XOUT32 Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc32k_arch_xtalen -#ifndef CONF_XOSC32K_XTALEN -#define CONF_XOSC32K_XTALEN 1 -#endif - -// Control Gain Mode -// <0x0=>Low Power mode -// <0x1=>Standard mode -// <0x2=>High Speed mode -// xosc32k_arch_cgm -#ifndef CONF_XOSC32K_CGM -#define CONF_XOSC32K_CGM 0x1 -#endif - -// -// - -// 32kHz Ultra Low Power Internal Oscillator Configuration -// Indicates whether configuration for OSCULP32K is enabled or not -// enable_osculp32k -#ifndef CONF_OSCULP32K_CONFIG -#define CONF_OSCULP32K_CONFIG 1 -#endif - -// 32kHz Ultra Low Power Internal Oscillator Control - -// Oscillator Calibration Control -// Indicates whether Oscillator Calibration is enabled or not -// osculp32k_calib_enable -#ifndef CONF_OSCULP32K_CALIB_ENABLE -#define CONF_OSCULP32K_CALIB_ENABLE 0 -#endif - -// Oscillator Calibration <0x0-0x3F> -// osculp32k_calib -#ifndef CONF_OSCULP32K_CALIB -#define CONF_OSCULP32K_CALIB 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_oscctrl_config.h b/software/firmware/project_oracle_base/config/hpl_oscctrl_config.h deleted file mode 100644 index 2404d96..0000000 --- a/software/firmware/project_oracle_base/config/hpl_oscctrl_config.h +++ /dev/null @@ -1,640 +0,0 @@ -/* Auto-generated config file hpl_oscctrl_config.h */ -#ifndef HPL_OSCCTRL_CONFIG_H -#define HPL_OSCCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for XOSC0 is enabled or not -// enable_xosc0 -#ifndef CONF_XOSC0_CONFIG -#define CONF_XOSC0_CONFIG 0 -#endif - -// Frequency <8000000-48000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc0_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC0_FREQUENCY 12000000 -#endif - -// External Multipurpose Crystal Oscillator Control -// Oscillator enable -// Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// xosc0_arch_enable -#ifndef CONF_XOSC0_ENABLE -#define CONF_XOSC0_ENABLE 0 -#endif - -// Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// xosc0_arch_startup -#ifndef CONF_XOSC0_STARTUP -#define CONF_XOSC0_STARTUP 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc0_arch_swben -#ifndef CONF_XOSC0_SWBEN -#define CONF_XOSC0_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc0_arch_cfden -#ifndef CONF_XOSC0_CFDEN -#define CONF_XOSC0_CFDEN 0 -#endif - -// Automatic Loop Control Enable -// Indicates whether Automatic Loop Control is enabled or not -// xosc0_arch_enalc -#ifndef CONF_XOSC0_ENALC -#define CONF_XOSC0_ENALC 0 -#endif - -// Low Buffer Gain Enable -// Indicates whether Low Buffer Gain is enabled or not -// xosc0_arch_lowbufgain -#ifndef CONF_XOSC0_LOWBUFGAIN -#define CONF_XOSC0_LOWBUFGAIN 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc0_arch_ondemand -#ifndef CONF_XOSC0_ONDEMAND -#define CONF_XOSC0_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc0_arch_runstdby -#ifndef CONF_XOSC0_RUNSTDBY -#define CONF_XOSC0_RUNSTDBY 0 -#endif - -// Crystal connected to XIN/XOUT Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc0_arch_xtalen -#ifndef CONF_XOSC0_XTALEN -#define CONF_XOSC0_XTALEN 0 -#endif -// -// - -#if CONF_XOSC0_FREQUENCY >= 32000000 -#define CONF_XOSC0_CFDPRESC 0x0 -#define CONF_XOSC0_IMULT 0x7 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 24000000 -#define CONF_XOSC0_CFDPRESC 0x1 -#define CONF_XOSC0_IMULT 0x6 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 16000000 -#define CONF_XOSC0_CFDPRESC 0x2 -#define CONF_XOSC0_IMULT 0x5 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 8000000 -#define CONF_XOSC0_CFDPRESC 0x3 -#define CONF_XOSC0_IMULT 0x4 -#define CONF_XOSC0_IPTAT 0x3 -#endif - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for XOSC1 is enabled or not -// enable_xosc1 -#ifndef CONF_XOSC1_CONFIG -#define CONF_XOSC1_CONFIG 0 -#endif - -// Frequency <8000000-48000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc1_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC1_FREQUENCY 12000000 -#endif - -// External Multipurpose Crystal Oscillator Control -// Oscillator enable -// Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// xosc1_arch_enable -#ifndef CONF_XOSC1_ENABLE -#define CONF_XOSC1_ENABLE 0 -#endif - -// Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// xosc1_arch_startup -#ifndef CONF_XOSC1_STARTUP -#define CONF_XOSC1_STARTUP 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc1_arch_swben -#ifndef CONF_XOSC1_SWBEN -#define CONF_XOSC1_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc1_arch_cfden -#ifndef CONF_XOSC1_CFDEN -#define CONF_XOSC1_CFDEN 0 -#endif - -// Automatic Loop Control Enable -// Indicates whether Automatic Loop Control is enabled or not -// xosc1_arch_enalc -#ifndef CONF_XOSC1_ENALC -#define CONF_XOSC1_ENALC 0 -#endif - -// Low Buffer Gain Enable -// Indicates whether Low Buffer Gain is enabled or not -// xosc1_arch_lowbufgain -#ifndef CONF_XOSC1_LOWBUFGAIN -#define CONF_XOSC1_LOWBUFGAIN 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc1_arch_ondemand -#ifndef CONF_XOSC1_ONDEMAND -#define CONF_XOSC1_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc1_arch_runstdby -#ifndef CONF_XOSC1_RUNSTDBY -#define CONF_XOSC1_RUNSTDBY 0 -#endif - -// Crystal connected to XIN/XOUT Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc1_arch_xtalen -#ifndef CONF_XOSC1_XTALEN -#define CONF_XOSC1_XTALEN 1 -#endif -// -// - -#if CONF_XOSC1_FREQUENCY >= 32000000 -#define CONF_XOSC1_CFDPRESC 0x0 -#define CONF_XOSC1_IMULT 0x7 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 24000000 -#define CONF_XOSC1_CFDPRESC 0x1 -#define CONF_XOSC1_IMULT 0x6 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 16000000 -#define CONF_XOSC1_CFDPRESC 0x2 -#define CONF_XOSC1_IMULT 0x5 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 8000000 -#define CONF_XOSC1_CFDPRESC 0x3 -#define CONF_XOSC1_IMULT 0x4 -#define CONF_XOSC1_IPTAT 0x3 -#endif - -// DFLL Configuration -// Indicates whether configuration for DFLL is enabled or not -// enable_dfll -#ifndef CONF_DFLL_CONFIG -#define CONF_DFLL_CONFIG 0 -#endif - -// Reference Clock Source -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source -// dfll_ref_clock -#ifndef CONF_DFLL_GCLK -#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -// Digital Frequency Locked Loop Control -// DFLL Enable -// Indicates whether DFLL is enabled or not -// dfll_arch_enable -#ifndef CONF_DFLL_ENABLE -#define CONF_DFLL_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// dfll_arch_ondemand -#ifndef CONF_DFLL_ONDEMAND -#define CONF_DFLL_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// dfll_arch_runstdby -#ifndef CONF_DFLL_RUNSTDBY -#define CONF_DFLL_RUNSTDBY 0 -#endif - -// USB Clock Recovery Mode -// Indicates whether USB Clock Recovery Mode is enabled or not -// dfll_arch_usbcrm -#ifndef CONF_DFLL_USBCRM -#define CONF_DFLL_USBCRM 0 -#endif - -// Wait Lock -// Indicates whether Wait Lock is enabled or not -// dfll_arch_waitlock -#ifndef CONF_DFLL_WAITLOCK -#define CONF_DFLL_WAITLOCK 1 -#endif - -// Bypass Coarse Lock -// Indicates whether Bypass Coarse Lock is enabled or not -// dfll_arch_bplckc -#ifndef CONF_DFLL_BPLCKC -#define CONF_DFLL_BPLCKC 0 -#endif - -// Quick Lock Disable -// Indicates whether Quick Lock Disable is enabled or not -// dfll_arch_qldis -#ifndef CONF_DFLL_QLDIS -#define CONF_DFLL_QLDIS 0 -#endif - -// Chill Cycle Disable -// Indicates whether Chill Cycle Disable is enabled or not -// dfll_arch_ccdis -#ifndef CONF_DFLL_CCDIS -#define CONF_DFLL_CCDIS 0 -#endif - -// Lose Lock After Wake -// Indicates whether Lose Lock After Wake is enabled or not -// dfll_arch_llaw -#ifndef CONF_DFLL_LLAW -#define CONF_DFLL_LLAW 0 -#endif - -// Stable DFLL Frequency -// Indicates whether Stable DFLL Frequency is enabled or not -// dfll_arch_stable -#ifndef CONF_DFLL_STABLE -#define CONF_DFLL_STABLE 0 -#endif - -// Operating Mode Selection -// <0=>Open Loop Mode -// <1=>Closed Loop Mode -// dfll_mode -#ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE 0x0 -#endif - -// Coarse Maximum Step <0x0-0x1F> -// dfll_arch_cstep -#ifndef CONF_DFLL_CSTEP -#define CONF_DFLL_CSTEP 0x1 -#endif - -// Fine Maximum Step <0x0-0xFF> -// dfll_arch_fstep -#ifndef CONF_DFLL_FSTEP -#define CONF_DFLL_FSTEP 0x1 -#endif - -// DFLL Multiply Factor <0x0-0xFFFF> -// dfll_mul -#ifndef CONF_DFLL_MUL -#define CONF_DFLL_MUL 0x0 -#endif - -// DFLL Calibration Overwrite -// Indicates whether Overwrite Calibration value of DFLL -// dfll_arch_calibration -#ifndef CONF_DFLL_OVERWRITE_CALIBRATION -#define CONF_DFLL_OVERWRITE_CALIBRATION 0 -#endif - -// Coarse Value <0x0-0x3F> -// dfll_arch_coarse -#ifndef CONF_DFLL_COARSE -#define CONF_DFLL_COARSE (0x1f / 4) -#endif - -// Fine Value <0x0-0xFF> -// dfll_arch_fine -#ifndef CONF_DFLL_FINE -#define CONF_DFLL_FINE (0x80) -#endif - -// - -// - -// - -// FDPLL0 Configuration -// Indicates whether configuration for FDPLL0 is enabled or not -// enable_fdpll0 -#ifndef CONF_FDPLL0_CONFIG -#define CONF_FDPLL0_CONFIG 1 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source. -// fdpll0_ref_clock -#ifndef CONF_FDPLL0_GCLK -#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Digital Phase Locked Loop Control -// Enable -// Indicates whether Digital Phase Locked Loop is enabled or not -// fdpll0_arch_enable -#ifndef CONF_FDPLL0_ENABLE -#define CONF_FDPLL0_ENABLE 1 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// fdpll0_arch_ondemand -#ifndef CONF_FDPLL0_ONDEMAND -#define CONF_FDPLL0_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// fdpll0_arch_runstdby -#ifndef CONF_FDPLL0_RUNSTDBY -#define CONF_FDPLL0_RUNSTDBY 0 -#endif - -// Loop Divider Ratio Fractional Part <0x0-0x1F> -// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll0_ldrfrac -#ifndef CONF_FDPLL0_LDRFRAC -#define CONF_FDPLL0_LDRFRAC 0x1 -#endif - -// Loop Divider Ratio Integer Part <0x0-0x1FFF> -// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll0_ldr -#ifndef CONF_FDPLL0_LDR -#define CONF_FDPLL0_LDR 0xe4d -#endif - -// Clock Divider <0x0-0x7FF> -// This Clock divider is only for XOSC clock input to DPLL -// fdpll0_clock_div -#ifndef CONF_FDPLL0_DIV -#define CONF_FDPLL0_DIV 0x0 -#endif - -// DCO Filter Enable -// Indicates whether DCO Filter Enable is enabled or not -// fdpll0_arch_dcoen -#ifndef CONF_FDPLL0_DCOEN -#define CONF_FDPLL0_DCOEN 0 -#endif - -// Sigma-Delta DCO Filter Selection <0x0-0x7> -// fdpll0_clock_dcofilter -#ifndef CONF_FDPLL0_DCOFILTER -#define CONF_FDPLL0_DCOFILTER 0x0 -#endif - -// Lock Bypass -// Indicates whether Lock Bypass is enabled or not -// fdpll0_arch_lbypass -#ifndef CONF_FDPLL0_LBYPASS -#define CONF_FDPLL0_LBYPASS 1 -#endif - -// Lock Time -// <0x0=>No time-out, automatic lock -// <0x4=>The Time-out if no lock within 800 us -// <0x5=>The Time-out if no lock within 900 us -// <0x6=>The Time-out if no lock within 1 ms -// <0x7=>The Time-out if no lock within 11 ms -// fdpll0_arch_ltime -#ifndef CONF_FDPLL0_LTIME -#define CONF_FDPLL0_LTIME 0x0 -#endif - -// Reference Clock Selection -// <0x0=>GCLK clock reference -// <0x1=>XOSC32K clock reference -// <0x2=>XOSC0 clock reference -// <0x3=>XOSC1 clock reference -// fdpll0_arch_refclk -#ifndef CONF_FDPLL0_REFCLK -#define CONF_FDPLL0_REFCLK 0x1 -#endif - -// Wake Up Fast -// Indicates whether Wake Up Fast is enabled or not -// fdpll0_arch_wuf -#ifndef CONF_FDPLL0_WUF -#define CONF_FDPLL0_WUF 0 -#endif - -// Proportional Integral Filter Selection <0x0-0xF> -// fdpll0_arch_filter -#ifndef CONF_FDPLL0_FILTER -#define CONF_FDPLL0_FILTER 0x0 -#endif - -// -// -// FDPLL1 Configuration -// Indicates whether configuration for FDPLL1 is enabled or not -// enable_fdpll1 -#ifndef CONF_FDPLL1_CONFIG -#define CONF_FDPLL1_CONFIG 0 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source. -// fdpll1_ref_clock -#ifndef CONF_FDPLL1_GCLK -#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Digital Phase Locked Loop Control -// Enable -// Indicates whether Digital Phase Locked Loop is enabled or not -// fdpll1_arch_enable -#ifndef CONF_FDPLL1_ENABLE -#define CONF_FDPLL1_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// fdpll1_arch_ondemand -#ifndef CONF_FDPLL1_ONDEMAND -#define CONF_FDPLL1_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// fdpll1_arch_runstdby -#ifndef CONF_FDPLL1_RUNSTDBY -#define CONF_FDPLL1_RUNSTDBY 0 -#endif - -// Loop Divider Ratio Fractional Part <0x0-0x1F> -// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll1_ldrfrac -#ifndef CONF_FDPLL1_LDRFRAC -#define CONF_FDPLL1_LDRFRAC 0xd -#endif - -// Loop Divider Ratio Integer Part <0x0-0x1FFF> -// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll1_ldr -#ifndef CONF_FDPLL1_LDR -#define CONF_FDPLL1_LDR 0x5b7 -#endif - -// Clock Divider <0x0-0x7FF> -// This Clock divider is only for XOSC clock input to DPLL -// fdpll1_clock_div -#ifndef CONF_FDPLL1_DIV -#define CONF_FDPLL1_DIV 0x0 -#endif - -// DCO Filter Enable -// Indicates whether DCO Filter Enable is enabled or not -// fdpll1_arch_dcoen -#ifndef CONF_FDPLL1_DCOEN -#define CONF_FDPLL1_DCOEN 0 -#endif - -// Sigma-Delta DCO Filter Selection <0x0-0x7> -// fdpll1_clock_dcofilter -#ifndef CONF_FDPLL1_DCOFILTER -#define CONF_FDPLL1_DCOFILTER 0x0 -#endif - -// Lock Bypass -// Indicates whether Lock Bypass is enabled or not -// fdpll1_arch_lbypass -#ifndef CONF_FDPLL1_LBYPASS -#define CONF_FDPLL1_LBYPASS 0 -#endif - -// Lock Time -// <0x0=>No time-out, automatic lock -// <0x4=>The Time-out if no lock within 800 us -// <0x5=>The Time-out if no lock within 900 us -// <0x6=>The Time-out if no lock within 1 ms -// <0x7=>The Time-out if no lock within 11 ms -// fdpll1_arch_ltime -#ifndef CONF_FDPLL1_LTIME -#define CONF_FDPLL1_LTIME 0x0 -#endif - -// Reference Clock Selection -// <0x0=>GCLK clock reference -// <0x1=>XOSC32K clock reference -// <0x2=>XOSC0 clock reference -// <0x3=>XOSC1 clock reference -// fdpll1_arch_refclk -#ifndef CONF_FDPLL1_REFCLK -#define CONF_FDPLL1_REFCLK 0x1 -#endif - -// Wake Up Fast -// Indicates whether Wake Up Fast is enabled or not -// fdpll1_arch_wuf -#ifndef CONF_FDPLL1_WUF -#define CONF_FDPLL1_WUF 0 -#endif - -// Proportional Integral Filter Selection <0x0-0xF> -// fdpll1_arch_filter -#ifndef CONF_FDPLL1_FILTER -#define CONF_FDPLL1_FILTER 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSCCTRL_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_port_config.h b/software/firmware/project_oracle_base/config/hpl_port_config.h deleted file mode 100644 index b5315f0..0000000 --- a/software/firmware/project_oracle_base/config/hpl_port_config.h +++ /dev/null @@ -1,522 +0,0 @@ -/* Auto-generated config file hpl_port_config.h */ -#ifndef HPL_PORT_CONFIG_H -#define HPL_PORT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// PORT Input Event 0 configuration -// enable_port_input_event_0 -#ifndef CONF_PORT_EVCTRL_PORT_0 -#define CONF_PORT_EVCTRL_PORT_0 0 -#endif - -// PORT Input Event 0 configuration on PORT A - -// PORTA Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled -// porta_input_event_enable_0 -#ifndef CONF_PORTA_EVCTRL_PORTEI_0 -#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTA Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_0 -#ifndef CONF_PORTA_EVCTRL_PID_0 -#define CONF_PORTA_EVCTRL_PID_0 0x0 -#endif - -// PORTA Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 0 -// porta_event_action_0 -#ifndef CONF_PORTA_EVCTRL_EVACT_0 -#define CONF_PORTA_EVCTRL_EVACT_0 0 -#endif - -// -// PORT Input Event 0 configuration on PORT B - -// PORTB Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled -// portb_input_event_enable_0 -#ifndef CONF_PORTB_EVCTRL_PORTEI_0 -#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTB Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_0 -#ifndef CONF_PORTB_EVCTRL_PID_0 -#define CONF_PORTB_EVCTRL_PID_0 0x0 -#endif - -// PORTB Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 0 -// portb_event_action_0 -#ifndef CONF_PORTB_EVCTRL_EVACT_0 -#define CONF_PORTB_EVCTRL_EVACT_0 0 -#endif - -// -// PORT Input Event 0 configuration on PORT C - -// PORTC Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled -// portc_input_event_enable_0 -#ifndef CONF_PORTC_EVCTRL_PORTEI_0 -#define CONF_PORTC_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTC Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_0 -#ifndef CONF_PORTC_EVCTRL_PID_0 -#define CONF_PORTC_EVCTRL_PID_0 0x0 -#endif - -// PORTC Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 0 -// portc_event_action_0 -#ifndef CONF_PORTC_EVCTRL_EVACT_0 -#define CONF_PORTC_EVCTRL_EVACT_0 0 -#endif - -// -// PORT Input Event 0 configuration on PORT D - -// PORTD Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled -// portd_input_event_enable_0 -#ifndef CONF_PORTD_EVCTRL_PORTEI_0 -#define CONF_PORTD_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTD Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_0 -#ifndef CONF_PORTD_EVCTRL_PID_0 -#define CONF_PORTD_EVCTRL_PID_0 0x0 -#endif - -// PORTD Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 0 -// portd_event_action_0 -#ifndef CONF_PORTD_EVCTRL_EVACT_0 -#define CONF_PORTD_EVCTRL_EVACT_0 0 -#endif - -// - -// - -// PORT Input Event 1 configuration -// enable_port_input_event_1 -#ifndef CONF_PORT_EVCTRL_PORT_1 -#define CONF_PORT_EVCTRL_PORT_1 0 -#endif - -// PORT Input Event 1 configuration on PORT A - -// PORTA Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled -// porta_input_event_enable_1 -#ifndef CONF_PORTA_EVCTRL_PORTEI_1 -#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTA Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_1 -#ifndef CONF_PORTA_EVCTRL_PID_1 -#define CONF_PORTA_EVCTRL_PID_1 0x0 -#endif - -// PORTA Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 1 -// porta_event_action_1 -#ifndef CONF_PORTA_EVCTRL_EVACT_1 -#define CONF_PORTA_EVCTRL_EVACT_1 0 -#endif - -// -// PORT Input Event 1 configuration on PORT B - -// PORTB Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled -// portb_input_event_enable_1 -#ifndef CONF_PORTB_EVCTRL_PORTEI_1 -#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTB Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_1 -#ifndef CONF_PORTB_EVCTRL_PID_1 -#define CONF_PORTB_EVCTRL_PID_1 0x0 -#endif - -// PORTB Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 1 -// portb_event_action_1 -#ifndef CONF_PORTB_EVCTRL_EVACT_1 -#define CONF_PORTB_EVCTRL_EVACT_1 0 -#endif - -// -// PORT Input Event 1 configuration on PORT C - -// PORTC Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled -// portc_input_event_enable_1 -#ifndef CONF_PORTC_EVCTRL_PORTEI_1 -#define CONF_PORTC_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTC Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_1 -#ifndef CONF_PORTC_EVCTRL_PID_1 -#define CONF_PORTC_EVCTRL_PID_1 0x0 -#endif - -// PORTC Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 1 -// portc_event_action_1 -#ifndef CONF_PORTC_EVCTRL_EVACT_1 -#define CONF_PORTC_EVCTRL_EVACT_1 0 -#endif - -// -// PORT Input Event 1 configuration on PORT D - -// PORTD Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled -// portd_input_event_enable_1 -#ifndef CONF_PORTD_EVCTRL_PORTEI_1 -#define CONF_PORTD_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTD Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_1 -#ifndef CONF_PORTD_EVCTRL_PID_1 -#define CONF_PORTD_EVCTRL_PID_1 0x0 -#endif - -// PORTD Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 1 -// portd_event_action_1 -#ifndef CONF_PORTD_EVCTRL_EVACT_1 -#define CONF_PORTD_EVCTRL_EVACT_1 0 -#endif - -// - -// - -// PORT Input Event 2 configuration -// enable_port_input_event_2 -#ifndef CONF_PORT_EVCTRL_PORT_2 -#define CONF_PORT_EVCTRL_PORT_2 0 -#endif - -// PORT Input Event 2 configuration on PORT A - -// PORTA Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled -// porta_input_event_enable_2 -#ifndef CONF_PORTA_EVCTRL_PORTEI_2 -#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTA Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_2 -#ifndef CONF_PORTA_EVCTRL_PID_2 -#define CONF_PORTA_EVCTRL_PID_2 0x0 -#endif - -// PORTA Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 2 -// porta_event_action_2 -#ifndef CONF_PORTA_EVCTRL_EVACT_2 -#define CONF_PORTA_EVCTRL_EVACT_2 0 -#endif - -// -// PORT Input Event 2 configuration on PORT B - -// PORTB Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled -// portb_input_event_enable_2 -#ifndef CONF_PORTB_EVCTRL_PORTEI_2 -#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTB Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_2 -#ifndef CONF_PORTB_EVCTRL_PID_2 -#define CONF_PORTB_EVCTRL_PID_2 0x0 -#endif - -// PORTB Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 2 -// portb_event_action_2 -#ifndef CONF_PORTB_EVCTRL_EVACT_2 -#define CONF_PORTB_EVCTRL_EVACT_2 0 -#endif - -// -// PORT Input Event 2 configuration on PORT C - -// PORTC Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled -// portc_input_event_enable_2 -#ifndef CONF_PORTC_EVCTRL_PORTEI_2 -#define CONF_PORTC_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTC Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_2 -#ifndef CONF_PORTC_EVCTRL_PID_2 -#define CONF_PORTC_EVCTRL_PID_2 0x0 -#endif - -// PORTC Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 2 -// portc_event_action_2 -#ifndef CONF_PORTC_EVCTRL_EVACT_2 -#define CONF_PORTC_EVCTRL_EVACT_2 0 -#endif - -// -// PORT Input Event 2 configuration on PORT D - -// PORTD Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled -// portd_input_event_enable_2 -#ifndef CONF_PORTD_EVCTRL_PORTEI_2 -#define CONF_PORTD_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTD Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_2 -#ifndef CONF_PORTD_EVCTRL_PID_2 -#define CONF_PORTD_EVCTRL_PID_2 0x0 -#endif - -// PORTD Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 2 -// portd_event_action_2 -#ifndef CONF_PORTD_EVCTRL_EVACT_2 -#define CONF_PORTD_EVCTRL_EVACT_2 0 -#endif - -// - -// - -// PORT Input Event 3 configuration -// enable_port_input_event_3 -#ifndef CONF_PORT_EVCTRL_PORT_3 -#define CONF_PORT_EVCTRL_PORT_3 0 -#endif - -// PORT Input Event 3 configuration on PORT A - -// PORTA Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled -// porta_input_event_enable_3 -#ifndef CONF_PORTA_EVCTRL_PORTEI_3 -#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTA Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_3 -#ifndef CONF_PORTA_EVCTRL_PID_3 -#define CONF_PORTA_EVCTRL_PID_3 0x0 -#endif - -// PORTA Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 3 -// porta_event_action_3 -#ifndef CONF_PORTA_EVCTRL_EVACT_3 -#define CONF_PORTA_EVCTRL_EVACT_3 0 -#endif - -// -// PORT Input Event 3 configuration on PORT B - -// PORTB Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled -// portb_input_event_enable_3 -#ifndef CONF_PORTB_EVCTRL_PORTEI_3 -#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTB Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_3 -#ifndef CONF_PORTB_EVCTRL_PID_3 -#define CONF_PORTB_EVCTRL_PID_3 0x0 -#endif - -// PORTB Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 3 -// portb_event_action_3 -#ifndef CONF_PORTB_EVCTRL_EVACT_3 -#define CONF_PORTB_EVCTRL_EVACT_3 0 -#endif - -// -// PORT Input Event 3 configuration on PORT C - -// PORTC Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled -// portc_input_event_enable_3 -#ifndef CONF_PORTC_EVCTRL_PORTEI_3 -#define CONF_PORTC_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTC Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_3 -#ifndef CONF_PORTC_EVCTRL_PID_3 -#define CONF_PORTC_EVCTRL_PID_3 0x0 -#endif - -// PORTC Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 3 -// portc_event_action_3 -#ifndef CONF_PORTC_EVCTRL_EVACT_3 -#define CONF_PORTC_EVCTRL_EVACT_3 0 -#endif - -// -// PORT Input Event 3 configuration on PORT D - -// PORTD Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled -// portd_input_event_enable_3 -#ifndef CONF_PORTD_EVCTRL_PORTEI_3 -#define CONF_PORTD_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTD Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_3 -#ifndef CONF_PORTD_EVCTRL_PID_3 -#define CONF_PORTD_EVCTRL_PID_3 0x0 -#endif - -// PORTD Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 3 -// portd_event_action_3 -#ifndef CONF_PORTD_EVCTRL_EVACT_3 -#define CONF_PORTD_EVCTRL_EVACT_3 0 -#endif - -// - -// - -#define CONF_PORTA_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ - | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ - | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) -#define CONF_PORTB_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ - | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ - | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) -#define CONF_PORTC_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ - | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ - | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) -#define CONF_PORTD_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \ - | CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \ - | CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3)) - -// <<< end of configuration section >>> - -#endif // HPL_PORT_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_qspi_config.h b/software/firmware/project_oracle_base/config/hpl_qspi_config.h deleted file mode 100644 index 405e355..0000000 --- a/software/firmware/project_oracle_base/config/hpl_qspi_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/* Auto-generated config file hpl_qspi_config.h */ -#ifndef HPL_QSPI_CONFIG_H -#define HPL_QSPI_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// Basic settings - -#ifndef CONF_CONF_QSPI_ENABLE -#define CONF_CONF_QSPI_ENABLE 1 -#endif - -// Baud rate <1-150000000> -// The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255 -// qspi_baud_rate -#ifndef CONF_QSPI_BAUD -#define CONF_QSPI_BAUD 375000 -#endif - -// Clock Polarity -// <0x0=>The inactive state value of SPCK is logic level zero. -// <0x1=>The inactive state value of SPCK is logic level one. -// Determines the inactive state value of the serial clock (SPCK). -// qspi_cpol -#ifndef CONF_QSPI_CPOL -#define CONF_QSPI_CPOL 0x0 -#endif - -// Clock Phase -// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. -// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. -// Determines which edge of SPCK causes data to change and which edge causes data to be captured. -// qspi_cpha -#ifndef CONF_QSPI_CPHA -#define CONF_QSPI_CPHA 0x0 -#endif - -// - -// Advanced Configuration -// qspi_advanced -#ifndef CONF_QSPI_ADVANCED -#define CONF_QSPI_ADVANCED 0 -#endif - -// Delay Before QSCK (ns) <0-255000> -// This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns). -// qspi_dlybs -#ifndef CONF_QSPI_DLY_BS -#define CONF_QSPI_DLY_BS 0 -#endif - -// Minimum Inactive QCS Delay (ns) <0-8160000> -// This field defines the minimum delay between the deactivation and the activation of QCS (in ns). -// qspi_dlycs -#ifndef CONF_QSPI_DLY_CS -#define CONF_QSPI_DLY_CS 0 -#endif - -// - -/* Calculate baud register value from requested baudrate value */ -#ifndef CONF_QSPI_BAUD_RATE -#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1) -#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255 -#warning Invalid baudrate, please check. -#endif -#endif - -/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */ -#ifndef CONF_QSPI_DLYCS -#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000) -#endif - -/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ -#ifndef CONF_QSPI_DLYBS -#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000) -#endif - -// <<< end of configuration section >>> - -#endif // HPL_QSPI_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_rtc_config.h b/software/firmware/project_oracle_base/config/hpl_rtc_config.h deleted file mode 100644 index 79c0192..0000000 --- a/software/firmware/project_oracle_base/config/hpl_rtc_config.h +++ /dev/null @@ -1,341 +0,0 @@ -/* Auto-generated config file hpl_rtc_config.h */ -#ifndef HPL_RTC_CONFIG_H -#define HPL_RTC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic settings - -#ifndef CONF_RTC_ENABLE -#define CONF_RTC_ENABLE 1 -#endif - -// Force reset RTC on initialization -// Force RTC to reset on initialization. -// Note that the previous power down data in RTC is lost if it's enabled. -// rtc_arch_init_reset -#ifndef CONF_RTC_INIT_RESET -#define CONF_RTC_INIT_RESET 1 -#endif - -// Prescaler configuration -// <0x0=>OFF(Peripheral clock divided by 1) -// <0x1=>Peripheral clock divided by 1 -// <0x2=>Peripheral clock divided by 2 -// <0x3=>Peripheral clock divided by 4 -// <0x4=>Peripheral clock divided by 8 -// <0x5=>Peripheral clock divided by 16 -// <0x6=>Peripheral clock divided by 32 -// <0x7=>Peripheral clock divided by 64 -// <0x8=>Peripheral clock divided by 128 -// <0x9=>Peripheral clock divided by 256 -// <0xA=>Peripheral clock divided by 512 -// <0xB=>Peripheral clock divided by 1024 -// These bits define the RTC clock relative to the peripheral clock -// rtc_arch_prescaler -#ifndef CONF_RTC_PRESCALER -#define CONF_RTC_PRESCALER 0x0 - -#endif - -// Compare Value <1-4294967295> -// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), -// by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. -// rtc_arch_comp_val - -#ifndef CONF_RTC_COMP_VAL - -#define CONF_RTC_COMP_VAL 32 - -#endif - -// RTC Tamper Input 0 settings -// tamper_input_0_settings -#ifndef CONF_TAMPER_INPUT_0_SETTINGS -#define CONF_TAMPER_INPUT_0_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 0 level -// tamper_level_0 -#ifndef CONF_RTC_TAMP_LVL_0 -#define CONF_RTC_TAMP_LVL_0 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_0 -#ifndef CONF_RTC_TAMPER_INACT_0 -#define CONF_RTC_TAMPER_INACT_0 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 0 -// tamper_debounce_enable_0 -#ifndef CONF_RTC_TAMP_DEBNC_0 -#define CONF_RTC_TAMP_DEBNC_0 0 -#endif - -// - -// RTC Tamper Input 1 settings -// tamper_input_1_settings -#ifndef CONF_TAMPER_INPUT_1_SETTINGS -#define CONF_TAMPER_INPUT_1_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 1 level -// tamper_level_1 -#ifndef CONF_RTC_TAMP_LVL_1 -#define CONF_RTC_TAMP_LVL_1 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_1 -#ifndef CONF_RTC_TAMPER_INACT_1 -#define CONF_RTC_TAMPER_INACT_1 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 1 -// tamper_debounce_enable_1 -#ifndef CONF_RTC_TAMP_DEBNC_1 -#define CONF_RTC_TAMP_DEBNC_1 0 -#endif - -// - -// RTC Tamper Input 2 settings -// tamper_input_2_settings -#ifndef CONF_TAMPER_INPUT_2_SETTINGS -#define CONF_TAMPER_INPUT_2_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 2 level -// tamper_level_2 -#ifndef CONF_RTC_TAMP_LVL_2 -#define CONF_RTC_TAMP_LVL_2 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_2 -#ifndef CONF_RTC_TAMPER_INACT_2 -#define CONF_RTC_TAMPER_INACT_2 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 2 -// tamper_debounce_enable_2 -#ifndef CONF_RTC_TAMP_DEBNC_2 -#define CONF_RTC_TAMP_DEBNC_2 0 -#endif - -// - -// RTC Tamper Input 3 settings -// tamper_input_3_settings -#ifndef CONF_TAMPER_INPUT_3_SETTINGS -#define CONF_TAMPER_INPUT_3_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 3 level -// tamper_level_3 -#ifndef CONF_RTC_TAMP_LVL_3 -#define CONF_RTC_TAMP_LVL_3 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_3 -#ifndef CONF_RTC_TAMPER_INACT_3 -#define CONF_RTC_TAMPER_INACT_3 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 3 -// tamper_debounce_enable_3 -#ifndef CONF_RTC_TAMP_DEBNC_3 -#define CONF_RTC_TAMP_DEBNC_3 0 -#endif - -// - -// RTC Tamper Input 4 settings -// tamper_input_4_settings -#ifndef CONF_TAMPER_INPUT_4_SETTINGS -#define CONF_TAMPER_INPUT_4_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 4 level -// tamper_level_4 -#ifndef CONF_RTC_TAMP_LVL_4 -#define CONF_RTC_TAMP_LVL_4 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_4 -#ifndef CONF_RTC_TAMPER_INACT_4 -#define CONF_RTC_TAMPER_INACT_4 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 4 -// tamper_debounce_enable_4 -#ifndef CONF_RTC_TAMP_DEBNC_4 -#define CONF_RTC_TAMP_DEBNC_4 0 -#endif - -// - -// RTC Tamper Active Layer Frequency Prescalar -// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2 -// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4 -// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8 -// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16 -// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32 -// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64 -// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128 -// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256 -// These bits define the RTC Tamper Active Layer Frequecny Prescalar -// rtc_tamper_active_layer_frequency_prescalar -#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES -#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0 -#endif - -// RTC Tamper Debounce Frequency Prescalar -// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2 -// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4 -// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8 -// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16 -// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32 -// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64 -// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128 -// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256 -// These bits define the RTC Debounce Frequency Prescalar -// rtc_tamper_debounce_frequency_prescalar -#ifndef CONF_RTC_TAMP_DEBF_PRES -#define CONF_RTC_TAMP_DEBF_PRES 0 -#endif - -// Event control -// rtc_event_control -#ifndef CONF_RTC_EVENT_CONTROL_ENABLE -#define CONF_RTC_EVENT_CONTROL_ENABLE 0 -#endif - -// Periodic Interval 0 Event Output -// This bit indicates whether Periodic interval 0 event is enabled and will be generated -// rtc_pereo0 -#ifndef CONF_RTC_PEREO0 -#define CONF_RTC_PEREO0 0 -#endif -// Periodic Interval 1 Event Output -// This bit indicates whether Periodic interval 1 event is enabled and will be generated -// rtc_pereo1 -#ifndef CONF_RTC_PEREO1 -#define CONF_RTC_PEREO1 0 -#endif -// Periodic Interval 2 Event Output -// This bit indicates whether Periodic interval 2 event is enabled and will be generated -// rtc_pereo2 -#ifndef CONF_RTC_PEREO2 -#define CONF_RTC_PEREO2 0 -#endif -// Periodic Interval 3 Event Output -// This bit indicates whether Periodic interval 3 event is enabled and will be generated -// rtc_pereo3 -#ifndef CONF_RTC_PEREO3 -#define CONF_RTC_PEREO3 0 -#endif -// Periodic Interval 4 Event Output -// This bit indicates whether Periodic interval 4 event is enabled and will be generated -// rtc_pereo4 -#ifndef CONF_RTC_PEREO4 -#define CONF_RTC_PEREO4 0 -#endif -// Periodic Interval 5 Event Output -// This bit indicates whether Periodic interval 5 event is enabled and will be generated -// rtc_pereo5 -#ifndef CONF_RTC_PEREO5 -#define CONF_RTC_PEREO5 0 -#endif -// Periodic Interval 6 Event Output -// This bit indicates whether Periodic interval 6 event is enabled and will be generated -// rtc_pereo6 -#ifndef CONF_RTC_PEREO6 -#define CONF_RTC_PEREO6 0 -#endif -// Periodic Interval 7 Event Output -// This bit indicates whether Periodic interval 7 event is enabled and will be generated -// rtc_pereo7 -#ifndef CONF_RTC_PEREO7 -#define CONF_RTC_PEREO7 0 -#endif - -// Compare 0 Event Output -// This bit indicates whether Compare O event is enabled and will be generated -// rtc_cmpeo0 -#ifndef CONF_RTC_COMPE0 -#define CONF_RTC_COMPE0 0 -#endif - -// Compare 1 Event Output -// This bit indicates whether Compare 1 event is enabled and will be generated -// rtc_cmpeo1 -#ifndef CONF_RTC_COMPE1 -#define CONF_RTC_COMPE1 0 -#endif -// Overflow Event Output -// This bit indicates whether Overflow event is enabled and will be generated -// rtc_ovfeo -#ifndef CONF_RTC_OVFEO -#define CONF_RTC_OVFEO 0 -#endif - -// Tamper Event Output -// This bit indicates whether Tamper event output is enabled and will be generated -// rtc_tampereo -#ifndef CONF_RTC_TAMPEREO -#define CONF_RTC_TAMPEREO 0 -#endif - -// Tamper Event Input -// This bit indicates whether Tamper event input is enabled and will be generated -// rtc_tampevei -#ifndef CONF_RTC_TAMPEVEI -#define CONF_RTC_TAMPEVEI 0 -#endif -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_RTC_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_systick_config.h b/software/firmware/project_oracle_base/config/hpl_systick_config.h deleted file mode 100644 index a7f2f36..0000000 --- a/software/firmware/project_oracle_base/config/hpl_systick_config.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Auto-generated config file hpl_systick_config.h */ -#ifndef HPL_SYSTICK_CONFIG_H -#define HPL_SYSTICK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Advanced settings -// SysTick exception request -// Indicates whether the generation of SysTick exception is enabled or not -// systick_arch_tickint -#ifndef CONF_SYSTICK_TICKINT -#define CONF_SYSTICK_TICKINT 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_SYSTICK_CONFIG_H diff --git a/software/firmware/project_oracle_base/config/hpl_tc_config.h b/software/firmware/project_oracle_base/config/hpl_tc_config.h deleted file mode 100644 index ae5921c..0000000 --- a/software/firmware/project_oracle_base/config/hpl_tc_config.h +++ /dev/null @@ -1,180 +0,0 @@ -/* Auto-generated config file hpl_tc_config.h */ -#ifndef HPL_TC_CONFIG_H -#define HPL_TC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef CONF_TC0_ENABLE -#define CONF_TC0_ENABLE 1 -#endif - -#include "peripheral_clk_config.h" - -// Basic configuration - -// Prescaler -// <0x0=> No division -// <0x1=> Divide by 2 -// <0x2=> Divide by 4 -// <0x3=> Divide by 8 -// <0x4=> Divide by 16 -// <0x5=> Divide by 64 -// <0x6=> Divide by 256 -// <0x7=> Divide by 1024 -// This defines the prescaler value -// timer_prescaler -#ifndef CONF_TC0_PRESCALER -#define CONF_TC0_PRESCALER 0x3 -#endif - -// Length of one timer tick in uS <0-4294967295> -// timer_tick -#ifndef CONF_TC0_TIMER_TICK -#define CONF_TC0_TIMER_TICK 1000 -#endif -// - -// Advanced configuration -// timer_advanced_configuration -#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE -#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0 -#endif - -// Prescaler and Counter Synchronization Selection -// Reload or reset counter on next GCLK -// Reload or reset counter on next prescaler clock -// Reload or reset counter on next GCLK and reset prescaler counter -// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. -// tc_arch_presync -#ifndef CONF_TC0_PRESCSYNC -#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val -#endif - -// Run in standby -// Indicates whether the module will continue to run in standby sleep mode -// tc_arch_runstdby -#ifndef CONF_TC0_RUNSTDBY -#define CONF_TC0_RUNSTDBY 0 -#endif - -// Run in debug mode -// Indicates whether the module will run in debug mode -// tc_arch_dbgrun -#ifndef CONF_TC0_DBGRUN -#define CONF_TC0_DBGRUN 0 -#endif - -// Run on demand -// Run if requested by some other peripheral in the device -// tc_arch_ondemand -#ifndef CONF_TC0_ONDEMAND -#define CONF_TC0_ONDEMAND 0 -#endif - -// - -// Event control -// timer_event_control -#ifndef CONF_TC0_EVENT_CONTROL_ENABLE -#define CONF_TC0_EVENT_CONTROL_ENABLE 0 -#endif - -// Output Event On Match or Capture on Channel 0 -// Enable output of event on timer tick -// tc_arch_mceo0 -#ifndef CONF_TC0_MCEO0 -#define CONF_TC0_MCEO0 0 -#endif - -// Output Event On Match or Capture on Channel 1 -// Enable output of event on timer tick -// tc_arch_mceo1 -#ifndef CONF_TC0_MCEO1 -#define CONF_TC0_MCEO1 0 -#endif - -// Output Event On Timer Tick -// Enable output of event on timer tick -// tc_arch_ovfeo -#ifndef CONF_TC0_OVFEO -#define CONF_TC0_OVFEO 0 -#endif - -// Event Input -// Enable asynchronous input events -// tc_arch_tcei -#ifndef CONF_TC0_TCEI -#define CONF_TC0_TCEI 0 -#endif - -// Inverted Event Input -// Invert the asynchronous input events -// tc_arch_tcinv -#ifndef CONF_TC0_TCINV -#define CONF_TC0_TCINV 0 -#endif - -// Event action -// <0=> Event action disabled -// <1=> Start, restart or re-trigger TC on event -// <2=> Count on event -// <3=> Start on event -// <4=> Time stamp capture -// <5=> Period captured in CC0, pulse width in CC1 -// <6=> Period captured in CC1, pulse width in CC0 -// <7=> Pulse width capture -// Event which will be performed on an event -// tc_arch_evact -#ifndef CONF_TC0_EVACT -#define CONF_TC0_EVACT 0 -#endif -// - -// Default values which the driver needs in order to work correctly - -// Mode set to 32-bit -#ifndef CONF_TC0_MODE -#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val -#endif - -// CC 1 register set to 0 -#ifndef CONF_TC0_CC1 -#define CONF_TC0_CC1 0 -#endif - -#ifndef CONF_TC0_ALOCK -#define CONF_TC0_ALOCK 0 -#endif - -// Not used in 32-bit mode -#define CONF_TC0_PER 0 - -// Calculating correct top value based on requested tick interval. -#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER) - -// Prescaler set to 64 -#if CONF_TC0_PRESCALER > 0x4 -#undef CONF_TC0_PRESCALE -#define CONF_TC0_PRESCALE 64 -#endif - -// Prescaler set to 256 -#if CONF_TC0_PRESCALER > 0x5 -#undef CONF_TC0_PRESCALE -#define CONF_TC0_PRESCALE 256 -#endif - -// Prescaler set to 1024 -#if CONF_TC0_PRESCALER > 0x6 -#undef CONF_TC0_PRESCALE -#define CONF_TC0_PRESCALE 1024 -#endif - -#ifndef CONF_TC0_CC0 -#define CONF_TC0_CC0 \ - (uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE))) -#endif - -// <<< end of configuration section >>> - -#endif // HPL_TC_CONFIG_H diff --git a/software/firmware/project_oracle_base/driver_init.c b/software/firmware/project_oracle_base/driver_init.c deleted file mode 100644 index fd64b05..0000000 --- a/software/firmware/project_oracle_base/driver_init.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_init.h" -#include -#include -#include - -#include - -struct timer_descriptor TIMER_0; -struct timer_descriptor TIMER_1; - -struct qspi_sync_descriptor QUAD_SPI_0; - -struct usart_sync_descriptor USART_0; - -struct i2c_m_sync_desc I2C_0; - -void EXTERNAL_IRQ_0_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_mclk_set_APBAMASK_EIC_bit(MCLK); - - ext_irq_init(); -} - -void QUAD_SPI_0_PORT_init(void) -{ -} - -void QUAD_SPI_0_CLOCK_init(void) -{ - hri_mclk_set_AHBMASK_QSPI_bit(MCLK); - hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK); - hri_mclk_set_APBCMASK_QSPI_bit(MCLK); -} - -void QUAD_SPI_0_init(void) -{ - QUAD_SPI_0_CLOCK_init(); - qspi_sync_init(&QUAD_SPI_0, QSPI); - QUAD_SPI_0_PORT_init(); -} - -/** - * \brief Timer initialization function - * - * Enables Timer peripheral, clocks and initializes Timer driver - */ -static void TIMER_0_init(void) -{ - hri_mclk_set_APBAMASK_RTC_bit(MCLK); - timer_init(&TIMER_0, RTC, _rtc_get_timer()); -} - -void USART_0_PORT_init(void) -{ - - gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0); - - gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1); -} - -void USART_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); -} - -void USART_0_init(void) -{ - USART_0_CLOCK_init(); - usart_sync_init(&USART_0, SERCOM0, (void *)NULL); - USART_0_PORT_init(); -} - -void I2C_0_PORT_init(void) -{ - - gpio_set_pin_pull_mode(PA16, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA16, PINMUX_PA16C_SERCOM1_PAD0); - - gpio_set_pin_pull_mode(PA17, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA17, PINMUX_PA17C_SERCOM1_PAD1); -} - -void I2C_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK); -} - -void I2C_0_init(void) -{ - I2C_0_CLOCK_init(); - i2c_m_sync_init(&I2C_0, SERCOM1); - I2C_0_PORT_init(); -} - -void delay_driver_init(void) -{ - delay_init(SysTick); -} - -/** - * \brief Timer initialization function - * - * Enables Timer peripheral, clocks and initializes Timer driver - */ -static void TIMER_1_init(void) -{ - hri_mclk_set_APBAMASK_TC0_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - timer_init(&TIMER_1, TC0, _tc_get_timer()); -} - -void system_init(void) -{ - init_mcu(); - - EXTERNAL_IRQ_0_init(); - - QUAD_SPI_0_init(); - - TIMER_0_init(); - - USART_0_init(); - - I2C_0_init(); - - delay_driver_init(); - - TIMER_1_init(); -} diff --git a/software/firmware/project_oracle_base/driver_init.h b/software/firmware/project_oracle_base/driver_init.h deleted file mode 100644 index c2af21b..0000000 --- a/software/firmware/project_oracle_base/driver_init.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_INIT_INCLUDED -#define DRIVER_INIT_INCLUDED - -#include "atmel_start_pins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include - -#include - -#include - -#include -#include -#include - -extern struct qspi_sync_descriptor QUAD_SPI_0; -extern struct timer_descriptor TIMER_0; - -extern struct usart_sync_descriptor USART_0; - -extern struct i2c_m_sync_desc I2C_0; - -extern struct timer_descriptor TIMER_1; - -void QUAD_SPI_0_PORT_init(void); -void QUAD_SPI_0_CLOCK_init(void); -void QUAD_SPI_0_init(void); - -void USART_0_PORT_init(void); -void USART_0_CLOCK_init(void); -void USART_0_init(void); - -void I2C_0_CLOCK_init(void); -void I2C_0_init(void); -void I2C_0_PORT_init(void); - -void delay_driver_init(void); - -/** - * \brief Perform system initialization, initialize pins and clocks for - * peripherals - */ -void system_init(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_INIT_INCLUDED diff --git a/software/firmware/project_oracle_base/examples/driver_examples.c b/software/firmware/project_oracle_base/examples/driver_examples.c deleted file mode 100644 index ea4bc45..0000000 --- a/software/firmware/project_oracle_base/examples/driver_examples.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_examples.h" -#include "driver_init.h" -#include "utils.h" - -/** - * Example of using EXTERNAL_IRQ_0 - */ -void EXTERNAL_IRQ_0_example(void) -{ -} - -/** - * Example of using QUAD_SPI_0 to get N25Q256A status value, - * and check bit 0 which indicate embedded operation is busy or not. - */ -void QUAD_SPI_0_example(void) -{ - uint8_t status = 0xFF; - struct _qspi_command cmd = { - .inst_frame.bits.inst_en = 1, - .inst_frame.bits.data_en = 1, - .inst_frame.bits.tfr_type = QSPI_READ_ACCESS, - .instruction = 0x05, - .buf_len = 1, - .rx_buf = &status, - }; - - qspi_sync_enable(&QUAD_SPI_0); - while (status & (1 << 0)) { - qspi_sync_serial_run_command(&QUAD_SPI_0, &cmd); - } - qspi_sync_deinit(&QUAD_SPI_0); -} - -static struct timer_task TIMER_0_task1, TIMER_0_task2; -/** - * Example of using TIMER_0. - */ -static void TIMER_0_task1_cb(const struct timer_task *const timer_task) -{ -} - -static void TIMER_0_task2_cb(const struct timer_task *const timer_task) -{ -} - -void TIMER_0_example(void) -{ - TIMER_0_task1.interval = 100; - TIMER_0_task1.cb = TIMER_0_task1_cb; - TIMER_0_task1.mode = TIMER_TASK_REPEAT; - TIMER_0_task2.interval = 200; - TIMER_0_task2.cb = TIMER_0_task2_cb; - TIMER_0_task2.mode = TIMER_TASK_REPEAT; - - timer_add_task(&TIMER_0, &TIMER_0_task1); - timer_add_task(&TIMER_0, &TIMER_0_task2); - timer_start(&TIMER_0); -} - -/** - * Example of using USART_0 to write "Hello World" using the IO abstraction. - */ -void USART_0_example(void) -{ - struct io_descriptor *io; - usart_sync_get_io_descriptor(&USART_0, &io); - usart_sync_enable(&USART_0); - - io_write(io, (uint8_t *)"Hello World!", 12); -} - -void I2C_0_example(void) -{ - struct io_descriptor *I2C_0_io; - - i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); - i2c_m_sync_enable(&I2C_0); - i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); - io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); -} - -void delay_example(void) -{ - delay_ms(5000); -} - -static struct timer_task TIMER_1_task1, TIMER_1_task2; - -/** - * Example of using TIMER_1. - */ -static void TIMER_1_task1_cb(const struct timer_task *const timer_task) -{ -} - -static void TIMER_1_task2_cb(const struct timer_task *const timer_task) -{ -} - -void TIMER_1_example(void) -{ - TIMER_1_task1.interval = 100; - TIMER_1_task1.cb = TIMER_1_task1_cb; - TIMER_1_task1.mode = TIMER_TASK_REPEAT; - TIMER_1_task2.interval = 200; - TIMER_1_task2.cb = TIMER_1_task2_cb; - TIMER_1_task2.mode = TIMER_TASK_REPEAT; - - timer_add_task(&TIMER_1, &TIMER_1_task1); - timer_add_task(&TIMER_1, &TIMER_1_task2); - timer_start(&TIMER_1); -} diff --git a/software/firmware/project_oracle_base/examples/driver_examples.h b/software/firmware/project_oracle_base/examples/driver_examples.h deleted file mode 100644 index f4bb117..0000000 --- a/software/firmware/project_oracle_base/examples/driver_examples.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_EXAMPLES_H_INCLUDED -#define DRIVER_EXAMPLES_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -void EXTERNAL_IRQ_0_example(void); - -void QUAD_SPI_0_example(void); - -void TIMER_0_example(void); - -void USART_0_example(void); - -void I2C_0_example(void); - -void delay_example(void); - -void TIMER_1_example(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/software/firmware/project_oracle_base/gcc/Makefile b/software/firmware/project_oracle_base/gcc/Makefile deleted file mode 100644 index 67a062f..0000000 --- a/software/firmware/project_oracle_base/gcc/Makefile +++ /dev/null @@ -1,289 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -ifdef SystemRoot - SHELL = cmd.exe - MK_DIR = mkdir -else - ifeq ($(shell uname), Linux) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW32) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW64) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), DARWIN) - MK_DIR = mkdir -p - endif -endif - -# List the subdirectories for creating object files -SUB_DIRS += \ - \ -hpl/pm \ -hpl/tc \ -hpl/osc32kctrl \ -hpl/ramecc \ -hpl/dmac \ -hal/src \ -gcc \ -hpl/mclk \ -hpl/qspi \ -hpl/eic \ -hpl/sercom \ -examples \ -hpl/gclk \ -hpl/oscctrl \ -hal/utils/src \ -gcc/gcc \ -hpl/rtc \ -hpl/systick \ -hpl/core \ -hpl/cmcc - -# List the object files -OBJS += \ -hal/src/hal_io.o \ -hpl/qspi/hpl_qspi.o \ -hpl/eic/hpl_eic.o \ -hpl/core/hpl_core_m4.o \ -hal/utils/src/utils_syscalls.o \ -hpl/systick/hpl_systick.o \ -hal/src/hal_timer.o \ -hal/src/hal_i2c_m_sync.o \ -hal/src/hal_delay.o \ -hpl/pm/hpl_pm.o \ -hpl/core/hpl_init.o \ -hpl/ramecc/hpl_ramecc.o \ -hal/utils/src/utils_list.o \ -hal/utils/src/utils_assert.o \ -hpl/dmac/hpl_dmac.o \ -hpl/oscctrl/hpl_oscctrl.o \ -hal/src/hal_usart_sync.o \ -hpl/mclk/hpl_mclk.o \ -hpl/sercom/hpl_sercom.o \ -hpl/gclk/hpl_gclk.o \ -hal/src/hal_init.o \ -gcc/gcc/startup_same54.o \ -main.o \ -hpl/osc32kctrl/hpl_osc32kctrl.o \ -hpl/rtc/hpl_rtc.o \ -examples/driver_examples.o \ -driver_init.o \ -hal/src/hal_ext_irq.o \ -hal/src/hal_atomic.o \ -hal/src/hal_gpio.o \ -hal/src/hal_qspi_sync.o \ -hal/utils/src/utils_event.o \ -hal/src/hal_sleep.o \ -hal/src/hal_cache.o \ -gcc/system_same54.o \ -atmel_start.o \ -hpl/tc/hpl_tc.o \ -hpl/cmcc/hpl_cmcc.o - -OBJS_AS_ARGS += \ -"hal/src/hal_io.o" \ -"hpl/qspi/hpl_qspi.o" \ -"hpl/eic/hpl_eic.o" \ -"hpl/core/hpl_core_m4.o" \ -"hal/utils/src/utils_syscalls.o" \ -"hpl/systick/hpl_systick.o" \ -"hal/src/hal_timer.o" \ -"hal/src/hal_i2c_m_sync.o" \ -"hal/src/hal_delay.o" \ -"hpl/pm/hpl_pm.o" \ -"hpl/core/hpl_init.o" \ -"hpl/ramecc/hpl_ramecc.o" \ -"hal/utils/src/utils_list.o" \ -"hal/utils/src/utils_assert.o" \ -"hpl/dmac/hpl_dmac.o" \ -"hpl/oscctrl/hpl_oscctrl.o" \ -"hal/src/hal_usart_sync.o" \ -"hpl/mclk/hpl_mclk.o" \ -"hpl/sercom/hpl_sercom.o" \ -"hpl/gclk/hpl_gclk.o" \ -"hal/src/hal_init.o" \ -"gcc/gcc/startup_same54.o" \ -"main.o" \ -"hpl/osc32kctrl/hpl_osc32kctrl.o" \ -"hpl/rtc/hpl_rtc.o" \ -"examples/driver_examples.o" \ -"driver_init.o" \ -"hal/src/hal_ext_irq.o" \ -"hal/src/hal_atomic.o" \ -"hal/src/hal_gpio.o" \ -"hal/src/hal_qspi_sync.o" \ -"hal/utils/src/utils_event.o" \ -"hal/src/hal_sleep.o" \ -"hal/src/hal_cache.o" \ -"gcc/system_same54.o" \ -"atmel_start.o" \ -"hpl/tc/hpl_tc.o" \ -"hpl/cmcc/hpl_cmcc.o" - -# List the directories containing header files -DIR_INCLUDES += \ --I"../" \ --I"../config" \ --I"../examples" \ --I"../hal/include" \ --I"../hal/utils/include" \ --I"../hpl/cmcc" \ --I"../hpl/core" \ --I"../hpl/dmac" \ --I"../hpl/eic" \ --I"../hpl/gclk" \ --I"../hpl/mclk" \ --I"../hpl/osc32kctrl" \ --I"../hpl/oscctrl" \ --I"../hpl/pm" \ --I"../hpl/port" \ --I"../hpl/qspi" \ --I"../hpl/ramecc" \ --I"../hpl/rtc" \ --I"../hpl/sercom" \ --I"../hpl/systick" \ --I"../hpl/tc" \ --I"../hri" \ --I"../" \ --I"../CMSIS/Core/Include" \ --I"../include" - -# List the dependency files -DEPS := $(OBJS:%.o=%.d) - -DEPS_AS_ARGS += \ -"hal/utils/src/utils_event.d" \ -"hal/src/hal_io.d" \ -"hpl/ramecc/hpl_ramecc.d" \ -"hpl/qspi/hpl_qspi.d" \ -"hpl/core/hpl_core_m4.d" \ -"hpl/eic/hpl_eic.d" \ -"hal/utils/src/utils_syscalls.d" \ -"hal/src/hal_i2c_m_sync.d" \ -"hal/src/hal_timer.d" \ -"hal/utils/src/utils_list.d" \ -"hpl/cmcc/hpl_cmcc.d" \ -"hpl/dmac/hpl_dmac.d" \ -"hal/utils/src/utils_assert.d" \ -"hal/src/hal_delay.d" \ -"hpl/core/hpl_init.d" \ -"hpl/pm/hpl_pm.d" \ -"hpl/gclk/hpl_gclk.d" \ -"hpl/sercom/hpl_sercom.d" \ -"gcc/gcc/startup_same54.d" \ -"hal/src/hal_init.d" \ -"hal/src/hal_usart_sync.d" \ -"hpl/mclk/hpl_mclk.d" \ -"driver_init.d" \ -"hpl/systick/hpl_systick.d" \ -"hpl/osc32kctrl/hpl_osc32kctrl.d" \ -"main.d" \ -"examples/driver_examples.d" \ -"hpl/rtc/hpl_rtc.d" \ -"hal/src/hal_qspi_sync.d" \ -"hal/src/hal_cache.d" \ -"hal/src/hal_sleep.d" \ -"hal/src/hal_ext_irq.d" \ -"hal/src/hal_gpio.d" \ -"hal/src/hal_atomic.d" \ -"hpl/tc/hpl_tc.d" \ -"hpl/oscctrl/hpl_oscctrl.d" \ -"gcc/system_same54.d" \ -"atmel_start.d" - -OUTPUT_FILE_NAME :=AtmelStart -QUOTE := " -OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf -OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf - -vpath %.c ../ -vpath %.s ../ -vpath %.S ../ - -# All Target -all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) - -# Linker target - -$(OUTPUT_FILE_PATH): $(OBJS) - @echo Building target: $@ - @echo Invoking: ARM/GNU Linker - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ --Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \ - \ --T"../gcc/gcc/same54p20a_flash.ld" \ --L"../gcc/gcc" - @echo Finished building target: $@ - - "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin" - "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \ - "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex" - "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \ - .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \ - "$(OUTPUT_FILE_NAME).eep" || exit 0 - "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss" - "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf" - - - -# Compiler targets - - - - -%.o: %.c - @echo Building file: $< - @echo ARM/GNU C Compiler - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ -$(DIR_INCLUDES) \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -%.o: %.s - @echo Building file: $< - @echo ARM/GNU Assembler - $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ -$(DIR_INCLUDES) \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -%.o: %.S - @echo Building file: $< - @echo ARM/GNU Preprocessing Assembler - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ -$(DIR_INCLUDES) \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -# Detect changes in the dependent files and recompile the respective object files. -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(DEPS)),) --include $(DEPS) -endif -endif - -$(SUB_DIRS): - $(MK_DIR) "$@" - -clean: - rm -f $(OBJS_AS_ARGS) - rm -f $(OUTPUT_FILE_PATH) - rm -f $(DEPS_AS_ARGS) - rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ - $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ - $(OUTPUT_FILE_NAME).srec \ No newline at end of file diff --git a/software/firmware/project_oracle_base/gcc/gcc/same54p20a_flash.ld b/software/firmware/project_oracle_base/gcc/gcc/same54p20a_flash.ld deleted file mode 100644 index 6b9660b..0000000 --- a/software/firmware/project_oracle_base/gcc/gcc/same54p20a_flash.ld +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAME54P20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/software/firmware/project_oracle_base/gcc/gcc/same54p20a_sram.ld b/software/firmware/project_oracle_base/gcc/gcc/same54p20a_sram.ld deleted file mode 100644 index 646b1bd..0000000 --- a/software/firmware/project_oracle_base/gcc/gcc/same54p20a_sram.ld +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAME54P20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/software/firmware/project_oracle_base/gcc/gcc/startup_same54.c b/software/firmware/project_oracle_base/gcc/gcc/startup_same54.c deleted file mode 100644 index 097a1c4..0000000 --- a/software/firmware/project_oracle_base/gcc/gcc/startup_same54.c +++ /dev/null @@ -1,678 +0,0 @@ -/** - * \file - * - * \brief gcc starttup file for SAME54 - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "same54.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M4 core handlers */ -void NonMaskableInt_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void MemManagement_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SVCall_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void DebugMonitor_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void MCLK_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void OSCCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ -void OSCCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ -void OSCCTRL_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, - OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, - OSCCTRL_DFLLRDY */ -void OSCCTRL_3_Handler(void) __attribute__(( - weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ -void OSCCTRL_4_Handler(void) __attribute__(( - weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ -void OSC32KCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SUPC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, - SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY - */ -void SUPC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */ -void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void EIC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */ -void EIC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */ -void EIC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */ -void EIC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */ -void EIC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */ -void EIC_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */ -void EIC_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */ -void EIC_7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */ -void EIC_8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */ -void EIC_9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */ -void EIC_10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */ -void EIC_11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */ -void EIC_12_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */ -void EIC_13_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */ -void EIC_14_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */ -void EIC_15_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */ -void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void NVMCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, - NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, - NVMCTRL_6, NVMCTRL_7 */ -void NVMCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ -void DMAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ -void DMAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ -void DMAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ -void DMAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ -void DMAC_4_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, - DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, - DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, - DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, - DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, - DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, - DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, - DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, - DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, - DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, - DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, - DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, - DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, - DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, - DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, - DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, - DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, - DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ -void EVSYS_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */ -void EVSYS_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */ -void EVSYS_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */ -void EVSYS_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */ -void EVSYS_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, - EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, - EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, - EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, - EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, - EVSYS_OVR_9 */ -void PAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void RAMECC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */ -void SERCOM0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */ -void SERCOM0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */ -void SERCOM0_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ -void SERCOM1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */ -void SERCOM1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */ -void SERCOM1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */ -void SERCOM1_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ -void SERCOM2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */ -void SERCOM2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */ -void SERCOM2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */ -void SERCOM2_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ -void SERCOM3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */ -void SERCOM3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */ -void SERCOM3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */ -void SERCOM3_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ -#ifdef ID_SERCOM4 -void SERCOM4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */ -void SERCOM4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */ -void SERCOM4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */ -void SERCOM4_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ -#endif -#ifdef ID_SERCOM5 -void SERCOM5_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */ -void SERCOM5_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */ -void SERCOM5_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */ -void SERCOM5_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ -#endif -#ifdef ID_SERCOM6 -void SERCOM6_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */ -void SERCOM6_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */ -void SERCOM6_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */ -void SERCOM6_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ -#endif -#ifdef ID_SERCOM7 -void SERCOM7_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */ -void SERCOM7_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */ -void SERCOM7_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */ -void SERCOM7_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ -#endif -#ifdef ID_CAN0 -void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_CAN1 -void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_USB -void USB_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, - USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, - USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, - USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, - USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, - USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, - USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, - USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, - USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, - USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, - USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, - USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, - USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, - USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ -void USB_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */ -void USB_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, - USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, - USB_TRCPT0_6, USB_TRCPT0_7 */ -void USB_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, - USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, - USB_TRCPT1_6, USB_TRCPT1_7 */ -#endif -#ifdef ID_GMAC -void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void TCC0_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, - TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ -void TCC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */ -void TCC0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */ -void TCC0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */ -void TCC0_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */ -void TCC0_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */ -void TCC0_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */ -void TCC1_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, - TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ -void TCC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */ -void TCC1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */ -void TCC1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */ -void TCC1_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */ -void TCC2_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, - TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ -void TCC2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */ -void TCC2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */ -void TCC2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */ -#ifdef ID_TCC3 -void TCC3_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, - TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ -void TCC3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */ -void TCC3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */ -#endif -#ifdef ID_TCC4 -void TCC4_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, - TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ -void TCC4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */ -void TCC4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */ -#endif -void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_TC4 -void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC5 -void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC6 -void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC7 -void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void PDEC_0_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ -void PDEC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */ -void PDEC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */ -void ADC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */ -void ADC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */ -void ADC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */ -void ADC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */ -void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void DAC_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ -void DAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */ -void DAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */ -void DAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */ -void DAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */ -#ifdef ID_I2S -void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void PCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_ICM -void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_PUKCC -void PUKCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_SDHC0 -void SDHC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SDHC1 -void SDHC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif - -/* Exception Table */ -__attribute__((section(".vectors"))) const DeviceVectors exception_table - = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void *)(&_estack), - - .pfnReset_Handler = (void *)Reset_Handler, - .pfnNonMaskableInt_Handler = (void *)NonMaskableInt_Handler, - .pfnHardFault_Handler = (void *)HardFault_Handler, - .pfnMemManagement_Handler = (void *)MemManagement_Handler, - .pfnBusFault_Handler = (void *)BusFault_Handler, - .pfnUsageFault_Handler = (void *)UsageFault_Handler, - .pvReservedM9 = (void *)(0UL), /* Reserved */ - .pvReservedM8 = (void *)(0UL), /* Reserved */ - .pvReservedM7 = (void *)(0UL), /* Reserved */ - .pvReservedM6 = (void *)(0UL), /* Reserved */ - .pfnSVCall_Handler = (void *)SVCall_Handler, - .pfnDebugMonitor_Handler = (void *)DebugMonitor_Handler, - .pvReservedM3 = (void *)(0UL), /* Reserved */ - .pfnPendSV_Handler = (void *)PendSV_Handler, - .pfnSysTick_Handler = (void *)SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ - .pfnMCLK_Handler = (void *)MCLK_Handler, /* 1 Main Clock */ - .pfnOSCCTRL_0_Handler = (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - .pfnOSCCTRL_1_Handler = (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - .pfnOSCCTRL_2_Handler - = (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, - OSCCTRL_DFLLRDY */ - .pfnOSCCTRL_3_Handler = (void *) - OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - .pfnOSCCTRL_4_Handler = (void *) - OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - .pfnOSC32KCTRL_Handler = (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ - .pfnSUPC_0_Handler = (void *)SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, - SUPC_VCORERDY, SUPC_VREGRDY */ - .pfnSUPC_1_Handler = (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ - .pfnWDT_Handler = (void *)WDT_Handler, /* 10 Watchdog Timer */ - .pfnRTC_Handler = (void *)RTC_Handler, /* 11 Real-Time Counter */ - .pfnEIC_0_Handler = (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */ - .pfnEIC_1_Handler = (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */ - .pfnEIC_2_Handler = (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */ - .pfnEIC_3_Handler = (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */ - .pfnEIC_4_Handler = (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */ - .pfnEIC_5_Handler = (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */ - .pfnEIC_6_Handler = (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */ - .pfnEIC_7_Handler = (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */ - .pfnEIC_8_Handler = (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */ - .pfnEIC_9_Handler = (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */ - .pfnEIC_10_Handler = (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */ - .pfnEIC_11_Handler = (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */ - .pfnEIC_12_Handler = (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */ - .pfnEIC_13_Handler = (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */ - .pfnEIC_14_Handler = (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */ - .pfnEIC_15_Handler = (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */ - .pfnFREQM_Handler = (void *)FREQM_Handler, /* 28 Frequency Meter */ - .pfnNVMCTRL_0_Handler = (void *) - NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, - NVMCTRL_7 */ - .pfnNVMCTRL_1_Handler = (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - .pfnDMAC_0_Handler = (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - .pfnDMAC_1_Handler = (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - .pfnDMAC_2_Handler = (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - .pfnDMAC_3_Handler = (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - .pfnDMAC_4_Handler = (void *)DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, - DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, - DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, - DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, - DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, - DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, - DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, - DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, - DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, - DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, - DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, - DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, - DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, - DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, - DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, - DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, - DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, - DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, - DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, - DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, - DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - .pfnEVSYS_0_Handler = (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ - .pfnEVSYS_1_Handler = (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ - .pfnEVSYS_2_Handler = (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ - .pfnEVSYS_3_Handler = (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ - .pfnEVSYS_4_Handler = (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, - EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, - EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, - EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - .pfnPAC_Handler = (void *)PAC_Handler, /* 41 Peripheral Access Controller */ - .pvReserved42 = (void *)(0UL), /* 42 Reserved */ - .pvReserved43 = (void *)(0UL), /* 43 Reserved */ - .pvReserved44 = (void *)(0UL), /* 44 Reserved */ - .pfnRAMECC_Handler = (void *)RAMECC_Handler, /* 45 RAM ECC */ - .pfnSERCOM0_0_Handler = (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */ - .pfnSERCOM0_1_Handler = (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */ - .pfnSERCOM0_2_Handler = (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */ - .pfnSERCOM0_3_Handler = (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - .pfnSERCOM1_0_Handler = (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */ - .pfnSERCOM1_1_Handler = (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */ - .pfnSERCOM1_2_Handler = (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */ - .pfnSERCOM1_3_Handler = (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - .pfnSERCOM2_0_Handler = (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */ - .pfnSERCOM2_1_Handler = (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */ - .pfnSERCOM2_2_Handler = (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */ - .pfnSERCOM2_3_Handler = (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - .pfnSERCOM3_0_Handler = (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */ - .pfnSERCOM3_1_Handler = (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */ - .pfnSERCOM3_2_Handler = (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */ - .pfnSERCOM3_3_Handler = (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ -#ifdef ID_SERCOM4 - .pfnSERCOM4_0_Handler = (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */ - .pfnSERCOM4_1_Handler = (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */ - .pfnSERCOM4_2_Handler = (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */ - .pfnSERCOM4_3_Handler = (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ -#else - .pvReserved62 = (void *)(0UL), /* 62 Reserved */ - .pvReserved63 = (void *)(0UL), /* 63 Reserved */ - .pvReserved64 = (void *)(0UL), /* 64 Reserved */ - .pvReserved65 = (void *)(0UL), /* 65 Reserved */ -#endif -#ifdef ID_SERCOM5 - .pfnSERCOM5_0_Handler = (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */ - .pfnSERCOM5_1_Handler = (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */ - .pfnSERCOM5_2_Handler = (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */ - .pfnSERCOM5_3_Handler = (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ -#else - .pvReserved66 = (void *)(0UL), /* 66 Reserved */ - .pvReserved67 = (void *)(0UL), /* 67 Reserved */ - .pvReserved68 = (void *)(0UL), /* 68 Reserved */ - .pvReserved69 = (void *)(0UL), /* 69 Reserved */ -#endif -#ifdef ID_SERCOM6 - .pfnSERCOM6_0_Handler = (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */ - .pfnSERCOM6_1_Handler = (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */ - .pfnSERCOM6_2_Handler = (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */ - .pfnSERCOM6_3_Handler = (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ -#else - .pvReserved70 = (void *)(0UL), /* 70 Reserved */ - .pvReserved71 = (void *)(0UL), /* 71 Reserved */ - .pvReserved72 = (void *)(0UL), /* 72 Reserved */ - .pvReserved73 = (void *)(0UL), /* 73 Reserved */ -#endif -#ifdef ID_SERCOM7 - .pfnSERCOM7_0_Handler = (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */ - .pfnSERCOM7_1_Handler = (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */ - .pfnSERCOM7_2_Handler = (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */ - .pfnSERCOM7_3_Handler = (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ -#else - .pvReserved74 = (void *)(0UL), /* 74 Reserved */ - .pvReserved75 = (void *)(0UL), /* 75 Reserved */ - .pvReserved76 = (void *)(0UL), /* 76 Reserved */ - .pvReserved77 = (void *)(0UL), /* 77 Reserved */ -#endif -#ifdef ID_CAN0 - .pfnCAN0_Handler = (void *)CAN0_Handler, /* 78 Control Area Network 0 */ -#else - .pvReserved78 = (void *)(0UL), /* 78 Reserved */ -#endif -#ifdef ID_CAN1 - .pfnCAN1_Handler = (void *)CAN1_Handler, /* 79 Control Area Network 1 */ -#else - .pvReserved79 = (void *)(0UL), /* 79 Reserved */ -#endif -#ifdef ID_USB - .pfnUSB_0_Handler = (void *) - USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, - USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, - USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, - USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, - USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, - USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, - USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, - USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, - USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, - USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, - USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - .pfnUSB_1_Handler = (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */ - .pfnUSB_2_Handler = (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, - USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - .pfnUSB_3_Handler = (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, - USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ -#else - .pvReserved80 = (void *)(0UL), /* 80 Reserved */ - .pvReserved81 = (void *)(0UL), /* 81 Reserved */ - .pvReserved82 = (void *)(0UL), /* 82 Reserved */ - .pvReserved83 = (void *)(0UL), /* 83 Reserved */ -#endif -#ifdef ID_GMAC - .pfnGMAC_Handler = (void *)GMAC_Handler, /* 84 Ethernet MAC */ -#else - .pvReserved84 = (void *)(0UL), /* 84 Reserved */ -#endif - .pfnTCC0_0_Handler = (void *) - TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, - TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - .pfnTCC0_1_Handler = (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */ - .pfnTCC0_2_Handler = (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */ - .pfnTCC0_3_Handler = (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */ - .pfnTCC0_4_Handler = (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */ - .pfnTCC0_5_Handler = (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */ - .pfnTCC0_6_Handler = (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */ - .pfnTCC1_0_Handler = (void *) - TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, - TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - .pfnTCC1_1_Handler = (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */ - .pfnTCC1_2_Handler = (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */ - .pfnTCC1_3_Handler = (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */ - .pfnTCC1_4_Handler = (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */ - .pfnTCC2_0_Handler = (void *) - TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, - TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - .pfnTCC2_1_Handler = (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */ - .pfnTCC2_2_Handler = (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */ - .pfnTCC2_3_Handler = (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */ -#ifdef ID_TCC3 - .pfnTCC3_0_Handler - = (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, - TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - .pfnTCC3_1_Handler = (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */ - .pfnTCC3_2_Handler = (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */ -#else - .pvReserved101 = (void *)(0UL), /* 101 Reserved */ - .pvReserved102 = (void *)(0UL), /* 102 Reserved */ - .pvReserved103 = (void *)(0UL), /* 103 Reserved */ -#endif -#ifdef ID_TCC4 - .pfnTCC4_0_Handler - = (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, - TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - .pfnTCC4_1_Handler = (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */ - .pfnTCC4_2_Handler = (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */ -#else - .pvReserved104 = (void *)(0UL), /* 104 Reserved */ - .pvReserved105 = (void *)(0UL), /* 105 Reserved */ - .pvReserved106 = (void *)(0UL), /* 106 Reserved */ -#endif - .pfnTC0_Handler = (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */ - .pfnTC1_Handler = (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */ - .pfnTC2_Handler = (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */ - .pfnTC3_Handler = (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */ -#ifdef ID_TC4 - .pfnTC4_Handler = (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */ -#else - .pvReserved111 = (void *)(0UL), /* 111 Reserved */ -#endif -#ifdef ID_TC5 - .pfnTC5_Handler = (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */ -#else - .pvReserved112 = (void *)(0UL), /* 112 Reserved */ -#endif -#ifdef ID_TC6 - .pfnTC6_Handler = (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */ -#else - .pvReserved113 = (void *)(0UL), /* 113 Reserved */ -#endif -#ifdef ID_TC7 - .pfnTC7_Handler = (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */ -#else - .pvReserved114 = (void *)(0UL), /* 114 Reserved */ -#endif - .pfnPDEC_0_Handler = (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - .pfnPDEC_1_Handler = (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */ - .pfnPDEC_2_Handler = (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */ - .pfnADC0_0_Handler = (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ - .pfnADC0_1_Handler = (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */ - .pfnADC1_0_Handler = (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ - .pfnADC1_1_Handler = (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */ - .pfnAC_Handler = (void *)AC_Handler, /* 122 Analog Comparators */ - .pfnDAC_0_Handler - = (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - .pfnDAC_1_Handler = (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */ - .pfnDAC_2_Handler = (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */ - .pfnDAC_3_Handler = (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */ - .pfnDAC_4_Handler = (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */ -#ifdef ID_I2S - .pfnI2S_Handler = (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */ -#else - .pvReserved128 = (void *)(0UL), /* 128 Reserved */ -#endif - .pfnPCC_Handler = (void *)PCC_Handler, /* 129 Parallel Capture Controller */ - .pfnAES_Handler = (void *)AES_Handler, /* 130 Advanced Encryption Standard */ - .pfnTRNG_Handler = (void *)TRNG_Handler, /* 131 True Random Generator */ -#ifdef ID_ICM - .pfnICM_Handler = (void *)ICM_Handler, /* 132 Integrity Check Monitor */ -#else - .pvReserved132 = (void *)(0UL), /* 132 Reserved */ -#endif -#ifdef ID_PUKCC - .pfnPUKCC_Handler = (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ -#else - .pvReserved133 = (void *)(0UL), /* 133 Reserved */ -#endif - .pfnQSPI_Handler = (void *)QSPI_Handler, /* 134 Quad SPI interface */ -#ifdef ID_SDHC0 - .pfnSDHC0_Handler = (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ -#else - .pvReserved135 = (void *)(0UL), /* 135 Reserved */ -#endif -#ifdef ID_SDHC1 - .pfnSDHC1_Handler = (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ -#else - .pvReserved136 = (void *)(0UL) /* 136 Reserved */ -#endif -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *)&_sfixed; - SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); - -#if __FPU_USED - /* Enable FPU */ - SCB->CPACR |= (0xFu << 20); - __DSB(); - __ISB(); -#endif - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1) - ; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/software/firmware/project_oracle_base/gcc/system_same54.c b/software/firmware/project_oracle_base/gcc/system_same54.c deleted file mode 100644 index 468990e..0000000 --- a/software/firmware/project_oracle_base/gcc/system_same54.c +++ /dev/null @@ -1,64 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "same54.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/software/firmware/project_oracle_base/hal/documentation/quad_spi_sync.rst b/software/firmware/project_oracle_base/hal/documentation/quad_spi_sync.rst deleted file mode 100644 index a126e62..0000000 --- a/software/firmware/project_oracle_base/hal/documentation/quad_spi_sync.rst +++ /dev/null @@ -1,43 +0,0 @@ -The Quad SPI Synchronous Driver -================================= - -The Quad SPI Interface (QSPI) is a synchronous serial data link that provides -communication with external devices in master mode. - -The driver can be used for SPI serial memory middleware which support flash -earse, program and read. - - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Execute command in Serial Memory Mode - -Applications ------------- - -They are commonly used in an application for using serial flash memory operating -in single-bit SPI, Dual SPI and Quad SPI. - -Dependencies ------------- - -Serial NOR flash with Multiple I/O hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -N.A - -Known issues and workarounds ----------------------------- - -N/A - diff --git a/software/firmware/project_oracle_base/hal/documentation/timer.rst b/software/firmware/project_oracle_base/hal/documentation/timer.rst deleted file mode 100644 index c5ca63d..0000000 --- a/software/firmware/project_oracle_base/hal/documentation/timer.rst +++ /dev/null @@ -1,52 +0,0 @@ -============================ -The Timer driver (bare-bone) -============================ - -The Timer driver provides means for delayed and periodical function invocation. - -A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has -been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a -configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically -changes execution delays and periods for all tasks in the timers task queue. - -A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue -and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on -the period set in the task configuration. -In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to -reuse the memory of expired task in the callback. - -Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. - -Features --------- -* Initialization and de-initialization -* Starting and stopping -* Timer tasks - periodical invocation of functions -* Changing and obtaining of the period of a timer - -Applications ------------- -* Delayed and periodical function execution for middle-ware stacks and applications. - -Dependencies ------------- -* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. - -Concurrency ------------ -The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during -the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed -until the task adding or removing is complete. - -The task queue is not protected from the access by interrupts not used by the driver. Due to this -it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes -the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. - -Limitations ------------ -* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. -* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. - -Knows issues and workarounds ----------------------------- -Not applicable diff --git a/software/firmware/project_oracle_base/hal/include/hal_atomic.h b/software/firmware/project_oracle_base/hal/include/hal_atomic.h deleted file mode 100644 index 82151fc..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_atomic.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_ATOMIC_H_INCLUDED -#define _HAL_ATOMIC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_atomic - * - *@{ - */ - -/** - * \brief Type for the register holding global interrupt enable flag - */ -typedef uint32_t hal_atomic_t; - -/** - * \brief Helper macro for entering critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_enterCritical() function to enter critical - * sections. No semicolon is required after the macro. - * - * \section atomic_usage Usage Example - * \code - * CRITICAL_SECTION_ENTER() - * Critical code - * CRITICAL_SECTION_LEAVE() - * \endcode - */ -#define CRITICAL_SECTION_ENTER() \ - { \ - volatile hal_atomic_t __atomic; \ - atomic_enter_critical(&__atomic); - -/** - * \brief Helper macro for leaving critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_leaveCritical() function to leave critical - * sections. No semicolon is required after the macro. - */ -#define CRITICAL_SECTION_LEAVE() \ - atomic_leave_critical(&__atomic); \ - } - -/** - * \brief Disable interrupts, enter critical section - * - * Disables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[out] atomic The pointer to a variable to store the value of global - * interrupt enable flag - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Exit atomic section - * - * Enables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[in] atomic The pointer to a variable, which stores the latest stored - * value of the global interrupt enable flag - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t atomic_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_cache.h b/software/firmware/project_oracle_base/hal/include/hal_cache.h deleted file mode 100644 index 071486b..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_cache.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * \file - * - * \brief HAL cache functionality implementation. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#ifndef HAL_CACHE_H_ -#define HAL_CACHE_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Enable cache module - * - * \param[in] pointer pointing to the starting address of cache module - * - * \return status of operation - */ -int32_t cache_enable(const void *hw); - -/** - * \brief Disable cache module - * - * \param[in] pointer pointing to the starting address of cache module - * - * \return status of operation - */ -int32_t cache_disable(const void *hw); - -/** - * \brief Initialize cache module - * - * This function initialize cache module configuration. - * - * \return status of operation - */ -int32_t cache_init(void); - -/** - * \brief Configure cache module - * - * \param[in] pointer pointing to the starting address of cache module - * \param[in] cache configuration structure pointer - * - * \return status of operation - */ -int32_t cache_configure(const void *hw, struct _cache_cfg *cache); - -/** - * \brief Invalidate entire cache entries - * - * \param[in] pointer pointing to the starting address of cache module - * - * \return status of operation - */ -int32_t cache_invalidate_all(const void *hw); - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_CACHE_H_ */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_delay.h b/software/firmware/project_oracle_base/hal/include/hal_delay.h deleted file mode 100644 index 9d4aa5c..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_delay.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#ifndef _HAL_DELAY_H_INCLUDED -#define _HAL_DELAY_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_delay Delay Driver - * - *@{ - */ - -/** - * \brief Initialize Delay driver - * - * \param[in] hw The pointer to hardware instance - */ -void delay_init(void *const hw); - -/** - * \brief Perform delay in us - * - * This function performs delay for the given amount of microseconds. - * - * \param[in] us The amount delay in us - */ -void delay_us(const uint16_t us); - -/** - * \brief Perform delay in ms - * - * This function performs delay for the given amount of milliseconds. - * - * \param[in] ms The amount delay in ms - */ -void delay_ms(const uint16_t ms); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t delay_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_gpio.h b/software/firmware/project_oracle_base/hal/include/hal_gpio.h deleted file mode 100644 index fbfa2d4..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_gpio.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ -#ifndef _HAL_GPIO_INCLUDED_ -#define _HAL_GPIO_INCLUDED_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Set gpio pull mode - * - * Set pin pull mode, non existing pull modes throws an fatal assert - * - * \param[in] pin The pin number for device - * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor - * GPIO_PULL_UP = Pull pin high with internal resistor - * GPIO_PULL_OFF = Disable pin pull mode - */ -static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) -{ - _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); -} - -/** - * \brief Set pin function - * - * Select which function a pin will be used for - * - * \param[in] pin The pin number for device - * \param[in] function The pin function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) -{ - _gpio_set_pin_function(pin, function); -} - -/** - * \brief Set port data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - _gpio_set_direction(port, mask, direction); -} - -/** - * \brief Set gpio data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] pin The pin number for device - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) -{ - _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); -} - -/** - * \brief Set port level - * - * Sets output level on the pins defined by the bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply port level to the corresponding - * pin - * \param[in] level true = Pin levels set to "high" state - * false = Pin levels set to "low" state - */ -static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - _gpio_set_level(port, mask, level); -} - -/** - * \brief Set gpio level - * - * Sets output level on a pin - * - * \param[in] pin The pin number for device - * \param[in] level true = Pin level set to "high" state - * false = Pin level set to "low" state - */ -static inline void gpio_set_pin_level(const uint8_t pin, const bool level) -{ - _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); -} - -/** - * \brief Toggle out level on pins - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding - * pin - */ -static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) -{ - _gpio_toggle_level(port, mask); -} - -/** - * \brief Toggle output level on pin - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] pin The pin number for device - */ -static inline void gpio_toggle_pin_level(const uint8_t pin) -{ - _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); -} - -/** - * \brief Get input level on pins - * - * Read the input level on pins connected to a port - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t gpio_get_port_level(const enum gpio_port port) -{ - return _gpio_get_level(port); -} - -/** - * \brief Get level on pin - * - * Reads the level on pins connected to a port - * - * \param[in] pin The pin number for device - */ -static inline bool gpio_get_pin_level(const uint8_t pin) -{ - return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); -} -/** - * \brief Get current driver version - */ -uint32_t gpio_get_version(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/software/firmware/project_oracle_base/hal/include/hal_init.h b/software/firmware/project_oracle_base/hal/include/hal_init.h deleted file mode 100644 index d7bc6fe..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_init.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_INIT_H_INCLUDED -#define _HAL_INIT_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_init Init Driver - * - *@{ - */ - -/** - * \brief Initialize the hardware abstraction layer - * - * This function calls the various initialization functions. - * Currently the following initialization functions are supported: - * - System clock initialization - */ -static inline void init_mcu(void) -{ - _init_chip(); -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t init_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_io.h b/software/firmware/project_oracle_base/hal/include/hal_io.h deleted file mode 100644 index f50401d..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_io.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * \brief I/O related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_IO_INCLUDED -#define _HAL_IO_INCLUDED - -/** - * \addtogroup doc_driver_hal_helper_io I/O Driver - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I/O descriptor - * - * The I/O descriptor forward declaration. - */ -struct io_descriptor; - -/** - * \brief I/O write function pointer type - */ -typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read function pointer type - */ -typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O descriptor - */ -struct io_descriptor { - io_write_t write; /*! The write function pointer. */ - io_read_t read; /*! The read function pointer. */ -}; - -/** - * \brief I/O write interface - * - * This function writes up to \p length of bytes to a given I/O descriptor. - * It returns the number of bytes actually write. - * - * \param[in] descr An I/O descriptor to write - * \param[in] buf The buffer pointer to story the write data - * \param[in] length The number of bytes to write - * - * \return The number of bytes written - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read interface - * - * This function reads up to \p length bytes from a given I/O descriptor, and - * stores it in the buffer pointed to by \p buf. It returns the number of bytes - * actually read. - * - * \param[in] descr An I/O descriptor to read - * \param[in] buf The buffer pointer to story the read data - * \param[in] length The number of bytes to read - * - * \return The number of bytes actually read. This number can be less than the - * requested length. E.g., in a driver that uses ring buffer for - * reception, it may depend on the availability of data in the - * ring buffer. - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_IO_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_qspi_sync.h b/software/firmware/project_oracle_base/hal/include/hal_qspi_sync.h deleted file mode 100644 index de80199..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_qspi_sync.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - * \file - * - * \brief Quad QSPI related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_QSPI_INCLUDED -#define _HAL_QSPI_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_quad_spi_sync - * - *@{ - */ - -/** - * \brief QSPI descriptor structure - */ -struct qspi_sync_descriptor { - struct _qspi_sync_dev dev; -}; - -/** - * \brief Initialize QSPI low level driver. - * - * \param[in] qspi Pointer to the QSPI device instance - * \param[in] hw Pointer to the hardware base - * - * \return Operation status. - * \retval ERR_NONE Success - */ -int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *hw); - -/** - * \brief Deinitialize QSPI low level driver. - * - * \param[in] qspi Pointer to the QSPI device instance - * - * \return Operation status. - * \retval ERR_NONE Success - */ -int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi); - -/** - * \brief Enable QSPI for access without interrupts - * - * \param[in] qspi Pointer to the QSPI device instance - * - * \return Operation status. - * \retval ERR_NONE Success - */ -int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi); - -/** - * \brief Disable QSPI for access without interrupts - * - * Disable QSPI. Deactivate all CS pins if it works as master. - * - * \param[in] qspi Pointer to the QSPI device instance - * - * \return Operation status. - * \retval ERR_NONE Success - */ -int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi); - -/** \brief Execute command in Serial Memory Mode. - * - * \param[in] qspi Pointer to the HAL QSPI instance - * \param[in] cmd Pointer to the command structure - * - * \return Operation status. - * \retval ERR_NONE Success - */ -int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t qspi_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_QSPI_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_sleep.h b/software/firmware/project_oracle_base/hal/include/hal_sleep.h deleted file mode 100644 index b90ef6a..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_sleep.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SLEEP_H_INCLUDED -#define _HAL_SLEEP_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_sleep - * - *@{ - */ - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t sleep_get_version(void); -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_timer.h b/software/firmware/project_oracle_base/hal/include/hal_timer.h deleted file mode 100644 index 47a3948..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_timer.h +++ /dev/null @@ -1,207 +0,0 @@ -/** - * \file - * - * \brief Timer task functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_TIMER_H_INCLUDED -#define _HAL_TIMER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_timer - * - * @{ - */ - -/** - * \brief Timer mode type - */ -enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; - -/** - * \brief Timer task descriptor - * - * The timer task descriptor forward declaration. - */ -struct timer_task; - -/** - * \brief Timer task callback function type - */ -typedef void (*timer_cb_t)(const struct timer_task *const timer_task); - -/** - * \brief Timer task structure - */ -struct timer_task { - struct list_element elem; /*! List element. */ - uint32_t time_label; /*! Absolute timer start time. */ - - uint32_t interval; /*! Number of timer ticks before calling the task. */ - timer_cb_t cb; /*! Function pointer to the task. */ - enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ -}; - -/** - * \brief Timer structure - */ -struct timer_descriptor { - struct _timer_hpl_interface *func; - struct _timer_device device; - uint32_t time; - struct list_descriptor tasks; /*! Timer tasks list. */ - volatile uint8_t flags; -}; - -/** - * \brief Initialize timer - * - * This function initializes the given timer. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[out] descr A timer descriptor to initialize - * \param[in] hw The pointer to the hardware instance - * \param[in] func The pointer to a set of function pointers - * - * \return Initialization status. - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); - -/** - * \brief Deinitialize timer - * - * This function deinitializes the given timer. - * It checks if the given hardware is initialized and if the given hardware is - * permitted to be deinitialized. - * - * \param[in] descr A timer descriptor to deinitialize - * - * \return De-initialization status. - */ -int32_t timer_deinit(struct timer_descriptor *const descr); - -/** - * \brief Start timer - * - * This function starts the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to start - * - * \return Timer starting status. - */ -int32_t timer_start(struct timer_descriptor *const descr); - -/** - * \brief Stop timer - * - * This function stops the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * - * \return Timer stopping status. - */ -int32_t timer_stop(struct timer_descriptor *const descr); - -/** - * \brief Set amount of clock cycles per timer tick - * - * This function sets the amount of clock cycles per timer tick for the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * \param[in] clock_cycles The amount of clock cycles per tick to set - * - * \return Setting clock cycles amount status. - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); - -/** - * \brief Retrieve the amount of clock cycles in a tick - * - * This function retrieves how many clock cycles there are in a single timer tick. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to convert ticks to - * clock cycles - * \param[out] cycles The amount of clock cycles - * - * \return The status of clock cycles retrieving. - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); - -/** - * \brief Add timer task - * - * This function adds the given timer task to the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to add task to - * \param[in] task A task to add - * - * \return Timer's task adding status. - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); - -/** - * \brief Remove timer task - * - * This function removes the given timer task from the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to remove task from - * \param[in] task A task to remove - * - * \return Timer's task removing status. - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t timer_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hal_usart_sync.h b/software/firmware/project_oracle_base/hal/include/hal_usart_sync.h deleted file mode 100644 index 1ef22fc..0000000 --- a/software/firmware/project_oracle_base/hal/include/hal_usart_sync.h +++ /dev/null @@ -1,247 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SYNC_USART_H_INCLUDED -#define _HAL_SYNC_USART_H_INCLUDED - -#include "hal_io.h" -#include - -/** - * \addtogroup doc_driver_hal_usart_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Synchronous USART descriptor - */ -struct usart_sync_descriptor { - struct io_descriptor io; - struct _usart_sync_device device; -}; - -/** - * \brief Initialize USART interface - * - * This function initializes the given I/O descriptor to be used - * as USART interface descriptor. - * It checks if the given hardware is not initialized and - * if the given hardware is permitted to be initialized. - * - * \param[out] descr A USART descriptor which is used to communicate via USART - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to as set of functions pointers - * - * \return Initialization status. - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); - -/** - * \brief Deinitialize USART interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and - * if the given hardware is permitted to be deinitialized. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return De-initialization status. - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); - -/** - * \brief Enable USART interface - * - * Enables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Enabling status. - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); - -/** - * \brief Disable USART interface - * - * Disables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Disabling status. - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve I/O descriptor - * - * This function retrieves the I/O descriptor of the given USART descriptor. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] io An I/O descriptor to retrieve - * - * \return The status of the I/O descriptor retrieving. - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); - -/** - * \brief Specify action for flow control pins - * - * This function sets the action (or state) for the flow control pins - * if the flow control is enabled. - * It sets the state of flow control pins only if the automatic support of - * the flow control is not supported by the hardware. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] state A state to set the flow control pins - * - * \return The status of flow control action setup. - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state); - -/** - * \brief Set USART baud rate - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] baud_rate A baud rate to set - * - * \return The status of baud rate setting. - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); - -/** - * \brief Set USART data order - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] data_order A data order to set - * - * \return The status of data order setting. - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); - -/** - * \brief Set USART mode - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] mode A mode to set - * - * \return The status of mode setting. - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); - -/** - * \brief Set USART parity - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] parity A parity to set - * - * \return The status of parity setting. - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); - -/** - * \brief Set USART stop bits - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] stop_bits Stop bits to set - * - * \return The status of stop bits setting. - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); - -/** - * \brief Set USART character size - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] size A character size to set - * - * \return The status of character size setting. - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins - * if the flow control is enabled. - * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case - * if the flow control is done by the hardware - * and the pins state cannot be read out. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] state The state of flow control pins - * - * \return The status of flow control state reading. - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state); - -/** - * \brief Check if the USART transmitter is empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART TX empty checking. - * \retval 0 The USART transmitter is not empty - * \retval 1 The USART transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Check if the USART receiver is not empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART RX empty checking. - * \retval 1 The USART receiver is not empty - * \retval 0 The USART receiver is empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usart_sync_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_calendar.h b/software/firmware/project_oracle_base/hal/include/hpl_calendar.h deleted file mode 100644 index 187997a..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_calendar.h +++ /dev/null @@ -1,321 +0,0 @@ -/** - * \file - * - * \brief Generic CALENDAR functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_CALENDER_H_INCLUDED -#define _HPL_CALENDER_H_INCLUDED - -#include -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Calendar structure - * - * The Calendar structure forward declaration. - */ -struct calendar_dev; - -/** - * \brief Available mask options for alarms. - * - * Available mask options for alarms. - */ -enum calendar_alarm_option { - /** Alarm disabled. */ - CALENDAR_ALARM_MATCH_DISABLED = 0, - /** Alarm match on second. */ - CALENDAR_ALARM_MATCH_SEC, - /** Alarm match on second and minute. */ - CALENDAR_ALARM_MATCH_MIN, - /** Alarm match on second, minute, and hour. */ - CALENDAR_ALARM_MATCH_HOUR, - /** Alarm match on second, minute, hour, and day. */ - CALENDAR_ALARM_MATCH_DAY, - /** Alarm match on second, minute, hour, day, and month. */ - CALENDAR_ALARM_MATCH_MONTH, - /** Alarm match on second, minute, hour, day, month and year. */ - CALENDAR_ALARM_MATCH_YEAR -}; - -/** - * \brief Available mode for alarms. - */ -enum calendar_alarm_mode { ONESHOT = 1, REPEAT }; -/** - * \brief Prototype of callback on alarm match - */ -typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev); - -/** - * \brief Prototype of callback on tamper detect - */ -typedef void (*tamper_drv_cb_t)(struct calendar_dev *const dev); - -/** - * \brief Structure of Calendar instance - */ -struct calendar_dev { - /** Pointer to the hardware base */ - void *hw; - /** Alarm match callback */ - calendar_drv_cb_alarm_t callback; - /** Tamper callback */ - tamper_drv_cb_t callback_tamper; - /** IRQ struct */ - struct _irq_descriptor irq; -}; -/** - * \brief Time struct for calendar - */ -struct calendar_time { - /*range from 0 to 59*/ - uint8_t sec; - /*range from 0 to 59*/ - uint8_t min; - /*range from 0 to 23*/ - uint8_t hour; -}; - -/** - * \brief Time struct for calendar - */ -struct calendar_date { - /*range from 1 to 28/29/30/31*/ - uint8_t day; - /*range from 1 to 12*/ - uint8_t month; - /*absolute year>= 1970(such as 2000)*/ - uint16_t year; -}; - -/** \brief Calendar driver struct - * - */ -struct calendar_descriptor { - struct calendar_dev device; - struct list_descriptor alarms; - /*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/ - uint32_t base_year; - uint8_t flags; -}; - -/** \brief Date&Time struct for calendar - */ -struct calendar_date_time { - struct calendar_time time; - struct calendar_date date; -}; - -/** \brief struct for alarm time - */ -struct _calendar_alarm { - struct calendar_date_time datetime; - uint32_t timestamp; - enum calendar_alarm_option option; - enum calendar_alarm_mode mode; -}; - -/** \enum for tamper detection mode - */ -enum tamper_detection_mode { TAMPER_MODE_OFF = 0U, TAMPER_MODE_WAKE, TAMPER_MODE_CAPTURE, TAMPER_MODE_ACTL }; - -/** \enum for tamper detection mode - */ -enum tamper_id { TAMPID0 = 0U, TAMPID1, TAMPID2, TAMPID3, TAMPID4 }; -/** - * \brief Initialize Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_init(struct calendar_dev *const dev); - -/** - * \brief Deinitialize Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_deinit(struct calendar_dev *const dev); - -/** - * \brief Enable Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_enable(struct calendar_dev *const dev); - -/** - * \brief Disable Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_disable(struct calendar_dev *const dev); -/** - * \brief Set time for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] p_calendar_time Pointer to the time configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_time(struct calendar_dev *const dev, struct calendar_time *const p_calendar_time); - -/** - * \brief Set date for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] p_calendar_date Pointer to the date configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_date(struct calendar_dev *const dev, struct calendar_date *const p_calendar_date); - -/** - * \brief Get the time for calendar HAL instance and hardware - * Retrieve the time from calendar instance. - * - * \param[in] dev The pointer to calendar device struct - * \param[in] date_time Pointer to value that will be filled with current time - * - * \return Return current counter value - */ -uint32_t _calendar_get_date_time(struct calendar_dev *const dev, struct calendar_date_time *const date_time); - -/** - * \brief Set compare value for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] alarm Pointer to the configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_alarm(struct calendar_dev *const dev, struct _calendar_alarm *const alarm); - -/** - * \brief Register callback for calendar alarm - * - * \param[in] dev The pointer to calendar device struct - * \param[in] callback The pointer to callback function - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback); - -/** - * \brief Set calendar IRQ - * - * \param[in] dev The pointer to calendar device struct - */ -void _calendar_set_irq(struct calendar_dev *const dev); - -/** - * \brief Register callback for tamper detection - * - * \param[in] dev The pointer to calendar device struct - * \param[in] callback The pointer to callback function - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_t callback_tamper); - -/** - * \brief Find tamper is detected on specified pin - * - * \param[in] dev The pointer to calendar device struct - * \param[in] enum Tamper ID number - * - * \return true on detection success and false on failure. - */ -bool _is_tamper_detected(struct calendar_dev *const dev, enum tamper_id tamper_id_pin); - -/** - * \brief brief Clear the Tamper ID flag - * - * \param[in] dev The pointer to calendar device struct - * \param[in] enum Tamper ID number - * - * \return ERR_NONE - */ -int32_t _tamper_clear_tampid_flag(struct calendar_dev *const dev, enum tamper_id tamper_id_pin); - -/** - * \brief Enable Debounce Asynchronous Feature - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _tamper_enable_debounce_asynchronous(struct calendar_dev *const dev); - -/** - * \brief Disable Tamper Debounce Asynchronous Feature - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _tamper_disable_debounce_asynchronous(struct calendar_dev *const dev); - -/** - * \brief Enable Tamper Debounce Majority Feature - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _tamper_enable_debounce_majority(struct calendar_dev *const dev); - -/** - * \brief Enable Tamper Debounce Majority Feature - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _tamper_disable_debounce_majority(struct calendar_dev *const dev); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_RTC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_cmcc.h b/software/firmware/project_oracle_base/hal/include/hpl_cmcc.h deleted file mode 100644 index cb26091..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_cmcc.h +++ /dev/null @@ -1,277 +0,0 @@ -/** - * \file - * - * \brief Generic CMCC(Cortex M Cache Controller) related functionality. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#ifndef HPL_CMCC_H_ -#define HPL_CMCC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * \Cache driver MACROS - */ -#define CMCC_DISABLE 0U -#define CMCC_ENABLE 1U -#define IS_CMCC_DISABLED 0U -#define IS_CMCC_ENABLED 1U -#define CMCC_WAY_NOS 4U -#define CMCC_LINE_NOS 64U -#define CMCC_MONITOR_DISABLE 0U - -/** - * \brief Cache size configurations - */ -enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB }; - -/** - * \brief Way Numbers - */ -enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 }; - -/** - * \brief Cache monitor configurations - */ -enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT }; - -/** - * \brief Cache configuration structure - */ -struct _cache_cfg { - enum conf_cache_size cache_size; - bool data_cache_disable; - bool inst_cache_disable; - bool gclk_gate_disable; -}; - -/** - * \brief Cache enable status - */ -static inline bool _is_cache_enabled(const void *hw) -{ - return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false); -} - -/** - * \brief Cache disable status - */ -static inline bool _is_cache_disabled(const void *hw) -{ - return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false); -} - -/** - * \brief Cache enable - */ -static inline int32_t _cmcc_enable(const void *hw) -{ - int32_t return_value; - - if (_is_cache_disabled(hw)) { - hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN); - return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE; - } else { - return_value = ERR_NO_CHANGE; - } - - return return_value; -} - -/** - * \brief Cache disable - */ -static inline int32_t _cmcc_disable(const void *hw) -{ - hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos)); - while (!(_is_cache_disabled(hw))) - ; - - return ERR_NONE; -} - -/** - * \brief Initialize Cache Module - * - * This function initialize low level cmcc module configuration. - * - * \return initialize status - */ -int32_t _cmcc_init(void); - -/** - * \brief Configure CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] cache configuration structure pointer - * - * \return status of operation - */ -int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl); - -/** - * \brief Enable data cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache - * - * \return status of operation - */ -int32_t _cmcc_enable_data_cache(const void *hw, bool value); - -/** - * \brief Enable instruction cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache - * - * \return status of operation - */ -int32_t _cmcc_enable_inst_cache(const void *hw, bool value); - -/** - * \brief Enable clock gating in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate - * - * \return status of operation - */ -int32_t _cmcc_enable_clock_gating(const void *hw, bool value); - -/** - * \brief Configure the cache size in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache size configuration enumerator - * 0->1K, 1->2K, 2->4K(default) - * - * \return status of operation - */ -int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size); - -/** - * \brief Lock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_lock_way(const void *hw, enum way_num_index); - -/** - * \brief Unlock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_unlock_way(const void *hw, enum way_num_index); - -/** - * \brief Invalidate the mentioned cache line in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num" enumerator (valid arg is 0-3) - * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) - * - * \return status of operation - */ -int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num); - -/** - * \brief Invalidate entire cache entries in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_invalidate_all(const void *hw); - -/** - * \brief Configure cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache monitor configurations enumerator - * - * \return status of operation - */ -int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg); - -/** - * \brief Enable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_enable_monitor(const void *hw); - -/** - * \brief Disable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_disable_monitor(const void *hw); - -/** - * \brief Reset cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_reset_monitor(const void *hw); - -/** - * \brief Get cache monitor event counter value from CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return event counter value - */ -uint32_t _cmcc_get_monitor_event_count(const void *hw); - -#ifdef __cplusplus -} -#endif -#endif /* HPL_CMCC_H_ */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_core.h b/software/firmware/project_oracle_base/hal/include/hpl_core.h deleted file mode 100644 index 9324c43..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_core.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief CPU core related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_H_INCLUDED -#define _HPL_CORE_H_INCLUDED - -/** - * \addtogroup HPL Core - * - * \section hpl_core_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_core_port.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_delay.h b/software/firmware/project_oracle_base/hal/include/hpl_delay.h deleted file mode 100644 index a0f1ac8..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_delay.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * \brief Delay related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DELAY_H_INCLUDED -#define _HPL_DELAY_H_INCLUDED - -/** - * \addtogroup HPL Delay - * - * \section hpl_delay_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Initialize delay functionality - * - * \param[in] hw The pointer to hardware instance - */ -void _delay_init(void *const hw); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - * - * \param[in] us The amount of us to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_us(const uint16_t us); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - * - * \param[in] ms The amount of ms to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_ms(const uint16_t ms); - -/** - * \brief Delay loop to delay n number of cycles - * - * \param[in] hw The pointer to hardware instance - * \param[in] cycles The amount of cycles to delay for - */ -void _delay_cycles(void *const hw, uint32_t cycles); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_dma.h b/software/firmware/project_oracle_base/hal/include/hpl_dma.h deleted file mode 100644 index 1e08434..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_dma.h +++ /dev/null @@ -1,176 +0,0 @@ -/** - * \file - * - * \brief DMA related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DMA_H_INCLUDED -#define _HPL_DMA_H_INCLUDED - -/** - * \addtogroup HPL DMA - * - * \section hpl_dma_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct _dma_resource; - -/** - * \brief DMA callback types - */ -enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; - -/** - * \brief DMA interrupt callbacks - */ -struct _dma_callbacks { - void (*transfer_done)(struct _dma_resource *resource); - void (*error)(struct _dma_resource *resource); -}; - -/** - * \brief DMA resource structure - */ -struct _dma_resource { - struct _dma_callbacks dma_cb; - void * back; -}; - -/** - * \brief Initialize DMA - * - * This function does low level DMA configuration. - * - * \return initialize status - */ -int32_t _dma_init(void); - -/** - * \brief Set destination address - * - * \param[in] channel DMA channel to set destination address for - * \param[in] dst Destination address - * - * \return setting status - */ -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); - -/** - * \brief Set source address - * - * \param[in] channel DMA channel to set source address for - * \param[in] src Source address - * - * \return setting status - */ -int32_t _dma_set_source_address(const uint8_t channel, const void *const src); - -/** - * \brief Set next descriptor address - * - * \param[in] current_channel Current DMA channel to set next descriptor address - * \param[in] next_channel Next DMA channel used as next descriptor - * - * \return setting status - */ -int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); - -/** - * \brief Enable/disable source address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set source address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); - -/** - * \brief Enable/disable Destination address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set destination address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); -/** - * \brief Set the amount of data to be transfered per transaction - * - * \param[in] channel DMA channel to set data amount for - * \param[in] amount Data amount - * - * \return status of operation - */ -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); - -/** - * \brief Trigger DMA transaction on the given channel - * - * \param[in] channel DMA channel to trigger transaction on - * - * \return status of operation - */ -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); - -/** - * \brief Retrieves DMA resource structure - * - * \param[out] resource The resource to be retrieved - * \param[in] channel DMA channel to retrieve structure for - * - * \return status of operation - */ -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); - -/** - * \brief Enable/disable DMA interrupt - * - * \param[in] channel DMA channel to enable/disable interrupt for - * \param[in] type The type of interrupt to disable/enable if applicable - * \param[in] state Enable or disable - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); - -#ifdef __cplusplus -} -#endif - -#endif /* HPL_DMA_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_gpio.h b/software/firmware/project_oracle_base/hal/include/hpl_gpio.h deleted file mode 100644 index 5cdd387..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_gpio.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief Port related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GPIO_H_INCLUDED -#define _HPL_GPIO_H_INCLUDED - -/** - * \addtogroup HPL Port - * - * \section hpl_port_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif -/** - * \brief Macros for the pin and port group, lower 5 - * bits stands for pin number in the group, higher 3 - * bits stands for port group - */ -#define GPIO_PIN(n) (((n)&0x1Fu) << 0) -#define GPIO_PORT(n) ((n) >> 5) -#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) -#define GPIO_PIN_FUNCTION_OFF 0xffffffff - -/** - * \brief PORT pull mode settings - */ -enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; - -/** - * \brief PORT direction settins - */ -enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; - -/** - * \brief PORT group abstraction - */ - -enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Port initialization function - * - * Port initialization function should setup the port module based - * on a static configuration file, this function should normally - * not be called directly, but is a part of hal_init() - */ -void _gpio_init(void); - -/** - * \brief Set direction on port with mask - * - * Set data direction for each pin, or disable the pin - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input - * and disable input buffer to disable the pin - * GPIO_DIRECTION_IN = set pin direction to input - * and enable input buffer to enable the pin - * GPIO_DIRECTION_OUT = set pin direction to output - * and disable input buffer - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction); - -/** - * \brief Set output level on port with mask - * - * Sets output state on pin to high or low with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - * \param[in] level true = pin level is set to 1 - * false = pin level is set to 0 - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); - -/** - * \brief Change output level to the opposite with mask - * - * Change pin output level to the opposite with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); - -/** - * \brief Get input levels on all port pins - * - * Get input level on all port pins, will read IN register if configured to - * input and OUT register if configured as output - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port); - -/** - * \brief Set pin pull mode - * - * Set pull mode on a single pin - * - * \notice This function will automatically change pin direction to input - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] pin The pin in the group that pull mode should be selected - * for - * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled - * GPIO_PULL_DOWN = pull resistor on pin will pull pin - * level to ground level - * GPIO_PULL_UP = pull resistor on pin will pull pin - * level to VCC - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode); - -/** - * \brief Set gpio function - * - * Select which function a gpio is used for - * - * \param[in] gpio The gpio to set function for - * \param[in] function The gpio function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); - -#include -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_i2c_m_async.h b/software/firmware/project_oracle_base/hal/include/hpl_i2c_m_async.h deleted file mode 100644 index 8a9491d..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_i2c_m_async.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED -#define _HPL_I2C_M_ASYNC_H_INCLUDED - -#include "hpl_i2c_m_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c master callback names - */ -enum _i2c_m_async_callback_type { - I2C_M_ASYNC_DEVICE_ERROR, - I2C_M_ASYNC_DEVICE_TX_COMPLETE, - I2C_M_ASYNC_DEVICE_RX_COMPLETE -}; - -struct _i2c_m_async_device; - -typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); -typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); - -/** - * \brief i2c callback pointers structure - */ -struct _i2c_m_async_callback { - _i2c_error_cb_t error; - _i2c_complete_cb_t tx_complete; - _i2c_complete_cb_t rx_complete; -}; - -/** - * \brief i2c device structure - */ -struct _i2c_m_async_device { - struct _i2c_m_service service; - void * hw; - struct _i2c_m_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C in interrupt mode - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c interrupt device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C in interrupt mode - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Register callback to I2C - * - * This function does low level I2C callback register. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] cb_type The callback type request - * \param[in] func The callback function pointer - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, - FUNC_PTR func); - -/** - * \brief Generate stop condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Operation status - * \retval 0 Operation executed successfully - * \retval <0 Operation failed - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Returns the number of bytes left or not used in the I2C message buffer - * - * This function will return the number of bytes left (not written to the bus) or still free - * (not received from the bus) in the message buffer, depending on direction of transmission. - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Number of bytes or error code - * \retval >0 Positive number indicating bytes left - * \retval 0 Buffer is full/empty depending on direction - * \retval <0 Error code - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable/disable I2C master interrupt - * - * param[in] device The pointer to I2C master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/software/firmware/project_oracle_base/hal/include/hpl_i2c_m_sync.h b/software/firmware/project_oracle_base/hal/include/hpl_i2c_m_sync.h deleted file mode 100644 index ce173ae..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_i2c_m_sync.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_SYNC_H_INCLUDED -#define _HPL_I2C_M_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c flags - */ -#define I2C_M_RD 0x0001 /* read data, from slave to master */ -#define I2C_M_BUSY 0x0100 -#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ -#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ -#define I2C_M_FAIL 0x1000 -#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ - -/** - * \brief i2c Return codes - */ -#define I2C_OK 0 /* Operation successful */ -#define I2C_ACK -1 /* Received ACK from device on I2C bus */ -#define I2C_NACK -2 /* Received NACK from device on I2C bus */ -#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ -#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ -#define I2C_ERR_BUS -5 /* Bus error */ -#define I2C_ERR_BUSY -6 /* Device busy */ -#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ - -/** - * \brief i2c I2C Modes - */ -#define I2C_STANDARD_MODE 0x00 -#define I2C_FASTMODE 0x01 -#define I2C_HIGHSPEED_MODE 0x02 - -/** - * \brief i2c master message structure - */ -struct _i2c_m_msg { - uint16_t addr; - volatile uint16_t flags; - int32_t len; - uint8_t * buffer; -}; - -/** - * \brief i2c master service - */ -struct _i2c_m_service { - struct _i2c_m_msg msg; - uint16_t mode; - uint16_t trise; -}; - -/** - * \brief i2c sync master device structure - */ -struct _i2c_m_sync_device { - struct _i2c_m_service service; - void * hw; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Send send condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_dev The pointer to i2c device struct - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/software/firmware/project_oracle_base/hal/include/hpl_i2c_s_async.h b/software/firmware/project_oracle_base/hal/include/hpl_i2c_s_async.h deleted file mode 100644 index 92a5765..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_i2c_s_async.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED -#define _HPL_I2C_S_ASYNC_H_INCLUDED - -#include "hpl_i2c_s_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c callback types - */ -enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; - -/** - * \brief Forward declaration of I2C Slave device - */ -struct _i2c_s_async_device; - -/** - * \brief i2c slave callback function type - */ -typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); - -/** - * \brief i2c slave callback pointers structure - */ -struct _i2c_s_async_callback { - void (*error)(struct _i2c_s_async_device *const device); - void (*tx)(struct _i2c_s_async_device *const device); - void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); -}; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_async_device { - void * hw; - struct _i2c_s_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize asynchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c interrupt device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); - -/** - * \brief Deinitialize asynchronous I2C in interrupt mode - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); - -/** - * \brief Abort data transmission - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); - -/** - * \brief Enable/disable I2C slave interrupt - * - * param[in] device The pointer to I2C slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool disable); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_i2c_s_sync.h b/software/firmware/project_oracle_base/hal/include/hpl_i2c_s_sync.h deleted file mode 100644 index 93b5934..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_i2c_s_sync.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_SYNC_H_INCLUDED -#define _HPL_I2C_S_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I2C Slave status type - */ -typedef uint32_t i2c_s_status_t; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_sync_device { - void *hw; -}; - -#include - -/** - * \name HPL functions - */ - -/** - * \brief Initialize synchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize synchronous I2C slave - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); - -/** - * \brief Clear the Data Ready interrupt flag - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); - -/** - * \brief Read a byte from the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Data received via I2C interface. - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if I2C is ready to send next byte - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the ready check. - * \retval true if the I2C is ready to send next byte - * \retval false if the I2C is not ready to send next byte - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if there is data received by I2C - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the data received check. - * \retval true if the I2C has received a byte - * \retval false if the I2C has not received a byte - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_init.h b/software/firmware/project_oracle_base/hal/include/hpl_init.h deleted file mode 100644 index 71bf49c..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_init.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * \file - * - * \brief Init related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_INIT_H_INCLUDED -#define _HPL_INIT_H_INCLUDED - -/** - * \addtogroup HPL Init - * - * \section hpl_init_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initializes clock sources - */ -void _sysctrl_init_sources(void); - -/** - * \brief Initializes Power Manager - */ -void _pm_init(void); - -/** - * \brief Initialize generators - */ -void _gclk_init_generators(void); - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void); - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _sysctrl_init_referenced_generators(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _oscctrl_init_referenced_generators(void); - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void); - -/** - * \brief Initialize clock generator - */ -void _lpmcu_misc_regs_init(void); - -/** - * \brief Initialize clock generator - */ -void _pmc_init(void); - -/** - * \brief Set performance level - * - * \param[in] level The performance level to set - */ -void _set_performance_level(const uint8_t level); - -/** - * \brief Initialize the chip - */ -void _init_chip(void); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_irq.h b/software/firmware/project_oracle_base/hal/include/hpl_irq.h deleted file mode 100644 index 2894944..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_irq.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * \file - * - * \brief IRQ related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_IRQ_H_INCLUDED -#define _HPL_IRQ_H_INCLUDED - -/** - * \addtogroup HPL IRQ - * - * \section hpl_irq_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief IRQ descriptor - */ -struct _irq_descriptor { - void (*handler)(void *parameter); - void *parameter; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve current IRQ number - * - * \return The current IRQ number - */ -uint8_t _irq_get_current(void); - -/** - * \brief Disable the given IRQ - * - * \param[in] n The number of IRQ to disable - */ -void _irq_disable(uint8_t n); - -/** - * \brief Set the given IRQ - * - * \param[in] n The number of IRQ to set - */ -void _irq_set(uint8_t n); - -/** - * \brief Clear the given IRQ - * - * \param[in] n The number of IRQ to clear - */ -void _irq_clear(uint8_t n); - -/** - * \brief Enable the given IRQ - * - * \param[in] n The number of IRQ to enable - */ -void _irq_enable(uint8_t n); - -/** - * \brief Register IRQ handler - * - * \param[in] number The number registered IRQ - * \param[in] irq The pointer to irq handler to register - * - * \return The status of IRQ handler registering - * \retval -1 Passed parameters were invalid - * \retval 0 The registering is completed successfully - */ -void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_missing_features.h b/software/firmware/project_oracle_base/hal/include/hpl_missing_features.h deleted file mode 100644 index 7071db2..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_missing_features.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - * \file - * - * \brief Family-dependent missing features expected by HAL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_MISSING_FEATURES -#define _HPL_MISSING_FEATURES - -#endif /* _HPL_MISSING_FEATURES */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_pwm.h b/software/firmware/project_oracle_base/hal/include/hpl_pwm.h deleted file mode 100644 index ff87052..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_pwm.h +++ /dev/null @@ -1,193 +0,0 @@ -/** - * \file - * - * \brief PWM related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_PWM_H_INCLUDED -#define _HPL_PWM_H_INCLUDED - -/** - * \addtogroup HPL PWM - * - * \section hpl_pwm_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief PWM callback types - */ -enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; - -/** - * \brief PWM pulse-width period - */ -typedef uint32_t pwm_period_t; - -/** - * \brief PWM device structure - * - * The PWM device structure forward declaration. - */ -struct _pwm_device; - -/** - * \brief PWM interrupt callbacks - */ -struct _pwm_callback { - void (*pwm_period_cb)(struct _pwm_device *device); - void (*pwm_error_cb)(struct _pwm_device *device); -}; - -/** - * \brief PWM descriptor device structure - */ -struct _pwm_device { - struct _pwm_callback callback; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief PWM functions, pointers to low-level functions - */ -struct _pwm_hpl_interface { - int32_t (*init)(struct _pwm_device *const device, void *const hw); - void (*deinit)(struct _pwm_device *const device); - void (*start_pwm)(struct _pwm_device *const device); - void (*stop_pwm)(struct _pwm_device *const device); - void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - bool (*is_pwm_enabled)(const struct _pwm_device *const device); - pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); - uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); - void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); -}; -/** - * \brief Initialize TC - * - * This function does low level TC configuration. - * - * \param[in] device The pointer to PWM device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _pwm_init(struct _pwm_device *const device, void *const hw); - -/** - * \brief Deinitialize TC - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_deinit(struct _pwm_device *const device); - -/** - * \brief Retrieve offset of the given tc hardware instance - * - * \param[in] device The pointer to PWM device instance - * - * \return The offset of the given tc hardware instance - */ -uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); - -/** - * \brief Start hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_enable(struct _pwm_device *const device); - -/** - * \brief Stop hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_disable(struct _pwm_device *const device); - -/** - * \brief Set pwm parameter - * - * \param[in] device The pointer to PWM device instance - * \param[in] period Total period of one PWM cycle. - * \param[in] duty_cycle Period of PWM first half during one cycle. - */ -void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - -/** - * \brief Check if pwm is working - * - * \param[in] device The pointer to PWM device instance - * - * \return Check status. - * \retval true The given pwm is working - * \retval false The given pwm is not working - */ -bool _pwm_is_enabled(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform period value - * - * \param[in] device The pointer to PWM device instance - * - * \return Period value. - */ -pwm_period_t _pwm_get_period(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform duty cycle value - * - * \param[in] device The pointer to PWM device instance - * - * \return Duty cycle value - */ -uint32_t _pwm_get_duty(const struct _pwm_device *const device); - -/** - * \brief Enable/disable PWM interrupt - * - * param[in] device The pointer to PWM device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_qspi.h b/software/firmware/project_oracle_base/hal/include/hpl_qspi.h deleted file mode 100644 index f95ac3b..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_qspi.h +++ /dev/null @@ -1,149 +0,0 @@ -/** - * \file - * - * \brief Quad SPI related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_QSPI_H_INCLUDED -#define _HPL_QSPI_H_INCLUDED - -#include "compiler.h" - -/** - * \addtogroup hpl_qspi HPL QSPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Qspi access modes - */ -enum qspi_access { - /* Read access */ - QSPI_READ_ACCESS = 0, - /* Read memory access */ - QSPI_READMEM_ACCESS, - /* Write access */ - QSPI_WRITE_ACCESS, - /* Write memory access */ - QSPI_WRITEMEM_ACCESS -}; - -/** - * \brief QSPI command instruction/address/data width - */ -enum qspi_cmd_width { - /** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */ - QSPI_INST1_ADDR1_DATA1, - /** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */ - QSPI_INST1_ADDR1_DATA2, - /** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */ - QSPI_INST1_ADDR1_DATA4, - /** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */ - QSPI_INST1_ADDR2_DATA2, - /** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */ - QSPI_INST1_ADDR4_DATA4, - /** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */ - QSPI_INST2_ADDR2_DATA2, - /** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */ - QSPI_INST4_ADDR4_DATA4 -}; - -/** - * \brief QSPI command option code length in bits - */ -enum qspi_cmd_opt_len { - /** The option code is 1 bit long */ - QSPI_OPT_1BIT, - /** The option code is 2 bits long */ - QSPI_OPT_2BIT, - /** The option code is 4 bits long */ - QSPI_OPT_4BIT, - /** The option code is 8 bits long */ - QSPI_OPT_8BIT -}; - -/** - * \brief Qspi command structure - */ -struct _qspi_command { - union { - struct { - /* Width of QSPI Addr , inst data */ - uint32_t width : 3; - /* Reserved */ - uint32_t reserved0 : 1; - /* Enable Instruction */ - uint32_t inst_en : 1; - /* Enable Address */ - uint32_t addr_en : 1; - /* Enable Option */ - uint32_t opt_en : 1; - /* Enable Data */ - uint32_t data_en : 1; - /* Option Length */ - uint32_t opt_len : 2; - /* Address Length */ - uint32_t addr_len : 1; - /* Option Length */ - uint32_t reserved1 : 1; - /* Transfer type */ - uint32_t tfr_type : 2; - /* Continuous read mode */ - uint32_t continues_read : 1; - /* Enable Double Data Rate */ - uint32_t ddr_enable : 1; - /* Dummy Cycles Length */ - uint32_t dummy_cycles : 5; - /* Reserved */ - uint32_t reserved3 : 11; - } bits; - uint32_t word; - } inst_frame; - - uint8_t instruction; - uint8_t option; - uint32_t address; - - size_t buf_len; - const void *tx_buf; - void * rx_buf; -}; - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_QSPI_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_qspi_dma.h b/software/firmware/project_oracle_base/hal/include/hpl_qspi_dma.h deleted file mode 100644 index 7c6019a..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_qspi_dma.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief Quad SPI dma related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_QSPI_DMA_H_INCLUDED -#define _HPL_QSPI_DMA_H_INCLUDED - -#include -#include "hpl_irq.h" -#include "hpl_dma.h" - -/** - * \addtogroup hpl_qspi_dma HPL QSPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** The callback types */ -enum _qspi_dma_cb_type { - /** Callback type for DMA transfer done */ - QSPI_DMA_CB_XFER_DONE, - /** Callback type for DMA errors */ - QSPI_DMA_CB_ERROR, -}; - -/** - * \brief QSPI DMA callback type - */ -typedef void (*_qspi_dma_cb_t)(struct _dma_resource *resource); - -/** - * \brief The callbacks offered by QSPI driver - */ -struct _qspi_dma_callbacks { - _qspi_dma_cb_t xfer_done; - _qspi_dma_cb_t error; -}; - -/** - * QSPI dma driver instance. - */ -struct _qspi_dma_dev { - /** Pointer to private data or hardware base */ - void *prvt; - /** - * Pointer to the callback functions so that initialize the driver to - * handle interrupts. - */ - struct _qspi_dma_callbacks cb; - /** DMA resource */ - struct _dma_resource *resource; -}; - -/** - * \brief Initialize QSPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the QSPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw); - -/** - * \brief Deinitialize QSPI - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the QSPI device instance. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev); - -/** - * \brief Enable QSPI for access without interrupts - * \param[in, out] dev Pointer to the QSPI device instance. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev); - -/** - * \brief Disable QSPI for access without interrupts - * \param[in, out] dev Pointer to the QSPI device instance. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev); - -/** - * \brief Execute command in Serial Memory Mode. - * - * \param[in] dev The pointer to QSPI device instance - * \param[in] cmd The pointer to the command information - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd); - -/** - * \brief Register the QSPI device callback - * \param[in] dev Pointer to the SPI device instance. - * \param[in] type The callback type. - * \param[in] cb The callback function to register. NULL to disable callback. - * \return Always 0. - */ -void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_QSPI_DMA_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_qspi_sync.h b/software/firmware/project_oracle_base/hal/include/hpl_qspi_sync.h deleted file mode 100644 index 6958e10..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_qspi_sync.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - * \file - * - * \brief Quad SPI Sync related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_QSPI_SYNC_H_INCLUDED -#define _HPL_QSPI_SYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_qspi HPL QSPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Quad SPI polling driver instance. */ -struct _qspi_sync_dev { - /** Pointer to private data or hardware base */ - void *prvt; -}; - -/** - * \brief Initialize QSPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the QSPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw); - -/** - * \brief Deinitialize QSPI - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the QSPI device instance. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev); - -/** - * \brief Enable QSPI for access without interrupts - * \param[in, out] dev Pointer to the QSPI device instance. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev); - -/** - * \brief Disable QSPI for access without interrupts - * \param[in, out] dev Pointer to the QSPI device instance. - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev); - -/** - * \brief Execute command in Serial Memory Mode. - * - * \param[in] dev The pointer to QSPI device instance - * \param[in] cmd The pointer to the command information - * \return Operation status. - * \retval ERR_NONE Operation done successfully. - */ -int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_QSPI_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_ramecc.h b/software/firmware/project_oracle_base/hal/include/hpl_ramecc.h deleted file mode 100644 index d79d514..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_ramecc.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * \file - * - * \brief RAMECC related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RAMECC_H_INCLUDED -#define _HPL_RAMECC_H_INCLUDED - -/** - * \addtogroup HPL RAMECC - * - * \section hpl_ramecc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief RAMECC callback type - */ -typedef void (*ramecc_cb_t)(const uint32_t data); - -/** - * \brief RAMECC callback types - */ -enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; - -/** - * \brief RAMECC interrupt callbacks - */ -struct _ramecc_callbacks { - ramecc_cb_t dual_bit_err; - ramecc_cb_t single_bit_err; -}; - -/** - * \brief RAMECC device structure - */ -struct _ramecc_device { - struct _ramecc_callbacks ramecc_cb; - struct _irq_descriptor irq; -}; - -/** - * \brief Initialize RAMECC - * - * This function does low level RAMECC configuration. - * - * \return initialize status - */ -int32_t _ramecc_init(void); - -/** - * \brief Register RAMECC callback - * - * \param[in] type The type of callback - * \param[in] cb A callback function - */ -void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_RAMECC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_reset.h b/software/firmware/project_oracle_base/hal/include/hpl_reset.h deleted file mode 100644 index d627ea6..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_reset.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file - * - * \brief Reset related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RESET_H_INCLUDED -#define _HPL_RESET_H_INCLUDED - -/** - * \addtogroup HPL Reset - * - * \section hpl_reset_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Reset reason enumeration - * - * The list of possible reset reasons. - */ -enum reset_reason { - RESET_REASON_POR = 1, - RESET_REASON_BOD12 = 2, - RESET_REASON_BOD33 = 4, - RESET_REASON_NVM = 8, - RESET_REASON_EXT = 16, - RESET_REASON_WDT = 32, - RESET_REASON_SYST = 64, - RESET_REASON_BACKUP = 128 -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve the reset reason - * - * Retrieves the reset reason of the last MCU reset. - * - *\return An enum value indicating the reason of the last reset. - */ -enum reset_reason _get_reset_reason(void); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_sleep.h b/software/firmware/project_oracle_base/hal/include/hpl_sleep.h deleted file mode 100644 index 6731ec3..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_sleep.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SLEEP_H_INCLUDED -#define _HPL_SLEEP_H_INCLUDED - -/** - * \addtogroup HPL Sleep - * - * \section hpl_sleep_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Set the sleep mode for the device - * - * This function sets the sleep mode for the device. - * For an overview of which systems are disabled in sleep for the different - * sleep modes see datasheet. - * - * \param[in] mode Sleep mode to use - * - * \return the status of a sleep request - * \retval -1 The requested sleep mode was invalid - * \retval 0 The operation completed successfully, sleep mode is set - */ -int32_t _set_sleep_mode(const uint8_t mode); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi.h b/software/firmware/project_oracle_base/hal/include/hpl_spi.h deleted file mode 100644 index a5652e5..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_H_INCLUDED -#define _HPL_SPI_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SPI Dummy char is used when reading data from the SPI slave - */ -#define SPI_DUMMY_CHAR 0x1ff - -/** - * \brief SPI message to let driver to process - */ -//@{ -struct spi_msg { - /** Pointer to the output data buffer */ - uint8_t *txbuf; - /** Pointer to the input data buffer */ - uint8_t *rxbuf; - /** Size of the message data in SPI characters */ - uint32_t size; -}; -//@} - -/** - * \brief SPI transfer modes - * SPI transfer mode controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - */ -enum spi_transfer_mode { - /** Leading edge is rising edge, data sample on leading edge. */ - SPI_MODE_0, - /** Leading edge is rising edge, data sample on trailing edge. */ - SPI_MODE_1, - /** Leading edge is falling edge, data sample on leading edge. */ - SPI_MODE_2, - /** Leading edge is falling edge, data sample on trailing edge. */ - SPI_MODE_3 -}; - -/** - * \brief SPI character sizes - * The character size influence the way the data is sent/received. - * For char size <= 8 data is stored byte by byte. - * For char size between 9 ~ 16 data is stored in 2-byte length. - * Note that the default and recommended char size is 8 bit since it's - * supported by all system. - */ -enum spi_char_size { - /** Character size is 8 bit. */ - SPI_CHAR_SIZE_8 = 0, - /** Character size is 9 bit. */ - SPI_CHAR_SIZE_9 = 1, - /** Character size is 10 bit. */ - SPI_CHAR_SIZE_10 = 2, - /** Character size is 11 bit. */ - SPI_CHAR_SIZE_11 = 3, - /** Character size is 12 bit. */ - SPI_CHAR_SIZE_12 = 4, - /** Character size is 13 bit. */ - SPI_CHAR_SIZE_13 = 5, - /** Character size is 14 bit. */ - SPI_CHAR_SIZE_14 = 6, - /** Character size is 15 bit. */ - SPI_CHAR_SIZE_15 = 7, - /** Character size is 16 bit. */ - SPI_CHAR_SIZE_16 = 8 -}; - -/** - * \brief SPI data order - */ -enum spi_data_order { - /** MSB goes first. */ - SPI_DATA_ORDER_MSB_1ST = 0, - /** LSB goes first. */ - SPI_DATA_ORDER_LSB_1ST = 1 -}; - -/** \brief Transfer descriptor for SPI - * Transfer descriptor holds TX and RX buffers - */ -struct spi_xfer { - /** Pointer to data buffer to TX */ - uint8_t *txbuf; - /** Pointer to data buffer to RX */ - uint8_t *rxbuf; - /** Size of data characters to TX & RX */ - uint32_t size; -}; - -/** SPI generic driver. */ -struct spi_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Reference start of sync/async variables */ - uint32_t sync_async_misc[1]; -}; - -/** - * \brief Calculate the baudrate value for hardware to use to set baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] clk Clock frequency (Hz) for baudrate generation. - * \param[in] baud Target baudrate (bps). - * \return Error or baudrate value. - * \retval >0 Baudrate value. - * \retval ERR_INVALID_ARG Calculation fail. - */ -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi_async.h b/software/firmware/project_oracle_base/hal/include/hpl_spi_async.h deleted file mode 100644 index 8e5a848..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi_async.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_ASYNC_H_INCLUDED -#define _HPL_SPI_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Callbacks the SPI driver must offer in async mode - */ -//@{ -/** The callback types */ -enum _spi_async_dev_cb_type { - /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_TX, - /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_RX, - /** Callback type for \ref _spi_async_dev_cb_complete_t. */ - SPI_DEV_CB_COMPLETE, - /** Callback type for error */ - SPI_DEV_CB_ERROR, - /** Number of callbacks. */ - SPI_DEV_CB_N -}; - -struct _spi_async_dev; - -/** \brief The prototype for callback on SPI transfer error. - * If status code is zero, it indicates the normal completion, that is, - * SS deactivation. - * If status code belows zero, it indicates complete. - */ -typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); - -/** \brief The prototype for callback on SPI transmit/receive event - * For TX, the callback is invoked when transmit is done or ready to start - * transmit. - * For RX, the callback is invoked when receive is done or ready to read data, - * see \ref _spi_async_dev_read_one_t on data reading. - * Without DMA enabled, the callback is invoked on each character event. - * With DMA enabled, the callback is invoked on DMA buffer done. - */ -typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_async_dev_callbacks { - /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t tx; - /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t rx; - /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ - _spi_async_dev_cb_xfer_t complete; - /** Error callback, see \ref */ - _spi_async_dev_cb_error_t err; -}; -//@} - -/** - * \brief SPI async driver - */ -//@{ - -/** SPI driver to support async HAL */ -struct _spi_async_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; - - /** \brief Pointer to callback functions, ignored for polling mode - * Pointer to the callback functions so that initialize the driver to - * handle interrupts. - */ - struct _spi_async_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; -}; -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi_m_async.h b/software/firmware/project_oracle_base/hal/include/hpl_spi_m_async.h deleted file mode 100644 index 8d3555e..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi_m_async.h +++ /dev/null @@ -1,243 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED -#define _HPL_SPI_M_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_m_async_dev _spi_async_dev - -#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on after data transmission complate - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi_m_dma.h b/software/firmware/project_oracle_base/hal/include/hpl_spi_m_dma.h deleted file mode 100644 index 2b48300..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi_m_dma.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - * \file - * - * \brief SPI Master DMA related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_DMA_H_INCLUDED -#define _HPL_SPI_M_DMA_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI dma device driver. */ -#define _spi_m_dma_dev _spi_dma_dev - -#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); - -/** - * \brief Register the SPI device callback - * \param[in] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); - -/** \brief Do SPI data transfer (TX & RX) with DMA - * Log the TX & RX buffers and transfer them in background. It never blocks. - * - * \param[in] dev Pointer to the SPI device instance. - * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). - * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). - * \param[in] length spi transfer data length. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy. - */ -int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, - const uint16_t length); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi_m_sync.h b/software/firmware/project_oracle_base/hal/include/hpl_spi_m_sync.h deleted file mode 100644 index 38df15b..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi_m_sync.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_SYNC_H_INCLUDED -#define _HPL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI sync device driver. */ -#define _spi_m_sync_dev _spi_sync_dev - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); - -/** - * \brief Deinitialize SPI - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI char size - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Transfer the whole message without interrupt - * Transfer the message, it will keep waiting until the message finish or - * error. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] msg Pointer to the message instance to process. - * \return Error or number of characters transferred. - * \retval ERR_BUSY SPI hardware is not ready to start transfer (not - * enabled, busy applying settings, ...). - * \retval SPI_ERR_OVERFLOW Overflow error. - * \retval >=0 Number of characters transferred. - */ -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi_s_async.h b/software/firmware/project_oracle_base/hal/include/hpl_spi_s_async.h deleted file mode 100644 index 5647243..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi_s_async.h +++ /dev/null @@ -1,232 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED -#define _HPL_SPI_S_ASYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_s_async_dev _spi_async_dev - -#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on Slave Select (SS) rising - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI slave interrupt - * - * param[in] device The pointer to SPI slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi_s_sync.h b/software/firmware/project_oracle_base/hal/include/hpl_spi_s_sync.h deleted file mode 100644 index ff4c811..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi_s_sync.h +++ /dev/null @@ -1,232 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_SYNC_H_INCLUDED -#define _HPL_SPI_S_SYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI sync device driver. */ -#define _spi_s_sync_dev _spi_sync_dev - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retval 0 OK Status - */ -int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); - -/** - * \brief Check if TX ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return TX ready state - * \retval true TX ready - * \retval false TX not ready - */ -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if RX character ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return RX character ready state - * \retval true RX character ready - * \retval false RX character not ready - */ -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if SS deactiviation detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return SS deactiviation state - * \retval true SS deactiviation detected - * \retval false SS deactiviation not detected - */ -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if error is detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return Error detection state - * \retval true Error detected - * \retval false Error not detected - */ -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_spi_sync.h b/software/firmware/project_oracle_base/hal/include/hpl_spi_sync.h deleted file mode 100644 index dc88648..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_spi_sync.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_SYNC_H_INCLUDED -#define _HPL_SPI_SYNC_H_INCLUDED - -#include -#include - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * \section hpl_spi_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** SPI driver to support sync HAL */ -struct _spi_sync_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; -}; - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_time_measure.h b/software/firmware/project_oracle_base/hal/include/hpl_time_measure.h deleted file mode 100644 index 5d688df..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_time_measure.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * \file - * - * \brief Time measure related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIME_MEASURE_H_INCLUDED -#define _HPL_TIME_MEASURE_H_INCLUDED - -/** - * \addtogroup HPL Time measure - * - * \section hpl_time_measure_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief System time type - */ -typedef uint32_t system_time_t; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_init(void *const hw); - -/** - * \brief Deinitialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_deinit(void *const hw); - -/** - * \brief Get system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get(const void *const hw); - -/** - * \brief Get maximum possible system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get_max_time_value(const void *const hw); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_timer.h b/software/firmware/project_oracle_base/hal/include/hpl_timer.h deleted file mode 100644 index 845b846..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_timer.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * \file - * - * \brief Timer related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIMER_H_INCLUDED -#define _HPL_TIMER_H_INCLUDED - -/** - * \addtogroup HPL Timer - * - * \section hpl_timer_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Timer device structure - * - * The Timer device structure forward declaration. - */ -struct _timer_device; - -/** - * \brief Timer interrupt callbacks - */ -struct _timer_callbacks { - void (*period_expired)(struct _timer_device *device); -}; - -/** - * \brief Timer device structure - */ -struct _timer_device { - struct _timer_callbacks timer_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief Timer functions, pointers to low-level functions - */ -struct _timer_hpl_interface { - int32_t (*init)(struct _timer_device *const device, void *const hw); - void (*deinit)(struct _timer_device *const device); - void (*start_timer)(struct _timer_device *const device); - void (*stop_timer)(struct _timer_device *const device); - void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); - uint32_t (*get_period)(const struct _timer_device *const device); - bool (*is_timer_started)(const struct _timer_device *const device); - void (*set_timer_irq)(struct _timer_device *const device); -}; - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_usart.h b/software/firmware/project_oracle_base/hal/include/hpl_usart.h deleted file mode 100644 index 0e09501..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_usart.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_H_INCLUDED -#define _HPL_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART flow control state - */ -union usart_flow_control_state { - struct { - uint8_t cts : 1; - uint8_t rts : 1; - uint8_t unavailable : 1; - uint8_t reserved : 5; - } bit; - uint8_t value; -}; - -/** - * \brief USART baud rate mode - */ -enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; - -/** - * \brief USART data order - */ -enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; - -/** - * \brief USART mode - */ -enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; - -/** - * \brief USART parity - */ -enum usart_parity { - USART_PARITY_EVEN = 0, - USART_PARITY_ODD = 1, - USART_PARITY_NONE = 2, - USART_PARITY_SPACE = 3, - USART_PARITY_MARK = 4 -}; - -/** - * \brief USART stop bits mode - */ -enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; - -/** - * \brief USART character size - */ -enum usart_character_size { - USART_CHARACTER_SIZE_8BITS = 0, - USART_CHARACTER_SIZE_9BITS = 1, - USART_CHARACTER_SIZE_5BITS = 5, - USART_CHARACTER_SIZE_6BITS = 6, - USART_CHARACTER_SIZE_7BITS = 7 -}; - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_usart_async.h b/software/firmware/project_oracle_base/hal/include/hpl_usart_async.h deleted file mode 100644 index 3f833d1..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_usart_async.h +++ /dev/null @@ -1,270 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_ASYNC_H_INCLUDED -#define _HPL_USART_ASYNC_H_INCLUDED - -/** - * \addtogroup HPL USART - * - * \section hpl_usart_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_usart.h" -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART callback types - */ -enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; - -/** - * \brief USART device structure - * - * The USART device structure forward declaration. - */ -struct _usart_async_device; - -/** - * \brief USART interrupt callbacks - */ -struct _usart_async_callbacks { - void (*tx_byte_sent)(struct _usart_async_device *device); - void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); - void (*tx_done_cb)(struct _usart_async_device *device); - void (*error_cb)(struct _usart_async_device *device); -}; - -/** - * \brief USART descriptor device structure - */ -struct _usart_async_device { - struct _usart_async_callbacks usart_cb; - struct _irq_descriptor irq; - void * hw; -}; -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize asynchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_deinit(struct _usart_async_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable(struct _usart_async_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_disable(struct _usart_async_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); - -/** - * \brief Enable data register empty interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); - -/** - * \brief Enable transmission complete interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); - -/** - * \brief Enable/disable USART interrupt - * - * param[in] device The pointer to USART device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/include/hpl_usart_sync.h b/software/firmware/project_oracle_base/hal/include/hpl_usart_sync.h deleted file mode 100644 index abc7264..0000000 --- a/software/firmware/project_oracle_base/hal/include/hpl_usart_sync.h +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SYNC_USART_H_INCLUDED -#define _HPL_SYNC_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART descriptor device structure - */ -struct _usart_sync_device { - void *hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_deinit(struct _usart_sync_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_enable(struct _usart_sync_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_disable(struct _usart_sync_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); - -/** - * \brief Read a byte from the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - * - * \return Data received via USART interface. - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART transmitter has sent the byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART transmitter has sent the byte - * \retval false if the USART transmitter has not send the byte - */ -bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); - -/** - * \brief Check if there is data received by USART - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the data received check. - * \retval true if the USART has received a byte - * \retval false if the USART has not received a byte - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/src/hal_atomic.c b/software/firmware/project_oracle_base/hal/src/hal_atomic.c deleted file mode 100644 index f56418e..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_atomic.c +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_atomic.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Disable interrupts, enter critical section - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic) -{ - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); -} - -/** - * \brief Exit atomic section - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic) -{ - __DMB(); - __set_PRIMASK(*atomic); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t atomic_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_cache.c b/software/firmware/project_oracle_base/hal/src/hal_cache.c deleted file mode 100644 index b2e75aa..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_cache.c +++ /dev/null @@ -1,78 +0,0 @@ -/** - * \file - * - * \brief HAL cache functionality implementation. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#include -#include - -/** - * \brief Initialize cache module - */ -int32_t cache_init(void) -{ - return _cmcc_init(); -} - -/** - * \brief Enable cache module - */ -int32_t cache_enable(const void *hw) -{ - return _cmcc_enable(hw); -} - -/** - * \brief Disable cache module - */ -int32_t cache_disable(const void *hw) -{ - return _cmcc_disable(hw); -} - -/** - * \brief Configure cache module - */ -int32_t cache_configure(const void *hw, struct _cache_cfg *cache) -{ - return _cmcc_configure(hw, cache); -} - -/** - * \brief Invalidate entire cache entries - */ -int32_t cache_invalidate_all(const void *hw) -{ - return _cmcc_invalidate_all(hw); -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_delay.c b/software/firmware/project_oracle_base/hal/src/hal_delay.c deleted file mode 100644 index 6f77cc7..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_delay.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include "hal_delay.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief The pointer to a hardware instance used by the driver. - */ -static void *hardware; - -/** - * \brief Initialize Delay driver - */ -void delay_init(void *const hw) -{ - _delay_init(hardware = hw); -} - -/** - * \brief Perform delay in us - */ -void delay_us(const uint16_t us) -{ - _delay_cycles(hardware, _get_cycles_for_us(us)); -} - -/** - * \brief Perform delay in ms - */ -void delay_ms(const uint16_t ms) -{ - _delay_cycles(hardware, _get_cycles_for_ms(ms)); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t delay_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_gpio.c b/software/firmware/project_oracle_base/hal/src/hal_gpio.c deleted file mode 100644 index 00dfea6..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_gpio.c +++ /dev/null @@ -1,44 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_gpio.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t gpio_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_init.c b/software/firmware/project_oracle_base/hal/src/hal_init.c deleted file mode 100644 index fb65341..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_init.c +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_init.h" - -/** - * \brief Driver version - */ -#define HAL_INIT_VERSION 0x00000001u - -/** - * \brief Retrieve the current driver version - */ -uint32_t init_get_version(void) -{ - return HAL_INIT_VERSION; -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_io.c b/software/firmware/project_oracle_base/hal/src/hal_io.c deleted file mode 100644 index 7e8feb0..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_io.c +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief I/O functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t io_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \brief I/O write interface - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->write(io_descr, buf, length); -} - -/** - * \brief I/O read interface - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->read(io_descr, buf, length); -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_qspi_sync.c b/software/firmware/project_oracle_base/hal/src/hal_qspi_sync.c deleted file mode 100644 index 0e62532..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_qspi_sync.c +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief Quad SPI related functionality implementation. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_qspi_sync.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Driver version - */ -#define QSPI_SYNC_DRIVER_VERSION 0x00000001u - -int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *const hw) -{ - ASSERT(qspi && hw); - - return _qspi_sync_init(&qspi->dev, hw); -} - -int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi) -{ - ASSERT(qspi); - - return _qspi_sync_deinit(&qspi->dev); -} - -int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi) -{ - ASSERT(qspi); - - return _qspi_sync_enable(&qspi->dev); -} - -int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi) -{ - ASSERT(qspi); - - return _qspi_sync_disable(&qspi->dev); -} - -int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd) -{ - ASSERT(qspi && cmd); - - return _qspi_sync_serial_run_command(&qspi->dev, cmd); -} - -uint32_t qspi_sync_get_version(void) -{ - return QSPI_SYNC_DRIVER_VERSION; -} - -#ifdef __cplusplus -} -#endif diff --git a/software/firmware/project_oracle_base/hal/src/hal_sleep.c b/software/firmware/project_oracle_base/hal/src/hal_sleep.c deleted file mode 100644 index 89472f1..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_sleep.c +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_sleep.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode) -{ - if (ERR_NONE != _set_sleep_mode(mode)) - return ERR_INVALID_ARG; - - _go_to_sleep(); - - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version - */ -uint32_t sleep_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_timer.c b/software/firmware/project_oracle_base/hal/src/hal_timer.c deleted file mode 100644 index 50108f9..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_timer.c +++ /dev/null @@ -1,251 +0,0 @@ -/** - * \file - * - * \brief Timer functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_timer.h" -#include -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Timer flags - */ -#define TIMER_FLAG_QUEUE_IS_TAKEN 1 -#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 - -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); -static void timer_process_counted(struct _timer_device *device); - -/** - * \brief Initialize timer - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) -{ - ASSERT(descr && hw && func); - descr->func = func; - descr->func->init(&descr->device, hw); - descr->time = 0; - descr->device.timer_cb.period_expired = timer_process_counted; - - return ERR_NONE; -} - -/** - * \brief Deinitialize timer - */ -int32_t timer_deinit(struct timer_descriptor *const descr) -{ - ASSERT(descr && descr->func); - descr->func->deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Start timer - */ -int32_t timer_start(struct timer_descriptor *const descr) -{ - ASSERT(descr && descr->func); - if (descr->func->is_timer_started(&descr->device)) { - return ERR_DENIED; - } - descr->func->start_timer(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Stop timer - */ -int32_t timer_stop(struct timer_descriptor *const descr) -{ - ASSERT(descr && descr->func); - if (!descr->func->is_timer_started(&descr->device)) { - return ERR_DENIED; - } - descr->func->stop_timer(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Set amount of clock cycler per timer tick - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) -{ - ASSERT(descr && descr->func); - descr->func->set_timer_period(&descr->device, clock_cycles); - - return ERR_NONE; -} - -/** - * \brief Add timer task - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) -{ - ASSERT(descr && task && descr->func); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_ALREADY_INITIALIZED; - } - task->time_label = descr->time; - timer_add_timer_task(&descr->tasks, task, descr->time); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - descr->func->set_timer_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Remove timer task - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) -{ - ASSERT(descr && task && descr->func); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (!is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_NOT_FOUND; - } - list_delete_element(&descr->tasks, task); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - descr->func->set_timer_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Retrieve the amount of clock cycles in a tick - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) -{ - ASSERT(descr && cycles && descr->func); - *cycles = descr->func->get_period(&descr->device); - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t timer_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal Insert a timer task into sorted timer's list - * - * \param[in] head The pointer to the head of timer task list - * \param[in] task The pointer to task to add - * \param[in] time Current timer time - */ -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) -{ - struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); - - if (!head) { - list_insert_as_head(list, new_task); - return; - } - - for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { - uint32_t time_left; - - if (it->time_label <= time) { - time_left = it->interval - (time - it->time_label); - } else { - time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; - } - if (time_left >= new_task->interval) - break; - prev = it; - } - - if (it == head) { - list_insert_as_head(list, new_task); - } else { - list_insert_after(prev, new_task); - } -} - -/** - * \internal Process interrupts - */ -static void timer_process_counted(struct _timer_device *device) -{ - struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); - struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); - uint32_t time = ++timer->time; - - if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { - timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; - return; - } - - while (it && ((time - it->time_label) >= it->interval)) { - struct timer_task *tmp = it; - - list_remove_head(&timer->tasks); - if (TIMER_TASK_REPEAT == tmp->mode) { - tmp->time_label = time; - timer_add_timer_task(&timer->tasks, tmp, time); - } - it = (struct timer_task *)list_get_head(&timer->tasks); - - tmp->cb(tmp); - } -} diff --git a/software/firmware/project_oracle_base/hal/src/hal_usart_sync.c b/software/firmware/project_oracle_base/hal/src/hal_usart_sync.c deleted file mode 100644 index ab99c1d..0000000 --- a/software/firmware/project_oracle_base/hal/src/hal_usart_sync.c +++ /dev/null @@ -1,276 +0,0 @@ -/** - * \file - * - * \brief I/O USART related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_usart_sync.h" -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief Initialize usart interface - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) -{ - int32_t init_status; - ASSERT(descr && hw); - init_status = _usart_sync_init(&descr->device, hw); - if (init_status) { - return init_status; - } - - descr->io.read = usart_sync_read; - descr->io.write = usart_sync_write; - - return ERR_NONE; -} - -/** - * \brief Uninitialize usart interface - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_deinit(&descr->device); - - descr->io.read = NULL; - descr->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Enable usart interface - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Disable usart interface - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) -{ - ASSERT(descr && io); - - *io = &descr->io; - return ERR_NONE; -} - -/** - * \brief Specify action for flow control pins - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state) -{ - ASSERT(descr); - _usart_sync_set_flow_control_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Set usart baud rate - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) -{ - ASSERT(descr); - _usart_sync_set_baud_rate(&descr->device, baud_rate); - - return ERR_NONE; -} - -/** - * \brief Set usart data order - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) -{ - ASSERT(descr); - _usart_sync_set_data_order(&descr->device, data_order); - - return ERR_NONE; -} - -/** - * \brief Set usart mode - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) -{ - ASSERT(descr); - _usart_sync_set_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set usart parity - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) -{ - ASSERT(descr); - _usart_sync_set_parity(&descr->device, parity); - - return ERR_NONE; -} - -/** - * \brief Set usart stop bits - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) -{ - ASSERT(descr); - _usart_sync_set_stop_bits(&descr->device, stop_bits); - - return ERR_NONE; -} - -/** - * \brief Set usart character size - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) -{ - ASSERT(descr); - _usart_sync_set_character_size(&descr->device, size); - - return ERR_NONE; -} - -/** - * \brief Retrieve the state of flow control pins - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state) -{ - ASSERT(descr && state); - *state = _usart_sync_get_flow_control_state(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Check if the usart transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_ready_to_send(&descr->device); -} - -/** - * \brief Check if the usart receiver is not empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_byte_received(&descr->device); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t usart_sync_get_version(void) -{ - return DRIVER_VERSION; -} - -/* - * \internal Write the given data to usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf Data to write to usart - * \param[in] length The number of bytes to write - * - * \return The number of bytes written. - */ -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - while (!_usart_sync_is_ready_to_send(&descr->device)) - ; - do { - _usart_sync_write_byte(&descr->device, buf[offset]); - while (!_usart_sync_is_ready_to_send(&descr->device)) - ; - } while (++offset < length); - while (!_usart_sync_is_transmit_done(&descr->device)) - ; - return (int32_t)offset; -} - -/* - * \internal Read data from usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - do { - while (!_usart_sync_is_byte_received(&descr->device)) - ; - buf[offset] = _usart_sync_read_byte(&descr->device); - } while (++offset < length); - - return (int32_t)offset; -} diff --git a/software/firmware/project_oracle_base/hal/utils/include/compiler.h b/software/firmware/project_oracle_base/hal/utils/include/compiler.h deleted file mode 100644 index f35db3d..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/compiler.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - * \file - * - * \brief Header - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -/****************************************************************************** - * compiler.h - * - * Created: 05.05.2014 - * Author: N. Fomin - ******************************************************************************/ - -#ifndef _COMPILER_H -#define _COMPILER_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifndef _UNIT_TEST_ -#include "parts.h" -#endif -#include "err_codes.h" - -#ifdef __cplusplus -} -#endif - -#endif /* _COMPILER_H */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/err_codes.h b/software/firmware/project_oracle_base/hal/utils/include/err_codes.h deleted file mode 100644 index a7aff01..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/err_codes.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * \brief Error code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef ERROR_CODES_H_INCLUDED -#define ERROR_CODES_H_INCLUDED - -#define ERR_NONE 0 -#define ERR_INVALID_DATA -1 -#define ERR_NO_CHANGE -2 -#define ERR_ABORTED -3 -#define ERR_BUSY -4 -#define ERR_SUSPEND -5 -#define ERR_IO -6 -#define ERR_REQ_FLUSHED -7 -#define ERR_TIMEOUT -8 -#define ERR_BAD_DATA -9 -#define ERR_NOT_FOUND -10 -#define ERR_UNSUPPORTED_DEV -11 -#define ERR_NO_MEMORY -12 -#define ERR_INVALID_ARG -13 -#define ERR_BAD_ADDRESS -14 -#define ERR_BAD_FORMAT -15 -#define ERR_BAD_FRQ -16 -#define ERR_DENIED -17 -#define ERR_ALREADY_INITIALIZED -18 -#define ERR_OVERFLOW -19 -#define ERR_NOT_INITIALIZED -20 -#define ERR_SAMPLERATE_UNAVAILABLE -21 -#define ERR_RESOLUTION_UNAVAILABLE -22 -#define ERR_BAUDRATE_UNAVAILABLE -23 -#define ERR_PACKET_COLLISION -24 -#define ERR_PROTOCOL -25 -#define ERR_PIN_MUX_INVALID -26 -#define ERR_UNSUPPORTED_OP -27 -#define ERR_NO_RESOURCE -28 -#define ERR_NOT_READY -29 -#define ERR_FAILURE -30 -#define ERR_WRONG_LENGTH -31 - -#endif diff --git a/software/firmware/project_oracle_base/hal/utils/include/events.h b/software/firmware/project_oracle_base/hal/utils/include/events.h deleted file mode 100644 index 3ee891a..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/events.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _EVENTS_H_INCLUDED -#define _EVENTS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \brief List of events. Must start with 0, be unique and follow numerical order. - */ -#define EVENT_IS_READY_TO_SLEEP_ID 0 -#define EVENT_PREPARE_TO_SLEEP_ID 1 -#define EVENT_WOKEN_UP_ID 2 - -#ifdef __cplusplus -} -#endif - -#endif /* _EVENTS_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/parts.h b/software/firmware/project_oracle_base/hal/utils/include/parts.h deleted file mode 100644 index 98bb969..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/parts.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - * \file - * - * \brief Atmel part identification macros - * - * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -#include "same54.h" - -#include "hri_e54.h" - -#endif /* ATMEL_PARTS_H */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils.h b/software/firmware/project_oracle_base/hal/utils/include/utils.h deleted file mode 100644 index 1cf2699..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils.h +++ /dev/null @@ -1,368 +0,0 @@ -/** - * \file - * - * \brief Different macros. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef UTILS_H_INCLUDED -#define UTILS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_macro - * - * @{ - */ - -/** - * \brief Retrieve pointer to parent structure - */ -#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) - -/** - * \brief Retrieve array size - */ -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param[in] arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - -/** - * \brief Set aligned boundary. - */ -#if defined __GNUC__ -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif defined __ICCARM__ -#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#elif defined __CC_ARM -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#endif - -/** - * \brief Flash located data macros - */ -#if defined __GNUC__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __ICCARM__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __CC_ARM -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#endif - -/** - * \brief Optimization - */ -#if defined __GNUC__ -#define OPTIMIZE_HIGH __attribute__((optimize(s))) -#elif defined __CC_ARM -#define OPTIMIZE_HIGH _Pragma("O3") -#elif defined __ICCARM__ -#define OPTIMIZE_HIGH _Pragma("optimize=high") -#endif - -/** - * \brief RAM located function attribute - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define RAMFUNC __ramfunc -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#endif - -/** - * \brief No-init section. - * Place a data object or a function in a no-init section. - */ -#if defined(__CC_ARM) -#define NO_INIT(a) __attribute__((zero_init)) -#elif defined(__ICCARM__) -#define NO_INIT(a) __no_init -#elif defined(__GNUC__) -#define NO_INIT(a) __attribute__((section(".no_init"))) -#endif - -/** - * \brief Set user-defined section. - * Place a data object or a function in a user-defined section. - */ -#if defined(__CC_ARM) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#elif defined(__ICCARM__) -#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) -#elif defined(__GNUC__) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#endif - -/** - * \brief Define WEAK attribute. - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define WEAK __attribute__((weak)) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define WEAK __weak -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define WEAK __attribute__((weak)) -#endif - -/** - * \brief Pointer to function - */ -typedef void (*FUNC_PTR)(void); - -#define LE_BYTE0(a) ((uint8_t)(a)) -#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) -#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) -#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) - -#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) -#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) - -/** \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - * - * @{ */ - -/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define clz(u) __builtin_clz(u) -#else -#define clz(u) \ - ( \ - ((u) == 0) \ - ? 32 \ - : ((u) & (1ul << 31)) \ - ? 0 \ - : ((u) & (1ul << 30)) \ - ? 1 \ - : ((u) & (1ul << 29)) \ - ? 2 \ - : ((u) & (1ul << 28)) \ - ? 3 \ - : ((u) & (1ul << 27)) \ - ? 4 \ - : ((u) & (1ul << 26)) \ - ? 5 \ - : ((u) & (1ul << 25)) \ - ? 6 \ - : ((u) & (1ul << 24)) \ - ? 7 \ - : ((u) & (1ul << 23)) \ - ? 8 \ - : ((u) & (1ul << 22)) \ - ? 9 \ - : ((u) & (1ul << 21)) \ - ? 10 \ - : ((u) & (1ul << 20)) \ - ? 11 \ - : ((u) & (1ul << 19)) \ - ? 12 \ - : ((u) & (1ul << 18)) \ - ? 13 \ - : ((u) & (1ul << 17)) ? 14 \ - : ((u) & (1ul << 16)) ? 15 \ - : ((u) & (1ul << 15)) ? 16 \ - : ((u) & (1ul << 14)) ? 17 \ - : ((u) & (1ul << 13)) ? 18 \ - : ((u) & (1ul << 12)) ? 19 \ - : ((u) \ - & (1ul \ - << 11)) \ - ? 20 \ - : ((u) \ - & (1ul \ - << 10)) \ - ? 21 \ - : ((u) \ - & (1ul \ - << 9)) \ - ? 22 \ - : ((u) \ - & (1ul \ - << 8)) \ - ? 23 \ - : ((u) & (1ul << 7)) ? 24 \ - : ((u) & (1ul << 6)) ? 25 \ - : ((u) \ - & (1ul \ - << 5)) \ - ? 26 \ - : ((u) & (1ul << 4)) ? 27 \ - : ((u) & (1ul << 3)) ? 28 \ - : ((u) & (1ul << 2)) ? 29 \ - : ( \ - (u) & (1ul << 1)) \ - ? 30 \ - : 31) -#endif - -/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define ctz(u) __builtin_ctz(u) -#else -#define ctz(u) \ - ( \ - (u) & (1ul << 0) \ - ? 0 \ - : (u) & (1ul << 1) \ - ? 1 \ - : (u) & (1ul << 2) \ - ? 2 \ - : (u) & (1ul << 3) \ - ? 3 \ - : (u) & (1ul << 4) \ - ? 4 \ - : (u) & (1ul << 5) \ - ? 5 \ - : (u) & (1ul << 6) \ - ? 6 \ - : (u) & (1ul << 7) \ - ? 7 \ - : (u) & (1ul << 8) \ - ? 8 \ - : (u) & (1ul << 9) \ - ? 9 \ - : (u) & (1ul << 10) \ - ? 10 \ - : (u) & (1ul << 11) \ - ? 11 \ - : (u) & (1ul << 12) \ - ? 12 \ - : (u) & (1ul << 13) \ - ? 13 \ - : (u) & (1ul << 14) \ - ? 14 \ - : (u) & (1ul << 15) \ - ? 15 \ - : (u) & (1ul << 16) \ - ? 16 \ - : (u) & (1ul << 17) \ - ? 17 \ - : (u) & (1ul << 18) \ - ? 18 \ - : (u) & (1ul << 19) ? 19 \ - : (u) & (1ul << 20) ? 20 \ - : (u) & (1ul << 21) ? 21 \ - : (u) & (1ul << 22) ? 22 \ - : (u) & (1ul << 23) ? 23 \ - : (u) & (1ul << 24) ? 24 \ - : (u) & (1ul << 25) ? 25 \ - : (u) & (1ul << 26) ? 26 \ - : (u) & (1ul << 27) ? 27 \ - : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) -#endif -/** @} */ - -/** - * \brief Counts the number of bits in a mask (no more than 32 bits) - * \param[in] mask Mask of which to count the bits. - */ -#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) - -/** - * \brief Retrieve the start position of bits mask (no more than 32 bits) - * \param[in] mask Mask of which to retrieve the start position. - */ -#define pos_of_mask(mask) ctz(mask) - -/** - * \brief Return division result of a/b and round up the result to the closest - * number divisible by "b" - */ -#define round_up(a, b) (((a)-1) / (b) + 1) - -/** - * \brief Get the minimum of x and y - */ -#define min(x, y) ((x) > (y) ? (y) : (x)) - -/** - * \brief Get the maximum of x and y - */ -#define max(x, y) ((x) > (y) ? (x) : (y)) - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* UTILS_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils_assert.h b/software/firmware/project_oracle_base/hal/utils/include/utils_assert.h deleted file mode 100644 index c2328d6..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils_assert.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _ASSERT_H_INCLUDED -#define _ASSERT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifndef USE_SIMPLE_ASSERT -//# define USE_SIMPLE_ASSERT -#endif - -/** - * \brief Assert macro - * - * This macro is used to throw asserts. It can be mapped to different function - * based on debug level. - * - * \param[in] condition A condition to be checked; - * assert is thrown if the given condition is false - */ -#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) - -#ifdef DEBUG - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) \ - if (!(condition)) \ - __asm("BKPT #0"); -#else -#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) -#endif - -#else /* DEBUG */ - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) ((void)0) -#else -#define ASSERT_IMPL(condition, file, line) ((void)0) -#endif - -#endif /* DEBUG */ - -/** - * \brief Assert function - * - * This function is used to throw asserts. - * - * \param[in] condition A condition to be checked; assert is thrown if the given - * condition is false - * \param[in] file File name - * \param[in] line Line number - */ -void assert(const bool condition, const char *const file, const int line); - -#ifdef __cplusplus -} -#endif -#endif /* _ASSERT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils_decrement_macro.h b/software/firmware/project_oracle_base/hal/utils/include/utils_decrement_macro.h deleted file mode 100644 index 2b52469..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils_decrement_macro.h +++ /dev/null @@ -1,309 +0,0 @@ -/** - * \file - * - * \brief Decrement macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_DECREMENT_MACRO_H -#define _UTILS_DECREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time decrement, result value is entire integer literal - * - * \param[in] val - value to be decremented - */ -#define DEC_VALUE(val) DEC_##val - -// Preprocessor increment implementation -#define DEC_256 255 -#define DEC_255 254 -#define DEC_254 253 -#define DEC_253 252 -#define DEC_252 251 -#define DEC_251 250 -#define DEC_250 249 -#define DEC_249 248 -#define DEC_248 247 -#define DEC_247 246 -#define DEC_246 245 -#define DEC_245 244 -#define DEC_244 243 -#define DEC_243 242 -#define DEC_242 241 -#define DEC_241 240 -#define DEC_240 239 -#define DEC_239 238 -#define DEC_238 237 -#define DEC_237 236 -#define DEC_236 235 -#define DEC_235 234 -#define DEC_234 233 -#define DEC_233 232 -#define DEC_232 231 -#define DEC_231 230 -#define DEC_230 229 -#define DEC_229 228 -#define DEC_228 227 -#define DEC_227 226 -#define DEC_226 225 -#define DEC_225 224 -#define DEC_224 223 -#define DEC_223 222 -#define DEC_222 221 -#define DEC_221 220 -#define DEC_220 219 -#define DEC_219 218 -#define DEC_218 217 -#define DEC_217 216 -#define DEC_216 215 -#define DEC_215 214 -#define DEC_214 213 -#define DEC_213 212 -#define DEC_212 211 -#define DEC_211 210 -#define DEC_210 209 -#define DEC_209 208 -#define DEC_208 207 -#define DEC_207 206 -#define DEC_206 205 -#define DEC_205 204 -#define DEC_204 203 -#define DEC_203 202 -#define DEC_202 201 -#define DEC_201 200 -#define DEC_200 199 -#define DEC_199 198 -#define DEC_198 197 -#define DEC_197 196 -#define DEC_196 195 -#define DEC_195 194 -#define DEC_194 193 -#define DEC_193 192 -#define DEC_192 191 -#define DEC_191 190 -#define DEC_190 189 -#define DEC_189 188 -#define DEC_188 187 -#define DEC_187 186 -#define DEC_186 185 -#define DEC_185 184 -#define DEC_184 183 -#define DEC_183 182 -#define DEC_182 181 -#define DEC_181 180 -#define DEC_180 179 -#define DEC_179 178 -#define DEC_178 177 -#define DEC_177 176 -#define DEC_176 175 -#define DEC_175 174 -#define DEC_174 173 -#define DEC_173 172 -#define DEC_172 171 -#define DEC_171 170 -#define DEC_170 169 -#define DEC_169 168 -#define DEC_168 167 -#define DEC_167 166 -#define DEC_166 165 -#define DEC_165 164 -#define DEC_164 163 -#define DEC_163 162 -#define DEC_162 161 -#define DEC_161 160 -#define DEC_160 159 -#define DEC_159 158 -#define DEC_158 157 -#define DEC_157 156 -#define DEC_156 155 -#define DEC_155 154 -#define DEC_154 153 -#define DEC_153 152 -#define DEC_152 151 -#define DEC_151 150 -#define DEC_150 149 -#define DEC_149 148 -#define DEC_148 147 -#define DEC_147 146 -#define DEC_146 145 -#define DEC_145 144 -#define DEC_144 143 -#define DEC_143 142 -#define DEC_142 141 -#define DEC_141 140 -#define DEC_140 139 -#define DEC_139 138 -#define DEC_138 137 -#define DEC_137 136 -#define DEC_136 135 -#define DEC_135 134 -#define DEC_134 133 -#define DEC_133 132 -#define DEC_132 131 -#define DEC_131 130 -#define DEC_130 129 -#define DEC_129 128 -#define DEC_128 127 -#define DEC_127 126 -#define DEC_126 125 -#define DEC_125 124 -#define DEC_124 123 -#define DEC_123 122 -#define DEC_122 121 -#define DEC_121 120 -#define DEC_120 119 -#define DEC_119 118 -#define DEC_118 117 -#define DEC_117 116 -#define DEC_116 115 -#define DEC_115 114 -#define DEC_114 113 -#define DEC_113 112 -#define DEC_112 111 -#define DEC_111 110 -#define DEC_110 109 -#define DEC_109 108 -#define DEC_108 107 -#define DEC_107 106 -#define DEC_106 105 -#define DEC_105 104 -#define DEC_104 103 -#define DEC_103 102 -#define DEC_102 101 -#define DEC_101 100 -#define DEC_100 99 -#define DEC_99 98 -#define DEC_98 97 -#define DEC_97 96 -#define DEC_96 95 -#define DEC_95 94 -#define DEC_94 93 -#define DEC_93 92 -#define DEC_92 91 -#define DEC_91 90 -#define DEC_90 89 -#define DEC_89 88 -#define DEC_88 87 -#define DEC_87 86 -#define DEC_86 85 -#define DEC_85 84 -#define DEC_84 83 -#define DEC_83 82 -#define DEC_82 81 -#define DEC_81 80 -#define DEC_80 79 -#define DEC_79 78 -#define DEC_78 77 -#define DEC_77 76 -#define DEC_76 75 -#define DEC_75 74 -#define DEC_74 73 -#define DEC_73 72 -#define DEC_72 71 -#define DEC_71 70 -#define DEC_70 69 -#define DEC_69 68 -#define DEC_68 67 -#define DEC_67 66 -#define DEC_66 65 -#define DEC_65 64 -#define DEC_64 63 -#define DEC_63 62 -#define DEC_62 61 -#define DEC_61 60 -#define DEC_60 59 -#define DEC_59 58 -#define DEC_58 57 -#define DEC_57 56 -#define DEC_56 55 -#define DEC_55 54 -#define DEC_54 53 -#define DEC_53 52 -#define DEC_52 51 -#define DEC_51 50 -#define DEC_50 49 -#define DEC_49 48 -#define DEC_48 47 -#define DEC_47 46 -#define DEC_46 45 -#define DEC_45 44 -#define DEC_44 43 -#define DEC_43 42 -#define DEC_42 41 -#define DEC_41 40 -#define DEC_40 39 -#define DEC_39 38 -#define DEC_38 37 -#define DEC_37 36 -#define DEC_36 35 -#define DEC_35 34 -#define DEC_34 33 -#define DEC_33 32 -#define DEC_32 31 -#define DEC_31 30 -#define DEC_30 29 -#define DEC_29 28 -#define DEC_28 27 -#define DEC_27 26 -#define DEC_26 25 -#define DEC_25 24 -#define DEC_24 23 -#define DEC_23 22 -#define DEC_22 21 -#define DEC_21 20 -#define DEC_20 19 -#define DEC_19 18 -#define DEC_18 17 -#define DEC_17 16 -#define DEC_16 15 -#define DEC_15 14 -#define DEC_14 13 -#define DEC_13 12 -#define DEC_12 11 -#define DEC_11 10 -#define DEC_10 9 -#define DEC_9 8 -#define DEC_8 7 -#define DEC_7 6 -#define DEC_6 5 -#define DEC_5 4 -#define DEC_4 3 -#define DEC_3 2 -#define DEC_2 1 -#define DEC_1 0 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_DECREMENT_MACRO_H */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils_event.h b/software/firmware/project_oracle_base/hal/utils/include/utils_event.h deleted file mode 100644 index 13067c4..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils_event.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_EVENT_H_INCLUDED -#define _UTILS_EVENT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \brief The maximum amount of events - */ -#define EVENT_MAX_AMOUNT 8 - -/** - * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the - * closest number divisible by 8. - */ -#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) - -/** - * \brief The type of event ID. IDs should start with 0 and be in numerical order. - */ -typedef uint8_t event_id_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef uintptr_t event_data_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef void (*event_cb_t)(event_id_t id, event_data_t data); - -/** - * \brief Event structure - */ -struct event { - struct list_element elem; /*! The pointer to next event */ - uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ - event_cb_t cb; /*! Callback to be called when an event occurs */ -}; - -/** - * \brief Subscribe to event - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to subscribe to - * \param[in] cb The callback function to call when the given event occurs - * - * \return The status of subscription - */ -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); - -/** - * \brief Remove event from subscription - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to remove subscription from - * - * \return The status of subscription removing - */ -int32_t event_unsubscribe(struct event *const event, const event_id_t id); - -/** - * \brief Post event - * - * \param[in] id The event ID to post - * \param[in] data The event data to be passed to event subscribers - */ -void event_post(const event_id_t id, const event_data_t data); - -#ifdef __cplusplus -} -#endif - -#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils_increment_macro.h b/software/firmware/project_oracle_base/hal/utils/include/utils_increment_macro.h deleted file mode 100644 index 464c6cb..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils_increment_macro.h +++ /dev/null @@ -1,308 +0,0 @@ -/** - * \file - * - * \brief Increment macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_INCREMENT_MACRO_H -#define _UTILS_INCREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time increment, result value is entire integer literal - * - * \param[in] val - value to be incremented (254 max) - */ -#define INC_VALUE(val) SP_INC_##val - -// Preprocessor increment implementation -#define SP_INC_0 1 -#define SP_INC_1 2 -#define SP_INC_2 3 -#define SP_INC_3 4 -#define SP_INC_4 5 -#define SP_INC_5 6 -#define SP_INC_6 7 -#define SP_INC_7 8 -#define SP_INC_8 9 -#define SP_INC_9 10 -#define SP_INC_10 11 -#define SP_INC_11 12 -#define SP_INC_12 13 -#define SP_INC_13 14 -#define SP_INC_14 15 -#define SP_INC_15 16 -#define SP_INC_16 17 -#define SP_INC_17 18 -#define SP_INC_18 19 -#define SP_INC_19 20 -#define SP_INC_20 21 -#define SP_INC_21 22 -#define SP_INC_22 23 -#define SP_INC_23 24 -#define SP_INC_24 25 -#define SP_INC_25 26 -#define SP_INC_26 27 -#define SP_INC_27 28 -#define SP_INC_28 29 -#define SP_INC_29 30 -#define SP_INC_30 31 -#define SP_INC_31 32 -#define SP_INC_32 33 -#define SP_INC_33 34 -#define SP_INC_34 35 -#define SP_INC_35 36 -#define SP_INC_36 37 -#define SP_INC_37 38 -#define SP_INC_38 39 -#define SP_INC_39 40 -#define SP_INC_40 41 -#define SP_INC_41 42 -#define SP_INC_42 43 -#define SP_INC_43 44 -#define SP_INC_44 45 -#define SP_INC_45 46 -#define SP_INC_46 47 -#define SP_INC_47 48 -#define SP_INC_48 49 -#define SP_INC_49 50 -#define SP_INC_50 51 -#define SP_INC_51 52 -#define SP_INC_52 53 -#define SP_INC_53 54 -#define SP_INC_54 55 -#define SP_INC_55 56 -#define SP_INC_56 57 -#define SP_INC_57 58 -#define SP_INC_58 59 -#define SP_INC_59 60 -#define SP_INC_60 61 -#define SP_INC_61 62 -#define SP_INC_62 63 -#define SP_INC_63 64 -#define SP_INC_64 65 -#define SP_INC_65 66 -#define SP_INC_66 67 -#define SP_INC_67 68 -#define SP_INC_68 69 -#define SP_INC_69 70 -#define SP_INC_70 71 -#define SP_INC_71 72 -#define SP_INC_72 73 -#define SP_INC_73 74 -#define SP_INC_74 75 -#define SP_INC_75 76 -#define SP_INC_76 77 -#define SP_INC_77 78 -#define SP_INC_78 79 -#define SP_INC_79 80 -#define SP_INC_80 81 -#define SP_INC_81 82 -#define SP_INC_82 83 -#define SP_INC_83 84 -#define SP_INC_84 85 -#define SP_INC_85 86 -#define SP_INC_86 87 -#define SP_INC_87 88 -#define SP_INC_88 89 -#define SP_INC_89 90 -#define SP_INC_90 91 -#define SP_INC_91 92 -#define SP_INC_92 93 -#define SP_INC_93 94 -#define SP_INC_94 95 -#define SP_INC_95 96 -#define SP_INC_96 97 -#define SP_INC_97 98 -#define SP_INC_98 99 -#define SP_INC_99 100 -#define SP_INC_100 101 -#define SP_INC_101 102 -#define SP_INC_102 103 -#define SP_INC_103 104 -#define SP_INC_104 105 -#define SP_INC_105 106 -#define SP_INC_106 107 -#define SP_INC_107 108 -#define SP_INC_108 109 -#define SP_INC_109 110 -#define SP_INC_110 111 -#define SP_INC_111 112 -#define SP_INC_112 113 -#define SP_INC_113 114 -#define SP_INC_114 115 -#define SP_INC_115 116 -#define SP_INC_116 117 -#define SP_INC_117 118 -#define SP_INC_118 119 -#define SP_INC_119 120 -#define SP_INC_120 121 -#define SP_INC_121 122 -#define SP_INC_122 123 -#define SP_INC_123 124 -#define SP_INC_124 125 -#define SP_INC_125 126 -#define SP_INC_126 127 -#define SP_INC_127 128 -#define SP_INC_128 129 -#define SP_INC_129 130 -#define SP_INC_130 131 -#define SP_INC_131 132 -#define SP_INC_132 133 -#define SP_INC_133 134 -#define SP_INC_134 135 -#define SP_INC_135 136 -#define SP_INC_136 137 -#define SP_INC_137 138 -#define SP_INC_138 139 -#define SP_INC_139 140 -#define SP_INC_140 141 -#define SP_INC_141 142 -#define SP_INC_142 143 -#define SP_INC_143 144 -#define SP_INC_144 145 -#define SP_INC_145 146 -#define SP_INC_146 147 -#define SP_INC_147 148 -#define SP_INC_148 149 -#define SP_INC_149 150 -#define SP_INC_150 151 -#define SP_INC_151 152 -#define SP_INC_152 153 -#define SP_INC_153 154 -#define SP_INC_154 155 -#define SP_INC_155 156 -#define SP_INC_156 157 -#define SP_INC_157 158 -#define SP_INC_158 159 -#define SP_INC_159 160 -#define SP_INC_160 161 -#define SP_INC_161 162 -#define SP_INC_162 163 -#define SP_INC_163 164 -#define SP_INC_164 165 -#define SP_INC_165 166 -#define SP_INC_166 167 -#define SP_INC_167 168 -#define SP_INC_168 169 -#define SP_INC_169 170 -#define SP_INC_170 171 -#define SP_INC_171 172 -#define SP_INC_172 173 -#define SP_INC_173 174 -#define SP_INC_174 175 -#define SP_INC_175 176 -#define SP_INC_176 177 -#define SP_INC_177 178 -#define SP_INC_178 179 -#define SP_INC_179 180 -#define SP_INC_180 181 -#define SP_INC_181 182 -#define SP_INC_182 183 -#define SP_INC_183 184 -#define SP_INC_184 185 -#define SP_INC_185 186 -#define SP_INC_186 187 -#define SP_INC_187 188 -#define SP_INC_188 189 -#define SP_INC_189 190 -#define SP_INC_190 191 -#define SP_INC_191 192 -#define SP_INC_192 193 -#define SP_INC_193 194 -#define SP_INC_194 195 -#define SP_INC_195 196 -#define SP_INC_196 197 -#define SP_INC_197 198 -#define SP_INC_198 199 -#define SP_INC_199 200 -#define SP_INC_200 201 -#define SP_INC_201 202 -#define SP_INC_202 203 -#define SP_INC_203 204 -#define SP_INC_204 205 -#define SP_INC_205 206 -#define SP_INC_206 207 -#define SP_INC_207 208 -#define SP_INC_208 209 -#define SP_INC_209 210 -#define SP_INC_210 211 -#define SP_INC_211 212 -#define SP_INC_212 213 -#define SP_INC_213 214 -#define SP_INC_214 215 -#define SP_INC_215 216 -#define SP_INC_216 217 -#define SP_INC_217 218 -#define SP_INC_218 219 -#define SP_INC_219 220 -#define SP_INC_220 221 -#define SP_INC_221 222 -#define SP_INC_222 223 -#define SP_INC_223 224 -#define SP_INC_224 225 -#define SP_INC_225 226 -#define SP_INC_226 227 -#define SP_INC_227 228 -#define SP_INC_228 229 -#define SP_INC_229 230 -#define SP_INC_230 231 -#define SP_INC_231 232 -#define SP_INC_232 233 -#define SP_INC_233 234 -#define SP_INC_234 235 -#define SP_INC_235 236 -#define SP_INC_236 237 -#define SP_INC_237 238 -#define SP_INC_238 239 -#define SP_INC_239 240 -#define SP_INC_240 241 -#define SP_INC_241 242 -#define SP_INC_242 243 -#define SP_INC_243 244 -#define SP_INC_244 245 -#define SP_INC_245 246 -#define SP_INC_246 247 -#define SP_INC_247 248 -#define SP_INC_248 249 -#define SP_INC_249 250 -#define SP_INC_250 251 -#define SP_INC_251 252 -#define SP_INC_252 253 -#define SP_INC_253 254 -#define SP_INC_254 255 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils_list.h b/software/firmware/project_oracle_base/hal/utils/include/utils_list.h deleted file mode 100644 index 977e8cc..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils_list.h +++ /dev/null @@ -1,164 +0,0 @@ -/** - * \file - * - * \brief List declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_LIST_H_INCLUDED -#define _UTILS_LIST_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_list - * - * @{ - */ - -#include - -/** - * \brief List element type - */ -struct list_element { - struct list_element *next; -}; - -/** - * \brief List head type - */ -struct list_descriptor { - struct list_element *head; -}; - -/** - * \brief Reset list - * - * \param[in] list The pointer to a list descriptor - */ -static inline void list_reset(struct list_descriptor *const list) -{ - list->head = NULL; -} - -/** - * \brief Retrieve list head - * - * \param[in] list The pointer to a list descriptor - * - * \return A pointer to the head of the given list or NULL if the list is - * empty - */ -static inline void *list_get_head(const struct list_descriptor *const list) -{ - return (void *)list->head; -} - -/** - * \brief Retrieve next list head - * - * \param[in] list The pointer to a list element - * - * \return A pointer to the next list element or NULL if there is not next - * element - */ -static inline void *list_get_next_element(const void *const element) -{ - return element ? ((struct list_element *)element)->next : NULL; -} - -/** - * \brief Insert an element as list head - * - * \param[in] list The pointer to a list element - * \param[in] element An element to insert to the given list - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element); - -/** - * \brief Insert an element after the given list element - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_after(void *const after, void *const element); - -/** - * \brief Insert an element at list end - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element); - -/** - * \brief Check whether an element belongs to a list - * - * \param[in] list The pointer to a list - * \param[in] element An element to check - * - * \return The result of checking - * \retval true If the given element is an element of the given list - * \retval false Otherwise - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element); - -/** - * \brief Removes list head - * - * This function removes the list head and sets the next element after the list - * head as a new list head. - * - * \param[in] list The pointer to a list - * - * \return The pointer to the new list head of NULL if the list head is NULL - */ -void *list_remove_head(struct list_descriptor *const list); - -/** - * \brief Removes the list element - * - * \param[in] list The pointer to a list - * \param[in] element An element to remove - * - * \return The result of element removing - * \retval true The given element is removed from the given list - * \retval false The given element is not an element of the given list - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils_recursion_macro.h b/software/firmware/project_oracle_base/hal/utils/include/utils_recursion_macro.h deleted file mode 100644 index 294314c..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils_recursion_macro.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * \file - * - * \brief Recursion macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_RECURSION_MACRO_H -#define _UTILS_RECURSION_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Macro recursion - * - * \param[in] macro Macro to be repeated recursively - * \param[in] arg A recursive threshold, building on this to decline by times - * defined with parameter n - * \param[in] n The number of repetitious calls to macro - */ -#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg) - -#define RECURSION0(macro, arg) -#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0) -#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1) -#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2) -#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3) -#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_RECURSION_MACRO_H */ diff --git a/software/firmware/project_oracle_base/hal/utils/include/utils_repeat_macro.h b/software/firmware/project_oracle_base/hal/utils/include/utils_repeat_macro.h deleted file mode 100644 index 89e6f52..0000000 --- a/software/firmware/project_oracle_base/hal/utils/include/utils_repeat_macro.h +++ /dev/null @@ -1,322 +0,0 @@ -/** - * \file - * - * \brief Repeat macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_REPEAT_MACRO_H -#define _UTILS_REPEAT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Sequently repeates specified macro for n times (255 max). - * - * Specified macro shall have two arguments: macro(arg, i) - * arg - user defined argument, which have the same value for all iterations. - * i - iteration number; numbering begins from zero and increments on each - * iteration. - * - * \param[in] macro - macro to be repeated - * \param[in] arg - user defined argument for repeated macro - * \param[in] n - total number of iterations (255 max) - */ -#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) - -#define REPEAT1(macro, arg, n) macro(arg, n) -#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) -#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) -#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) -#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) -#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) -#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) -#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) -#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) -#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) -#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) -#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) -#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) -#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) -#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) -#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) -#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) -#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) -#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) -#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) -#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) -#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) -#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) -#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) -#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) -#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) -#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) -#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) -#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) -#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) -#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) -#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) -#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) -#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) -#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) -#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) -#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) -#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) -#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) -#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) -#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) -#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) -#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) -#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) -#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) -#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) -#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) -#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) -#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) -#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) -#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) -#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) -#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) -#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) -#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) -#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) -#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) -#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) -#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) -#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) -#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) -#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) -#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) -#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) -#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) -#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) -#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) -#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) -#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) -#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) -#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) -#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) -#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) -#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) -#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) -#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) -#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) -#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) -#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) -#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) -#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) -#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) -#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) -#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) -#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) -#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) -#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) -#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) -#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) -#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) -#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) -#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) -#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) -#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) -#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) -#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) -#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) -#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) -#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) -#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) -#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) -#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) -#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) -#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) -#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) -#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) -#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) -#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) -#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) -#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) -#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) -#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) -#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) -#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) -#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) -#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) -#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) -#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) -#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) -#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) -#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) -#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) -#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) -#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) -#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) -#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) -#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) -#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) -#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) -#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) -#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) -#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) -#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) -#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) -#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) -#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) -#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) -#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) -#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) -#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) -#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) -#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) -#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) -#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) -#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) -#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) -#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) -#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) -#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) -#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) -#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) -#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) -#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) -#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) -#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) -#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) -#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) -#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) -#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) -#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) -#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) -#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) -#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) -#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) -#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) -#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) -#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) -#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) -#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) -#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) -#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) -#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) -#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) -#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) -#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) -#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) -#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) -#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) -#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) -#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) -#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) -#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) -#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) -#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) -#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) -#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) -#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) -#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) -#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) -#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) -#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) -#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) -#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) -#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) -#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) -#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) -#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) -#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) -#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) -#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) -#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) -#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) -#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) -#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) -#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) -#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) -#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) -#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) -#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) -#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) -#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) -#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) -#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) -#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) -#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) -#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) -#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) -#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) -#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) -#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) -#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) -#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) -#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) -#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) -#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) -#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) -#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) -#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) -#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) -#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) -#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) -#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) -#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) -#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) -#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) -#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) -#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) -#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) -#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) -#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) -#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) -#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) -#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) -#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) -#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) -#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) -#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) -#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) -#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) -#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) -#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) -#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) -#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) -#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) -#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/software/firmware/project_oracle_base/hal/utils/src/utils_assert.c b/software/firmware/project_oracle_base/hal/utils/src/utils_assert.c deleted file mode 100644 index b376c97..0000000 --- a/software/firmware/project_oracle_base/hal/utils/src/utils_assert.c +++ /dev/null @@ -1,46 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include - -/** - * \brief Assert function - */ -void assert(const bool condition, const char *const file, const int line) -{ - if (!(condition)) { - __asm("BKPT #0"); - } - (void)file; - (void)line; -} diff --git a/software/firmware/project_oracle_base/hal/utils/src/utils_event.c b/software/firmware/project_oracle_base/hal/utils/src/utils_event.c deleted file mode 100644 index d1af9d0..0000000 --- a/software/firmware/project_oracle_base/hal/utils/src/utils_event.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * \file - * - * \brief Events implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) - -static struct list_descriptor events; -static uint8_t subscribed[EVENT_MASK_SIZE]; - -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - - ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); - - if (event->mask[position] & mask) { - return ERR_NO_CHANGE; /* Already subscribed */ - } - - if (!is_list_element(&events, event)) { - memset(event->mask, 0, EVENT_MASK_SIZE); - list_insert_as_head(&events, event); - } - event->cb = cb; - event->mask[position] |= mask; - - subscribed[position] |= mask; - - return ERR_NONE; -} - -int32_t event_unsubscribe(struct event *const event, const event_id_t id) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - uint8_t i; - - ASSERT(event && (id < EVENT_MAX_AMOUNT)); - - if (!(event->mask[position] & mask)) { - return ERR_NO_CHANGE; /* Already unsubscribed */ - } - - event->mask[position] &= ~mask; - - /* Check if there are more subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - break; - } - } - if (!current) { - subscribed[position] &= ~mask; - } - - /* Remove event from the list. Can be unsave, document it! */ - for (i = 0; i < ARRAY_SIZE(event->mask); i++) { - if (event->mask[i]) { - return ERR_NONE; - } - } - list_delete_element(&events, event); - - return ERR_NONE; -} - -void event_post(const event_id_t id, const event_data_t data) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - - ASSERT((id < EVENT_MAX_AMOUNT)); - - if (!(subscribed[position] & mask)) { - return; /* No subscribers */ - } - - /* Find all subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - current->cb(id, data); - } - } -} diff --git a/software/firmware/project_oracle_base/hal/utils/src/utils_list.c b/software/firmware/project_oracle_base/hal/utils/src/utils_list.c deleted file mode 100644 index 4006a01..0000000 --- a/software/firmware/project_oracle_base/hal/utils/src/utils_list.c +++ /dev/null @@ -1,136 +0,0 @@ -/** - * \file - * - * \brief List functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Check whether element belongs to list - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element) -{ - struct list_element *it; - for (it = list->head; it; it = it->next) { - if (it == element) { - return true; - } - } - - return false; -} - -/** - * \brief Insert an element as list head - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element) -{ - ASSERT(!is_list_element(list, element)); - - ((struct list_element *)element)->next = list->head; - list->head = (struct list_element *)element; -} - -/** - * \brief Insert an element after the given list element - */ -void list_insert_after(void *const after, void *const element) -{ - ((struct list_element *)element)->next = ((struct list_element *)after)->next; - ((struct list_element *)after)->next = (struct list_element *)element; -} - -/** - * \brief Insert an element at list end - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element) -{ - struct list_element *it = list->head; - - ASSERT(!is_list_element(list, element)); - - if (!list->head) { - list->head = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; - return; - } - - while (it->next) { - it = it->next; - } - it->next = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; -} - -/** - * \brief Removes list head - */ -void *list_remove_head(struct list_descriptor *const list) -{ - if (list->head) { - struct list_element *tmp = list->head; - - list->head = list->head->next; - return (void *)tmp; - } - - return NULL; -} - -/** - * \brief Removes list element - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element) -{ - if (!element) { - return false; - } - - if (list->head == element) { - list->head = list->head->next; - return true; - } else { - struct list_element *it = list->head; - - while (it && it->next != element) { - it = it->next; - } - if (it) { - it->next = ((struct list_element *)element)->next; - return true; - } - } - - return false; -} - -//@} diff --git a/software/firmware/project_oracle_base/hal/utils/src/utils_syscalls.c b/software/firmware/project_oracle_base/hal/utils/src/utils_syscalls.c deleted file mode 100644 index 79e2f1f..0000000 --- a/software/firmware/project_oracle_base/hal/utils/src/utils_syscalls.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - * \file - * - * \brief Syscalls for SAM0 (GCC). - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#undef errno -extern int errno; -extern int _end; - -extern caddr_t _sbrk(int incr); -extern int link(char *old, char *_new); -extern int _close(int file); -extern int _fstat(int file, struct stat *st); -extern int _isatty(int file); -extern int _lseek(int file, int ptr, int dir); -extern void _exit(int status); -extern void _kill(int pid, int sig); -extern int _getpid(void); - -/** - * \brief Replacement of C library of _sbrk - */ -extern caddr_t _sbrk(int incr) -{ - static unsigned char *heap = NULL; - unsigned char * prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_end; - } - prev_heap = heap; - - heap += incr; - - return (caddr_t)prev_heap; -} - -/** - * \brief Replacement of C library of link - */ -extern int link(char *old, char *_new) -{ - (void)old, (void)_new; - return -1; -} - -/** - * \brief Replacement of C library of _close - */ -extern int _close(int file) -{ - (void)file; - return -1; -} - -/** - * \brief Replacement of C library of _fstat - */ -extern int _fstat(int file, struct stat *st) -{ - (void)file; - st->st_mode = S_IFCHR; - - return 0; -} - -/** - * \brief Replacement of C library of _isatty - */ -extern int _isatty(int file) -{ - (void)file; - return 1; -} - -/** - * \brief Replacement of C library of _lseek - */ -extern int _lseek(int file, int ptr, int dir) -{ - (void)file, (void)ptr, (void)dir; - return 0; -} - -/** - * \brief Replacement of C library of _exit - */ -extern void _exit(int status) -{ - printf("Exiting with status %d.\n", status); - - for (;;) - ; -} - -/** - * \brief Replacement of C library of _kill - */ -extern void _kill(int pid, int sig) -{ - (void)pid, (void)sig; - return; -} - -/** - * \brief Replacement of C library of _getpid - */ -extern int _getpid(void) -{ - return -1; -} - -#ifdef __cplusplus -} -#endif diff --git a/software/firmware/project_oracle_base/hpl/cmcc/hpl_cmcc.c b/software/firmware/project_oracle_base/hpl/cmcc/hpl_cmcc.c deleted file mode 100644 index bddf0e1..0000000 --- a/software/firmware/project_oracle_base/hpl/cmcc/hpl_cmcc.c +++ /dev/null @@ -1,354 +0,0 @@ -/** - * \file - * - * \brief Generic CMCC(Cortex M Cache Controller) related functionality. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#include -#include -#include - -/** - * \brief Initialize Cache Module - * - * This function does low level cache configuration. - * - * \return initialize status - */ -int32_t _cmcc_init(void) -{ - int32_t return_value; - - _cmcc_disable(CMCC); - - if (_is_cache_disabled(CMCC)) { - hri_cmcc_write_CFG_reg( - CMCC, - (CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos) - | (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE))); - - _cmcc_enable(CMCC); - return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE; - } else { - return_value = ERR_NOT_INITIALIZED; - } - - return return_value; -} - -/** - * \brief Configure CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] cache configuration structure pointer - * - * \return status of operation - */ -int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl) -{ - int32_t return_value; - - _cmcc_disable(hw); - - if (_is_cache_disabled(hw)) { - hri_cmcc_write_CFG_reg( - hw, - (CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos) - | (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable))); - - return_value = ERR_NONE; - } else { - return_value = ERR_NOT_INITIALIZED; - } - - return return_value; -} - -/** - * \brief Enable data cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache - * - * \return status of operation - */ -int32_t _cmcc_enable_data_cache(const void *hw, bool value) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp &= ~CMCC_CFG_DCDIS; - tmp |= ((!value) << CMCC_CFG_DCDIS_Pos); - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Enable instruction cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache - * - * \return status of operation - */ -int32_t _cmcc_enable_inst_cache(const void *hw, bool value) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp &= ~CMCC_CFG_ICDIS; - tmp |= ((!value) << CMCC_CFG_ICDIS_Pos); - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Enable clock gating in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate - * - * \return status of operation - */ -int32_t _cmcc_enable_clock_gating(const void *hw, bool value) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp |= value; - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Configure the cache size in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache size configuration enumerator - * 0->1K, 1->2K, 2->4K(default) - * - * \return status of operation - */ -int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp &= (~CMCC_CFG_CSIZESW_Msk); - tmp |= (size << CMCC_CFG_CSIZESW_Pos); - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Lock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_lock_way(const void *hw, enum way_num_index num) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_LCKWAY_reg(hw); - tmp |= CMCC_LCKWAY_LCKWAY(num); - - ret = _cmcc_disable(hw); - hri_cmcc_write_LCKWAY_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Unlock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_LCKWAY_reg(hw); - tmp &= (~CMCC_LCKWAY_LCKWAY(num)); - - ret = _cmcc_disable(hw); - hri_cmcc_write_LCKWAY_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Invalidate the mentioned cache line in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num" enumerator (valid arg is 0-3) - * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) - * - * \return status of operation - */ -int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num) -{ - int32_t return_value; - - if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) { - _cmcc_disable(hw); - while (!(_is_cache_disabled(hw))) - ; - hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num))); - return_value = ERR_NONE; - } else { - return_value = ERR_INVALID_ARG; - } - - return return_value; -} - -/** - * \brief Invalidate entire cache entries in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_invalidate_all(const void *hw) -{ - int32_t return_value; - - _cmcc_disable(hw); - if (_is_cache_disabled(hw)) { - hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL); - return_value = ERR_NONE; - } else { - return_value = ERR_FAILURE; - } - - return return_value; -} - -/** - * \brief Configure cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache monitor configurations enumerator - * - * \return status of operation - */ -int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg) -{ - hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg)); - - return ERR_NONE; -} - -/** - * \brief Enable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_enable_monitor(const void *hw) -{ - hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE); - - return ERR_NONE; -} - -/** - * \brief Disable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_disable_monitor(const void *hw) -{ - hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos)); - - return ERR_NONE; -} - -/** - * \brief Reset cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_reset_monitor(const void *hw) -{ - hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST); - - return ERR_NONE; -} - -/** - * \brief Get cache monitor event counter value from CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return event counter value - */ -uint32_t _cmcc_get_monitor_event_count(const void *hw) -{ - return hri_cmcc_read_MSR_reg(hw); -} diff --git a/software/firmware/project_oracle_base/hpl/core/hpl_core_m4.c b/software/firmware/project_oracle_base/hpl/core/hpl_core_m4.c deleted file mode 100644 index b691512..0000000 --- a/software/firmware/project_oracle_base/hpl/core/hpl_core_m4.c +++ /dev/null @@ -1,203 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#ifndef _UNIT_TEST_ -#include -#endif -#include -#include - -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 1000000 -#endif - -#if CONF_CPU_FREQUENCY < 1000 -#define CPU_FREQ_POWER 3 -#elif CONF_CPU_FREQUENCY < 10000 -#define CPU_FREQ_POWER 4 -#elif CONF_CPU_FREQUENCY < 100000 -#define CPU_FREQ_POWER 5 -#elif CONF_CPU_FREQUENCY < 1000000 -#define CPU_FREQ_POWER 6 -#elif CONF_CPU_FREQUENCY < 10000000 -#define CPU_FREQ_POWER 7 -#elif CONF_CPU_FREQUENCY < 100000000 -#define CPU_FREQ_POWER 8 -#elif CONF_CPU_FREQUENCY < 1000000000 -#define CPU_FREQ_POWER 9 -#endif - -/** - * \brief The array of interrupt handlers - */ -struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; - -/** - * \brief Reset MCU - */ -void _reset_mcu(void) -{ - NVIC_SystemReset(); -} - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * \brief Retrieve current IRQ number - */ -uint8_t _irq_get_current(void) -{ - return (uint8_t)__get_IPSR() - 16; -} - -/** - * \brief Disable the given IRQ - */ -void _irq_disable(uint8_t n) -{ - NVIC_DisableIRQ((IRQn_Type)n); -} - -/** - * \brief Set the given IRQ - */ -void _irq_set(uint8_t n) -{ - NVIC_SetPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Clear the given IRQ - */ -void _irq_clear(uint8_t n) -{ - NVIC_ClearPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Enable the given IRQ - */ -void _irq_enable(uint8_t n) -{ - NVIC_EnableIRQ((IRQn_Type)n); -} - -/** - * \brief Register IRQ handler - */ -void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) -{ - ASSERT(n < PERIPH_COUNT_IRQn); - - _irq_table[n] = irq; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Default_Handler(void) -{ - while (1) { - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 9: - return (us * (freq / 1000000) - 1) + 1; - case 8: - return (us * (freq / 100000) - 1) / 10 + 1; - case 7: - return (us * (freq / 10000) - 1) / 100 + 1; - case 6: - return (us * (freq / 1000) - 1) / 1000 + 1; - case 5: - return (us * (freq / 100) - 1) / 10000 + 1; - case 4: - return (us * (freq / 10) - 1) / 100000 + 1; - default: - return (us * freq - 1) / 1000000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -uint32_t _get_cycles_for_us(const uint16_t us) -{ - return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 9: - return (ms * (freq / 1000000)) * 1000; - case 8: - return (ms * (freq / 100000)) * 100; - case 7: - return (ms * (freq / 10000)) * 10; - case 6: - return (ms * (freq / 1000)); - case 5: - return (ms * (freq / 100) - 1) / 10 + 1; - case 4: - return (ms * (freq / 10) - 1) / 100 + 1; - default: - return (ms * freq - 1) / 1000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -uint32_t _get_cycles_for_ms(const uint16_t ms) -{ - return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} diff --git a/software/firmware/project_oracle_base/hpl/core/hpl_core_port.h b/software/firmware/project_oracle_base/hpl/core/hpl_core_port.h deleted file mode 100644 index 3f3e8f2..0000000 --- a/software/firmware/project_oracle_base/hpl/core/hpl_core_port.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_PORT_H_INCLUDED -#define _HPL_CORE_PORT_H_INCLUDED - -#include - -/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR - * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), - * there will be assembling errors. - * So the following things are not included for assembling. - */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) - -#ifndef _UNIT_TEST_ -#include -#endif - -/** - * \brief Check if it's in ISR handling - * \return \c true if it's in ISR - */ -static inline bool _is_in_isr(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); -} - -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hpl/core/hpl_init.c b/software/firmware/project_oracle_base/hpl/core/hpl_init.c deleted file mode 100644 index be0db93..0000000 --- a/software/firmware/project_oracle_base/hpl/core/hpl_init.c +++ /dev/null @@ -1,78 +0,0 @@ -/** - * \file - * - * \brief HPL initialization related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#include -#include -#include -#include - -/* Referenced GCLKs (out of 0~11), should be initialized firstly - */ -#define _GCLK_INIT_1ST 0x00000000 -/* Not referenced GCLKs, initialized last */ -#define _GCLK_INIT_LAST 0x00000FFF - -/** - * \brief Initialize the hardware abstraction layer - */ -void _init_chip(void) -{ - hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); - - _osc32kctrl_init_sources(); - _oscctrl_init_sources(); - _mclk_init(); -#if _GCLK_INIT_1ST - _gclk_init_generators_by_fref(_GCLK_INIT_1ST); -#endif - _oscctrl_init_referenced_generators(); - _gclk_init_generators_by_fref(_GCLK_INIT_LAST); - -#if CONF_DMAC_ENABLE - hri_mclk_set_AHBMASK_DMAC_bit(MCLK); - _dma_init(); -#endif - -#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) - _port_event_init(); -#endif - -#if CONF_CMCC_ENABLE - cache_init(); -#endif -} diff --git a/software/firmware/project_oracle_base/hpl/dmac/hpl_dmac.c b/software/firmware/project_oracle_base/hpl/dmac/hpl_dmac.c deleted file mode 100644 index b08448b..0000000 --- a/software/firmware/project_oracle_base/hpl/dmac/hpl_dmac.c +++ /dev/null @@ -1,263 +0,0 @@ - -/** - * \file - * - * \brief Generic DMAC related functionality. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include - -#if CONF_DMAC_ENABLE -/* Section containing first descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -DmacDescriptor _descriptor_section[DMAC_CH_NUM]; - -/* Section containing current descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -DmacDescriptor _write_back_section[DMAC_CH_NUM]; - -/* Array containing callbacks for DMAC channels */ -static struct _dma_resource _resources[DMAC_CH_NUM]; - -/* DMAC interrupt handler */ -static void _dmac_handler(void); - -/* This macro DMAC configuration */ -#define DMAC_CHANNEL_CFG(i, n) \ - {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ - | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ - DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ - (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ - | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ - DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ - | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ - | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ - | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, - -/* DMAC channel configuration */ -struct dmac_channel_cfg { - uint32_t ctrla; - uint8_t prilvl; - uint8_t evctrl; - uint16_t btctrl; -}; - -/* DMAC channel configurations */ -const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; - -/** - * \brief Initialize DMAC - */ -int32_t _dma_init(void) -{ - uint8_t i; - - hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); - hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); - hri_dmac_set_CTRL_SWRST_bit(DMAC); - while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) - ; - - hri_dmac_write_CTRL_reg(DMAC, - (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) - | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) - | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); - hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); - - hri_dmac_write_PRICTRL0_reg( - DMAC, - DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) - | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) - | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) - | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); - hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); - hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); - - for (i = 0; i < DMAC_CH_NUM; i++) { - hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); - hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); - hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); - hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); - hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); - } - - for (i = 0; i < 5; i++) { - NVIC_DisableIRQ(DMAC_0_IRQn + i); - NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); - NVIC_EnableIRQ(DMAC_0_IRQn + i); - } - - hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); - - return ERR_NONE; -} - -/** - * \brief Enable/disable DMA interrupt - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) -{ - if (DMA_TRANSFER_COMPLETE_CB == type) { - hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); - } else if (DMA_TRANSFER_ERROR_CB == type) { - hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); - } -} - -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) -{ - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); - - return ERR_NONE; -} - -int32_t _dma_set_source_address(const uint8_t channel, const void *const src) -{ - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); - - return ERR_NONE; -} - -int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) -{ - hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], - (uint32_t)&_descriptor_section[next_channel]); - - return ERR_NONE; -} - -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} - -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) -{ - uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); - uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); - - return ERR_NONE; -} - -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) -{ - hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); - hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); - - if (software_trigger) { - hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); - } - - return ERR_NONE; -} - -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) -{ - *resource = &_resources[channel]; - - return ERR_NONE; -} - -int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} -/** - * \internal DMAC interrupt handler - */ -static void _dmac_handler(void) -{ - uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); - struct _dma_resource *tmp_resource = &_resources[channel]; - - if (hri_dmac_get_CHINTFLAG_TERR_bit(DMAC, channel)) { - hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); - tmp_resource->dma_cb.error(tmp_resource); - } else if (hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC, channel)) { - hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel); - tmp_resource->dma_cb.transfer_done(tmp_resource); - } -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_0_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_1_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_2_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_3_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_4_Handler(void) -{ - _dmac_handler(); -} - -#endif /* CONF_DMAC_ENABLE */ diff --git a/software/firmware/project_oracle_base/hpl/gclk/hpl_gclk.c b/software/firmware/project_oracle_base/hpl/gclk/hpl_gclk.c deleted file mode 100644 index 211ccc3..0000000 --- a/software/firmware/project_oracle_base/hpl/gclk/hpl_gclk.c +++ /dev/null @@ -1,312 +0,0 @@ - -/** - * \file - * - * \brief Generic Clock Controller related functionality. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initializes generators - */ -void _gclk_init_generators(void) -{ - -#if CONF_GCLK_GENERATOR_0_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 0, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_1_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 1, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_2_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 2, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_3_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 3, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_4_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 4, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_5_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 5, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_6_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 6, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_7_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 7, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_8_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 8, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_9_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 9, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_10_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 10, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_11_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 11, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); -#endif -} - -void _gclk_init_generators_by_fref(uint32_t bm) -{ - -#if CONF_GCLK_GENERATOR_0_CONFIG == 1 - if (bm & (1ul << 0)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 0, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_1_CONFIG == 1 - if (bm & (1ul << 1)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 1, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_2_CONFIG == 1 - if (bm & (1ul << 2)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 2, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_3_CONFIG == 1 - if (bm & (1ul << 3)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 3, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_4_CONFIG == 1 - if (bm & (1ul << 4)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 4, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_5_CONFIG == 1 - if (bm & (1ul << 5)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 5, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_6_CONFIG == 1 - if (bm & (1ul << 6)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 6, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_7_CONFIG == 1 - if (bm & (1ul << 7)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 7, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_8_CONFIG == 1 - if (bm & (1ul << 8)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 8, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_9_CONFIG == 1 - if (bm & (1ul << 9)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 9, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_10_CONFIG == 1 - if (bm & (1ul << 10)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 10, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_11_CONFIG == 1 - if (bm & (1ul << 11)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 11, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); - } -#endif -} diff --git a/software/firmware/project_oracle_base/hpl/gclk/hpl_gclk_base.h b/software/firmware/project_oracle_base/hpl/gclk/hpl_gclk_base.h deleted file mode 100644 index 3e7d282..0000000 --- a/software/firmware/project_oracle_base/hpl/gclk/hpl_gclk_base.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief Generic Clock Controller. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GCLK_H_INCLUDED -#define _HPL_GCLK_H_INCLUDED - -#include -#ifdef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup gclk_group GCLK Hardware Proxy Layer - * - * \section gclk_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Enable clock on the given channel with the given clock source - * - * This function maps the given clock source to the given clock channel - * and enables channel. - * - * \param[in] channel The channel to enable clock for - * \param[in] source The clock source for the given channel - */ -static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) -{ - - hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); -} - -/** - * \brief Initialize GCLK generators by function references - * \param[in] bm Bit mapping for referenced generators, - * a bit 1 in position triggers generator initialization. - */ -void _gclk_init_generators_by_fref(uint32_t bm); - -//@} -/**@}*/ -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hpl/mclk/hpl_mclk.c b/software/firmware/project_oracle_base/hpl/mclk/hpl_mclk.c deleted file mode 100644 index 6684320..0000000 --- a/software/firmware/project_oracle_base/hpl/mclk/hpl_mclk.c +++ /dev/null @@ -1,44 +0,0 @@ -/** - * \file - * - * \brief SAM Main Clock. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void) -{ - void *hw = (void *)MCLK; - hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); -} diff --git a/software/firmware/project_oracle_base/hpl/osc32kctrl/hpl_osc32kctrl.c b/software/firmware/project_oracle_base/hpl/osc32kctrl/hpl_osc32kctrl.c deleted file mode 100644 index 8859b42..0000000 --- a/software/firmware/project_oracle_base/hpl/osc32kctrl/hpl_osc32kctrl.c +++ /dev/null @@ -1,82 +0,0 @@ - -/** - * \file - * - * \brief SAM 32k Oscillators Controller. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void) -{ - void * hw = (void *)OSC32KCTRL; - uint16_t calib = 0; - -#if CONF_XOSC32K_CONFIG == 1 - hri_osc32kctrl_write_XOSC32K_reg( - hw, - OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) - | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) - | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) - | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) | -#ifdef CONF_XOSC32K_CGM - OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | -#endif - (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); - - hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); - - hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); -#endif - -#if CONF_OSCULP32K_CONFIG == 1 - calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); - hri_osc32kctrl_write_OSCULP32K_reg(hw, -#if CONF_OSCULP32K_CALIB_ENABLE == 1 - OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) -#else - OSC32KCTRL_OSCULP32K_CALIB(calib) -#endif - ); -#endif - -#if CONF_XOSC32K_CONFIG -#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 - while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) - ; -#endif -#endif - - hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); - (void)calib; -} diff --git a/software/firmware/project_oracle_base/hpl/oscctrl/hpl_oscctrl.c b/software/firmware/project_oracle_base/hpl/oscctrl/hpl_oscctrl.c deleted file mode 100644 index 9f55076..0000000 --- a/software/firmware/project_oracle_base/hpl/oscctrl/hpl_oscctrl.c +++ /dev/null @@ -1,230 +0,0 @@ - -/** - * \file - * - * \brief SAM Oscillators Controller. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void) -{ - void *hw = (void *)OSCCTRL; - -#if CONF_XOSC0_CONFIG == 1 - hri_oscctrl_write_XOSCCTRL_reg( - hw, - 0, - OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) - | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) - | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) - | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); -#endif - -#if CONF_XOSC0_CONFIG == 1 -#if CONF_XOSC0_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) - ; -#endif -#if CONF_XOSC0_ENALC == 1 - hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0); -#endif -#if CONF_XOSC0_ONDEMAND == 1 - hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); -#endif -#endif - -#if CONF_XOSC1_CONFIG == 1 - hri_oscctrl_write_XOSCCTRL_reg( - hw, - 1, - OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) - | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) - | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) - | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); -#endif - -#if CONF_XOSC1_CONFIG == 1 -#if CONF_XOSC1_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) - ; -#endif -#if CONF_XOSC1_ENALC == 1 - hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1); -#endif -#if CONF_XOSC1_ONDEMAND == 1 - hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); -#endif -#endif - - (void)hw; -} - -void _oscctrl_init_referenced_generators(void) -{ - void *hw = (void *)OSCCTRL; - -#if CONF_DFLL_CONFIG == 1 - hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); - while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) - ; - uint8_t tmp; - hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); -#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); -#endif - - hri_oscctrl_write_DFLLMUL_reg(hw, - OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) - | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); - while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) - ; - - hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); - while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) - ; - - tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; - hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); - while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) - ; - -#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 - hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); -#endif - hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); - while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) - ; - - tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) - | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) - | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) - | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; - hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); - while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) - ; -#endif - -#if CONF_FDPLL0_CONFIG == 1 -#if CONF_FDPLL0_REFCLK == 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); -#endif - hri_oscctrl_write_DPLLRATIO_reg( - hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); - hri_oscctrl_write_DPLLCTRLB_reg( - hw, - 0, - OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) - | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) - | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) - | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) - | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); - hri_oscctrl_write_DPLLCTRLA_reg(hw, - 0, - (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); -#endif - -#if CONF_FDPLL1_CONFIG == 1 -#if CONF_FDPLL1_REFCLK == 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); -#endif - hri_oscctrl_write_DPLLRATIO_reg( - hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); - hri_oscctrl_write_DPLLCTRLB_reg( - hw, - 1, - OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) - | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) - | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) - | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) - | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); - hri_oscctrl_write_DPLLCTRLA_reg(hw, - 1, - (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); -#endif - -#if CONF_DFLL_CONFIG == 1 - if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { - hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; - - while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) - ; - } else { - while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) - ; - } -#if CONF_DFLL_ONDEMAND == 1 - hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_FDPLL0_CONFIG == 1 -#if CONF_FDPLL0_ENABLE == 1 - while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) - ; -#endif -#if CONF_FDPLL0_ONDEMAND == 1 - hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); -#endif -#endif - -#if CONF_FDPLL1_CONFIG == 1 -#if CONF_FDPLL1_ENABLE == 1 - while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) - ; -#endif -#if CONF_FDPLL1_ONDEMAND == 1 - hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); -#endif -#endif - -#if CONF_DFLL_CONFIG == 1 - while (hri_gclk_read_SYNCBUSY_reg(GCLK)) - ; - hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); - while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) - ; -#endif - (void)hw; -} diff --git a/software/firmware/project_oracle_base/hpl/pm/hpl_pm.c b/software/firmware/project_oracle_base/hpl/pm/hpl_pm.c deleted file mode 100644 index 55dc4db..0000000 --- a/software/firmware/project_oracle_base/hpl/pm/hpl_pm.c +++ /dev/null @@ -1,68 +0,0 @@ - -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Set the sleep mode for the device - */ -int32_t _set_sleep_mode(const uint8_t mode) -{ - uint8_t delay = 10; - - switch (mode) { - case 2: - case 4: - case 5: - case 6: - case 7: - hri_pm_write_SLEEPCFG_reg(PM, mode); - /* A small latency happens between the store instruction and actual - * writing of the SLEEPCFG register due to bridges. Software has to make - * sure the SLEEPCFG register reads the wanted value before issuing WFI - * instruction. - */ - do { - if (hri_pm_read_SLEEPCFG_reg(PM) == mode) { - break; - } - } while (--delay); - break; - default: - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} diff --git a/software/firmware/project_oracle_base/hpl/pm/hpl_pm_base.h b/software/firmware/project_oracle_base/hpl/pm/hpl_pm_base.h deleted file mode 100644 index 5a50a91..0000000 --- a/software/firmware/project_oracle_base/hpl/pm/hpl_pm_base.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HPL_PM_BASE_H_INCLUDED -#define _HPL_PM_BASE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hpl/port/hpl_gpio_base.h b/software/firmware/project_oracle_base/hpl/port/hpl_gpio_base.h deleted file mode 100644 index f32c40f..0000000 --- a/software/firmware/project_oracle_base/hpl/port/hpl_gpio_base.h +++ /dev/null @@ -1,172 +0,0 @@ - -/** - * \file - * - * \brief SAM PORT. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include - -/** - * \brief Set direction on port with mask - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - switch (direction) { - case GPIO_DIRECTION_OFF: - hri_port_clear_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_IN: - hri_port_clear_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg(PORT, - port, - PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN - | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_OUT: - hri_port_set_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - default: - ASSERT(false); - } -} - -/** - * \brief Set output level on port with mask - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - if (level) { - hri_port_set_OUT_reg(PORT, port, mask); - } else { - hri_port_clear_OUT_reg(PORT, port, mask); - } -} - -/** - * \brief Change output level to the opposite with mask - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) -{ - hri_port_toggle_OUT_reg(PORT, port, mask); -} - -/** - * \brief Get input levels on all port pins - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port) -{ - uint32_t tmp; - - CRITICAL_SECTION_ENTER(); - - uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); - - tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; - tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; - - CRITICAL_SECTION_LEAVE(); - - return tmp; -} - -/** - * \brief Set pin pull mode - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode) -{ - switch (pull_mode) { - case GPIO_PULL_OFF: - hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); - break; - - case GPIO_PULL_UP: - hri_port_clear_DIR_reg(PORT, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_set_OUT_reg(PORT, port, 1U << pin); - break; - - case GPIO_PULL_DOWN: - hri_port_clear_DIR_reg(PORT, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_clear_OUT_reg(PORT, port, 1U << pin); - break; - - default: - ASSERT(false); - break; - } -} - -/** - * \brief Set gpio pin function - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) -{ - uint8_t port = GPIO_PORT(gpio); - uint8_t pin = GPIO_PIN(gpio); - - if (function == GPIO_PIN_FUNCTION_OFF) { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); - - } else { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); - - if (pin & 1) { - // Odd numbered pin - hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); - } else { - // Even numbered pin - hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); - } - } -} - -static inline void _port_event_init() -{ - hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 3, CONF_PORTD_EVCTRL); -} diff --git a/software/firmware/project_oracle_base/hpl/qspi/hpl_qspi.c b/software/firmware/project_oracle_base/hpl/qspi/hpl_qspi.c deleted file mode 100644 index 351b3ea..0000000 --- a/software/firmware/project_oracle_base/hpl/qspi/hpl_qspi.c +++ /dev/null @@ -1,156 +0,0 @@ -/** - * \file - * - * \brief QSPI Driver - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Memory copy function. - * - * \param dst Pointer to destination buffer. - * \param src Pointer to source buffer. - * \param count Bytes to be copied. - */ -static void _qspi_memcpy(uint8_t *dst, uint8_t *src, uint32_t count) -{ - while (count--) { - *dst++ = *src++; - } -} - -/** - * \brief Ends ongoing transfer by releasing CS of QSPI peripheral. - * - * \param qspi Pointer to an Qspi instance. - */ -static inline void _qspi_end_transfer(void *hw) -{ - hri_qspi_write_CTRLA_reg(hw, QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER); -} - -int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw) -{ - ASSERT(dev && hw); - dev->prvt = hw; - hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST); - - hri_qspi_write_CTRLB_reg(hw, - QSPI_CTRLB_MODE_MEMORY | QSPI_CTRLB_CSMODE_LASTXFER | QSPI_CTRLB_DATALEN(0) - | QSPI_CTRLB_DLYBCT(0) | QSPI_CTRLB_DLYCS(CONF_QSPI_DLYCS)); - - hri_qspi_write_BAUD_reg(hw, - CONF_QSPI_CPOL << QSPI_BAUD_CPOL_Pos | CONF_QSPI_CPHA << QSPI_BAUD_CPHA_Pos - | QSPI_BAUD_BAUD(CONF_QSPI_BAUD_RATE) | QSPI_BAUD_DLYBS(CONF_QSPI_DLYBS)); - return ERR_NONE; -} - -int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev) -{ - hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST); - return ERR_NONE; -} - -int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev) -{ - hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_ENABLE); - return ERR_NONE; -} - -int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev) -{ - hri_qspi_write_CTRLA_reg(dev->prvt, 0); - return ERR_NONE; -} - -/** - * \brief Set instruction frame param. - */ -static void _qspi_sync_command_set_ifr(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd) -{ - void *hw = dev->prvt; - if (cmd->inst_frame.bits.addr_en) { - hri_qspi_write_INSTRADDR_reg(hw, cmd->address); - } - - if (cmd->inst_frame.bits.inst_en) { - hri_qspi_write_INSTRCTRL_INSTR_bf(hw, cmd->instruction); - } - - if (cmd->inst_frame.bits.opt_en) { - hri_qspi_write_INSTRCTRL_OPTCODE_bf(hw, cmd->option); - } - - hri_qspi_write_INSTRFRAME_reg(hw, cmd->inst_frame.word); -} - -/** - * \brief Access QSPI mapping memory via AHB. - */ -static void _qspi_sync_run_transfer(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd) -{ - void * hw = dev->prvt; - uint8_t *qspi_mem = (uint8_t *)QSPI_AHB; - if (cmd->inst_frame.bits.addr_en) - qspi_mem += cmd->address; - - /* To synchronize system bus accesses */ - hri_qspi_read_INSTRFRAME_reg(hw); - - ASSERT(cmd->tx_buf || cmd->rx_buf); - - if (cmd->tx_buf) { - _qspi_memcpy((uint8_t *)qspi_mem, (uint8_t *)cmd->tx_buf, cmd->buf_len); - } else { - _qspi_memcpy((uint8_t *)cmd->rx_buf, (uint8_t *)qspi_mem, cmd->buf_len); - } - - __DSB(); - __ISB(); -} - -int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd) -{ - _qspi_sync_command_set_ifr(dev, cmd); - - if (cmd->inst_frame.bits.data_en) { - _qspi_sync_run_transfer(dev, cmd); - } - - _qspi_end_transfer(dev->prvt); - - while (!hri_qspi_get_INTFLAG_INSTREND_bit(dev->prvt)) - ; - hri_qspi_clear_INTFLAG_INSTREND_bit(dev->prvt); - return ERR_NONE; -} diff --git a/software/firmware/project_oracle_base/hpl/ramecc/hpl_ramecc.c b/software/firmware/project_oracle_base/hpl/ramecc/hpl_ramecc.c deleted file mode 100644 index 4c158b2..0000000 --- a/software/firmware/project_oracle_base/hpl/ramecc/hpl_ramecc.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief Generic RAMECC related functionality. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/* RAMECC device descriptor */ -struct _ramecc_device device; - -/** - * \brief Initialize RAMECC - */ -int32_t _ramecc_init(void) -{ - if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { - return ERR_ABORTED; - } - - NVIC_DisableIRQ(RAMECC_IRQn); - NVIC_ClearPendingIRQ(RAMECC_IRQn); - NVIC_EnableIRQ(RAMECC_IRQn); - - return ERR_NONE; -} - -void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) -{ - if (RAMECC_DUAL_ERROR_CB == type) { - device.ramecc_cb.dual_bit_err = cb; - hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); - } else if (RAMECC_SINGLE_ERROR_CB == type) { - device.ramecc_cb.single_bit_err = cb; - hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); - } -} - -/** - * \internal RAMECC interrupt handler - */ -void RAMECC_Handler(void) -{ - struct _ramecc_device *dev = (struct _ramecc_device *)&device; - volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); - - if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { - dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); - } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { - dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); - } else { - return; - } -} diff --git a/software/firmware/project_oracle_base/hpl/rtc/hpl_rtc.c b/software/firmware/project_oracle_base/hpl/rtc/hpl_rtc.c deleted file mode 100644 index e49dc4a..0000000 --- a/software/firmware/project_oracle_base/hpl/rtc/hpl_rtc.c +++ /dev/null @@ -1,188 +0,0 @@ - -/** - * \file - * - * \brief RTC Driver - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -/*!< Pointer to hpl device */ -static struct _timer_device *_rtc_dev = NULL; - -/** - * \brief Initialize Timer - */ -int32_t _rtc_timer_init(struct _timer_device *const dev, void *const hw) -{ - ASSERT(dev); - - dev->hw = hw; - - hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST); - hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST); - -#if CONF_RTC_EVENT_CONTROL_ENABLE == 1 - hri_rtcmode0_write_EVCTRL_reg( - dev->hw, - (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos) | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos) - | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos) | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos) - | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos) - | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos) - | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos) - | (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos) - | (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos)); -#endif - - hri_rtcmode0_write_CTRLA_reg( - dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC | RTC_MODE0_CTRLA_MATCHCLR); - hri_rtcmode0_write_COMP_reg(dev->hw, 0, CONF_RTC_COMP_VAL); - hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw); - - _rtc_dev = dev; - - return ERR_NONE; -} - -/** - * \brief De-initialize Timer - */ -void _rtc_timer_deinit(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - NVIC_DisableIRQ(RTC_IRQn); - - hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST); -} - -/** - * \brief Start hardware timer - */ -void _rtc_timer_start(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - NVIC_EnableIRQ(RTC_IRQn); - hri_rtcmode0_write_COUNT_reg(dev->hw, 0); - hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_COUNT); - hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw); -} - -/** - * \brief Stop hardware timer - */ -void _rtc_timer_stop(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw); -} - -/** - * \brief Set timer period - */ -void _rtc_timer_set_period(struct _timer_device *const dev, const uint32_t clock_cycles) -{ - hri_rtcmode0_write_COMP_reg(dev->hw, 0, clock_cycles); -} - -/** - * \brief Retrieve timer period - */ -uint32_t _rtc_timer_get_period(const struct _timer_device *const dev) -{ - return hri_rtcmode0_read_COMP_reg(dev->hw, 0); -} - -/** - * \brief Check if timer is running - */ -bool _rtc_timer_is_started(const struct _timer_device *const dev) -{ - return hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw); -} - -/** - * \brief Set timer IRQ - */ -void _rtc_timer_set_irq(struct _timer_device *const dev) -{ - (void)dev; -} - -/** - * \brief RTC Timer interrupt handler - * - * \param[in] p The pointer to calendar device struct - */ -static void _rtc_timer_interrupt_handler(struct _timer_device *dev) -{ - /* Read and mask interrupt flag register */ - uint16_t flag = hri_rtcmode0_read_INTFLAG_reg(dev->hw); - - if (flag & RTC_MODE0_INTFLAG_CMP0) { - if (dev->timer_cb.period_expired) { - dev->timer_cb.period_expired(dev); - } - /* Clear interrupt flag */ - hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw); - } -} -/** - * \brief Set of pointer to hal_timer helper functions - */ -static struct _timer_hpl_interface _rtc_timer_functions = {_rtc_timer_init, - _rtc_timer_deinit, - _rtc_timer_start, - _rtc_timer_stop, - _rtc_timer_set_period, - _rtc_timer_get_period, - _rtc_timer_is_started, - _rtc_timer_set_irq}; - -/** - * \brief Retrieve timer helper functions - */ -struct _timer_hpl_interface *_rtc_get_timer(void) -{ - return &_rtc_timer_functions; -} - -/** - * \brief Rtc interrupt handler - */ -void RTC_Handler(void) -{ - _rtc_timer_interrupt_handler(_rtc_dev); -} diff --git a/software/firmware/project_oracle_base/hpl/rtc/hpl_rtc_base.h b/software/firmware/project_oracle_base/hpl/rtc/hpl_rtc_base.h deleted file mode 100644 index 06e3bd7..0000000 --- a/software/firmware/project_oracle_base/hpl/rtc/hpl_rtc_base.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief RTC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HPL_RTC2_V200_H_INCLUDED -#define _HPL_RTC2_V200_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Retrieve timer helper functions - * - * \return A pointer to set of timer helper functions - */ -struct _timer_hpl_interface *_rtc_get_timer(void); - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_RTC2_V200_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hpl/sercom/hpl_sercom.c b/software/firmware/project_oracle_base/hpl/sercom/hpl_sercom.c deleted file mode 100644 index 7d096f6..0000000 --- a/software/firmware/project_oracle_base/hpl/sercom/hpl_sercom.c +++ /dev/null @@ -1,2950 +0,0 @@ - -/** - * \file - * - * \brief SAM Serial Communication Interface - * - * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONF_SERCOM_0_USART_ENABLE -#define CONF_SERCOM_0_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_USART_ENABLE -#define CONF_SERCOM_1_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_USART_ENABLE -#define CONF_SERCOM_3_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_USART_ENABLE -#define CONF_SERCOM_4_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_USART_ENABLE -#define CONF_SERCOM_5_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_USART_ENABLE -#define CONF_SERCOM_6_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_USART_ENABLE -#define CONF_SERCOM_7_USART_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as USART. */ -#define SERCOM_USART_AMOUNT \ - (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ - + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ - + CONF_SERCOM_7_USART_ENABLE) - -/** - * \brief Macro is used to fill usart configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define SERCOM_CONFIGURATION(n) \ - { \ - n, \ - SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ - | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ - | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ - | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ - | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ - | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ - | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ - | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ - | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ - SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ - | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ - | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ - | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ - | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ - | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ - SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ - | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ - | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ - | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ - (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ - CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ - } - -/** - * \brief SERCOM USART configuration type - */ -struct usart_configuration { - uint8_t number; - hri_sercomusart_ctrla_reg_t ctrl_a; - hri_sercomusart_ctrlb_reg_t ctrl_b; - hri_sercomusart_ctrlc_reg_t ctrl_c; - hri_sercomusart_baud_reg_t baud; - uint8_t fractional; - hri_sercomusart_rxpl_reg_t rxpl; - hri_sercomusart_dbgctrl_reg_t debug_ctrl; -}; - -#if SERCOM_USART_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct usart_configuration _usarts[1] = {{0}}; -#else -/** - * \brief Array of SERCOM USART configurations - */ -static struct usart_configuration _usarts[] = { -#if CONF_SERCOM_0_USART_ENABLE == 1 - SERCOM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_USART_ENABLE == 1 - SERCOM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_USART_ENABLE == 1 - SERCOM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_USART_ENABLE == 1 - SERCOM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_USART_ENABLE == 1 - SERCOM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_USART_ENABLE == 1 - SERCOM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_USART_ENABLE == 1 - SERCOM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_USART_ENABLE == 1 - SERCOM_CONFIGURATION(7), -#endif -}; -#endif - -static uint8_t _get_sercom_index(const void *const hw); -static uint8_t _sercom_get_irq_num(const void *const hw); -static void _sercom_init_irq_param(const void *const hw, void *dev); -static uint8_t _sercom_get_hardware_index(const void *const hw); - -static int32_t _usart_init(void *const hw); -static inline void _usart_deinit(void *const hw); -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); -static void _usart_set_data_order(void *const hw, const enum usart_data_order order); -static void _usart_set_mode(void *const hw, const enum usart_mode mode); -static void _usart_set_parity(void *const hw, const enum usart_parity parity); -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); -static void _usart_set_character_size(void *const hw, const enum usart_character_size size); - -/** - * \brief Initialize synchronous SERCOM USART - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _usart_init(hw); -} - -/** - * \brief Initialize asynchronous SERCOM USART - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _usart_init(hw); - if (init_status) { - return init_status; - } - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - return ERR_NONE; -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_sync_deinit(struct _usart_sync_device *const device) -{ - _usart_deinit(device->hw); -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_async_deinit(struct _usart_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _usart_deinit(device->hw); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_sync_enable(struct _usart_sync_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_async_enable(struct _usart_async_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_sync_disable(struct _usart_sync_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_async_disable(struct _usart_async_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Set baud rate - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set baud rate - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set data order - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set data order - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set mode - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set mode - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set parity - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set parity - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set stop bits mode - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set stop bits mode - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set character size - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Set character size - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given SERCOM USART instance - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_DATA_reg(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if USART transmission complete - */ -bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_TXC_bit(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if there is data received by USART - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_RXC_bit(device->hw); -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Enable data register empty interrupt - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_DRE_bit(device->hw); -} - -/** - * \brief Enable transmission complete interrupt - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_TXC_bit(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given sercom hardware instance - */ -static uint8_t _sercom_get_hardware_index(const void *const hw) -{ - Sercom *const sercom_modules[] = SERCOM_INSTS; - /* Find index for SERCOM instance. */ - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { - return i; - } - } - return 0; -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Enable/disable USART interrupt - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { - hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); - hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); - } else if (USART_ASYNC_RX_DONE == type) { - hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); - } else if (USART_ASYNC_ERROR == type) { - hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static uint8_t _get_sercom_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_usarts); i++) { - if (_usarts[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return 0; -} - -/** - * \brief Init irq param with the given sercom hardware instance - */ -static void _sercom_init_irq_param(const void *const hw, void *dev) -{ -} - -/** - * \internal Initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - * - * \return The status of initialization - */ -static int32_t _usart_init(void *const hw) -{ - uint8_t i = _get_sercom_index(hw); - - if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { - uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; - if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - } - hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); - } - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - - hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); - hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); - hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); - if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { - ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; - ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; - } else { - hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); - } - - hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); - hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); - - return ERR_NONE; -} - -/** - * \internal De-initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _usart_deinit(void *const hw) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate SERCOM clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { - return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; - } - - if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { - return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); - } - - if (USART_BAUDRATE_SYNCH == mode) { - return clock_rate / baud / 2 - 1; - } - - return 0; -} - -/** - * \internal Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_BAUD_reg(hw, baud_rate); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -static void _usart_set_data_order(void *const hw, const enum usart_data_order order) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_DORD_bit(hw, order); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -static void _usart_set_mode(void *const hw, const enum usart_mode mode) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -static void _usart_set_parity(void *const hw, const enum usart_parity parity) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - - if (USART_PARITY_NONE != parity) { - hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); - } else { - hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); - } - - hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -static void _usart_set_character_size(void *const hw, const enum usart_character_size size) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomusart_set_CTRLA_ENABLE_bit(hw); - } -} - - /* Sercom I2C implementation */ - -#ifndef CONF_SERCOM_0_I2CM_ENABLE -#define CONF_SERCOM_0_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CM_ENABLE -#define CONF_SERCOM_2_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CM_ENABLE -#define CONF_SERCOM_3_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CM_ENABLE -#define CONF_SERCOM_4_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CM_ENABLE -#define CONF_SERCOM_5_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CM_ENABLE -#define CONF_SERCOM_6_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CM_ENABLE -#define CONF_SERCOM_7_I2CM_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Master. */ -#define SERCOM_I2CM_AMOUNT \ - (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ - + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) - -/** - * \brief Macro is used to fill i2cm configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CM_CONFIGURATION(n) \ - { \ - (n), \ - (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ - | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ - SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ - CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ - } - -#define ERROR_FLAG (1 << 7) -#define SB_FLAG (1 << 1) -#define MB_FLAG (1 << 0) - -#define CMD_STOP 0x3 -#define I2C_IDLE 0x1 -#define I2C_SM 0x0 -#define I2C_FM 0x1 -#define I2C_HS 0x2 -#define TEN_ADDR_FRAME 0x78 -#define TEN_ADDR_MASK 0x3ff -#define SEVEN_ADDR_MASK 0x7f - -/** - * \brief SERCOM I2CM configuration type - */ -struct i2cm_configuration { - uint8_t number; - hri_sercomi2cm_ctrla_reg_t ctrl_a; - hri_sercomi2cm_ctrlb_reg_t ctrl_b; - hri_sercomi2cm_baud_reg_t baud; - hri_sercomi2cm_dbgctrl_reg_t dbgctrl; - uint16_t trise; - uint32_t clk; /* SERCOM peripheral clock frequency */ -}; - -static inline int32_t _i2c_m_enable_implementation(void *hw); -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); - -#if SERCOM_I2CM_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct i2cm_configuration _i2cms[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2CM configurations - */ -static struct i2cm_configuration _i2cms[] = { -#if CONF_SERCOM_0_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(7), -#endif -}; -#endif - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2cm_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { - if (_i2cms[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -static inline void _sercom_i2c_send_stop(void *const hw) -{ - hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); -} - -/** - * \brief SERCOM I2CM analyze hardware status and transfer next byte - */ -static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) -{ - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); - - if (flags & MB_FLAG) { - /* tx error */ - if (status & SERCOM_I2CM_STATUS_ARBLOST) { - hri_sercomi2cm_clear_interrupt_MB_bit(hw); - msg->flags |= I2C_M_FAIL; - msg->flags &= ~I2C_M_BUSY; - - if (status & SERCOM_I2CM_STATUS_BUSERR) { - return I2C_ERR_BUS; - } - - return I2C_ERR_BAD_ADDRESS; - } else { - if (status & SERCOM_I2CM_STATUS_RXNACK) { - - /* Slave rejects to receive more data */ - if (msg->len > 0) { - msg->flags |= I2C_M_FAIL; - } - - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - - return I2C_NACK; - } - - if (msg->flags & I2C_M_TEN) { - hri_sercomi2cm_write_ADDR_reg(hw, - ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - msg->flags &= ~I2C_M_TEN; - - return I2C_OK; - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } else { - hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); - msg->buffer++; - msg->len--; - } - - return I2C_OK; - } - } else if (flags & SB_FLAG) { - if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { - msg->len--; - - /* last byte, send nack */ - if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } - - /* Accessing DATA.DATA auto-triggers I2C bus operations. - * The operation performed depends on the state of - * CTRLB.ACKACT, CTRLB.SMEN - **/ - *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); - } else { - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - return I2C_NACK; - } - - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - } - - return I2C_OK; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - return _i2c_m_enable_implementation(i2c_dev->hw); -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Retrieve IRQ number for the given hardware instance - */ -static uint8_t _sercom_get_irq_num(const void *const hw) -{ - return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); -} - -/** - * \brief Initialize sercom i2c module to use in async mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) -{ - int32_t init_status; - - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); - if (init_status) { - return init_status; - } - - _sercom_init_irq_param(hw, (void *)i2c_dev); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - return ERR_NONE; -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Transfer the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - return ERR_NONE; -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail, return the error code - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) -{ - int ret; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (msg->len == 0) { - return ERR_NONE; - } - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); - - ret = _sercom_i2c_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Set callback to be called in interrupt handler - * - * \param[in] i2c_dev The pointer to master i2c device - * \param[in] type The callback type - * \param[in] func The callback function pointer - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, - FUNC_PTR func) -{ - switch (type) { - case I2C_M_ASYNC_DEVICE_ERROR: - i2c_dev->cb.error = (_i2c_error_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_TX_COMPLETE: - i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_RX_COMPLETE: - i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; - break; - default: - /* error */ - break; - } - - return ERR_NONE; -} - -/** - * \brief Set stop condition on I2C - * - * \param i2c_dev Pointer to master i2c device - * - * \return Operation status - * \retval I2C_OK Operation was successfull - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -/** - * \brief Get number of bytes left in transfer buffer - * - * \param i2c_dev Pointer to i2c master device - * - * \return Bytes left in buffer - * \retval =>0 Bytes left in buffer - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) -{ - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return i2c_dev->service.msg.len; - } - - return 0; -} - -/** - * \brief Initialize sercom i2c module to use in sync mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) -{ - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - return _i2c_m_sync_init_impl(&i2c_dev->service, hw); -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - return _i2c_m_enable_implementation(i2c_dev->hw); -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C master interrupt - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state) -{ - if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); - hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); - } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { - hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \brief Wait for bus response - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] flags Store the hardware response - * - * \return Bus response status. - * \retval 0 Bus response status OK - * \retval <0 Bus response fail - */ -inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) -{ - uint32_t timeout = 65535; - void * hw = i2c_dev->hw; - - do { - *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); - - if (timeout-- == 0) { - return I2C_ERR_BUS; - } - } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); - - return I2C_OK; -} - -/** - * \brief Send the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint32_t flags; - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - return _sercom_i2c_sync_analyse_flags(hw, flags, msg); -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail or partial fail, return the error code - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) -{ - uint32_t flags; - int ret; - void * hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return I2C_ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); - - ret = _sercom_i2c_sync_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - while (i2c_dev->service.msg.flags & I2C_M_BUSY) { - ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - - if (ret) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); - } - - return ret; -} - -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -static inline int32_t _i2c_m_enable_implementation(void *const hw) -{ - int timeout = 65535; - int timeout_attempt = 4; - - ASSERT(hw); - - /* Enable interrupts */ - hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); - - while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { - timeout--; - - if (timeout <= 0) { - if (--timeout_attempt) - timeout = 65535; - else - return I2C_ERR_BUSY; - hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); - } - } - return ERR_NONE; -} - -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) -{ - uint8_t i = _get_i2cm_index(hw); - - if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { - uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; - if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); - } - hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); - } - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - - hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); - hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); - hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); - - service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); - - service->trise = _i2cms[i].trise; - - return ERR_NONE; -} - - /* SERCOM I2C slave */ - -#ifndef CONF_SERCOM_0_I2CS_ENABLE -#define CONF_SERCOM_0_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CS_ENABLE -#define CONF_SERCOM_1_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CS_ENABLE -#define CONF_SERCOM_2_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CS_ENABLE -#define CONF_SERCOM_3_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CS_ENABLE -#define CONF_SERCOM_4_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CS_ENABLE -#define CONF_SERCOM_5_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CS_ENABLE -#define CONF_SERCOM_6_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CS_ENABLE -#define CONF_SERCOM_7_I2CS_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Slave. */ -#define SERCOM_I2CS_AMOUNT \ - (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ - + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) - -/** - * \brief Macro is used to fill I2C slave configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CS_CONFIGURATION(n) \ - { \ - n, \ - SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ - | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ - | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ - SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ - (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ - | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ - } - -/** - * \brief Macro to check 10-bit addressing - */ -#define I2CS_7BIT_ADDRESSING_MASK 0x7F - -static int32_t _i2c_s_init(void *const hw); -static int8_t _get_i2c_s_index(const void *const hw); -static inline void _i2c_s_deinit(void *const hw); -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); - -/** - * \brief SERCOM I2C slave configuration type - */ -struct i2cs_configuration { - uint8_t number; - hri_sercomi2cs_ctrla_reg_t ctrl_a; - hri_sercomi2cs_ctrlb_reg_t ctrl_b; - hri_sercomi2cs_addr_reg_t address; -}; - -#if SERCOM_I2CS_AMOUNT < 1 -/** Dummy array for compiling. */ -static struct i2cs_configuration _i2css[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2C slave configurations - */ -static struct i2cs_configuration _i2css[] = { -#if CONF_SERCOM_0_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(5), -#endif -}; -#endif - -/** - * \brief Initialize synchronous I2C slave - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) -{ - int32_t status; - - ASSERT(device); - - status = _i2c_s_init(hw); - if (status) { - return status; - } - device->hw = hw; - - return ERR_NONE; -} - -/** - * \brief Initialize asynchronous I2C slave - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _i2c_s_init(hw); - if (init_status) { - return init_status; - } - - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - - return ERR_NONE; -} - -/** - * \brief Deinitialize synchronous I2C - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) -{ - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Deinitialize asynchronous I2C - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given I2C instance - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_DATA_reg(device->hw); -} - -/** - * \brief Check if I2C is ready to send next byt - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Check if there is data received by I2C - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Clear the Data Ready interrupt flag - */ -int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Abort data transmission - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C slave interrupt - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); - } else if (I2C_S_DEVICE_ERROR == type) { - hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); - } - - return ERR_NONE; -} - -/** - * \internal Initalize i2c slave hardware - * - * \param[in] p The pointer to hardware instance - * - *\ return status of initialization - */ -static int32_t _i2c_s_init(void *const hw) -{ - int8_t i = _get_i2c_s_index(hw); - if (i == -1) { - return ERR_INVALID_ARG; - } - - if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { - uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; - if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); - } - hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); - } - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - - hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); - hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); - hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); - - return ERR_NONE; -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - * - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2c_s_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2css); i++) { - if (_i2css[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _i2c_s_deinit(void *const hw) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - * \param[in] address Address to set - */ -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) -{ - bool enabled; - - enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); - } - - return ERR_NONE; -} - - /* Sercom SPI implementation */ - -#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) -#endif - -#define SPI_DEV_IRQ_MODE 0x8000 - -#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) -#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) - -COMPILER_PACK_SET(1) -/** Initialization configuration of registers. */ -struct sercomspi_regs_cfg { - uint32_t ctrla; - uint32_t ctrlb; - uint32_t addr; - uint8_t baud; - uint8_t dbgctrl; - uint16_t dummy_byte; - uint8_t n; -}; -COMPILER_PACK_RESET() - -/** Build configuration from header macros. */ -#define SERCOMSPI_REGS(n) \ - { \ - (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ - | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ - | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ - | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ - ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ - | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ - | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ - | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ - (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ - | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ - ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ - (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ - CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ - n /* sercom number */ \ - } - -#ifndef CONF_SERCOM_0_SPI_ENABLE -#define CONF_SERCOM_0_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_SPI_ENABLE -#define CONF_SERCOM_1_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_SPI_ENABLE -#define CONF_SERCOM_2_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_SPI_ENABLE -#define CONF_SERCOM_3_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_SPI_ENABLE -#define CONF_SERCOM_4_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_SPI_ENABLE -#define CONF_SERCOM_5_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_SPI_ENABLE -#define CONF_SERCOM_6_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_SPI_ENABLE -#define CONF_SERCOM_7_SPI_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as SPI */ -#define SERCOM_SPI_AMOUNT \ - (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ - + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) - -#if SERCOM_SPI_AMOUNT < 1 -/** Dummy array for compiling. */ -static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; -#else -/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ -static const struct sercomspi_regs_cfg sercomspi_regs[] = { -#if CONF_SERCOM_0_SPI_ENABLE - SERCOMSPI_REGS(0), -#endif -#if CONF_SERCOM_1_SPI_ENABLE - SERCOMSPI_REGS(1), -#endif -#if CONF_SERCOM_2_SPI_ENABLE - SERCOMSPI_REGS(2), -#endif -#if CONF_SERCOM_3_SPI_ENABLE - SERCOMSPI_REGS(3), -#endif -#if CONF_SERCOM_4_SPI_ENABLE - SERCOMSPI_REGS(4), -#endif -#if CONF_SERCOM_5_SPI_ENABLE - SERCOMSPI_REGS(5), -#endif -#if CONF_SERCOM_6_SPI_ENABLE - SERCOMSPI_REGS(6), -#endif -#if CONF_SERCOM_7_SPI_ENABLE - SERCOMSPI_REGS(7), -#endif -}; -#endif - -/** \internal De-initialize SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return De-initialization status - */ -static int32_t _spi_deinit(void *const hw) -{ - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_set_CTRLA_SWRST_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_sync_enable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_set_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_async_enable(void *const hw) -{ - _spi_sync_enable(hw); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_EnableIRQ((IRQn_Type)irq++); - } - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_sync_disable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_async_disable(void *const hw) -{ - _spi_sync_disable(hw); - hri_sercomspi_clear_INTEN_reg( - hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq++); - } - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI mode - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] mode The mode to set - * - * \return Setting mode status - */ -static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); - ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI baudrate - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting baudrate status - */ -static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_write_BAUD_reg(hw, baud_val); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI char size - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * \param[out] size Stored char size - * - * \return Setting char size status - */ -static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) -{ - /* Only 8-bit or 9-bit accepted */ - if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { - return ERR_INVALID_ARG; - } - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { - return ERR_BUSY; - } - - hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); - *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI data order - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting data order status - */ -static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - - if (dord == SPI_DATA_ORDER_LSB_1ST) { - ctrla |= SERCOM_SPI_CTRLA_DORD; - } else { - ctrla &= ~SERCOM_SPI_CTRLA_DORD; - } - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \brief Load SERCOM registers to init for SPI master mode - * The settings will be applied with default master mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg( - hw, - (regs->ctrlb - & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) - | (SERCOM_SPI_CTRLB_RXEN)); - hri_sercomspi_write_BAUD_reg(hw, regs->baud); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); -} - -/** \brief Load SERCOM registers to init for SPI slave mode - * The settings will be applied with default slave mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg(hw, - (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) - | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); - hri_sercomspi_write_ADDR_reg(hw, regs->addr); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); - while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) - ; -} - -/** \brief Return the pointer to register settings of specific SERCOM - * \param[in] hw_addr The hardware register base address. - * \return Pointer to register settings of specific SERCOM. - */ -static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) -{ - uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); - uint8_t i; - - for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { - if (sercomspi_regs[i].n == n) { - return &sercomspi_regs[i]; - } - } - - return NULL; -} - -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) -{ - const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); - - ASSERT(dev && hw); - - if (regs == NULL) { - return ERR_INVALID_ARG; - } - - if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; - if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); - } - hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); - } - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - - dev->prvt = hw; - - if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { - _spi_load_regs_slave(hw, regs); - } else { - _spi_load_regs_master(hw, regs); - } - - /* Load character size from default hardware configuration */ - dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; - - dev->dummy_byte = regs->dummy_byte; - - return ERR_NONE; -} - -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) -{ - return _spi_m_sync_init(dev, hw); -} - -int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) -{ - struct _spi_async_dev *spid = dev; - /* Do hardware initialize. */ - int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); - - if (rc < 0) { - return rc; - } - - _sercom_init_irq_param(hw, (void *)dev); - /* Initialize callbacks: must use them */ - spid->callbacks.complete = NULL; - spid->callbacks.rx = NULL; - spid->callbacks.tx = NULL; - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - irq++; - } - - return ERR_NONE; -} - -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) -{ - return _spi_m_async_init(dev, hw); -} - -int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_m_async_enable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_m_async_disable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) -{ - int32_t rc; - ASSERT(dev); - - /* Not accept 0es */ - if (clk == 0 || baud == 0) { - return ERR_INVALID_ARG; - } - - /* Check baudrate range of current assigned clock */ - if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { - return ERR_INVALID_ARG; - } - - rc = ((clk >> 1) / baud) - 1; - return rc; -} - -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -/** Wait until SPI bus idle. */ -static inline void _spi_wait_bus_idle(void *const hw) -{ - while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { - ; - } - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); -} - -/** Holds run time information for message sync transaction. */ -struct _spi_trans_ctrl { - /** Pointer to transmitting data buffer. */ - uint8_t *txbuf; - /** Pointer to receiving data buffer. */ - uint8_t *rxbuf; - /** Count number of data transmitted. */ - uint32_t txcnt; - /** Count number of data received. */ - uint32_t rxcnt; - /** Data character size. */ - uint8_t char_size; -}; - -/** Check interrupt flag of RXC and update transaction runtime information. */ -static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) -{ - uint32_t data; - - if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { - return false; - } - - data = hri_sercomspi_read_DATA_reg(hw); - - if (ctrl->rxbuf) { - *ctrl->rxbuf++ = (uint8_t)data; - - if (ctrl->char_size > 1) { - *ctrl->rxbuf++ = (uint8_t)(data >> 8); - } - } - - ctrl->rxcnt++; - - return true; -} - -/** Check interrupt flag of DRE and update transaction runtime information. */ -static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, - uint16_t dummy) -{ - uint32_t data; - - if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { - return; - } - - if (ctrl->txbuf) { - data = *ctrl->txbuf++; - - if (ctrl->char_size > 1) { - data |= (*ctrl->txbuf) << 8; - ctrl->txbuf++; - } - } else { - data = dummy; - } - - ctrl->txcnt++; - hri_sercomspi_write_DATA_reg(hw, data); -} - -/** Check interrupt flag of ERROR and update transaction runtime information. */ -static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) -{ - if (SERCOM_SPI_INTFLAG_ERROR & iflag) { - hri_sercomspi_clear_STATUS_reg(hw, ~0); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return ERR_OVERFLOW; - } - - return ERR_NONE; -} - -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) -{ - void * hw = dev->prvt; - int32_t rc = 0; - struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; - - ASSERT(dev && hw); - - /* If settings are not applied (pending), we can not go on */ - if (hri_sercomspi_is_syncing( - hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { - return ERR_BUSY; - } - - /* SPI must be enabled to start synchronous transfer */ - if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { - return ERR_NOT_INITIALIZED; - } - - for (;;) { - uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); - - if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { - /* In master mode, do not start next byte before previous byte received - * to make better output waveform */ - if (ctrl.rxcnt >= ctrl.txcnt) { - _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); - } - } - - rc = _spi_err_check(iflag, hw); - - if (rc < 0) { - break; - } - if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { - rc = ctrl.txcnt; - break; - } - } - /* Wait until SPI bus idle */ - _spi_wait_bus_idle(hw); - - return rc; -} - -int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (state) { - hri_sercomspi_set_INTEN_DRE_bit(hw); - } else { - hri_sercomspi_clear_INTEN_DRE_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx(dev, state); -} - -int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev); - ASSERT(hw); - - if (state) { - hri_sercomspi_set_INTEN_RXC_bit(hw); - } else { - hri_sercomspi_clear_INTEN_RXC_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_rx(dev, state); -} - -int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) -{ - ASSERT(dev && dev->prvt); - - if (state) { - hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); - } else { - hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx_complete(dev, state); -} - -int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - typedef void (*func_t)(void); - struct _spi_async_dev *spid = dev; - - ASSERT(dev && (cb_type < SPI_DEV_CB_N)); - - func_t *p_ls = (func_t *)&spid->callbacks; - p_ls[cb_type] = (func_t)func; - - return ERR_NONE; -} - -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - return _spi_m_async_register_callback(dev, cb_type, func); -} - -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); -} - -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); -} - -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); - return true; - } - return false; -} - -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { - hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return true; - } - return false; -} - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - ASSERT(device); - - if (SPI_DEV_CB_ERROR == type) { - hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); - } -} - -/** - * \brief Enable/disable SPI slave interrupt - * - * param[in] device The pointer to SPI slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - _spi_m_async_set_irq_state(device, type, state); -} diff --git a/software/firmware/project_oracle_base/hpl/systick/hpl_systick.c b/software/firmware/project_oracle_base/hpl/systick/hpl_systick.c deleted file mode 100644 index a75e91e..0000000 --- a/software/firmware/project_oracle_base/hpl/systick/hpl_systick.c +++ /dev/null @@ -1,107 +0,0 @@ - -/** - * \file - * - * \brief SysTick related functionality implementation. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#ifdef _UNIT_TEST_ -#include -#endif - -/** - * \brief Initialize system time module - */ -void _system_time_init(void *const hw) -{ - (void)hw; - SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); - SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) - | (1 << SysTick_CTRL_CLKSOURCE_Pos); -} -/** - * \brief Initialize delay functionality - */ -void _delay_init(void *const hw) -{ - _system_time_init(hw); -} - -/** - * \brief De-initialize system time module - */ -void _system_time_deinit(void *const hw) -{ - (void)hw; - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; -} - -/** - * \brief Get system time - */ -system_time_t _system_time_get(const void *const hw) -{ - (void)hw; - return (system_time_t)SysTick->VAL; -} - -/** - * \brief Get maximum possible system time - */ -system_time_t _system_time_get_max_time_value(const void *const hw) -{ - (void)hw; - return 0xFFFFFF; -} -/** - * \brief Delay loop to delay n number of cycles - */ -void _delay_cycles(void *const hw, uint32_t cycles) -{ - (void)hw; - uint8_t n = cycles >> 24; - uint32_t buf = cycles; - - while (n--) { - SysTick->LOAD = 0xFFFFFF; - SysTick->VAL = 0xFFFFFF; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; - buf -= 0xFFFFFF; - } - - SysTick->LOAD = buf; - SysTick->VAL = buf; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; -} diff --git a/software/firmware/project_oracle_base/hpl/tc/hpl_tc.c b/software/firmware/project_oracle_base/hpl/tc/hpl_tc.c deleted file mode 100644 index 80b6259..0000000 --- a/software/firmware/project_oracle_base/hpl/tc/hpl_tc.c +++ /dev/null @@ -1,360 +0,0 @@ - -/** - * \file - * - * \brief SAM TC - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#ifndef CONF_TC0_ENABLE -#define CONF_TC0_ENABLE 0 -#endif -#ifndef CONF_TC1_ENABLE -#define CONF_TC1_ENABLE 0 -#endif -#ifndef CONF_TC2_ENABLE -#define CONF_TC2_ENABLE 0 -#endif -#ifndef CONF_TC3_ENABLE -#define CONF_TC3_ENABLE 0 -#endif -#ifndef CONF_TC4_ENABLE -#define CONF_TC4_ENABLE 0 -#endif -#ifndef CONF_TC5_ENABLE -#define CONF_TC5_ENABLE 0 -#endif -#ifndef CONF_TC6_ENABLE -#define CONF_TC6_ENABLE 0 -#endif -#ifndef CONF_TC7_ENABLE -#define CONF_TC7_ENABLE 0 -#endif - -/** - * \brief Macro is used to fill usart configuration structure based on its - * number - * - * \param[in] n The number of structures - */ -#define TC_CONFIGURATION(n) \ - { \ - n, TC##n##_IRQn, \ - TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ - | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ - | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ - (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ - | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ - | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ - (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ - } -/** - * \brief TC configuration type - */ -struct tc_configuration { - uint8_t number; - IRQn_Type irq; - hri_tc_ctrla_reg_t ctrl_a; - hri_tc_evctrl_reg_t event_ctrl; - hri_tc_dbgctrl_reg_t dbg_ctrl; - hri_tccount8_per_reg_t per; - hri_tccount32_cc_reg_t cc0; - hri_tccount32_cc_reg_t cc1; -}; - -/** - * \brief Array of TC configurations - */ -static struct tc_configuration _tcs[] = { -#if CONF_TC0_ENABLE == 1 - TC_CONFIGURATION(0), -#endif -#if CONF_TC1_ENABLE == 1 - TC_CONFIGURATION(1), -#endif -#if CONF_TC2_ENABLE == 1 - TC_CONFIGURATION(2), -#endif -#if CONF_TC3_ENABLE == 1 - TC_CONFIGURATION(3), -#endif -#if CONF_TC4_ENABLE == 1 - TC_CONFIGURATION(4), -#endif -#if CONF_TC5_ENABLE == 1 - TC_CONFIGURATION(5), -#endif -#if CONF_TC6_ENABLE == 1 - TC_CONFIGURATION(6), -#endif -#if CONF_TC7_ENABLE == 1 - TC_CONFIGURATION(7), -#endif -}; -/** - * \brief Set of pointer to hal_timer helper functions - */ -static struct _timer_hpl_interface _tc_timer_functions = { - _tc_timer_init, - _tc_timer_deinit, - _tc_timer_start, - _tc_timer_stop, - _tc_timer_set_period, - _tc_timer_get_period, - _tc_timer_is_started, - _tc_timer_set_irq, -}; - -static struct _timer_device *_tc0_dev = NULL; - -static int8_t get_tc_index(const void *const hw); -static void _tc_init_irq_param(const void *const hw, void *dev); -static inline uint8_t _get_hardware_offset(const void *const hw); -/** - * \brief Initialize TC - */ -int32_t _tc_timer_init(struct _timer_device *const device, void *const hw) -{ - int8_t i = get_tc_index(hw); - - device->hw = hw; - ASSERT(ARRAY_SIZE(_tcs)); - - if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { - if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { - hri_tc_clear_CTRLA_ENABLE_bit(hw); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); - } - hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST); - } - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - - hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); - hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); - hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); - hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ); - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); - - } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { - hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); - hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1); - - } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { - hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); - hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1); - hri_tccount8_write_PER_reg(hw, _tcs[i].per); - } - hri_tc_set_INTEN_OVF_bit(hw); - - _tc_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ(_tcs[i].irq); - NVIC_ClearPendingIRQ(_tcs[i].irq); - NVIC_EnableIRQ(_tcs[i].irq); - - return ERR_NONE; -} -/** - * \brief De-initialize TC - */ -void _tc_timer_deinit(struct _timer_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - ASSERT(ARRAY_SIZE(_tcs)); - - NVIC_DisableIRQ(_tcs[i].irq); - - hri_tc_clear_CTRLA_ENABLE_bit(hw); - hri_tc_set_CTRLA_SWRST_bit(hw); -} -/** - * \brief Start hardware timer - */ -void _tc_timer_start(struct _timer_device *const device) -{ - hri_tc_set_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Stop hardware timer - */ -void _tc_timer_stop(struct _timer_device *const device) -{ - hri_tc_clear_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Set timer period - */ -void _tc_timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles) -{ - void *const hw = device->hw; - - if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - hri_tccount32_write_CC_reg(hw, 0, clock_cycles); - } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles); - } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - hri_tccount8_write_PER_reg(hw, clock_cycles); - } -} -/** - * \brief Retrieve timer period - */ -uint32_t _tc_timer_get_period(const struct _timer_device *const device) -{ - void *const hw = device->hw; - - if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - return hri_tccount32_read_CC_reg(hw, 0); - } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - return hri_tccount16_read_CC_reg(hw, 0); - } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - return hri_tccount8_read_PER_reg(hw); - } - - return 0; -} -/** - * \brief Check if timer is running - */ -bool _tc_timer_is_started(const struct _timer_device *const device) -{ - return hri_tc_get_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Retrieve timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void) -{ - return &_tc_timer_functions; -} - -/** - * \brief Retrieve pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void) -{ - return NULL; -} -/** - * \brief Set timer IRQ - * - * \param[in] hw The pointer to hardware instance - */ -void _tc_timer_set_irq(struct _timer_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - ASSERT(ARRAY_SIZE(_tcs)); - - _irq_set(_tcs[i].irq); -} -/** - * \internal TC interrupt handler for Timer - * - * \param[in] instance TC instance number - */ -static void tc_interrupt_handler(struct _timer_device *device) -{ - void *const hw = device->hw; - - if (hri_tc_get_interrupt_OVF_bit(hw)) { - hri_tc_clear_interrupt_OVF_bit(hw); - device->timer_cb.period_expired(device); - } -} - -/** - * \brief TC interrupt handler - */ -void TC0_Handler(void) -{ - tc_interrupt_handler(_tc0_dev); -} - -/** - * \internal Retrieve TC index - * - * \param[in] hw The pointer to hardware instance - * - * \return The index of TC configuration - */ -static int8_t get_tc_index(const void *const hw) -{ - uint8_t index = _get_hardware_offset(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_tcs); i++) { - if (_tcs[i].number == index) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \brief Init irq param with the given tc hardware instance - */ -static void _tc_init_irq_param(const void *const hw, void *dev) -{ - if (hw == TC0) { - _tc0_dev = (struct _timer_device *)dev; - } -} - -/** - * \internal Retrieve TC hardware index - * - * \param[in] hw The pointer to hardware instance - */ -static inline uint8_t _get_hardware_offset(const void *const hw) -{ - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if ((uint32_t)hw == (uint32_t)tc_modules[i]) { - return i; - } - } - return 0; -} diff --git a/software/firmware/project_oracle_base/hpl/tc/hpl_tc_base.h b/software/firmware/project_oracle_base/hpl/tc/hpl_tc_base.h deleted file mode 100644 index 6619699..0000000 --- a/software/firmware/project_oracle_base/hpl/tc/hpl_tc_base.h +++ /dev/null @@ -1,226 +0,0 @@ -/** - * \file - * - * \brief SAM Timer/Counter - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HPL_TC_BASE_H_INCLUDED -#define _HPL_TC_BASE_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup tc_group TC Hardware Proxy Layer - * - * \section tc_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize TC - * - * This function does low level TC configuration. - * - * \param[in] device The pointer to TC device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _tc_timer_init(struct _timer_device *const device, void *const hw); - -/** - * \brief De-initialize TC - * - * \param[in] device The pointer to TC device instance - */ -void _tc_timer_deinit(struct _timer_device *const device); - -/** - * \brief Start hardware timer - * - * \param[in] device The pointer to TC device instance - */ -void _tc_timer_start(struct _timer_device *const device); - -/** - * \brief Stop hardware timer - * - * \param[in] device The pointer to TC device instance - */ -void _tc_timer_stop(struct _timer_device *const device); - -/** - * \brief Set timer period - * - * \param[in] device The pointer to TC device instance - */ -void _tc_timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); - -/** - * \brief Retrieve timer period - * - * \param[in] device The pointer to TC device instance - * - * \return Timer period - */ -uint32_t _tc_timer_get_period(const struct _timer_device *const device); - -/** - * \brief Check if timer is running - * - * \param[in] device The pointer to TC device instance - * - * \return Check status. - * \retval true The given timer is running - * \retval false The given timer is not running - */ -bool _tc_timer_is_started(const struct _timer_device *const device); - -/** - * \brief Set timer IRQ - * - * \param[in] device The pointer to TC device instance - */ -void _tc_timer_set_irq(struct _timer_device *const device); - -/** - * \brief Retrieve timer helper functions - * - * \return A pointer to set of timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void); -/** - * \brief Initialize TC for PWM - * - * This function does low level TC configuration. - * - * \param[in] device The pointer to TC device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _tc_pwm_init(struct _pwm_device *const device, void *const hw); - -/** - * \brief De-initialize TC for PWM - * - * \param[in] device The pointer to TC device instance - */ -void _tc_pwm_deinit(struct _pwm_device *const device); - -/** - * \brief Retrieve offset of the given tc hardware instance - * - * \param[in] device The pointer to TC device instance - * - * \return The offset of the given tc hardware instance - */ -uint8_t _tc_pwm_get_hardware_offset(const struct _pwm_device *const device); - -/** - * \brief Start PWM - * - * \param[in] device The pointer to TC device instance - */ -void _tc_start_pwm(struct _pwm_device *const device); - -/** - * \brief Stop PWM - * - * \param[in] device The pointer to TC device instance - */ -void _tc_stop_pwm(struct _pwm_device *const device); - -/** - * \brief Check if PWM is running - * - * \param[in] device The pointer to TC device instance - * - * \return Check status. - * \retval true The given timer is running - * \retval false The given timer is not running - */ -bool _tc_is_pwm_enabled(const struct _pwm_device *const device); - -/** - * \brief Set PWM parameter - * \param[in] device The pointer to TC device instance - * \param[in] period Total period of one PWM cycle. - * \param[in] duty_cycle Period of PWM first half during one cycle. - */ -void _tc_set_pwm_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - -/** - * \brief Get pwm waveform period value - * \param[in] device The pointer to TC device instance - * \return Period value. - */ -pwm_period_t _tc_pwm_get_period(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform duty cycle value - * \param[in] device The pointer to TC device instance - * \return Duty cycle value - */ -uint32_t _tc_pwm_get_duty(const struct _pwm_device *const device); - -/** - * \brief Enable/disable PWM interrupt - * - * param[in] device The pointer to PWM device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -void _tc_pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); - -/** - * \brief Retrieve pwm helper functions - * - * \return A pointer to set of pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void); - -//@} -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/software/firmware/project_oracle_base/hri/hri_ac_e54.h b/software/firmware/project_oracle_base/hri/hri_ac_e54.h deleted file mode 100644 index 588499e..0000000 --- a/software/firmware/project_oracle_base/hri/hri_ac_e54.h +++ /dev/null @@ -1,1836 +0,0 @@ -/** - * \file - * - * \brief SAM AC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_AC_COMPONENT_ -#ifndef _HRI_AC_E54_H_INCLUDED_ -#define _HRI_AC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AC_CRITICAL_SECTIONS) -#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AC_CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_ac_calib_reg_t; -typedef uint16_t hri_ac_evctrl_reg_t; -typedef uint32_t hri_ac_compctrl_reg_t; -typedef uint32_t hri_ac_syncbusy_reg_t; -typedef uint8_t hri_ac_ctrla_reg_t; -typedef uint8_t hri_ac_ctrlb_reg_t; -typedef uint8_t hri_ac_dbgctrl_reg_t; -typedef uint8_t hri_ac_intenset_reg_t; -typedef uint8_t hri_ac_intflag_reg_t; -typedef uint8_t hri_ac_scaler_reg_t; -typedef uint8_t hri_ac_statusa_reg_t; -typedef uint8_t hri_ac_statusb_reg_t; -typedef uint8_t hri_ac_winctrl_reg_t; - -static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - while (((Ac *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - return ((Ac *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) -{ - return ((Ac *)hw)->INTFLAG.reg; -} - -static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - ((Ac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; -} - -static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; -} - -static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; - } -} - -static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; -} - -static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; -} - -static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; -} - -static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; - } -} - -static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; -} - -static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; -} - -static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; -} - -static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; - } -} - -static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; -} - -static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENSET.reg = mask; -} - -static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) -{ - return ((Ac *)hw)->INTENSET.reg; -} - -static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) -{ - ((Ac *)hw)->INTENSET.reg = data; - ((Ac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; -} - -static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSA.reg; -} - -static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; -} - -static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; -} - -static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSB.reg; -} - -static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Ac *)hw)->SYNCBUSY.reg; -} - -static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= ~AC_CTRLA_ENABLE; - tmp |= value << AC_CTRLA_ENABLE_Pos; - ((Ac *)hw)->CTRLA.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - return ((Ac *)hw)->CTRLA.reg; -} - -static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO0; - tmp |= value << AC_EVCTRL_COMPEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO1; - tmp |= value << AC_EVCTRL_COMPEO1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_WINEO0; - tmp |= value << AC_EVCTRL_WINEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI0; - tmp |= value << AC_EVCTRL_COMPEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI1; - tmp |= value << AC_EVCTRL_COMPEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI0; - tmp |= value << AC_EVCTRL_INVEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI1; - tmp |= value << AC_EVCTRL_INVEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->EVCTRL.reg; -} - -static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= ~AC_DBGCTRL_DBGRUN; - tmp |= value << AC_DBGCTRL_DBGRUN_Pos; - ((Ac *)hw)->DBGCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->DBGCTRL.reg; -} - -static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WEN0; - tmp |= value << AC_WINCTRL_WEN0_Pos; - ((Ac *)hw)->WINCTRL.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WINTSEL0_Msk; - tmp |= AC_WINCTRL_WINTSEL0(data); - ((Ac *)hw)->WINCTRL.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - return ((Ac *)hw)->WINCTRL.reg; -} - -static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, - hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= ~AC_SCALER_VALUE_Msk; - tmp |= AC_SCALER_VALUE(data); - ((Ac *)hw)->SCALER[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) -{ - return ((Ac *)hw)->SCALER[index].reg; -} - -static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_ENABLE; - tmp |= value << AC_COMPCTRL_ENABLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SINGLE; - tmp |= value << AC_COMPCTRL_SINGLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_RUNSTDBY; - tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SWAP; - tmp |= value << AC_COMPCTRL_SWAP_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYSTEN; - tmp |= value << AC_COMPCTRL_HYSTEN_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_INTSEL_Msk; - tmp |= AC_COMPCTRL_INTSEL(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXNEG_Msk; - tmp |= AC_COMPCTRL_MUXNEG(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXPOS_Msk; - tmp |= AC_COMPCTRL_MUXPOS(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SPEED_Msk; - tmp |= AC_COMPCTRL_SPEED(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYST_Msk; - tmp |= AC_COMPCTRL_HYST(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_FLEN_Msk; - tmp |= AC_COMPCTRL_FLEN(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_OUT_Msk; - tmp |= AC_COMPCTRL_OUT(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - return ((Ac *)hw)->COMPCTRL[index].reg; -} - -static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; - return tmp; -} - -static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->CALIB.reg; - tmp &= ~AC_CALIB_BIAS0_Msk; - tmp |= AC_CALIB_BIAS0(data); - ((Ac *)hw)->CALIB.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; - return tmp; -} - -static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) -{ - return ((Ac *)hw)->CALIB.reg; -} - -static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AC_E54_H_INCLUDED */ -#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_adc_e54.h b/software/firmware/project_oracle_base/hri/hri_adc_e54.h deleted file mode 100644 index 7bb7e6f..0000000 --- a/software/firmware/project_oracle_base/hri/hri_adc_e54.h +++ /dev/null @@ -1,3663 +0,0 @@ -/** - * \file - * - * \brief SAM ADC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_ADC_COMPONENT_ -#ifndef _HRI_ADC_E54_H_INCLUDED_ -#define _HRI_ADC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ADC_CRITICAL_SECTIONS) -#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ADC_CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_adc_calib_reg_t; -typedef uint16_t hri_adc_ctrla_reg_t; -typedef uint16_t hri_adc_ctrlb_reg_t; -typedef uint16_t hri_adc_gaincorr_reg_t; -typedef uint16_t hri_adc_inputctrl_reg_t; -typedef uint16_t hri_adc_offsetcorr_reg_t; -typedef uint16_t hri_adc_ress_reg_t; -typedef uint16_t hri_adc_result_reg_t; -typedef uint16_t hri_adc_winlt_reg_t; -typedef uint16_t hri_adc_winut_reg_t; -typedef uint32_t hri_adc_dseqctrl_reg_t; -typedef uint32_t hri_adc_dseqdata_reg_t; -typedef uint32_t hri_adc_dseqstat_reg_t; -typedef uint32_t hri_adc_syncbusy_reg_t; -typedef uint8_t hri_adc_avgctrl_reg_t; -typedef uint8_t hri_adc_dbgctrl_reg_t; -typedef uint8_t hri_adc_evctrl_reg_t; -typedef uint8_t hri_adc_intenset_reg_t; -typedef uint8_t hri_adc_intflag_reg_t; -typedef uint8_t hri_adc_refctrl_reg_t; -typedef uint8_t hri_adc_sampctrl_reg_t; -typedef uint8_t hri_adc_status_reg_t; -typedef uint8_t hri_adc_swtrig_reg_t; - -static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - while (((Adc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - return ((Adc *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) -{ - return ((Adc *)hw)->INTFLAG.reg; -} - -static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - ((Adc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; -} - -static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; -} - -static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; - } -} - -static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; -} - -static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; -} - -static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; -} - -static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; - } -} - -static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; -} - -static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; -} - -static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; -} - -static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; - } -} - -static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; -} - -static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENSET.reg = mask; -} - -static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) -{ - return ((Adc *)hw)->INTENSET.reg; -} - -static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) -{ - ((Adc *)hw)->INTENSET.reg = data; - ((Adc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) -{ - return ((Adc *)hw)->STATUS.reg; -} - -static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Adc *)hw)->SYNCBUSY.reg; -} - -static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; -} - -static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQSTAT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return ((Adc *)hw)->DSEQSTAT.reg; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESULT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) -{ - return ((Adc *)hw)->RESULT.reg; -} - -static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) -{ - return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; -} - -static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) -{ - return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; -} - -static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) -{ - return ((Adc *)hw)->RESS.reg; -} - -static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ENABLE; - tmp |= value << ADC_CTRLA_ENABLE_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_SLAVEEN; - tmp |= value << ADC_CTRLA_SLAVEEN_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_RUNSTDBY; - tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ONDEMAND; - tmp |= value << ADC_CTRLA_ONDEMAND_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_R2R; - tmp |= value << ADC_CTRLA_R2R_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_DUALSEL_Msk; - tmp |= ADC_CTRLA_DUALSEL(data); - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_PRESCALER_Msk; - tmp |= ADC_CTRLA_PRESCALER(data); - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - return ((Adc *)hw)->CTRLA.reg; -} - -static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHEI; - tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTEI; - tmp |= value << ADC_EVCTRL_STARTEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHINV; - tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTINV; - tmp |= value << ADC_EVCTRL_STARTINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_RESRDYEO; - tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_WINMONEO; - tmp |= value << ADC_EVCTRL_WINMONEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->EVCTRL.reg; -} - -static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= ~ADC_DBGCTRL_DBGRUN; - tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; - ((Adc *)hw)->DBGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->DBGCTRL.reg; -} - -static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_DIFFMODE; - tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_DSEQSTOP; - tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; - tmp |= ADC_INPUTCTRL_MUXPOS(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; - tmp |= ADC_INPUTCTRL_MUXNEG(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->INPUTCTRL.reg; -} - -static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_LEFTADJ; - tmp |= value << ADC_CTRLB_LEFTADJ_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_FREERUN; - tmp |= value << ADC_CTRLB_FREERUN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_CORREN; - tmp |= value << ADC_CTRLB_CORREN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_WINSS; - tmp |= value << ADC_CTRLB_WINSS_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_RESSEL_Msk; - tmp |= ADC_CTRLB_RESSEL(data); - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_WINMODE_Msk; - tmp |= ADC_CTRLB_WINMODE(data); - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->CTRLB.reg; -} - -static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFCOMP; - tmp |= value << ADC_REFCTRL_REFCOMP_Pos; - ((Adc *)hw)->REFCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFSEL_Msk; - tmp |= ADC_REFCTRL_REFSEL(data); - ((Adc *)hw)->REFCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->REFCTRL.reg; -} - -static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; - tmp |= ADC_AVGCTRL_SAMPLENUM(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_ADJRES_Msk; - tmp |= ADC_AVGCTRL_ADJRES(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->AVGCTRL.reg; -} - -static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_OFFCOMP; - tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; - ((Adc *)hw)->SAMPCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; - tmp |= ADC_SAMPCTRL_SAMPLEN(data); - ((Adc *)hw)->SAMPCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->SAMPCTRL.reg; -} - -static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= ~ADC_WINLT_WINLT_Msk; - tmp |= ADC_WINLT_WINLT(data); - ((Adc *)hw)->WINLT.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - return ((Adc *)hw)->WINLT.reg; -} - -static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= ~ADC_WINUT_WINUT_Msk; - tmp |= ADC_WINUT_WINUT(data); - ((Adc *)hw)->WINUT.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - return ((Adc *)hw)->WINUT.reg; -} - -static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= ~ADC_GAINCORR_GAINCORR_Msk; - tmp |= ADC_GAINCORR_GAINCORR(data); - ((Adc *)hw)->GAINCORR.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - return ((Adc *)hw)->GAINCORR.reg; -} - -static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, - hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; - tmp |= ADC_OFFSETCORR_OFFSETCORR(data); - ((Adc *)hw)->OFFSETCORR.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - return ((Adc *)hw)->OFFSETCORR.reg; -} - -static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_FLUSH; - tmp |= value << ADC_SWTRIG_FLUSH_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_START; - tmp |= value << ADC_SWTRIG_START_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->SWTRIG.reg; -} - -static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_INPUTCTRL; - tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_CTRLB; - tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_REFCTRL; - tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_AVGCTRL; - tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_SAMPCTRL; - tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_WINLT; - tmp |= value << ADC_DSEQCTRL_WINLT_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_WINUT; - tmp |= value << ADC_DSEQCTRL_WINUT_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_GAINCORR; - tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_OFFSETCORR; - tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_AUTOSTART; - tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg = data; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return ((Adc *)hw)->DSEQCTRL.reg; -} - -static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASCOMP_Msk; - tmp |= ADC_CALIB_BIASCOMP(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASR2R_Msk; - tmp |= ADC_CALIB_BIASR2R(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASREFBUF_Msk; - tmp |= ADC_CALIB_BIASREFBUF(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) -{ - return ((Adc *)hw)->CALIB.reg; -} - -static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQDATA.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ADC_E54_H_INCLUDED */ -#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_aes_e54.h b/software/firmware/project_oracle_base/hri/hri_aes_e54.h deleted file mode 100644 index c1070e2..0000000 --- a/software/firmware/project_oracle_base/hri/hri_aes_e54.h +++ /dev/null @@ -1,1287 +0,0 @@ -/** - * \file - * - * \brief SAM AES - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_AES_COMPONENT_ -#ifndef _HRI_AES_E54_H_INCLUDED_ -#define _HRI_AES_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AES_CRITICAL_SECTIONS) -#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AES_CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_aes_ciplen_reg_t; -typedef uint32_t hri_aes_ctrla_reg_t; -typedef uint32_t hri_aes_ghash_reg_t; -typedef uint32_t hri_aes_hashkey_reg_t; -typedef uint32_t hri_aes_indata_reg_t; -typedef uint32_t hri_aes_intvectv_reg_t; -typedef uint32_t hri_aes_keyword_reg_t; -typedef uint32_t hri_aes_randseed_reg_t; -typedef uint8_t hri_aes_ctrlb_reg_t; -typedef uint8_t hri_aes_databufptr_reg_t; -typedef uint8_t hri_aes_dbgctrl_reg_t; -typedef uint8_t hri_aes_intenset_reg_t; -typedef uint8_t hri_aes_intflag_reg_t; - -static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) -{ - return ((Aes *)hw)->INTFLAG.reg; -} - -static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - ((Aes *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; -} - -static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; -} - -static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; - } -} - -static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; -} - -static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; -} - -static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; -} - -static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; - } -} - -static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; -} - -static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENSET.reg = mask; -} - -static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) -{ - return ((Aes *)hw)->INTENSET.reg; -} - -static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) -{ - ((Aes *)hw)->INTENSET.reg = data; - ((Aes *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_ENABLE; - tmp |= value << AES_CTRLA_ENABLE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CIPHER; - tmp |= value << AES_CTRLA_CIPHER_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_STARTMODE; - tmp |= value << AES_CTRLA_STARTMODE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_LOD; - tmp |= value << AES_CTRLA_LOD_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYGEN; - tmp |= value << AES_CTRLA_KEYGEN_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_XORKEY; - tmp |= value << AES_CTRLA_XORKEY_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_AESMODE_Msk; - tmp |= AES_CTRLA_AESMODE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CFBS_Msk; - tmp |= AES_CTRLA_CFBS(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYSIZE_Msk; - tmp |= AES_CTRLA_KEYSIZE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CTYPE_Msk; - tmp |= AES_CTRLA_CTYPE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLA.reg; -} - -static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_START; - tmp |= value << AES_CTRLB_START_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_NEWMSG; - tmp |= value << AES_CTRLB_NEWMSG_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_EOM; - tmp |= value << AES_CTRLB_EOM_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_GFMUL; - tmp |= value << AES_CTRLB_GFMUL_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLB.reg; -} - -static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, - hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; - tmp |= AES_DATABUFPTR_INDATAPTR(data); - ((Aes *)hw)->DATABUFPTR.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) -{ - return ((Aes *)hw)->DATABUFPTR.reg; -} - -static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp &= ~AES_DBGCTRL_DBGRUN; - tmp |= value << AES_DBGCTRL_DBGRUN_Pos; - ((Aes *)hw)->DBGCTRL.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) -{ - return ((Aes *)hw)->DBGCTRL.reg; -} - -static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->INDATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) -{ - return ((Aes *)hw)->INDATA.reg; -} - -static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, - hri_aes_hashkey_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->HASHKEY[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->HASHKEY[index].reg; -} - -static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->GHASH[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->GHASH[index].reg; -} - -static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CIPLEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) -{ - return ((Aes *)hw)->CIPLEN.reg; -} - -static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->RANDSEED.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) -{ - return ((Aes *)hw)->RANDSEED.reg; -} - -static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->KEYWORD[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INTVECTV[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AES_E54_H_INCLUDED */ -#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_can_e54.h b/software/firmware/project_oracle_base/hri/hri_can_e54.h deleted file mode 100644 index 2c02884..0000000 --- a/software/firmware/project_oracle_base/hri/hri_can_e54.h +++ /dev/null @@ -1,16997 +0,0 @@ -/** - * \file - * - * \brief SAM CAN - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_CAN_COMPONENT_ -#ifndef _HRI_CAN_E54_H_INCLUDED_ -#define _HRI_CAN_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CAN_CRITICAL_SECTIONS) -#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CAN_CRITICAL_SECTION_ENTER() -#define CAN_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_can_cccr_reg_t; -typedef uint32_t hri_can_crel_reg_t; -typedef uint32_t hri_can_dbtp_reg_t; -typedef uint32_t hri_can_ecr_reg_t; -typedef uint32_t hri_can_endn_reg_t; -typedef uint32_t hri_can_gfc_reg_t; -typedef uint32_t hri_can_hpms_reg_t; -typedef uint32_t hri_can_ie_reg_t; -typedef uint32_t hri_can_ile_reg_t; -typedef uint32_t hri_can_ils_reg_t; -typedef uint32_t hri_can_ir_reg_t; -typedef uint32_t hri_can_mrcfg_reg_t; -typedef uint32_t hri_can_nbtp_reg_t; -typedef uint32_t hri_can_ndat1_reg_t; -typedef uint32_t hri_can_ndat2_reg_t; -typedef uint32_t hri_can_psr_reg_t; -typedef uint32_t hri_can_rwd_reg_t; -typedef uint32_t hri_can_rxbc_reg_t; -typedef uint32_t hri_can_rxesc_reg_t; -typedef uint32_t hri_can_rxf0a_reg_t; -typedef uint32_t hri_can_rxf0c_reg_t; -typedef uint32_t hri_can_rxf0s_reg_t; -typedef uint32_t hri_can_rxf1a_reg_t; -typedef uint32_t hri_can_rxf1c_reg_t; -typedef uint32_t hri_can_rxf1s_reg_t; -typedef uint32_t hri_can_sidfc_reg_t; -typedef uint32_t hri_can_tdcr_reg_t; -typedef uint32_t hri_can_test_reg_t; -typedef uint32_t hri_can_tocc_reg_t; -typedef uint32_t hri_can_tocv_reg_t; -typedef uint32_t hri_can_tscc_reg_t; -typedef uint32_t hri_can_tscv_reg_t; -typedef uint32_t hri_can_txbar_reg_t; -typedef uint32_t hri_can_txbc_reg_t; -typedef uint32_t hri_can_txbcf_reg_t; -typedef uint32_t hri_can_txbcie_reg_t; -typedef uint32_t hri_can_txbcr_reg_t; -typedef uint32_t hri_can_txbrp_reg_t; -typedef uint32_t hri_can_txbtie_reg_t; -typedef uint32_t hri_can_txbto_reg_t; -typedef uint32_t hri_can_txefa_reg_t; -typedef uint32_t hri_can_txefc_reg_t; -typedef uint32_t hri_can_txefs_reg_t; -typedef uint32_t hri_can_txesc_reg_t; -typedef uint32_t hri_can_txfqs_reg_t; -typedef uint32_t hri_can_xidam_reg_t; -typedef uint32_t hri_can_xidfc_reg_t; - -static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; -} - -static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CREL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) -{ - return ((Can *)hw)->CREL.reg; -} - -static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) -{ - return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; -} - -static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) -{ - return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; -} - -static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ENDN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) -{ - return ((Can *)hw)->ENDN.reg; -} - -static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) -{ - return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; -} - -static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) -{ - return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; -} - -static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCV.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) -{ - return ((Can *)hw)->TSCV.reg; -} - -static inline bool hri_can_get_ECR_RP_bit(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ECR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) -{ - return ((Can *)hw)->ECR.reg; -} - -static inline bool hri_can_get_PSR_EP_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; -} - -static inline bool hri_can_get_PSR_EW_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; -} - -static inline bool hri_can_get_PSR_BO_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; -} - -static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; -} - -static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; -} - -static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; -} - -static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->PSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) -{ - return ((Can *)hw)->PSR.reg; -} - -static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->HPMS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) -{ - return ((Can *)hw)->HPMS.reg; -} - -static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; -} - -static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0S.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) -{ - return ((Can *)hw)->RXF0S.reg; -} - -static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; -} - -static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1S.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) -{ - return ((Can *)hw)->RXF1S.reg; -} - -static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXFQS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) -{ - return ((Can *)hw)->TXFQS.reg; -} - -static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; -} - -static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBRP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) -{ - return ((Can *)hw)->TXBRP.reg; -} - -static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; -} - -static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; -} - -static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; -} - -static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; -} - -static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; -} - -static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; -} - -static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; -} - -static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; -} - -static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; -} - -static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; -} - -static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; -} - -static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; -} - -static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; -} - -static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; -} - -static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; -} - -static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; -} - -static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; -} - -static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; -} - -static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; -} - -static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; -} - -static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; -} - -static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; -} - -static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; -} - -static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; -} - -static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; -} - -static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; -} - -static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; -} - -static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; -} - -static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; -} - -static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; -} - -static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; -} - -static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; -} - -static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTO.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) -{ - return ((Can *)hw)->TXBTO.reg; -} - -static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; -} - -static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; -} - -static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; -} - -static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; -} - -static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; -} - -static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; -} - -static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; -} - -static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; -} - -static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; -} - -static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; -} - -static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; -} - -static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; -} - -static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; -} - -static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; -} - -static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; -} - -static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; -} - -static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; -} - -static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; -} - -static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; -} - -static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; -} - -static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; -} - -static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; -} - -static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; -} - -static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; -} - -static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; -} - -static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; -} - -static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; -} - -static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; -} - -static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; -} - -static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; -} - -static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; -} - -static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; -} - -static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) -{ - return ((Can *)hw)->TXBCF.reg; -} - -static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; -} - -static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) -{ - return ((Can *)hw)->TXEFS.reg; -} - -static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->MRCFG.reg; - tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; - return tmp; -} - -static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->MRCFG.reg; - tmp &= ~CAN_MRCFG_QOS_Msk; - tmp |= CAN_MRCFG_QOS(data); - ((Can *)hw)->MRCFG.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->MRCFG.reg; - tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; - return tmp; -} - -static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->MRCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) -{ - return ((Can *)hw)->MRCFG.reg; -} - -static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_TDC; - tmp |= value << CAN_DBTP_TDC_Pos; - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DSJW_Msk; - tmp |= CAN_DBTP_DSJW(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DTSEG2_Msk; - tmp |= CAN_DBTP_DTSEG2(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DTSEG1_Msk; - tmp |= CAN_DBTP_DTSEG1(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DBRP_Msk; - tmp |= CAN_DBTP_DBRP(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) -{ - return ((Can *)hw)->DBTP.reg; -} - -static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TEST.reg; - tmp &= ~CAN_TEST_LBCK; - tmp |= value << CAN_TEST_LBCK_Pos; - ((Can *)hw)->TEST.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TEST_RX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= CAN_TEST_RX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TEST_RX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TEST.reg; - tmp &= ~CAN_TEST_RX; - tmp |= value << CAN_TEST_RX_Pos; - ((Can *)hw)->TEST.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_RX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; - return tmp; -} - -static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TEST.reg; - tmp &= ~CAN_TEST_TX_Msk; - tmp |= CAN_TEST_TX(data); - ((Can *)hw)->TEST.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; - return tmp; -} - -static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) -{ - return ((Can *)hw)->TEST.reg; -} - -static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; - return tmp; -} - -static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RWD.reg; - tmp &= ~CAN_RWD_WDC_Msk; - tmp |= CAN_RWD_WDC(data); - ((Can *)hw)->RWD.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; - return tmp; -} - -static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; - return tmp; -} - -static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RWD.reg; - tmp &= ~CAN_RWD_WDV_Msk; - tmp |= CAN_RWD_WDV(data); - ((Can *)hw)->RWD.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; - return tmp; -} - -static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) -{ - return ((Can *)hw)->RWD.reg; -} - -static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_INIT; - tmp |= value << CAN_CCCR_INIT_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_CCE; - tmp |= value << CAN_CCCR_CCE_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_ASM; - tmp |= value << CAN_CCCR_ASM_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_CSA; - tmp |= value << CAN_CCCR_CSA_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_CSR; - tmp |= value << CAN_CCCR_CSR_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_MON_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_MON; - tmp |= value << CAN_CCCR_MON_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_DAR; - tmp |= value << CAN_CCCR_DAR_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_TEST; - tmp |= value << CAN_CCCR_TEST_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_FDOE; - tmp |= value << CAN_CCCR_FDOE_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_BRSE; - tmp |= value << CAN_CCCR_BRSE_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_PXHD; - tmp |= value << CAN_CCCR_PXHD_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_EFBI; - tmp |= value << CAN_CCCR_EFBI_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_TXP; - tmp |= value << CAN_CCCR_TXP_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_NISO; - tmp |= value << CAN_CCCR_NISO_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) -{ - return ((Can *)hw)->CCCR.reg; -} - -static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NTSEG2_Msk; - tmp |= CAN_NBTP_NTSEG2(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NTSEG1_Msk; - tmp |= CAN_NBTP_NTSEG1(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NBRP_Msk; - tmp |= CAN_NBTP_NBRP(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NSJW_Msk; - tmp |= CAN_NBTP_NSJW(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) -{ - return ((Can *)hw)->NBTP.reg; -} - -static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; - return tmp; -} - -static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TSCC.reg; - tmp &= ~CAN_TSCC_TSS_Msk; - tmp |= CAN_TSCC_TSS(data); - ((Can *)hw)->TSCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; - return tmp; -} - -static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; - return tmp; -} - -static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TSCC.reg; - tmp &= ~CAN_TSCC_TCP_Msk; - tmp |= CAN_TSCC_TCP(data); - ((Can *)hw)->TSCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; - return tmp; -} - -static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) -{ - return ((Can *)hw)->TSCC.reg; -} - -static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCC.reg; - tmp &= ~CAN_TOCC_ETOC; - tmp |= value << CAN_TOCC_ETOC_Pos; - ((Can *)hw)->TOCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; - return tmp; -} - -static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCC.reg; - tmp &= ~CAN_TOCC_TOS_Msk; - tmp |= CAN_TOCC_TOS(data); - ((Can *)hw)->TOCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; - return tmp; -} - -static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; - return tmp; -} - -static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCC.reg; - tmp &= ~CAN_TOCC_TOP_Msk; - tmp |= CAN_TOCC_TOP(data); - ((Can *)hw)->TOCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; - return tmp; -} - -static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) -{ - return ((Can *)hw)->TOCC.reg; -} - -static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCV.reg; - tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; - return tmp; -} - -static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCV.reg; - tmp &= ~CAN_TOCV_TOC_Msk; - tmp |= CAN_TOCV_TOC(data); - ((Can *)hw)->TOCV.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCV.reg; - tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; - return tmp; -} - -static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) -{ - return ((Can *)hw)->TOCV.reg; -} - -static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; - return tmp; -} - -static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TDCR.reg; - tmp &= ~CAN_TDCR_TDCF_Msk; - tmp |= CAN_TDCR_TDCF(data); - ((Can *)hw)->TDCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; - return tmp; -} - -static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; - return tmp; -} - -static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TDCR.reg; - tmp &= ~CAN_TDCR_TDCO_Msk; - tmp |= CAN_TDCR_TDCO(data); - ((Can *)hw)->TDCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; - return tmp; -} - -static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) -{ - return ((Can *)hw)->TDCR.reg; -} - -static inline void hri_can_set_IR_RF0N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0N; - tmp |= value << CAN_IR_RF0N_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF0W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0W; - tmp |= value << CAN_IR_RF0W_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF0F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0F; - tmp |= value << CAN_IR_RF0F_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF0L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0L; - tmp |= value << CAN_IR_RF0L_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1N; - tmp |= value << CAN_IR_RF1N_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1W; - tmp |= value << CAN_IR_RF1W_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1F; - tmp |= value << CAN_IR_RF1F_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1L; - tmp |= value << CAN_IR_RF1L_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_HPM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_HPM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_HPM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_HPM; - tmp |= value << CAN_IR_HPM_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_HPM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_HPM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TC; - tmp |= value << CAN_IR_TC_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TCF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TCF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TCF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TCF; - tmp |= value << CAN_IR_TCF_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TCF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TCF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TFE; - tmp |= value << CAN_IR_TFE_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFN_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFN; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFN; - tmp |= value << CAN_IR_TEFN_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFW; - tmp |= value << CAN_IR_TEFW_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFF; - tmp |= value << CAN_IR_TEFF_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFL; - tmp |= value << CAN_IR_TEFL_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TSW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TSW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TSW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TSW; - tmp |= value << CAN_IR_TSW_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TSW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TSW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_MRAF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_MRAF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_MRAF; - tmp |= value << CAN_IR_MRAF_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TOO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TOO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TOO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TOO; - tmp |= value << CAN_IR_TOO_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TOO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TOO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_DRX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_DRX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_DRX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_DRX; - tmp |= value << CAN_IR_DRX_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_DRX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_DRX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_BEC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_BEC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_BEC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_BEC; - tmp |= value << CAN_IR_BEC_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_BEC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_BEC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_BEU_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_BEU; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_BEU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_BEU; - tmp |= value << CAN_IR_BEU_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_BEU_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_BEU; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_ELO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_ELO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_ELO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_ELO; - tmp |= value << CAN_IR_ELO_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_ELO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_ELO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_EP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_EP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_EP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_EP; - tmp |= value << CAN_IR_EP_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_EP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_EP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_EP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_EP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_EW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_EW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_EW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_EW; - tmp |= value << CAN_IR_EW_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_EW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_EW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_EW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_EW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_BO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_BO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_BO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_BO; - tmp |= value << CAN_IR_BO_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_BO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_BO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_BO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_BO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_WDI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_WDI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_WDI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_WDI; - tmp |= value << CAN_IR_WDI_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_WDI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_WDI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_PEA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_PEA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_PEA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_PEA; - tmp |= value << CAN_IR_PEA_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_PEA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_PEA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_PED_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_PED; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_PED_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_PED; - tmp |= value << CAN_IR_PED_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_PED_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_PED; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_PED_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_PED; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_ARA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_ARA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_ARA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_ARA; - tmp |= value << CAN_IR_ARA_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_ARA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_ARA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) -{ - return ((Can *)hw)->IR.reg; -} - -static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0NE; - tmp |= value << CAN_IE_RF0NE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0WE; - tmp |= value << CAN_IE_RF0WE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0FE; - tmp |= value << CAN_IE_RF0FE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0LE; - tmp |= value << CAN_IE_RF0LE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1NE; - tmp |= value << CAN_IE_RF1NE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1WE; - tmp |= value << CAN_IE_RF1WE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1FE; - tmp |= value << CAN_IE_RF1FE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1LE; - tmp |= value << CAN_IE_RF1LE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_HPME_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_HPME; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_HPME_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_HPME; - tmp |= value << CAN_IE_HPME_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_HPME_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_HPME; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TCE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TCE; - tmp |= value << CAN_IE_TCE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TCFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TCFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TCFE; - tmp |= value << CAN_IE_TCFE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TFEE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TFEE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TFEE; - tmp |= value << CAN_IE_TFEE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFNE; - tmp |= value << CAN_IE_TEFNE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFWE; - tmp |= value << CAN_IE_TEFWE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFFE; - tmp |= value << CAN_IE_TEFFE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFLE; - tmp |= value << CAN_IE_TEFLE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TSWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TSWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TSWE; - tmp |= value << CAN_IE_TSWE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_MRAFE; - tmp |= value << CAN_IE_MRAFE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TOOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TOOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TOOE; - tmp |= value << CAN_IE_TOOE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_DRXE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_DRXE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_DRXE; - tmp |= value << CAN_IE_DRXE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_BECE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_BECE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_BECE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_BECE; - tmp |= value << CAN_IE_BECE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_BECE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_BECE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_BEUE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_BEUE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_BEUE; - tmp |= value << CAN_IE_BEUE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_ELOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_ELOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_ELOE; - tmp |= value << CAN_IE_ELOE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_EPE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_EPE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_EPE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_EPE; - tmp |= value << CAN_IE_EPE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_EPE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_EPE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_EWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_EWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_EWE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_EWE; - tmp |= value << CAN_IE_EWE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_EWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_EWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_BOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_BOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_BOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_BOE; - tmp |= value << CAN_IE_BOE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_BOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_BOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_WDIE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_WDIE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_WDIE; - tmp |= value << CAN_IE_WDIE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_PEAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_PEAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_PEAE; - tmp |= value << CAN_IE_PEAE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_PEDE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_PEDE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_PEDE; - tmp |= value << CAN_IE_PEDE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_ARAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_ARAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_ARAE; - tmp |= value << CAN_IE_ARAE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) -{ - return ((Can *)hw)->IE.reg; -} - -static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0NL; - tmp |= value << CAN_ILS_RF0NL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0WL; - tmp |= value << CAN_ILS_RF0WL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0FL; - tmp |= value << CAN_ILS_RF0FL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0LL; - tmp |= value << CAN_ILS_RF0LL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1NL; - tmp |= value << CAN_ILS_RF1NL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1WL; - tmp |= value << CAN_ILS_RF1WL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1FL; - tmp |= value << CAN_ILS_RF1FL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1LL; - tmp |= value << CAN_ILS_RF1LL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_HPML_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_HPML; - tmp |= value << CAN_ILS_HPML_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TCL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TCL; - tmp |= value << CAN_ILS_TCL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TCFL; - tmp |= value << CAN_ILS_TCFL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TFEL; - tmp |= value << CAN_ILS_TFEL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFNL; - tmp |= value << CAN_ILS_TEFNL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFWL; - tmp |= value << CAN_ILS_TEFWL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFFL; - tmp |= value << CAN_ILS_TEFFL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFLL; - tmp |= value << CAN_ILS_TEFLL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TSWL; - tmp |= value << CAN_ILS_TSWL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_MRAFL; - tmp |= value << CAN_ILS_MRAFL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TOOL; - tmp |= value << CAN_ILS_TOOL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_DRXL; - tmp |= value << CAN_ILS_DRXL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_BECL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_BECL; - tmp |= value << CAN_ILS_BECL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_BEUL; - tmp |= value << CAN_ILS_BEUL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_ELOL; - tmp |= value << CAN_ILS_ELOL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_EPL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_EPL; - tmp |= value << CAN_ILS_EPL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_EWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_EWL; - tmp |= value << CAN_ILS_EWL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_BOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_BOL; - tmp |= value << CAN_ILS_BOL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_WDIL; - tmp |= value << CAN_ILS_WDIL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_PEAL; - tmp |= value << CAN_ILS_PEAL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_PEDL; - tmp |= value << CAN_ILS_PEDL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_ARAL; - tmp |= value << CAN_ILS_ARAL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) -{ - return ((Can *)hw)->ILS.reg; -} - -static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILE.reg; - tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILE.reg; - tmp &= ~CAN_ILE_EINT0; - tmp |= value << CAN_ILE_EINT0_Pos; - ((Can *)hw)->ILE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILE.reg; - tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILE.reg; - tmp &= ~CAN_ILE_EINT1; - tmp |= value << CAN_ILE_EINT1_Pos; - ((Can *)hw)->ILE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) -{ - return ((Can *)hw)->ILE.reg; -} - -static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_RRFE; - tmp |= value << CAN_GFC_RRFE_Pos; - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_RRFS; - tmp |= value << CAN_GFC_RRFS_Pos; - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; - return tmp; -} - -static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_ANFE_Msk; - tmp |= CAN_GFC_ANFE(data); - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; - return tmp; -} - -static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; - return tmp; -} - -static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_ANFS_Msk; - tmp |= CAN_GFC_ANFS(data); - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; - return tmp; -} - -static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) -{ - return ((Can *)hw)->GFC.reg; -} - -static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; - return tmp; -} - -static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->SIDFC.reg; - tmp &= ~CAN_SIDFC_FLSSA_Msk; - tmp |= CAN_SIDFC_FLSSA(data); - ((Can *)hw)->SIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; - return tmp; -} - -static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; - return tmp; -} - -static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->SIDFC.reg; - tmp &= ~CAN_SIDFC_LSS_Msk; - tmp |= CAN_SIDFC_LSS(data); - ((Can *)hw)->SIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; - return tmp; -} - -static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) -{ - return ((Can *)hw)->SIDFC.reg; -} - -static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; - return tmp; -} - -static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->XIDFC.reg; - tmp &= ~CAN_XIDFC_FLESA_Msk; - tmp |= CAN_XIDFC_FLESA(data); - ((Can *)hw)->XIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; - return tmp; -} - -static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; - return tmp; -} - -static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->XIDFC.reg; - tmp &= ~CAN_XIDFC_LSE_Msk; - tmp |= CAN_XIDFC_LSE(data); - ((Can *)hw)->XIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; - return tmp; -} - -static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) -{ - return ((Can *)hw)->XIDFC.reg; -} - -static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDAM.reg; - tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; - return tmp; -} - -static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->XIDAM.reg; - tmp &= ~CAN_XIDAM_EIDM_Msk; - tmp |= CAN_XIDAM_EIDM(data); - ((Can *)hw)->XIDAM.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDAM.reg; - tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; - return tmp; -} - -static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDAM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) -{ - return ((Can *)hw)->XIDAM.reg; -} - -static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND0; - tmp |= value << CAN_NDAT1_ND0_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND1; - tmp |= value << CAN_NDAT1_ND1_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND2; - tmp |= value << CAN_NDAT1_ND2_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND3; - tmp |= value << CAN_NDAT1_ND3_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND4; - tmp |= value << CAN_NDAT1_ND4_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND5; - tmp |= value << CAN_NDAT1_ND5_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND6; - tmp |= value << CAN_NDAT1_ND6_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND7; - tmp |= value << CAN_NDAT1_ND7_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND8; - tmp |= value << CAN_NDAT1_ND8_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND9; - tmp |= value << CAN_NDAT1_ND9_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND10; - tmp |= value << CAN_NDAT1_ND10_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND11; - tmp |= value << CAN_NDAT1_ND11_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND12; - tmp |= value << CAN_NDAT1_ND12_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND13; - tmp |= value << CAN_NDAT1_ND13_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND14; - tmp |= value << CAN_NDAT1_ND14_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND15; - tmp |= value << CAN_NDAT1_ND15_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND16; - tmp |= value << CAN_NDAT1_ND16_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND17; - tmp |= value << CAN_NDAT1_ND17_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND18; - tmp |= value << CAN_NDAT1_ND18_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND19; - tmp |= value << CAN_NDAT1_ND19_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND20; - tmp |= value << CAN_NDAT1_ND20_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND21; - tmp |= value << CAN_NDAT1_ND21_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND22; - tmp |= value << CAN_NDAT1_ND22_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND23; - tmp |= value << CAN_NDAT1_ND23_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND24; - tmp |= value << CAN_NDAT1_ND24_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND25; - tmp |= value << CAN_NDAT1_ND25_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND26; - tmp |= value << CAN_NDAT1_ND26_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND27; - tmp |= value << CAN_NDAT1_ND27_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND28; - tmp |= value << CAN_NDAT1_ND28_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND29; - tmp |= value << CAN_NDAT1_ND29_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND30; - tmp |= value << CAN_NDAT1_ND30_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND31; - tmp |= value << CAN_NDAT1_ND31_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) -{ - return ((Can *)hw)->NDAT1.reg; -} - -static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND32; - tmp |= value << CAN_NDAT2_ND32_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND33; - tmp |= value << CAN_NDAT2_ND33_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND34; - tmp |= value << CAN_NDAT2_ND34_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND35; - tmp |= value << CAN_NDAT2_ND35_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND36; - tmp |= value << CAN_NDAT2_ND36_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND37; - tmp |= value << CAN_NDAT2_ND37_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND38; - tmp |= value << CAN_NDAT2_ND38_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND39; - tmp |= value << CAN_NDAT2_ND39_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND40; - tmp |= value << CAN_NDAT2_ND40_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND41; - tmp |= value << CAN_NDAT2_ND41_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND42; - tmp |= value << CAN_NDAT2_ND42_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND43; - tmp |= value << CAN_NDAT2_ND43_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND44; - tmp |= value << CAN_NDAT2_ND44_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND45; - tmp |= value << CAN_NDAT2_ND45_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND46; - tmp |= value << CAN_NDAT2_ND46_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND47; - tmp |= value << CAN_NDAT2_ND47_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND48; - tmp |= value << CAN_NDAT2_ND48_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND49; - tmp |= value << CAN_NDAT2_ND49_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND50; - tmp |= value << CAN_NDAT2_ND50_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND51; - tmp |= value << CAN_NDAT2_ND51_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND52; - tmp |= value << CAN_NDAT2_ND52_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND53; - tmp |= value << CAN_NDAT2_ND53_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND54; - tmp |= value << CAN_NDAT2_ND54_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND55; - tmp |= value << CAN_NDAT2_ND55_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND56; - tmp |= value << CAN_NDAT2_ND56_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND57; - tmp |= value << CAN_NDAT2_ND57_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND58; - tmp |= value << CAN_NDAT2_ND58_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND59; - tmp |= value << CAN_NDAT2_ND59_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND60; - tmp |= value << CAN_NDAT2_ND60_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND61; - tmp |= value << CAN_NDAT2_ND61_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND62; - tmp |= value << CAN_NDAT2_ND62_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND63; - tmp |= value << CAN_NDAT2_ND63_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) -{ - return ((Can *)hw)->NDAT2.reg; -} - -static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0OM; - tmp |= value << CAN_RXF0C_F0OM_Pos; - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0SA_Msk; - tmp |= CAN_RXF0C_F0SA(data); - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0S_Msk; - tmp |= CAN_RXF0C_F0S(data); - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0WM_Msk; - tmp |= CAN_RXF0C_F0WM(data); - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) -{ - return ((Can *)hw)->RXF0C.reg; -} - -static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0A.reg; - tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0A.reg; - tmp &= ~CAN_RXF0A_F0AI_Msk; - tmp |= CAN_RXF0A_F0AI(data); - ((Can *)hw)->RXF0A.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0A.reg; - tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0A.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) -{ - return ((Can *)hw)->RXF0A.reg; -} - -static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXBC.reg; - tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; - return tmp; -} - -static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXBC.reg; - tmp &= ~CAN_RXBC_RBSA_Msk; - tmp |= CAN_RXBC_RBSA(data); - ((Can *)hw)->RXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXBC.reg; - tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; - return tmp; -} - -static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXBC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) -{ - return ((Can *)hw)->RXBC.reg; -} - -static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1OM; - tmp |= value << CAN_RXF1C_F1OM_Pos; - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1SA_Msk; - tmp |= CAN_RXF1C_F1SA(data); - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1S_Msk; - tmp |= CAN_RXF1C_F1S(data); - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1WM_Msk; - tmp |= CAN_RXF1C_F1WM(data); - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) -{ - return ((Can *)hw)->RXF1C.reg; -} - -static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1A.reg; - tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1A.reg; - tmp &= ~CAN_RXF1A_F1AI_Msk; - tmp |= CAN_RXF1A_F1AI(data); - ((Can *)hw)->RXF1A.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1A.reg; - tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1A.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) -{ - return ((Can *)hw)->RXF1A.reg; -} - -static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; - return tmp; -} - -static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXESC.reg; - tmp &= ~CAN_RXESC_F0DS_Msk; - tmp |= CAN_RXESC_F0DS(data); - ((Can *)hw)->RXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; - return tmp; -} - -static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; - return tmp; -} - -static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXESC.reg; - tmp &= ~CAN_RXESC_F1DS_Msk; - tmp |= CAN_RXESC_F1DS(data); - ((Can *)hw)->RXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; - return tmp; -} - -static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; - return tmp; -} - -static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXESC.reg; - tmp &= ~CAN_RXESC_RBDS_Msk; - tmp |= CAN_RXESC_RBDS(data); - ((Can *)hw)->RXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; - return tmp; -} - -static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) -{ - return ((Can *)hw)->RXESC.reg; -} - -static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_TFQM; - tmp |= value << CAN_TXBC_TFQM_Pos; - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; - return tmp; -} - -static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_TBSA_Msk; - tmp |= CAN_TXBC_TBSA(data); - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; - return tmp; -} - -static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; - return tmp; -} - -static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_NDTB_Msk; - tmp |= CAN_TXBC_NDTB(data); - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; - return tmp; -} - -static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; - return tmp; -} - -static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_TFQS_Msk; - tmp |= CAN_TXBC_TFQS(data); - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; - return tmp; -} - -static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) -{ - return ((Can *)hw)->TXBC.reg; -} - -static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXESC.reg; - tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; - return tmp; -} - -static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXESC.reg; - tmp &= ~CAN_TXESC_TBDS_Msk; - tmp |= CAN_TXESC_TBDS(data); - ((Can *)hw)->TXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXESC.reg; - tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; - return tmp; -} - -static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) -{ - return ((Can *)hw)->TXESC.reg; -} - -static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR0; - tmp |= value << CAN_TXBAR_AR0_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR1; - tmp |= value << CAN_TXBAR_AR1_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR2; - tmp |= value << CAN_TXBAR_AR2_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR3; - tmp |= value << CAN_TXBAR_AR3_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR4; - tmp |= value << CAN_TXBAR_AR4_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR5; - tmp |= value << CAN_TXBAR_AR5_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR6; - tmp |= value << CAN_TXBAR_AR6_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR7; - tmp |= value << CAN_TXBAR_AR7_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR8; - tmp |= value << CAN_TXBAR_AR8_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR9; - tmp |= value << CAN_TXBAR_AR9_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR10; - tmp |= value << CAN_TXBAR_AR10_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR11; - tmp |= value << CAN_TXBAR_AR11_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR12; - tmp |= value << CAN_TXBAR_AR12_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR13; - tmp |= value << CAN_TXBAR_AR13_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR14; - tmp |= value << CAN_TXBAR_AR14_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR15; - tmp |= value << CAN_TXBAR_AR15_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR16; - tmp |= value << CAN_TXBAR_AR16_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR17; - tmp |= value << CAN_TXBAR_AR17_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR18; - tmp |= value << CAN_TXBAR_AR18_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR19; - tmp |= value << CAN_TXBAR_AR19_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR20; - tmp |= value << CAN_TXBAR_AR20_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR21; - tmp |= value << CAN_TXBAR_AR21_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR22; - tmp |= value << CAN_TXBAR_AR22_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR23; - tmp |= value << CAN_TXBAR_AR23_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR24; - tmp |= value << CAN_TXBAR_AR24_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR25; - tmp |= value << CAN_TXBAR_AR25_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR26; - tmp |= value << CAN_TXBAR_AR26_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR27; - tmp |= value << CAN_TXBAR_AR27_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR28; - tmp |= value << CAN_TXBAR_AR28_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR29; - tmp |= value << CAN_TXBAR_AR29_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR30; - tmp |= value << CAN_TXBAR_AR30_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR31; - tmp |= value << CAN_TXBAR_AR31_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) -{ - return ((Can *)hw)->TXBAR.reg; -} - -static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR0; - tmp |= value << CAN_TXBCR_CR0_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR1; - tmp |= value << CAN_TXBCR_CR1_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR2; - tmp |= value << CAN_TXBCR_CR2_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR3; - tmp |= value << CAN_TXBCR_CR3_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR4; - tmp |= value << CAN_TXBCR_CR4_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR5; - tmp |= value << CAN_TXBCR_CR5_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR6; - tmp |= value << CAN_TXBCR_CR6_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR7; - tmp |= value << CAN_TXBCR_CR7_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR8; - tmp |= value << CAN_TXBCR_CR8_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR9; - tmp |= value << CAN_TXBCR_CR9_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR10; - tmp |= value << CAN_TXBCR_CR10_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR11; - tmp |= value << CAN_TXBCR_CR11_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR12; - tmp |= value << CAN_TXBCR_CR12_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR13; - tmp |= value << CAN_TXBCR_CR13_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR14; - tmp |= value << CAN_TXBCR_CR14_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR15; - tmp |= value << CAN_TXBCR_CR15_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR16; - tmp |= value << CAN_TXBCR_CR16_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR17; - tmp |= value << CAN_TXBCR_CR17_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR18; - tmp |= value << CAN_TXBCR_CR18_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR19; - tmp |= value << CAN_TXBCR_CR19_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR20; - tmp |= value << CAN_TXBCR_CR20_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR21; - tmp |= value << CAN_TXBCR_CR21_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR22; - tmp |= value << CAN_TXBCR_CR22_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR23; - tmp |= value << CAN_TXBCR_CR23_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR24; - tmp |= value << CAN_TXBCR_CR24_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR25; - tmp |= value << CAN_TXBCR_CR25_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR26; - tmp |= value << CAN_TXBCR_CR26_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR27; - tmp |= value << CAN_TXBCR_CR27_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR28; - tmp |= value << CAN_TXBCR_CR28_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR29; - tmp |= value << CAN_TXBCR_CR29_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR30; - tmp |= value << CAN_TXBCR_CR30_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR31; - tmp |= value << CAN_TXBCR_CR31_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) -{ - return ((Can *)hw)->TXBCR.reg; -} - -static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE0; - tmp |= value << CAN_TXBTIE_TIE0_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE1; - tmp |= value << CAN_TXBTIE_TIE1_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE2; - tmp |= value << CAN_TXBTIE_TIE2_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE3; - tmp |= value << CAN_TXBTIE_TIE3_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE4; - tmp |= value << CAN_TXBTIE_TIE4_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE5; - tmp |= value << CAN_TXBTIE_TIE5_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE6; - tmp |= value << CAN_TXBTIE_TIE6_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE7; - tmp |= value << CAN_TXBTIE_TIE7_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE8; - tmp |= value << CAN_TXBTIE_TIE8_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE9; - tmp |= value << CAN_TXBTIE_TIE9_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE10; - tmp |= value << CAN_TXBTIE_TIE10_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE11; - tmp |= value << CAN_TXBTIE_TIE11_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE12; - tmp |= value << CAN_TXBTIE_TIE12_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE13; - tmp |= value << CAN_TXBTIE_TIE13_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE14; - tmp |= value << CAN_TXBTIE_TIE14_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE15; - tmp |= value << CAN_TXBTIE_TIE15_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE16; - tmp |= value << CAN_TXBTIE_TIE16_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE17; - tmp |= value << CAN_TXBTIE_TIE17_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE18; - tmp |= value << CAN_TXBTIE_TIE18_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE19; - tmp |= value << CAN_TXBTIE_TIE19_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE20; - tmp |= value << CAN_TXBTIE_TIE20_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE21; - tmp |= value << CAN_TXBTIE_TIE21_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE22; - tmp |= value << CAN_TXBTIE_TIE22_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE23; - tmp |= value << CAN_TXBTIE_TIE23_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE24; - tmp |= value << CAN_TXBTIE_TIE24_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE25; - tmp |= value << CAN_TXBTIE_TIE25_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE26; - tmp |= value << CAN_TXBTIE_TIE26_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE27; - tmp |= value << CAN_TXBTIE_TIE27_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE28; - tmp |= value << CAN_TXBTIE_TIE28_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE29; - tmp |= value << CAN_TXBTIE_TIE29_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE30; - tmp |= value << CAN_TXBTIE_TIE30_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE31; - tmp |= value << CAN_TXBTIE_TIE31_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) -{ - return ((Can *)hw)->TXBTIE.reg; -} - -static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE0; - tmp |= value << CAN_TXBCIE_CFIE0_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE1; - tmp |= value << CAN_TXBCIE_CFIE1_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE2; - tmp |= value << CAN_TXBCIE_CFIE2_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE3; - tmp |= value << CAN_TXBCIE_CFIE3_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE4; - tmp |= value << CAN_TXBCIE_CFIE4_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE5; - tmp |= value << CAN_TXBCIE_CFIE5_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE6; - tmp |= value << CAN_TXBCIE_CFIE6_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE7; - tmp |= value << CAN_TXBCIE_CFIE7_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE8; - tmp |= value << CAN_TXBCIE_CFIE8_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE9; - tmp |= value << CAN_TXBCIE_CFIE9_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE10; - tmp |= value << CAN_TXBCIE_CFIE10_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE11; - tmp |= value << CAN_TXBCIE_CFIE11_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE12; - tmp |= value << CAN_TXBCIE_CFIE12_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE13; - tmp |= value << CAN_TXBCIE_CFIE13_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE14; - tmp |= value << CAN_TXBCIE_CFIE14_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE15; - tmp |= value << CAN_TXBCIE_CFIE15_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE16; - tmp |= value << CAN_TXBCIE_CFIE16_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE17; - tmp |= value << CAN_TXBCIE_CFIE17_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE18; - tmp |= value << CAN_TXBCIE_CFIE18_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE19; - tmp |= value << CAN_TXBCIE_CFIE19_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE20; - tmp |= value << CAN_TXBCIE_CFIE20_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE21; - tmp |= value << CAN_TXBCIE_CFIE21_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE22; - tmp |= value << CAN_TXBCIE_CFIE22_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE23; - tmp |= value << CAN_TXBCIE_CFIE23_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE24; - tmp |= value << CAN_TXBCIE_CFIE24_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE25; - tmp |= value << CAN_TXBCIE_CFIE25_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE26; - tmp |= value << CAN_TXBCIE_CFIE26_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE27; - tmp |= value << CAN_TXBCIE_CFIE27_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE28; - tmp |= value << CAN_TXBCIE_CFIE28_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE29; - tmp |= value << CAN_TXBCIE_CFIE29_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE30; - tmp |= value << CAN_TXBCIE_CFIE30_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE31; - tmp |= value << CAN_TXBCIE_CFIE31_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) -{ - return ((Can *)hw)->TXBCIE.reg; -} - -static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= ~CAN_TXEFC_EFSA_Msk; - tmp |= CAN_TXEFC_EFSA(data); - ((Can *)hw)->TXEFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= ~CAN_TXEFC_EFS_Msk; - tmp |= CAN_TXEFC_EFS(data); - ((Can *)hw)->TXEFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= ~CAN_TXEFC_EFWM_Msk; - tmp |= CAN_TXEFC_EFWM(data); - ((Can *)hw)->TXEFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) -{ - return ((Can *)hw)->TXEFC.reg; -} - -static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFA.reg; - tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFA.reg; - tmp &= ~CAN_TXEFA_EFAI_Msk; - tmp |= CAN_TXEFA_EFAI(data); - ((Can *)hw)->TXEFA.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFA.reg; - tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) -{ - return ((Can *)hw)->TXEFA.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CAN_E54_H_INCLUDED */ -#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_ccl_e54.h b/software/firmware/project_oracle_base/hri/hri_ccl_e54.h deleted file mode 100644 index c5c4867..0000000 --- a/software/firmware/project_oracle_base/hri/hri_ccl_e54.h +++ /dev/null @@ -1,776 +0,0 @@ -/** - * \file - * - * \brief SAM CCL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_CCL_COMPONENT_ -#ifndef _HRI_CCL_E54_H_INCLUDED_ -#define _HRI_CCL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CCL_CRITICAL_SECTIONS) -#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CCL_CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_ccl_lutctrl_reg_t; -typedef uint8_t hri_ccl_ctrl_reg_t; -typedef uint8_t hri_ccl_seqctrl_reg_t; - -static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_ENABLE; - tmp |= value << CCL_CTRL_ENABLE_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_RUNSTDBY; - tmp |= value << CCL_CTRL_RUNSTDBY_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) -{ - return ((Ccl *)hw)->CTRL.reg; -} - -static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; - tmp |= CCL_SEQCTRL_SEQSEL(data); - ((Ccl *)hw)->SEQCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->SEQCTRL[index].reg; -} - -static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_ENABLE; - tmp |= value << CCL_LUTCTRL_ENABLE_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_EDGESEL; - tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INVEI; - tmp |= value << CCL_LUTCTRL_INVEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEI; - tmp |= value << CCL_LUTCTRL_LUTEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEO; - tmp |= value << CCL_LUTCTRL_LUTEO_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; - tmp |= CCL_LUTCTRL_FILTSEL(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL0_Msk; - tmp |= CCL_LUTCTRL_INSEL0(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL1_Msk; - tmp |= CCL_LUTCTRL_INSEL1(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL2_Msk; - tmp |= CCL_LUTCTRL_INSEL2(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_TRUTH_Msk; - tmp |= CCL_LUTCTRL_TRUTH(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->LUTCTRL[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CCL_E54_H_INCLUDED */ -#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_cmcc_e54.h b/software/firmware/project_oracle_base/hri/hri_cmcc_e54.h deleted file mode 100644 index c973d35..0000000 --- a/software/firmware/project_oracle_base/hri/hri_cmcc_e54.h +++ /dev/null @@ -1,361 +0,0 @@ -/** - * \file - * - * \brief SAM CMCC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_CMCC_COMPONENT_ -#ifndef _HRI_CMCC_E54_H_INCLUDED_ -#define _HRI_CMCC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) -#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CMCC_CRITICAL_SECTION_ENTER() -#define CMCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_cmcc_cfg_reg_t; -typedef uint32_t hri_cmcc_ctrl_reg_t; -typedef uint32_t hri_cmcc_lckway_reg_t; -typedef uint32_t hri_cmcc_maint0_reg_t; -typedef uint32_t hri_cmcc_maint1_reg_t; -typedef uint32_t hri_cmcc_mcfg_reg_t; -typedef uint32_t hri_cmcc_mctrl_reg_t; -typedef uint32_t hri_cmcc_men_reg_t; -typedef uint32_t hri_cmcc_msr_reg_t; -typedef uint32_t hri_cmcc_sr_reg_t; -typedef uint32_t hri_cmcc_type_reg_t; - -static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; -} - -static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; -} - -static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->TYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) -{ - return ((Cmcc *)hw)->TYPE.reg; -} - -static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) -{ - return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; -} - -static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->SR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) -{ - return ((Cmcc *)hw)->SR.reg; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) -{ - return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) -{ - return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MSR.reg; -} - -static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) -{ - return ((Cmcc *)hw)->CFG.reg; -} - -static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->LCKWAY.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) -{ - return ((Cmcc *)hw)->LCKWAY.reg; -} - -static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MCFG.reg; -} - -static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MEN.reg; -} - -static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CTRL.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MAINT0.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MAINT1.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCTRL.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CMCC_E54_H_INCLUDED */ -#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_dac_e54.h b/software/firmware/project_oracle_base/hri/hri_dac_e54.h deleted file mode 100644 index 911dd52..0000000 --- a/software/firmware/project_oracle_base/hri/hri_dac_e54.h +++ /dev/null @@ -1,1706 +0,0 @@ -/** - * \file - * - * \brief SAM DAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_DAC_COMPONENT_ -#ifndef _HRI_DAC_E54_H_INCLUDED_ -#define _HRI_DAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DAC_CRITICAL_SECTIONS) -#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DAC_CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dac_dacctrl_reg_t; -typedef uint16_t hri_dac_data_reg_t; -typedef uint16_t hri_dac_databuf_reg_t; -typedef uint16_t hri_dac_result_reg_t; -typedef uint32_t hri_dac_syncbusy_reg_t; -typedef uint8_t hri_dac_ctrla_reg_t; -typedef uint8_t hri_dac_ctrlb_reg_t; -typedef uint8_t hri_dac_dbgctrl_reg_t; -typedef uint8_t hri_dac_evctrl_reg_t; -typedef uint8_t hri_dac_intenset_reg_t; -typedef uint8_t hri_dac_intflag_reg_t; -typedef uint8_t hri_dac_status_reg_t; - -static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) -{ - while (((Dac *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) -{ - return ((Dac *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; -} - -static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; -} - -static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; -} - -static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; -} - -static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; -} - -static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; -} - -static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; -} - -static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; -} - -static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; -} - -static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; -} - -static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; -} - -static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; -} - -static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; -} - -static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; -} - -static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; -} - -static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; -} - -static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; -} - -static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; -} - -static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; -} - -static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; -} - -static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; -} - -static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; -} - -static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; -} - -static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; -} - -static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) -{ - return ((Dac *)hw)->INTFLAG.reg; -} - -static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - ((Dac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; -} - -static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; -} - -static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; - } -} - -static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; -} - -static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; -} - -static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; -} - -static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; - } -} - -static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; -} - -static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; -} - -static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; -} - -static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; - } -} - -static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; -} - -static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; -} - -static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; -} - -static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; - } -} - -static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; -} - -static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; -} - -static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; -} - -static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; - } -} - -static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; -} - -static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; -} - -static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; -} - -static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; - } -} - -static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; -} - -static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; -} - -static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; -} - -static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; - } -} - -static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; -} - -static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; -} - -static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; -} - -static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; - } -} - -static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; -} - -static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENSET.reg = mask; -} - -static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) -{ - return ((Dac *)hw)->INTENSET.reg; -} - -static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) -{ - ((Dac *)hw)->INTENSET.reg = data; - ((Dac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; -} - -static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; -} - -static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; -} - -static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; -} - -static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) -{ - return ((Dac *)hw)->STATUS.reg; -} - -static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; -} - -static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dac *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Dac *)hw)->SYNCBUSY.reg; -} - -static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, - hri_dac_result_reg_t mask) -{ - return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; -} - -static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) -{ - return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; -} - -static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, - hri_dac_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->RESULT[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) -{ - return ((Dac *)hw)->RESULT[index].reg; -} - -static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= ~DAC_CTRLA_ENABLE; - tmp |= value << DAC_CTRLA_ENABLE_Pos; - ((Dac *)hw)->CTRLA.reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg &= ~mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg ^= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) -{ - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - return ((Dac *)hw)->CTRLA.reg; -} - -static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_DIFF; - tmp |= value << DAC_CTRLB_DIFF_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_REFSEL_Msk; - tmp |= DAC_CTRLB_REFSEL(data); - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) -{ - return ((Dac *)hw)->CTRLB.reg; -} - -static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_STARTEI0; - tmp |= value << DAC_EVCTRL_STARTEI0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_STARTEI1; - tmp |= value << DAC_EVCTRL_STARTEI1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_EMPTYEO0; - tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_EMPTYEO1; - tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_INVEI0; - tmp |= value << DAC_EVCTRL_INVEI0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_INVEI1; - tmp |= value << DAC_EVCTRL_INVEI1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_RESRDYEO0; - tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_RESRDYEO1; - tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) -{ - return ((Dac *)hw)->EVCTRL.reg; -} - -static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_LEFTADJ; - tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_ENABLE; - tmp |= value << DAC_DACCTRL_ENABLE_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_FEXT; - tmp |= value << DAC_DACCTRL_FEXT_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_RUNSTDBY; - tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_DITHER; - tmp |= value << DAC_DACCTRL_DITHER_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_CCTRL_Msk; - tmp |= DAC_DACCTRL_CCTRL(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_REFRESH_Msk; - tmp |= DAC_DACCTRL_REFRESH(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_OSR_Msk; - tmp |= DAC_DACCTRL_OSR(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) -{ - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - return ((Dac *)hw)->DACCTRL[index].reg; -} - -static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp &= ~DAC_DBGCTRL_DBGRUN; - tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; - ((Dac *)hw)->DBGCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dac *)hw)->DBGCTRL.reg; -} - -static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATA[index].reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATABUF[index].reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); - DAC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DAC_E54_H_INCLUDED */ -#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_dmac_e54.h b/software/firmware/project_oracle_base/hri/hri_dmac_e54.h deleted file mode 100644 index b4a6ba1..0000000 --- a/software/firmware/project_oracle_base/hri/hri_dmac_e54.h +++ /dev/null @@ -1,6800 +0,0 @@ -/** - * \file - * - * \brief SAM DMAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_DMAC_COMPONENT_ -#ifndef _HRI_DMAC_E54_H_INCLUDED_ -#define _HRI_DMAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) -#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DMAC_CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dmac_crcctrl_reg_t; -typedef uint16_t hri_dmac_ctrl_reg_t; -typedef uint16_t hri_dmac_intpend_reg_t; -typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; -typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; -typedef uint32_t hri_dmac_active_reg_t; -typedef uint32_t hri_dmac_baseaddr_reg_t; -typedef uint32_t hri_dmac_busych_reg_t; -typedef uint32_t hri_dmac_chctrla_reg_t; -typedef uint32_t hri_dmac_crcchksum_reg_t; -typedef uint32_t hri_dmac_crcdatain_reg_t; -typedef uint32_t hri_dmac_intstatus_reg_t; -typedef uint32_t hri_dmac_pendch_reg_t; -typedef uint32_t hri_dmac_prictrl0_reg_t; -typedef uint32_t hri_dmac_swtrigctrl_reg_t; -typedef uint32_t hri_dmac_wrbaddr_reg_t; -typedef uint32_t hri_dmacchannel_chctrla_reg_t; -typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; -typedef uint8_t hri_dmac_chctrlb_reg_t; -typedef uint8_t hri_dmac_chevctrl_reg_t; -typedef uint8_t hri_dmac_chintenset_reg_t; -typedef uint8_t hri_dmac_chintflag_reg_t; -typedef uint8_t hri_dmac_chprilvl_reg_t; -typedef uint8_t hri_dmac_chstatus_reg_t; -typedef uint8_t hri_dmac_crcstatus_reg_t; -typedef uint8_t hri_dmac_dbgctrl_reg_t; -typedef uint8_t hri_dmacchannel_chctrlb_reg_t; -typedef uint8_t hri_dmacchannel_chevctrl_reg_t; -typedef uint8_t hri_dmacchannel_chintenset_reg_t; -typedef uint8_t hri_dmacchannel_chintflag_reg_t; -typedef uint8_t hri_dmacchannel_chprilvl_reg_t; -typedef uint8_t hri_dmacchannel_chstatus_reg_t; - -static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTSTATUS.reg; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; -} - -static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->BUSYCH.reg; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PENDCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->PENDCH.reg; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->ACTIVE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) -{ - return ((Dmac *)hw)->ACTIVE.reg; -} - -static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_DMAENABLE; - tmp |= value << DMAC_CTRL_DMAENABLE_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN0; - tmp |= value << DMAC_CTRL_LVLEN0_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN1; - tmp |= value << DMAC_CTRL_LVLEN1_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN2; - tmp |= value << DMAC_CTRL_LVLEN2_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN3; - tmp |= value << DMAC_CTRL_LVLEN3_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CTRL.reg; -} - -static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, - hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; - tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; - tmp |= DMAC_CRCCTRL_CRCPOLY(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; - tmp |= DMAC_CRCCTRL_CRCSRC(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; - tmp |= DMAC_CRCCTRL_CRCMODE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCTRL.reg; -} - -static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, - hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; - tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); - ((Dmac *)hw)->CRCDATAIN.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCDATAIN.reg; -} - -static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, - hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; - tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); - ((Dmac *)hw)->CRCCHKSUM.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCHKSUM.reg; -} - -static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= ~DMAC_DBGCTRL_DBGRUN; - tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; - ((Dmac *)hw)->DBGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->DBGCTRL.reg; -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, - hri_dmac_swtrigctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->SWTRIGCTRL.reg; -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN0; - tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN1; - tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN2; - tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN3; - tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS0_Msk; - tmp |= DMAC_PRICTRL0_QOS0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS1_Msk; - tmp |= DMAC_PRICTRL0_QOS1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS2_Msk; - tmp |= DMAC_PRICTRL0_QOS2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS3_Msk; - tmp |= DMAC_PRICTRL0_QOS3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) -{ - return ((Dmac *)hw)->PRICTRL0.reg; -} - -static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TERR; - tmp |= value << DMAC_INTPEND_TERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TCMPL; - tmp |= value << DMAC_INTPEND_TCMPL_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_SUSP; - tmp |= value << DMAC_INTPEND_SUSP_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_CRCERR; - tmp |= value << DMAC_INTPEND_CRCERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_FERR; - tmp |= value << DMAC_INTPEND_FERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_BUSY; - tmp |= value << DMAC_INTPEND_BUSY_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_PEND; - tmp |= value << DMAC_INTPEND_PEND_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_ID_Msk; - tmp |= DMAC_INTPEND_ID(data); - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTPEND.reg; -} - -static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, - hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; - tmp |= DMAC_BASEADDR_BASEADDR(data); - ((Dmac *)hw)->BASEADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->BASEADDR.reg; -} - -static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; - tmp |= DMAC_WRBADDR_WRBADDR(data); - ((Dmac *)hw)->WRBADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->WRBADDR.reg; -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CRCSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCSTATUS.reg; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_VALID; - tmp |= value << DMAC_BTCTRL_VALID_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_SRCINC; - tmp |= value << DMAC_BTCTRL_SRCINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_DSTINC; - tmp |= value << DMAC_BTCTRL_DSTINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSEL; - tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; - tmp |= DMAC_BTCTRL_EVOSEL(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; - tmp |= DMAC_BTCTRL_BLOCKACT(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; - tmp |= DMAC_BTCTRL_BEATSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; - tmp |= DMAC_BTCTRL_STEPSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCTRL.reg; -} - -static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= ~DMAC_BTCNT_BTCNT_Msk; - tmp |= DMAC_BTCNT_BTCNT(data); - ((DmacDescriptor *)hw)->BTCNT.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCNT.reg; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t -hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; - tmp |= DMAC_SRCADDR_SRCADDR(data); - ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->SRCADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; - tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; - tmp |= DMAC_DSTADDR_DSTADDR(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DSTADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; - tmp |= DMAC_DESCADDR_DESCADDR(data); - ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DESCADDR.reg; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, - hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHINTFLAG.reg; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, - hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHINTENSET.reg; -} - -static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = data; - ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = mask; -} - -static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_RUNSTDBY; - tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLA_TRIGSRC(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; - tmp |= DMAC_CHCTRLA_TRIGACT(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; - tmp |= DMAC_CHCTRLA_BURSTLEN(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; - tmp |= DMAC_CHCTRLA_THRESHOLD(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHCTRLA.reg; -} - -static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((DmacChannel *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHCTRLB.reg; -} - -static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; - tmp |= DMAC_CHPRILVL_PRILVL(data); - ((DmacChannel *)hw)->CHPRILVL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHPRILVL.reg; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVIE; - tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOE; - tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; - tmp |= DMAC_CHEVCTRL_EVACT(data); - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; - tmp |= DMAC_CHEVCTRL_EVOMODE(data); - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHEVCTRL.reg; -} - -static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, - hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHSTATUS.reg; -} - -static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; -} - -static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintflag_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; -} - -static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; -} - -static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t data) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; -} - -static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; -} - -static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_RUNSTDBY; - tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLA_TRIGSRC(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; - tmp |= DMAC_CHCTRLA_TRIGACT(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; - tmp |= DMAC_CHCTRLA_BURSTLEN(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; - tmp |= DMAC_CHCTRLA_THRESHOLD(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; -} - -static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; -} - -static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; - tmp |= DMAC_CHPRILVL_PRILVL(data); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; -} - -static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVIE; - tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOE; - tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; - tmp |= DMAC_CHEVCTRL_EVACT(data); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; - tmp |= DMAC_CHEVCTRL_EVOMODE(data); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; -} - -static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DMAC_E54_H_INCLUDED */ -#endif /* _SAME54_DMAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_dsu_e54.h b/software/firmware/project_oracle_base/hri/hri_dsu_e54.h deleted file mode 100644 index b192276..0000000 --- a/software/firmware/project_oracle_base/hri/hri_dsu_e54.h +++ /dev/null @@ -1,1256 +0,0 @@ -/** - * \file - * - * \brief SAM DSU - * - * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_DSU_COMPONENT_ -#ifndef _HRI_DSU_E54_H_INCLUDED_ -#define _HRI_DSU_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DSU_CRITICAL_SECTIONS) -#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DSU_CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_dsu_addr_reg_t; -typedef uint32_t hri_dsu_cfg_reg_t; -typedef uint32_t hri_dsu_cid0_reg_t; -typedef uint32_t hri_dsu_cid1_reg_t; -typedef uint32_t hri_dsu_cid2_reg_t; -typedef uint32_t hri_dsu_cid3_reg_t; -typedef uint32_t hri_dsu_data_reg_t; -typedef uint32_t hri_dsu_dcc_reg_t; -typedef uint32_t hri_dsu_did_reg_t; -typedef uint32_t hri_dsu_end_reg_t; -typedef uint32_t hri_dsu_entry0_reg_t; -typedef uint32_t hri_dsu_entry1_reg_t; -typedef uint32_t hri_dsu_length_reg_t; -typedef uint32_t hri_dsu_memtype_reg_t; -typedef uint32_t hri_dsu_pid0_reg_t; -typedef uint32_t hri_dsu_pid1_reg_t; -typedef uint32_t hri_dsu_pid2_reg_t; -typedef uint32_t hri_dsu_pid3_reg_t; -typedef uint32_t hri_dsu_pid4_reg_t; -typedef uint32_t hri_dsu_pid5_reg_t; -typedef uint32_t hri_dsu_pid6_reg_t; -typedef uint32_t hri_dsu_pid7_reg_t; -typedef uint8_t hri_dsu_ctrl_reg_t; -typedef uint8_t hri_dsu_statusa_reg_t; -typedef uint8_t hri_dsu_statusb_reg_t; - -static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; -} - -static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; -} - -static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSB.reg; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) -{ - return ((Dsu *)hw)->DID.reg; -} - -static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; -} - -static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY0.reg; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY1.reg; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->END.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) -{ - return ((Dsu *)hw)->END.reg; -} - -static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) -{ - return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MEMTYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) -{ - return ((Dsu *)hw)->MEMTYPE.reg; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID4.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID4.reg; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID5.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID5.reg; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID6.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID6.reg; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID7.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID7.reg; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID0.reg; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID1.reg; -} - -static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID2.reg; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID3.reg; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID0.reg; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID1.reg; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID2.reg; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID3.reg; -} - -static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_AMOD_Msk; - tmp |= DSU_ADDR_AMOD(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_ADDR_Msk; - tmp |= DSU_ADDR_ADDR(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) -{ - return ((Dsu *)hw)->ADDR.reg; -} - -static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= ~DSU_LENGTH_LENGTH_Msk; - tmp |= DSU_LENGTH_LENGTH(data); - ((Dsu *)hw)->LENGTH.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) -{ - return ((Dsu *)hw)->LENGTH.reg; -} - -static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= ~DSU_DATA_DATA_Msk; - tmp |= DSU_DATA_DATA(data); - ((Dsu *)hw)->DATA.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) -{ - return ((Dsu *)hw)->DATA.reg; -} - -static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= ~DSU_DCC_DATA_Msk; - tmp |= DSU_DCC_DATA(data); - ((Dsu *)hw)->DCC[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCC[index].reg; -} - -static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_ETBRAMEN; - tmp |= value << DSU_CFG_ETBRAMEN_Pos; - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; - return tmp; -} - -static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_LQOS_Msk; - tmp |= DSU_CFG_LQOS(data); - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; - return tmp; -} - -static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; - return tmp; -} - -static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; - tmp |= DSU_CFG_DCCDMALEVEL(data); - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; - return tmp; -} - -static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) -{ - return ((Dsu *)hw)->CFG.reg; -} - -static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; -} - -static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; -} - -static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; -} - -static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSA.reg; -} - -static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CTRL.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DSU_E54_H_INCLUDED */ -#endif /* _SAME54_DSU_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_e54.h b/software/firmware/project_oracle_base/hri/hri_e54.h deleted file mode 100644 index 46e77ca..0000000 --- a/software/firmware/project_oracle_base/hri/hri_e54.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - * \file - * - * \brief SAM E54 HRI top-level header file - * - * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HRI_E54_H_INCLUDED_ -#define _HRI_E54_H_INCLUDED_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif /* _HRI_E54_H_INCLUDED_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_eic_e54.h b/software/firmware/project_oracle_base/hri/hri_eic_e54.h deleted file mode 100644 index f86e452..0000000 --- a/software/firmware/project_oracle_base/hri/hri_eic_e54.h +++ /dev/null @@ -1,1838 +0,0 @@ -/** - * \file - * - * \brief SAM EIC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_EIC_COMPONENT_ -#ifndef _HRI_EIC_E54_H_INCLUDED_ -#define _HRI_EIC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EIC_CRITICAL_SECTIONS) -#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EIC_CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_eic_nmiflag_reg_t; -typedef uint32_t hri_eic_asynch_reg_t; -typedef uint32_t hri_eic_config_reg_t; -typedef uint32_t hri_eic_debouncen_reg_t; -typedef uint32_t hri_eic_dprescaler_reg_t; -typedef uint32_t hri_eic_evctrl_reg_t; -typedef uint32_t hri_eic_intenset_reg_t; -typedef uint32_t hri_eic_intflag_reg_t; -typedef uint32_t hri_eic_pinstate_reg_t; -typedef uint32_t hri_eic_syncbusy_reg_t; -typedef uint8_t hri_eic_ctrla_reg_t; -typedef uint8_t hri_eic_nmictrl_reg_t; - -static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - while (((Eic *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - return ((Eic *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) -{ - return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; -} - -static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) -{ - ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Eic *)hw)->NMIFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->NMIFLAG.reg; -} - -static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - ((Eic *)hw)->NMIFLAG.reg = mask; -} - -static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->INTFLAG.reg; -} - -static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - ((Eic *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); - ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); -} - -static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = mask; -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) -{ - return ((Eic *)hw)->INTENSET.reg; -} - -static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = data; - ((Eic *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Eic *)hw)->SYNCBUSY.reg; -} - -static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) -{ - return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; -} - -static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) -{ - return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; -} - -static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->PINSTATE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) -{ - return ((Eic *)hw)->PINSTATE.reg; -} - -static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_ENABLE; - tmp |= value << EIC_CTRLA_ENABLE_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_CKSEL; - tmp |= value << EIC_CTRLA_CKSEL_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg = data; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) -{ - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - return ((Eic *)hw)->CTRLA.reg; -} - -static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIFILTEN; - tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIASYNCH; - tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMISENSE_Msk; - tmp |= EIC_NMICTRL_NMISENSE(data); - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->NMICTRL.reg; -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; - tmp |= EIC_EVCTRL_EXTINTEO(data); - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->EVCTRL.reg; -} - -static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= ~EIC_ASYNCH_ASYNCH_Msk; - tmp |= EIC_ASYNCH_ASYNCH(data); - ((Eic *)hw)->ASYNCH.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) -{ - return ((Eic *)hw)->ASYNCH.reg; -} - -static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN0; - tmp |= value << EIC_CONFIG_FILTEN0_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN1; - tmp |= value << EIC_CONFIG_FILTEN1_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN2; - tmp |= value << EIC_CONFIG_FILTEN2_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN3; - tmp |= value << EIC_CONFIG_FILTEN3_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN4; - tmp |= value << EIC_CONFIG_FILTEN4_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN5; - tmp |= value << EIC_CONFIG_FILTEN5_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN6; - tmp |= value << EIC_CONFIG_FILTEN6_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN7; - tmp |= value << EIC_CONFIG_FILTEN7_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE0_Msk; - tmp |= EIC_CONFIG_SENSE0(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE1_Msk; - tmp |= EIC_CONFIG_SENSE1(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE2_Msk; - tmp |= EIC_CONFIG_SENSE2(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE3_Msk; - tmp |= EIC_CONFIG_SENSE3(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE4_Msk; - tmp |= EIC_CONFIG_SENSE4(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE5_Msk; - tmp |= EIC_CONFIG_SENSE5(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE6_Msk; - tmp |= EIC_CONFIG_SENSE6(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE7_Msk; - tmp |= EIC_CONFIG_SENSE7(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) -{ - return ((Eic *)hw)->CONFIG[index].reg; -} - -static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, - hri_eic_debouncen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; - return tmp; -} - -static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; - tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); - ((Eic *)hw)->DEBOUNCEN.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; - return tmp; -} - -static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) -{ - return ((Eic *)hw)->DEBOUNCEN.reg; -} - -static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_STATES0; - tmp |= value << EIC_DPRESCALER_STATES0_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_STATES1; - tmp |= value << EIC_DPRESCALER_STATES1_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_TICKON; - tmp |= value << EIC_DPRESCALER_TICKON_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, - hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; - tmp |= EIC_DPRESCALER_PRESCALER0(data); - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; - return tmp; -} - -static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, - hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; - tmp |= EIC_DPRESCALER_PRESCALER1(data); - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; - return tmp; -} - -static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) -{ - return ((Eic *)hw)->DPRESCALER.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EIC_E54_H_INCLUDED */ -#endif /* _SAME54_EIC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_evsys_e54.h b/software/firmware/project_oracle_base/hri/hri_evsys_e54.h deleted file mode 100644 index cd4a98a..0000000 --- a/software/firmware/project_oracle_base/hri/hri_evsys_e54.h +++ /dev/null @@ -1,1707 +0,0 @@ -/** - * \file - * - * \brief SAM EVSYS - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_EVSYS_COMPONENT_ -#ifndef _HRI_EVSYS_E54_H_INCLUDED_ -#define _HRI_EVSYS_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) -#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EVSYS_CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_evsys_intpend_reg_t; -typedef uint32_t hri_evsys_busych_reg_t; -typedef uint32_t hri_evsys_channel_reg_t; -typedef uint32_t hri_evsys_intstatus_reg_t; -typedef uint32_t hri_evsys_readyusr_reg_t; -typedef uint32_t hri_evsys_swevt_reg_t; -typedef uint32_t hri_evsys_user_reg_t; -typedef uint32_t hri_evsyschannel_channel_reg_t; -typedef uint8_t hri_evsys_chintenset_reg_t; -typedef uint8_t hri_evsys_chintflag_reg_t; -typedef uint8_t hri_evsys_chstatus_reg_t; -typedef uint8_t hri_evsys_ctrla_reg_t; -typedef uint8_t hri_evsys_prictrl_reg_t; -typedef uint8_t hri_evsyschannel_chintenset_reg_t; -typedef uint8_t hri_evsyschannel_chintflag_reg_t; -typedef uint8_t hri_evsyschannel_chstatus_reg_t; - -static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; -} - -static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, - hri_evsys_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTSTATUS.reg; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; -} - -static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) -{ - return ((Evsys *)hw)->BUSYCH.reg; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; -} - -static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->READYUSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) -{ - return ((Evsys *)hw)->READYUSR.reg; -} - -static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) -{ - return ((Evsys *)hw)->CTRLA.reg; -} - -static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= ~EVSYS_PRICTRL_RREN; - tmp |= value << EVSYS_PRICTRL_RREN_Pos; - ((Evsys *)hw)->PRICTRL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; - return tmp; -} - -static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) -{ - uint8_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= ~EVSYS_PRICTRL_PRI_Msk; - tmp |= EVSYS_PRICTRL_PRI(data); - ((Evsys *)hw)->PRICTRL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; - return tmp; -} - -static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) -{ - return ((Evsys *)hw)->PRICTRL.reg; -} - -static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_OVR; - tmp |= value << EVSYS_INTPEND_OVR_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_EVD; - tmp |= value << EVSYS_INTPEND_EVD_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_READY; - tmp |= value << EVSYS_INTPEND_READY_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_BUSY; - tmp |= value << EVSYS_INTPEND_BUSY_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_ID_Msk; - tmp |= EVSYS_INTPEND_ID(data); - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTPEND.reg; -} - -static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= ~EVSYS_USER_CHANNEL_Msk; - tmp |= EVSYS_USER_CHANNEL(data); - ((Evsys *)hw)->USER[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) -{ - return ((Evsys *)hw)->USER[index].reg; -} - -static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->SWEVT.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, - hri_evsys_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHINTFLAG.reg; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; -} - -static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; -} - -static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; - } else { - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; - } -} - -static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; -} - -static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; -} - -static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; -} - -static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; - } else { - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; - } -} - -static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; -} - -static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, - hri_evsys_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHINTENSET.reg; -} - -static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = data; - ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; -} - -static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; -} - -static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, - hri_evsys_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHSTATUS.reg; -} - -static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_RUNSTDBY; - tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_ONDEMAND; - tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHANNEL.reg; -} - -static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; -} - -static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintflag_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; -} - -static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; -} - -static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; -} - -static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; - } else { - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; - } -} - -static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; -} - -static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; -} - -static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; -} - -static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; - } else { - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; - } -} - -static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; -} - -static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; -} - -static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; -} - -static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t data) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; -} - -static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; -} - -static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; -} - -static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_RUNSTDBY; - tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_ONDEMAND; - tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EVSYS_E54_H_INCLUDED */ -#endif /* _SAME54_EVSYS_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_freqm_e54.h b/software/firmware/project_oracle_base/hri/hri_freqm_e54.h deleted file mode 100644 index 8cbc484..0000000 --- a/software/firmware/project_oracle_base/hri/hri_freqm_e54.h +++ /dev/null @@ -1,464 +0,0 @@ -/** - * \file - * - * \brief SAM FREQM - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_FREQM_COMPONENT_ -#ifndef _HRI_FREQM_E54_H_INCLUDED_ -#define _HRI_FREQM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) -#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define FREQM_CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_freqm_cfga_reg_t; -typedef uint32_t hri_freqm_syncbusy_reg_t; -typedef uint32_t hri_freqm_value_reg_t; -typedef uint8_t hri_freqm_ctrla_reg_t; -typedef uint8_t hri_freqm_ctrlb_reg_t; -typedef uint8_t hri_freqm_intenset_reg_t; -typedef uint8_t hri_freqm_intflag_reg_t; -typedef uint8_t hri_freqm_status_reg_t; - -static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - while (((Freqm *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - return ((Freqm *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTFLAG.reg; -} - -static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - ((Freqm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; -} - -static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; -} - -static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; - } else { - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; - } -} - -static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; -} - -static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENSET.reg = mask; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTENSET.reg; -} - -static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) -{ - ((Freqm *)hw)->INTENSET.reg = data; - ((Freqm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Freqm *)hw)->SYNCBUSY.reg; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->VALUE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) -{ - return ((Freqm *)hw)->VALUE.reg; -} - -static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= ~FREQM_CTRLA_ENABLE; - tmp |= value << FREQM_CTRLA_ENABLE_Pos; - ((Freqm *)hw)->CTRLA.reg = tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg = data; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg &= ~mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg ^= mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) -{ - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - return ((Freqm *)hw)->CTRLA.reg; -} - -static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) -{ - uint16_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= ~FREQM_CFGA_REFNUM_Msk; - tmp |= FREQM_CFGA_REFNUM(data); - ((Freqm *)hw)->CFGA.reg = tmp; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) -{ - return ((Freqm *)hw)->CFGA.reg; -} - -static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; -} - -static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; -} - -static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) -{ - return ((Freqm *)hw)->STATUS.reg; -} - -static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLB.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_FREQM_E54_H_INCLUDED */ -#endif /* _SAME54_FREQM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_gclk_e54.h b/software/firmware/project_oracle_base/hri/hri_gclk_e54.h deleted file mode 100644 index f83af2a..0000000 --- a/software/firmware/project_oracle_base/hri/hri_gclk_e54.h +++ /dev/null @@ -1,805 +0,0 @@ -/** - * \file - * - * \brief SAM GCLK - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_GCLK_COMPONENT_ -#ifndef _HRI_GCLK_E54_H_INCLUDED_ -#define _HRI_GCLK_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) -#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define GCLK_CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_gclk_genctrl_reg_t; -typedef uint32_t hri_gclk_pchctrl_reg_t; -typedef uint32_t hri_gclk_syncbusy_reg_t; -typedef uint8_t hri_gclk_ctrla_reg_t; - -static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - while (((Gclk *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - return ((Gclk *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Gclk *)hw)->SYNCBUSY.reg; -} - -static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg |= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg = data; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg &= ~mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg ^= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) -{ - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - return ((Gclk *)hw)->CTRLA.reg; -} - -static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_GENEN; - tmp |= value << GCLK_GENCTRL_GENEN_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_IDC; - tmp |= value << GCLK_GENCTRL_IDC_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OOV; - tmp |= value << GCLK_GENCTRL_OOV_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OE; - tmp |= value << GCLK_GENCTRL_OE_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIVSEL; - tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_RUNSTDBY; - tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_SRC_Msk; - tmp |= GCLK_GENCTRL_SRC(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIV_Msk; - tmp |= GCLK_GENCTRL_DIV(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg = data; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) -{ - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - return ((Gclk *)hw)->GENCTRL[index].reg; -} - -static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_CHEN; - tmp |= value << GCLK_PCHCTRL_CHEN_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_WRTLOCK; - tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_GEN_Msk; - tmp |= GCLK_PCHCTRL_GEN(data); - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Gclk *)hw)->PCHCTRL[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_GCLK_E54_H_INCLUDED */ -#endif /* _SAME54_GCLK_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_gmac_e54.h b/software/firmware/project_oracle_base/hri/hri_gmac_e54.h deleted file mode 100644 index 2875061..0000000 --- a/software/firmware/project_oracle_base/hri/hri_gmac_e54.h +++ /dev/null @@ -1,3766 +0,0 @@ -/** - * \file - * - * \brief SAM GMAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_GMAC_COMPONENT_ -#ifndef _HRI_GMAC_E54_H_INCLUDED_ -#define _HRI_GMAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_GMAC_CRITICAL_SECTIONS) -#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define GMAC_CRITICAL_SECTION_ENTER() -#define GMAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_gmac_ae_reg_t; -typedef uint32_t hri_gmac_bcfr_reg_t; -typedef uint32_t hri_gmac_bcft_reg_t; -typedef uint32_t hri_gmac_bfr64_reg_t; -typedef uint32_t hri_gmac_bft64_reg_t; -typedef uint32_t hri_gmac_cse_reg_t; -typedef uint32_t hri_gmac_dcfgr_reg_t; -typedef uint32_t hri_gmac_dtf_reg_t; -typedef uint32_t hri_gmac_ec_reg_t; -typedef uint32_t hri_gmac_efrn_reg_t; -typedef uint32_t hri_gmac_efrsh_reg_t; -typedef uint32_t hri_gmac_efrsl_reg_t; -typedef uint32_t hri_gmac_eftn_reg_t; -typedef uint32_t hri_gmac_eftsh_reg_t; -typedef uint32_t hri_gmac_eftsl_reg_t; -typedef uint32_t hri_gmac_fcse_reg_t; -typedef uint32_t hri_gmac_fr_reg_t; -typedef uint32_t hri_gmac_ft_reg_t; -typedef uint32_t hri_gmac_gtbft1518_reg_t; -typedef uint32_t hri_gmac_hrb_reg_t; -typedef uint32_t hri_gmac_hrt_reg_t; -typedef uint32_t hri_gmac_ihce_reg_t; -typedef uint32_t hri_gmac_imr_reg_t; -typedef uint32_t hri_gmac_ipgs_reg_t; -typedef uint32_t hri_gmac_isr_reg_t; -typedef uint32_t hri_gmac_jr_reg_t; -typedef uint32_t hri_gmac_lc_reg_t; -typedef uint32_t hri_gmac_lffe_reg_t; -typedef uint32_t hri_gmac_man_reg_t; -typedef uint32_t hri_gmac_mcf_reg_t; -typedef uint32_t hri_gmac_mfr_reg_t; -typedef uint32_t hri_gmac_mft_reg_t; -typedef uint32_t hri_gmac_ncfgr_reg_t; -typedef uint32_t hri_gmac_ncr_reg_t; -typedef uint32_t hri_gmac_nsc_reg_t; -typedef uint32_t hri_gmac_nsr_reg_t; -typedef uint32_t hri_gmac_ofr_reg_t; -typedef uint32_t hri_gmac_orhi_reg_t; -typedef uint32_t hri_gmac_orlo_reg_t; -typedef uint32_t hri_gmac_othi_reg_t; -typedef uint32_t hri_gmac_otlo_reg_t; -typedef uint32_t hri_gmac_pefrn_reg_t; -typedef uint32_t hri_gmac_pefrsh_reg_t; -typedef uint32_t hri_gmac_pefrsl_reg_t; -typedef uint32_t hri_gmac_peftn_reg_t; -typedef uint32_t hri_gmac_peftsh_reg_t; -typedef uint32_t hri_gmac_peftsl_reg_t; -typedef uint32_t hri_gmac_pfr_reg_t; -typedef uint32_t hri_gmac_pft_reg_t; -typedef uint32_t hri_gmac_rbqb_reg_t; -typedef uint32_t hri_gmac_rjfml_reg_t; -typedef uint32_t hri_gmac_rlpiti_reg_t; -typedef uint32_t hri_gmac_rlpitr_reg_t; -typedef uint32_t hri_gmac_roe_reg_t; -typedef uint32_t hri_gmac_rpq_reg_t; -typedef uint32_t hri_gmac_rpsf_reg_t; -typedef uint32_t hri_gmac_rre_reg_t; -typedef uint32_t hri_gmac_rse_reg_t; -typedef uint32_t hri_gmac_rsr_reg_t; -typedef uint32_t hri_gmac_sab_reg_t; -typedef uint32_t hri_gmac_samb1_reg_t; -typedef uint32_t hri_gmac_samt1_reg_t; -typedef uint32_t hri_gmac_sat_reg_t; -typedef uint32_t hri_gmac_scf_reg_t; -typedef uint32_t hri_gmac_sch_reg_t; -typedef uint32_t hri_gmac_scl_reg_t; -typedef uint32_t hri_gmac_svlan_reg_t; -typedef uint32_t hri_gmac_ta_reg_t; -typedef uint32_t hri_gmac_tbfr1023_reg_t; -typedef uint32_t hri_gmac_tbfr127_reg_t; -typedef uint32_t hri_gmac_tbfr1518_reg_t; -typedef uint32_t hri_gmac_tbfr255_reg_t; -typedef uint32_t hri_gmac_tbfr511_reg_t; -typedef uint32_t hri_gmac_tbft1023_reg_t; -typedef uint32_t hri_gmac_tbft127_reg_t; -typedef uint32_t hri_gmac_tbft1518_reg_t; -typedef uint32_t hri_gmac_tbft255_reg_t; -typedef uint32_t hri_gmac_tbft511_reg_t; -typedef uint32_t hri_gmac_tbqb_reg_t; -typedef uint32_t hri_gmac_tce_reg_t; -typedef uint32_t hri_gmac_ti_reg_t; -typedef uint32_t hri_gmac_tidm_reg_t; -typedef uint32_t hri_gmac_tisubn_reg_t; -typedef uint32_t hri_gmac_tlpiti_reg_t; -typedef uint32_t hri_gmac_tlpitr_reg_t; -typedef uint32_t hri_gmac_tmxbfr_reg_t; -typedef uint32_t hri_gmac_tn_reg_t; -typedef uint32_t hri_gmac_tpfcp_reg_t; -typedef uint32_t hri_gmac_tpq_reg_t; -typedef uint32_t hri_gmac_tpsf_reg_t; -typedef uint32_t hri_gmac_tsh_reg_t; -typedef uint32_t hri_gmac_tsl_reg_t; -typedef uint32_t hri_gmac_tsr_reg_t; -typedef uint32_t hri_gmac_tssn_reg_t; -typedef uint32_t hri_gmac_tsssl_reg_t; -typedef uint32_t hri_gmac_tur_reg_t; -typedef uint32_t hri_gmac_uce_reg_t; -typedef uint32_t hri_gmac_ufr_reg_t; -typedef uint32_t hri_gmac_ur_reg_t; -typedef uint32_t hri_gmac_wol_reg_t; -typedef uint32_t hri_gmacsa_sab_reg_t; -typedef uint32_t hri_gmacsa_sat_reg_t; - -static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - uint32_t tmp; - tmp = ((GmacSa *)hw)->SAB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) -{ - return ((GmacSa *)hw)->SAB.reg; -} - -static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - uint32_t tmp; - tmp = ((GmacSa *)hw)->SAT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) -{ - return ((GmacSa *)hw)->SAT.reg; -} - -static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, - hri_gmac_sab_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Gmac *)hw)->Sa[submodule_index].SAB.reg; -} - -static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, - hri_gmac_sat_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Gmac *)hw)->Sa[submodule_index].SAT.reg; -} - -static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; -} - -static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; -} - -static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; - } -} - -static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; -} - -static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; -} - -static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; -} - -static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; - } -} - -static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; -} - -static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; -} - -static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; -} - -static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; - } -} - -static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; -} - -static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; -} - -static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; -} - -static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; - } -} - -static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; -} - -static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; -} - -static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; -} - -static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; - } -} - -static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; -} - -static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; -} - -static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; -} - -static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; - } -} - -static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; -} - -static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; -} - -static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; -} - -static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; - } -} - -static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; -} - -static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; -} - -static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; -} - -static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; - } -} - -static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; -} - -static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; -} - -static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; -} - -static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; - } -} - -static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; -} - -static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; -} - -static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; -} - -static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; - } -} - -static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; -} - -static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; -} - -static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; -} - -static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; - } -} - -static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; -} - -static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; -} - -static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; -} - -static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; - } -} - -static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; -} - -static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; -} - -static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; -} - -static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; - } -} - -static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; -} - -static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; -} - -static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; -} - -static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; - } -} - -static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; -} - -static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; -} - -static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; -} - -static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; - } -} - -static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; -} - -static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; -} - -static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; -} - -static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; - } -} - -static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; -} - -static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; -} - -static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; -} - -static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; - } -} - -static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; -} - -static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; -} - -static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; -} - -static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; - } -} - -static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; -} - -static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; -} - -static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; -} - -static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; - } -} - -static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; -} - -static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; -} - -static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; -} - -static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; - } -} - -static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; -} - -static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; -} - -static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; -} - -static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; - } -} - -static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; -} - -static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; -} - -static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; -} - -static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; - } -} - -static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; -} - -static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; -} - -static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; -} - -static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; - } -} - -static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; -} - -static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; -} - -static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; -} - -static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; - } -} - -static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; -} - -static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; -} - -static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos; -} - -static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; - } -} - -static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; -} - -static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) -{ - ((Gmac *)hw)->IER.reg = mask; -} - -static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) -{ - return ((Gmac *)hw)->IMR.reg; -} - -static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) -{ - ((Gmac *)hw)->IER.reg = data; - ((Gmac *)hw)->IDR.reg = ~data; -} - -static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) -{ - ((Gmac *)hw)->IDR.reg = mask; -} - -static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) -{ - return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos; -} - -static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) -{ - return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos; -} - -static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) -{ - return ((Gmac *)hw)->NSR.reg; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) -{ - return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) -{ - return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RPQ.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) -{ - return ((Gmac *)hw)->RPQ.reg; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) -{ - return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFTSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFTSH.reg; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) -{ - return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFRSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFRSH.reg; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) -{ - return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFTSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFTSH.reg; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) -{ - return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFRSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFRSH.reg; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) -{ - return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->OTLO.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) -{ - return ((Gmac *)hw)->OTLO.reg; -} - -static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) -{ - return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; -} - -static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; -} - -static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->OTHI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) -{ - return ((Gmac *)hw)->OTHI.reg; -} - -static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) -{ - return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; -} - -static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; -} - -static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->FT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) -{ - return ((Gmac *)hw)->FT.reg; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) -{ - return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BCFT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) -{ - return ((Gmac *)hw)->BCFT.reg; -} - -static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) -{ - return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; -} - -static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; -} - -static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MFT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) -{ - return ((Gmac *)hw)->MFT.reg; -} - -static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) -{ - return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; -} - -static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; -} - -static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PFT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) -{ - return ((Gmac *)hw)->PFT.reg; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) -{ - return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BFT64.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) -{ - return ((Gmac *)hw)->BFT64.reg; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) -{ - return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT127.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT127.reg; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) -{ - return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT255.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT255.reg; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) -{ - return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT511.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT511.reg; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) -{ - return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT1023.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT1023.reg; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) -{ - return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT1518.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT1518.reg; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, - hri_gmac_gtbft1518_reg_t mask) -{ - return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->GTBFT1518.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) -{ - return ((Gmac *)hw)->GTBFT1518.reg; -} - -static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) -{ - return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; -} - -static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) -{ - return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; -} - -static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TUR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TUR.reg; -} - -static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) -{ - return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; -} - -static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; -} - -static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SCF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) -{ - return ((Gmac *)hw)->SCF.reg; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) -{ - return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MCF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) -{ - return ((Gmac *)hw)->MCF.reg; -} - -static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) -{ - return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; -} - -static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; -} - -static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) -{ - return ((Gmac *)hw)->EC.reg; -} - -static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) -{ - return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; -} - -static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; -} - -static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->LC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) -{ - return ((Gmac *)hw)->LC.reg; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) -{ - return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) -{ - return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->DTF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) -{ - return ((Gmac *)hw)->DTF.reg; -} - -static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) -{ - return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; -} - -static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) -{ - return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; -} - -static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->CSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) -{ - return ((Gmac *)hw)->CSE.reg; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) -{ - return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ORLO.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) -{ - return ((Gmac *)hw)->ORLO.reg; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) -{ - return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ORHI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) -{ - return ((Gmac *)hw)->ORHI.reg; -} - -static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) -{ - return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; -} - -static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; -} - -static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->FR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) -{ - return ((Gmac *)hw)->FR.reg; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) -{ - return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BCFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->BCFR.reg; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) -{ - return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->MFR.reg; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) -{ - return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->PFR.reg; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) -{ - return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BFR64.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) -{ - return ((Gmac *)hw)->BFR64.reg; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) -{ - return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR127.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR127.reg; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) -{ - return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR255.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR255.reg; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) -{ - return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR511.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR511.reg; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) -{ - return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR1023.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR1023.reg; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) -{ - return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR1518.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR1518.reg; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) -{ - return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TMXBFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TMXBFR.reg; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) -{ - return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->UFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->UFR.reg; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) -{ - return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->OFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->OFR.reg; -} - -static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) -{ - return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; -} - -static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; -} - -static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->JR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) -{ - return ((Gmac *)hw)->JR.reg; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) -{ - return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) -{ - return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->FCSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) -{ - return ((Gmac *)hw)->FCSE.reg; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) -{ - return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) -{ - return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->LFFE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) -{ - return ((Gmac *)hw)->LFFE.reg; -} - -static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) -{ - return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; -} - -static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) -{ - return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; -} - -static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) -{ - return ((Gmac *)hw)->RSE.reg; -} - -static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) -{ - return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; -} - -static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) -{ - return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; -} - -static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->AE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) -{ - return ((Gmac *)hw)->AE.reg; -} - -static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) -{ - return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; -} - -static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) -{ - return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; -} - -static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RRE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) -{ - return ((Gmac *)hw)->RRE.reg; -} - -static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) -{ - return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; -} - -static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) -{ - return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; -} - -static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ROE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) -{ - return ((Gmac *)hw)->ROE.reg; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) -{ - return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) -{ - return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->IHCE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) -{ - return ((Gmac *)hw)->IHCE.reg; -} - -static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) -{ - return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; -} - -static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) -{ - return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; -} - -static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TCE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) -{ - return ((Gmac *)hw)->TCE.reg; -} - -static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) -{ - return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; -} - -static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) -{ - return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; -} - -static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->UCE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) -{ - return ((Gmac *)hw)->UCE.reg; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) -{ - return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFTSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFTSL.reg; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) -{ - return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFTN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFTN.reg; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) -{ - return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFRSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFRSL.reg; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) -{ - return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFRN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFRN.reg; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) -{ - return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFTSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFTSL.reg; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) -{ - return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFTN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFTN.reg; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) -{ - return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFRSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFRSL.reg; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) -{ - return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFRN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFRN.reg; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask) -{ - return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw) -{ - return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RLPITR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw) -{ - return ((Gmac *)hw)->RLPITR.reg; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask) -{ - return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw) -{ - return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RLPITI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw) -{ - return ((Gmac *)hw)->RLPITI.reg; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask) -{ - return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw) -{ - return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TLPITR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TLPITR.reg; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask) -{ - return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw) -{ - return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TLPITI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw) -{ - return ((Gmac *)hw)->TLPITI.reg; -} - -static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) -{ - return ((Gmac *)hw)->NCR.reg; -} - -static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NCFGR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) -{ - return ((Gmac *)hw)->NCFGR.reg; -} - -static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->UR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) -{ - return ((Gmac *)hw)->UR.reg; -} - -static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->DCFGR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) -{ - return ((Gmac *)hw)->DCFGR.reg; -} - -static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSR.reg; -} - -static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RBQB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) -{ - return ((Gmac *)hw)->RBQB.reg; -} - -static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBQB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBQB.reg; -} - -static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) -{ - return ((Gmac *)hw)->RSR.reg; -} - -static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) -{ - return ((Gmac *)hw)->ISR.reg; -} - -static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MAN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) -{ - return ((Gmac *)hw)->MAN.reg; -} - -static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TPQ.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) -{ - return ((Gmac *)hw)->TPQ.reg; -} - -static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TPSF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) -{ - return ((Gmac *)hw)->TPSF.reg; -} - -static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RPSF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) -{ - return ((Gmac *)hw)->RPSF.reg; -} - -static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RJFML.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) -{ - return ((Gmac *)hw)->RJFML.reg; -} - -static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->HRB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) -{ - return ((Gmac *)hw)->HRB.reg; -} - -static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->HRT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) -{ - return ((Gmac *)hw)->HRT.reg; -} - -static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TIDM[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index) -{ - return ((Gmac *)hw)->TIDM[index].reg; -} - -static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->WOL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) -{ - return ((Gmac *)hw)->WOL.reg; -} - -static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->IPGS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) -{ - return ((Gmac *)hw)->IPGS.reg; -} - -static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SVLAN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) -{ - return ((Gmac *)hw)->SVLAN.reg; -} - -static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TPFCP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) -{ - return ((Gmac *)hw)->TPFCP.reg; -} - -static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SAMB1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) -{ - return ((Gmac *)hw)->SAMB1.reg; -} - -static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SAMT1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) -{ - return ((Gmac *)hw)->SAMT1.reg; -} - -static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NSC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) -{ - return ((Gmac *)hw)->NSC.reg; -} - -static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SCL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) -{ - return ((Gmac *)hw)->SCL.reg; -} - -static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SCH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) -{ - return ((Gmac *)hw)->SCH.reg; -} - -static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TISUBN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) -{ - return ((Gmac *)hw)->TISUBN.reg; -} - -static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSH.reg; -} - -static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSSSL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSSSL.reg; -} - -static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSSN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSSN.reg; -} - -static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSL.reg; -} - -static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) -{ - return ((Gmac *)hw)->TN.reg; -} - -static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TI.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) -{ - return ((Gmac *)hw)->TI.reg; -} - -static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TA.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_GMAC_E54_H_INCLUDED */ -#endif /* _SAME54_GMAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_hmatrixb_e54.h b/software/firmware/project_oracle_base/hri/hri_hmatrixb_e54.h deleted file mode 100644 index 2ef0684..0000000 --- a/software/firmware/project_oracle_base/hri/hri_hmatrixb_e54.h +++ /dev/null @@ -1,237 +0,0 @@ -/** - * \file - * - * \brief SAM HMATRIXB - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_HMATRIXB_COMPONENT_ -#ifndef _HRI_HMATRIXB_E54_H_INCLUDED_ -#define _HRI_HMATRIXB_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) -#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define HMATRIXB_CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_hmatrixb_pras_reg_t; -typedef uint32_t hri_hmatrixb_prbs_reg_t; -typedef uint32_t hri_hmatrixbprs_pras_reg_t; -typedef uint32_t hri_hmatrixbprs_prbs_reg_t; - -static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRAS.reg; -} - -static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRBS.reg; -} - -static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; -} - -static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_HMATRIXB_E54_H_INCLUDED */ -#endif /* _SAME54_HMATRIXB_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_i2s_e54.h b/software/firmware/project_oracle_base/hri/hri_i2s_e54.h deleted file mode 100644 index 42b88dc..0000000 --- a/software/firmware/project_oracle_base/hri/hri_i2s_e54.h +++ /dev/null @@ -1,3032 +0,0 @@ -/** - * \file - * - * \brief SAM I2S - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_I2S_COMPONENT_ -#ifndef _HRI_I2S_E54_H_INCLUDED_ -#define _HRI_I2S_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_I2S_CRITICAL_SECTIONS) -#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define I2S_CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_i2s_intenset_reg_t; -typedef uint16_t hri_i2s_intflag_reg_t; -typedef uint16_t hri_i2s_syncbusy_reg_t; -typedef uint32_t hri_i2s_clkctrl_reg_t; -typedef uint32_t hri_i2s_rxctrl_reg_t; -typedef uint32_t hri_i2s_rxdata_reg_t; -typedef uint32_t hri_i2s_txctrl_reg_t; -typedef uint32_t hri_i2s_txdata_reg_t; -typedef uint8_t hri_i2s_ctrla_reg_t; - -static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - while (((I2s *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - return ((I2s *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) -{ - return ((I2s *)hw)->INTFLAG.reg; -} - -static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - ((I2s *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; -} - -static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; -} - -static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; -} - -static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; -} - -static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; -} - -static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; -} - -static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; -} - -static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; -} - -static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; -} - -static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; -} - -static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; -} - -static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; -} - -static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; -} - -static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; -} - -static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; -} - -static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; -} - -static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENSET.reg = mask; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) -{ - return ((I2s *)hw)->INTENSET.reg; -} - -static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) -{ - ((I2s *)hw)->INTENSET.reg = data; - ((I2s *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) -{ - return ((I2s *)hw)->SYNCBUSY.reg; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) -{ - uint32_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->RXDATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return ((I2s *)hw)->RXDATA.reg; -} - -static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_ENABLE; - tmp |= value << I2S_CTRLA_ENABLE_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN0; - tmp |= value << I2S_CTRLA_CKEN0_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN1; - tmp |= value << I2S_CTRLA_CKEN1_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_TXEN; - tmp |= value << I2S_CTRLA_TXEN_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_RXEN; - tmp |= value << I2S_CTRLA_RXEN_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= mask; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg = data; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~mask; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= mask; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - return ((I2s *)hw)->CTRLA.reg; -} - -static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_BITDELAY; - tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSSEL; - tmp |= value << I2S_CLKCTRL_FSSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSINV; - tmp |= value << I2S_CLKCTRL_FSINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSOUTINV; - tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKSEL; - tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKOUTINV; - tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKSEL; - tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKEN; - tmp |= value << I2S_CLKCTRL_MCKEN_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTINV; - tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; - tmp |= I2S_CLKCTRL_SLOTSIZE(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; - tmp |= I2S_CLKCTRL_NBSLOTS(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; - tmp |= I2S_CLKCTRL_FSWIDTH(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; - tmp |= I2S_CLKCTRL_MCKDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; - tmp |= I2S_CLKCTRL_MCKOUTDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) -{ - return ((I2s *)hw)->CLKCTRL[index].reg; -} - -static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_TXSAME; - tmp |= value << I2S_TXCTRL_TXSAME_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTADJ; - tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_WORDADJ; - tmp |= value << I2S_TXCTRL_WORDADJ_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_BITREV; - tmp |= value << I2S_TXCTRL_BITREV_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS0; - tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS1; - tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS2; - tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS3; - tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS4; - tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS5; - tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS6; - tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS7; - tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_MONO; - tmp |= value << I2S_TXCTRL_MONO_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_DMA; - tmp |= value << I2S_TXCTRL_DMA_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; - tmp |= I2S_TXCTRL_TXDEFAULT(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_DATASIZE_Msk; - tmp |= I2S_TXCTRL_DATASIZE(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_EXTEND_Msk; - tmp |= I2S_TXCTRL_EXTEND(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) -{ - return ((I2s *)hw)->TXCTRL.reg; -} - -static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_CLKSEL; - tmp |= value << I2S_RXCTRL_CLKSEL_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTADJ; - tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_WORDADJ; - tmp |= value << I2S_RXCTRL_WORDADJ_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_BITREV; - tmp |= value << I2S_RXCTRL_BITREV_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS0; - tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS1; - tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS2; - tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS3; - tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS4; - tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS5; - tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS6; - tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS7; - tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_MONO; - tmp |= value << I2S_RXCTRL_MONO_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_DMA; - tmp |= value << I2S_RXCTRL_DMA_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_RXLOOP; - tmp |= value << I2S_RXCTRL_RXLOOP_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SERMODE_Msk; - tmp |= I2S_RXCTRL_SERMODE(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_DATASIZE_Msk; - tmp |= I2S_RXCTRL_DATASIZE(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_EXTEND_Msk; - tmp |= I2S_RXCTRL_EXTEND(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) -{ - return ((I2s *)hw)->RXCTRL.reg; -} - -static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXDATA.reg = data; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_I2S_E54_H_INCLUDED */ -#endif /* _SAME54_I2S_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_icm_e54.h b/software/firmware/project_oracle_base/hri/hri_icm_e54.h deleted file mode 100644 index 374caa4..0000000 --- a/software/firmware/project_oracle_base/hri/hri_icm_e54.h +++ /dev/null @@ -1,761 +0,0 @@ -/** - * \file - * - * \brief SAM ICM - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_ICM_COMPONENT_ -#ifndef _HRI_ICM_E54_H_INCLUDED_ -#define _HRI_ICM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ICM_CRITICAL_SECTIONS) -#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ICM_CRITICAL_SECTION_ENTER() -#define ICM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_icm_cfg_reg_t; -typedef uint32_t hri_icm_ctrl_reg_t; -typedef uint32_t hri_icm_dscr_reg_t; -typedef uint32_t hri_icm_hash_reg_t; -typedef uint32_t hri_icm_imr_reg_t; -typedef uint32_t hri_icm_isr_reg_t; -typedef uint32_t hri_icm_sr_reg_t; -typedef uint32_t hri_icm_uasr_reg_t; -typedef uint32_t hri_icm_uihval_reg_t; -typedef uint32_t hri_icmdescriptor_raddr_reg_t; -typedef uint32_t hri_icmdescriptor_rcfg_reg_t; -typedef uint32_t hri_icmdescriptor_rctrl_reg_t; -typedef uint32_t hri_icmdescriptor_rnext_reg_t; - -static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, - hri_icmdescriptor_raddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RADDR.reg; -} - -static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, - hri_icmdescriptor_rcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RCFG.reg; -} - -static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, - hri_icmdescriptor_rctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RCTRL.reg; -} - -static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, - hri_icmdescriptor_rnext_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RNEXT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RNEXT.reg; -} - -static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_URAD; -} - -static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) -{ - return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; -} - -static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; - } else { - ((Icm *)hw)->IER.reg = ICM_IMR_URAD; - } -} - -static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; -} - -static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); -} - -static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); -} - -static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); -} - -static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); -} - -static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); -} - -static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); -} - -static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); -} - -static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); -} - -static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); -} - -static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); -} - -static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); -} - -static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); -} - -static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = mask; -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) -{ - return ((Icm *)hw)->IMR.reg; -} - -static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = data; - ((Icm *)hw)->IDR.reg = ~data; -} - -static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = mask; -} - -static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->SR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) -{ - return ((Icm *)hw)->SR.reg; -} - -static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) -{ - return ((Icm *)hw)->ISR.reg; -} - -static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) -{ - return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; -} - -static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) -{ - return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; -} - -static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->UASR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) -{ - return ((Icm *)hw)->UASR.reg; -} - -static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) -{ - return ((Icm *)hw)->CFG.reg; -} - -static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->DSCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) -{ - return ((Icm *)hw)->DSCR.reg; -} - -static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->HASH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) -{ - return ((Icm *)hw)->HASH.reg; -} - -static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CTRL.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->UIHVAL[index].reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ICM_E54_H_INCLUDED */ -#endif /* _SAME54_ICM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_mclk_e54.h b/software/firmware/project_oracle_base/hri/hri_mclk_e54.h deleted file mode 100644 index 7e3963b..0000000 --- a/software/firmware/project_oracle_base/hri/hri_mclk_e54.h +++ /dev/null @@ -1,3556 +0,0 @@ -/** - * \file - * - * \brief SAM MCLK - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_MCLK_COMPONENT_ -#ifndef _HRI_MCLK_E54_H_INCLUDED_ -#define _HRI_MCLK_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) -#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define MCLK_CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_mclk_ahbmask_reg_t; -typedef uint32_t hri_mclk_apbamask_reg_t; -typedef uint32_t hri_mclk_apbbmask_reg_t; -typedef uint32_t hri_mclk_apbcmask_reg_t; -typedef uint32_t hri_mclk_apbdmask_reg_t; -typedef uint8_t hri_mclk_cpudiv_reg_t; -typedef uint8_t hri_mclk_hsdiv_reg_t; -typedef uint8_t hri_mclk_intenset_reg_t; -typedef uint8_t hri_mclk_intflag_reg_t; - -static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTFLAG.reg; -} - -static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - ((Mclk *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; -} - -static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; -} - -static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; - } else { - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; - } -} - -static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; -} - -static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENSET.reg = mask; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTENSET.reg; -} - -static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) -{ - ((Mclk *)hw)->INTENSET.reg = data; - ((Mclk *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENCLR.reg = mask; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) -{ - return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) -{ - return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->HSDIV.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->HSDIV.reg; -} - -static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - uint8_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= ~MCLK_CPUDIV_DIV_Msk; - tmp |= MCLK_CPUDIV_DIV(data); - ((Mclk *)hw)->CPUDIV.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; - return tmp; -} - -static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->CPUDIV.reg; -} - -static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB0; - tmp |= value << MCLK_AHBMASK_HPB0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB1; - tmp |= value << MCLK_AHBMASK_HPB1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB2; - tmp |= value << MCLK_AHBMASK_HPB2_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB3; - tmp |= value << MCLK_AHBMASK_HPB3_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DSU; - tmp |= value << MCLK_AHBMASK_DSU_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HMATRIX; - tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL; - tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HSRAM; - tmp |= value << MCLK_AHBMASK_HSRAM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_CMCC; - tmp |= value << MCLK_AHBMASK_CMCC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DMAC; - tmp |= value << MCLK_AHBMASK_DMAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_USB; - tmp |= value << MCLK_AHBMASK_USB_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_BKUPRAM; - tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_PAC; - tmp |= value << MCLK_AHBMASK_PAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_QSPI; - tmp |= value << MCLK_AHBMASK_QSPI_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_GMAC; - tmp |= value << MCLK_AHBMASK_GMAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_SDHC0; - tmp |= value << MCLK_AHBMASK_SDHC0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_SDHC1; - tmp |= value << MCLK_AHBMASK_SDHC1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_CAN0; - tmp |= value << MCLK_AHBMASK_CAN0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_CAN1; - tmp |= value << MCLK_AHBMASK_CAN1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_ICM; - tmp |= value << MCLK_AHBMASK_ICM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_PUKCC; - tmp |= value << MCLK_AHBMASK_PUKCC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_QSPI_2X; - tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; - tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; - tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->AHBMASK.reg; -} - -static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PAC; - tmp |= value << MCLK_APBAMASK_PAC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PM; - tmp |= value << MCLK_APBAMASK_PM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_MCLK; - tmp |= value << MCLK_APBAMASK_MCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RSTC; - tmp |= value << MCLK_APBAMASK_RSTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSCCTRL; - tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSC32KCTRL; - tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SUPC; - tmp |= value << MCLK_APBAMASK_SUPC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_GCLK; - tmp |= value << MCLK_APBAMASK_GCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_WDT; - tmp |= value << MCLK_APBAMASK_WDT_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RTC; - tmp |= value << MCLK_APBAMASK_RTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_EIC; - tmp |= value << MCLK_APBAMASK_EIC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_FREQM; - tmp |= value << MCLK_APBAMASK_FREQM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SERCOM0; - tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SERCOM1; - tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_TC0; - tmp |= value << MCLK_APBAMASK_TC0_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_TC1; - tmp |= value << MCLK_APBAMASK_TC1_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBAMASK.reg; -} - -static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_USB; - tmp |= value << MCLK_APBBMASK_USB_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_DSU; - tmp |= value << MCLK_APBBMASK_DSU_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_NVMCTRL; - tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_PORT; - tmp |= value << MCLK_APBBMASK_PORT_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_HMATRIX; - tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_EVSYS; - tmp |= value << MCLK_APBBMASK_EVSYS_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_SERCOM2; - tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_SERCOM3; - tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TCC0; - tmp |= value << MCLK_APBBMASK_TCC0_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TCC1; - tmp |= value << MCLK_APBBMASK_TCC1_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TC2; - tmp |= value << MCLK_APBBMASK_TC2_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TC3; - tmp |= value << MCLK_APBBMASK_TC3_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_RAMECC; - tmp |= value << MCLK_APBBMASK_RAMECC_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBBMASK.reg; -} - -static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_GMAC; - tmp |= value << MCLK_APBCMASK_GMAC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TCC2; - tmp |= value << MCLK_APBCMASK_TCC2_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TCC3; - tmp |= value << MCLK_APBCMASK_TCC3_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC4; - tmp |= value << MCLK_APBCMASK_TC4_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC5; - tmp |= value << MCLK_APBCMASK_TC5_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_PDEC; - tmp |= value << MCLK_APBCMASK_PDEC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AC; - tmp |= value << MCLK_APBCMASK_AC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AES; - tmp |= value << MCLK_APBCMASK_AES_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TRNG; - tmp |= value << MCLK_APBCMASK_TRNG_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_ICM; - tmp |= value << MCLK_APBCMASK_ICM_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_QSPI; - tmp |= value << MCLK_APBCMASK_QSPI_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_CCL; - tmp |= value << MCLK_APBCMASK_CCL_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBCMASK.reg; -} - -static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM4; - tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM5; - tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM6; - tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM7; - tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TCC4; - tmp |= value << MCLK_APBDMASK_TCC4_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TC6; - tmp |= value << MCLK_APBDMASK_TC6_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TC7; - tmp |= value << MCLK_APBDMASK_TC7_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_ADC0; - tmp |= value << MCLK_APBDMASK_ADC0_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_ADC1; - tmp |= value << MCLK_APBDMASK_ADC1_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_DAC; - tmp |= value << MCLK_APBDMASK_DAC_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_I2S; - tmp |= value << MCLK_APBDMASK_I2S_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_PCC; - tmp |= value << MCLK_APBDMASK_PCC_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBDMASK.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_MCLK_E54_H_INCLUDED */ -#endif /* _SAME54_MCLK_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_nvmctrl_e54.h b/software/firmware/project_oracle_base/hri/hri_nvmctrl_e54.h deleted file mode 100644 index 12d4022..0000000 --- a/software/firmware/project_oracle_base/hri/hri_nvmctrl_e54.h +++ /dev/null @@ -1,1618 +0,0 @@ -/** - * \file - * - * \brief SAM NVMCTRL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_NVMCTRL_COMPONENT_ -#ifndef _HRI_NVMCTRL_E54_H_INCLUDED_ -#define _HRI_NVMCTRL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) -#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define NVMCTRL_CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_nvmctrl_ctrla_reg_t; -typedef uint16_t hri_nvmctrl_ctrlb_reg_t; -typedef uint16_t hri_nvmctrl_intenset_reg_t; -typedef uint16_t hri_nvmctrl_intflag_reg_t; -typedef uint16_t hri_nvmctrl_status_reg_t; -typedef uint32_t hri_nvmctrl_addr_reg_t; -typedef uint32_t hri_nvmctrl_eccerr_reg_t; -typedef uint32_t hri_nvmctrl_param_reg_t; -typedef uint32_t hri_nvmctrl_pbldata_reg_t; -typedef uint32_t hri_nvmctrl_runlock_reg_t; -typedef uint32_t hri_nvmctrl_seestat_reg_t; -typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; -typedef uint8_t hri_nvmctrl_seecfg_reg_t; - -static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; -} - -static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; -} - -static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; -} - -static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; -} - -static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; -} - -static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; -} - -static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; -} - -static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; -} - -static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; -} - -static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; -} - -static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; -} - -static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, - hri_nvmctrl_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; -} - -static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; -} - -static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; -} - -static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; -} - -static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; -} - -static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; -} - -static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; -} - -static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; -} - -static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; -} - -static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; -} - -static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; -} - -static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; -} - -static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; -} - -static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; - } -} - -static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; -} - -static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; -} - -static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; -} - -static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; -} - -static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; -} - -static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; -} - -static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; -} - -static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; -} - -static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; -} - -static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, - hri_nvmctrl_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTENSET.reg; -} - -static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) -{ - ((Nvmctrl *)hw)->INTENSET.reg = data; - ((Nvmctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->PARAM.reg; -} - -static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, - hri_nvmctrl_status_reg_t mask) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->STATUS.reg; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, - hri_nvmctrl_runlock_reg_t mask) -{ - return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, - hri_nvmctrl_runlock_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->RUNLOCK.reg; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, - hri_nvmctrl_pbldata_reg_t mask) -{ - return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) -{ - return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, - hri_nvmctrl_pbldata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) -{ - return ((Nvmctrl *)hw)->PBLDATA[index].reg; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ECCERR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ECCERR.reg; -} - -static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->SEESTAT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->SEESTAT.reg; -} - -static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AUTOWS; - tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_SUSPEN; - tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AHBNS0; - tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AHBNS1; - tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; - tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; - tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; - tmp |= NVMCTRL_CTRLA_WMODE(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_PRM_Msk; - tmp |= NVMCTRL_CTRLA_PRM(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_RWS_Msk; - tmp |= NVMCTRL_CTRLA_RWS(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->CTRLA.reg; -} - -static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= ~NVMCTRL_ADDR_ADDR_Msk; - tmp |= NVMCTRL_ADDR_ADDR(data); - ((Nvmctrl *)hw)->ADDR.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ADDR.reg; -} - -static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; - tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; - ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; - tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; - ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, - hri_nvmctrl_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->DBGCTRL.reg; -} - -static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= ~NVMCTRL_SEECFG_WMODE; - tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; - ((Nvmctrl *)hw)->SEECFG.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= ~NVMCTRL_SEECFG_APRDIS; - tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; - ((Nvmctrl *)hw)->SEECFG.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->SEECFG.reg; -} - -static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_NVMCTRL_E54_H_INCLUDED */ -#endif /* _SAME54_NVMCTRL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_osc32kctrl_e54.h b/software/firmware/project_oracle_base/hri/hri_osc32kctrl_e54.h deleted file mode 100644 index 2eabbca..0000000 --- a/software/firmware/project_oracle_base/hri/hri_osc32kctrl_e54.h +++ /dev/null @@ -1,1199 +0,0 @@ -/** - * \file - * - * \brief SAM OSC32KCTRL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_OSC32KCTRL_COMPONENT_ -#ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_ -#define _HRI_OSC32KCTRL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; -typedef uint32_t hri_osc32kctrl_intenset_reg_t; -typedef uint32_t hri_osc32kctrl_intflag_reg_t; -typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; -typedef uint32_t hri_osc32kctrl_status_reg_t; -typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; -typedef uint8_t hri_osc32kctrl_evctrl_reg_t; -typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; - -static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; -} - -static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, - hri_osc32kctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; -} - -static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; -} - -static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, - hri_osc32kctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTENSET.reg; -} - -static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = data; - ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, - hri_osc32kctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->STATUS.reg; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; - tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); - ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->RTCCTRL.reg; -} - -static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; - tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; - tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN32K; - tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN1K; - tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; - tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; - tmp |= OSC32KCTRL_XOSC32K_CGM(data); - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->XOSC32K.reg; -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; - tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, - hri_osc32kctrl_cfdctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->CFDCTRL.reg; -} - -static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; - tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; - ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, - hri_osc32kctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; - tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->OSCULP32K.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */ -#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_oscctrl_e54.h b/software/firmware/project_oracle_base/hri/hri_oscctrl_e54.h deleted file mode 100644 index f331410..0000000 --- a/software/firmware/project_oracle_base/hri/hri_oscctrl_e54.h +++ /dev/null @@ -1,4441 +0,0 @@ -/** - * \file - * - * \brief SAM OSCCTRL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_OSCCTRL_COMPONENT_ -#ifndef _HRI_OSCCTRL_E54_H_INCLUDED_ -#define _HRI_OSCCTRL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) -#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSCCTRL_CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_oscctrl_dfllmul_reg_t; -typedef uint32_t hri_oscctrl_dfllval_reg_t; -typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; -typedef uint32_t hri_oscctrl_dpllratio_reg_t; -typedef uint32_t hri_oscctrl_dpllstatus_reg_t; -typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; -typedef uint32_t hri_oscctrl_intenset_reg_t; -typedef uint32_t hri_oscctrl_intflag_reg_t; -typedef uint32_t hri_oscctrl_status_reg_t; -typedef uint32_t hri_oscctrl_xoscctrl_reg_t; -typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; -typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; -typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; -typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; -typedef uint8_t hri_oscctrl_dfllctrla_reg_t; -typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; -typedef uint8_t hri_oscctrl_dfllsync_reg_t; -typedef uint8_t hri_oscctrl_dpllctrla_reg_t; -typedef uint8_t hri_oscctrl_evctrl_reg_t; -typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; - -static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg; -} - -static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg; -} - -static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) - >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, - hri_oscctrl_dpllsyncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; -} - -static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, - hri_oscctrl_dpllstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, - hri_oscctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) -{ - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDR(data); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) -{ - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - return ((OscctrlDpll *)hw)->DPLLRATIO.reg; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_WUF; - tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; - tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DIV(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) - >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) - >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t -hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) - >> OSCCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) - >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) -{ - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t -hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDR(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t -hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) -{ - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_WUF; - tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; - tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DIV(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, - hri_oscctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) -{ - ((Oscctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; -} - -static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; -} - -static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; -} - -static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; -} - -static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, - hri_oscctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTENSET.reg; -} - -static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) -{ - ((Oscctrl *)hw)->INTENSET.reg = data; - ((Oscctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->STATUS.reg; -} - -static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= ~OSCCTRL_EVCTRL_CFDEO0; - tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; - ((Oscctrl *)hw)->EVCTRL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= ~OSCCTRL_EVCTRL_CFDEO1; - tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; - ((Oscctrl *)hw)->EVCTRL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; - tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; - tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; - tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ENALC; - tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; - tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; - tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; - tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; - tmp |= OSCCTRL_XOSCCTRL_IMULT(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; - tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; - tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Oscctrl *)hw)->XOSCCTRL[index].reg; -} - -static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, - hri_oscctrl_dfllctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLCTRLA.reg; -} - -static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_MODE; - tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; - tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; - tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; - tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; - tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; - tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; - tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; - tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, - hri_oscctrl_dfllctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLCTRLB.reg; -} - -static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; - tmp |= OSCCTRL_DFLLVAL_FINE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; - tmp |= OSCCTRL_DFLLVAL_COARSE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; - tmp |= OSCCTRL_DFLLVAL_DIFF(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLVAL.reg; -} - -static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; - tmp |= OSCCTRL_DFLLMUL_MUL(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_FSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_CSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLMUL.reg; -} - -static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; - tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, - hri_oscctrl_dfllsync_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLSYNC.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSCCTRL_E54_H_INCLUDED */ -#endif /* _SAME54_OSCCTRL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_pac_e54.h b/software/firmware/project_oracle_base/hri/hri_pac_e54.h deleted file mode 100644 index 8963135..0000000 --- a/software/firmware/project_oracle_base/hri/hri_pac_e54.h +++ /dev/null @@ -1,1514 +0,0 @@ -/** - * \file - * - * \brief SAM PAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PAC_COMPONENT_ -#ifndef _HRI_PAC_E54_H_INCLUDED_ -#define _HRI_PAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PAC_CRITICAL_SECTIONS) -#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PAC_CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pac_intflaga_reg_t; -typedef uint32_t hri_pac_intflagahb_reg_t; -typedef uint32_t hri_pac_intflagb_reg_t; -typedef uint32_t hri_pac_intflagc_reg_t; -typedef uint32_t hri_pac_intflagd_reg_t; -typedef uint32_t hri_pac_statusa_reg_t; -typedef uint32_t hri_pac_statusb_reg_t; -typedef uint32_t hri_pac_statusc_reg_t; -typedef uint32_t hri_pac_statusd_reg_t; -typedef uint32_t hri_pac_wrctrl_reg_t; -typedef uint8_t hri_pac_evctrl_reg_t; -typedef uint8_t hri_pac_intenset_reg_t; - -static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; -} - -static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; -} - -static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; -} - -static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; -} - -static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; -} - -static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; -} - -static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; -} - -static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGAHB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGAHB.reg; -} - -static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGAHB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; -} - -static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; -} - -static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; -} - -static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; -} - -static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; -} - -static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; -} - -static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; -} - -static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; -} - -static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; -} - -static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; -} - -static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; -} - -static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; -} - -static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; -} - -static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; -} - -static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGA.reg; -} - -static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - ((Pac *)hw)->INTFLAGA.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; -} - -static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; -} - -static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; -} - -static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; -} - -static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; -} - -static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; -} - -static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; -} - -static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; -} - -static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; -} - -static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; -} - -static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; -} - -static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; -} - -static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; -} - -static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; -} - -static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; -} - -static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGB.reg; -} - -static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; -} - -static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; -} - -static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC; -} - -static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; -} - -static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; -} - -static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; -} - -static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; -} - -static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; -} - -static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; -} - -static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; -} - -static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; -} - -static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; -} - -static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; -} - -static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; -} - -static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; -} - -static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGC.reg; -} - -static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - ((Pac *)hw)->INTFLAGC.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; -} - -static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; -} - -static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; -} - -static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; -} - -static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; -} - -static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; -} - -static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; -} - -static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; -} - -static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; -} - -static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGD.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGD.reg; -} - -static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) -{ - ((Pac *)hw)->INTFLAGD.reg = mask; -} - -static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; -} - -static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; -} - -static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; - } else { - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; - } -} - -static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; -} - -static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENSET.reg = mask; -} - -static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) -{ - return ((Pac *)hw)->INTENSET.reg; -} - -static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) -{ - ((Pac *)hw)->INTENSET.reg = data; - ((Pac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; -} - -static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; -} - -static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; -} - -static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; -} - -static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; -} - -static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; -} - -static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; -} - -static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; -} - -static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; -} - -static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; -} - -static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSA.reg; -} - -static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; -} - -static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; -} - -static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; -} - -static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; -} - -static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; -} - -static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; -} - -static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; -} - -static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; -} - -static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; -} - -static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; -} - -static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; -} - -static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; -} - -static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; -} - -static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; -} - -static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSB.reg; -} - -static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; -} - -static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; -} - -static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos; -} - -static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; -} - -static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; -} - -static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; -} - -static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; -} - -static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; -} - -static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; -} - -static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; -} - -static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; -} - -static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; -} - -static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; -} - -static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSC.reg; -} - -static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; -} - -static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; -} - -static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; -} - -static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; -} - -static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; -} - -static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; -} - -static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; -} - -static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; -} - -static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; -} - -static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSD.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSD.reg; -} - -static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_PERID_Msk; - tmp |= PAC_WRCTRL_PERID(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_KEY_Msk; - tmp |= PAC_WRCTRL_KEY(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->WRCTRL.reg; -} - -static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; - return (bool)tmp; -} - -static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= ~PAC_EVCTRL_ERREO; - tmp |= value << PAC_EVCTRL_ERREO_Pos; - ((Pac *)hw)->EVCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->EVCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PAC_E54_H_INCLUDED */ -#endif /* _SAME54_PAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_pcc_e54.h b/software/firmware/project_oracle_base/hri/hri_pcc_e54.h deleted file mode 100644 index 42a5600..0000000 --- a/software/firmware/project_oracle_base/hri/hri_pcc_e54.h +++ /dev/null @@ -1,298 +0,0 @@ -/** - * \file - * - * \brief SAM PCC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PCC_COMPONENT_ -#ifndef _HRI_PCC_E54_H_INCLUDED_ -#define _HRI_PCC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PCC_CRITICAL_SECTIONS) -#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PCC_CRITICAL_SECTION_ENTER() -#define PCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pcc_imr_reg_t; -typedef uint32_t hri_pcc_isr_reg_t; -typedef uint32_t hri_pcc_mr_reg_t; -typedef uint32_t hri_pcc_rhr_reg_t; -typedef uint32_t hri_pcc_wpmr_reg_t; -typedef uint32_t hri_pcc_wpsr_reg_t; - -static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) -{ - ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; -} - -static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) -{ - return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; -} - -static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; - } else { - ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; - } -} - -static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) -{ - ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; -} - -static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) -{ - ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; -} - -static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) -{ - return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; -} - -static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; - } else { - ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; - } -} - -static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) -{ - ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; -} - -static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - ((Pcc *)hw)->IER.reg = mask; -} - -static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) -{ - return ((Pcc *)hw)->IMR.reg; -} - -static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) -{ - ((Pcc *)hw)->IER.reg = data; - ((Pcc *)hw)->IDR.reg = ~data; -} - -static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - ((Pcc *)hw)->IDR.reg = mask; -} - -static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) -{ - return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; -} - -static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) -{ - return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; -} - -static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) -{ - return ((Pcc *)hw)->ISR.reg; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) -{ - return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) -{ - return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->RHR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) -{ - return ((Pcc *)hw)->RHR.reg; -} - -static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->WPSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) -{ - return ((Pcc *)hw)->WPSR.reg; -} - -static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg |= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->MR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg = data; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg &= ~mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg ^= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) -{ - return ((Pcc *)hw)->MR.reg; -} - -static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg |= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->WPMR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg = data; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg &= ~mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg ^= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) -{ - return ((Pcc *)hw)->WPMR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PCC_E54_H_INCLUDED */ -#endif /* _SAME54_PCC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_pdec_e54.h b/software/firmware/project_oracle_base/hri/hri_pdec_e54.h deleted file mode 100644 index ec7ce30..0000000 --- a/software/firmware/project_oracle_base/hri/hri_pdec_e54.h +++ /dev/null @@ -1,2684 +0,0 @@ -/** - * \file - * - * \brief SAM PDEC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PDEC_COMPONENT_ -#ifndef _HRI_PDEC_E54_H_INCLUDED_ -#define _HRI_PDEC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) -#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PDEC_CRITICAL_SECTION_ENTER() -#define PDEC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_pdec_evctrl_reg_t; -typedef uint16_t hri_pdec_status_reg_t; -typedef uint32_t hri_pdec_cc_reg_t; -typedef uint32_t hri_pdec_ccbuf_reg_t; -typedef uint32_t hri_pdec_count_reg_t; -typedef uint32_t hri_pdec_ctrla_reg_t; -typedef uint32_t hri_pdec_syncbusy_reg_t; -typedef uint8_t hri_pdec_ctrlbset_reg_t; -typedef uint8_t hri_pdec_dbgctrl_reg_t; -typedef uint8_t hri_pdec_filter_reg_t; -typedef uint8_t hri_pdec_filterbuf_reg_t; -typedef uint8_t hri_pdec_intenset_reg_t; -typedef uint8_t hri_pdec_intflag_reg_t; -typedef uint8_t hri_pdec_presc_reg_t; -typedef uint8_t hri_pdec_prescbuf_reg_t; - -static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) -{ - while (((Pdec *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) -{ - return ((Pdec *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; -} - -static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; -} - -static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; -} - -static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; -} - -static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; -} - -static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; -} - -static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; -} - -static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; -} - -static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; -} - -static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; -} - -static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; -} - -static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; -} - -static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; -} - -static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; -} - -static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; -} - -static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; -} - -static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; -} - -static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; -} - -static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) -{ - return ((Pdec *)hw)->INTFLAG.reg; -} - -static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) -{ - ((Pdec *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; -} - -static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; - } else { - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; - } -} - -static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; -} - -static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); - ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); -} - -static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); -} - -static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) -{ - return ((Pdec *)hw)->CTRLBSET.reg; -} - -static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) -{ - ((Pdec *)hw)->CTRLBSET.reg = data; - ((Pdec *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; -} - -static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; -} - -static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; - } -} - -static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; -} - -static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; -} - -static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; -} - -static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; - } -} - -static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; -} - -static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; -} - -static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; -} - -static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; - } -} - -static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; -} - -static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; -} - -static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; -} - -static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; - } -} - -static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; -} - -static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; -} - -static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; -} - -static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; - } -} - -static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; -} - -static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; -} - -static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; -} - -static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; - } -} - -static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; -} - -static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - ((Pdec *)hw)->INTENSET.reg = mask; -} - -static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) -{ - return ((Pdec *)hw)->INTENSET.reg; -} - -static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) -{ - ((Pdec *)hw)->INTENSET.reg = data; - ((Pdec *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - ((Pdec *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; -} - -static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Pdec *)hw)->SYNCBUSY.reg; -} - -static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ENABLE; - tmp |= value << PDEC_CTRLA_ENABLE_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_RUNSTDBY; - tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ALOCK; - tmp |= value << PDEC_CTRLA_ALOCK_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_SWAP; - tmp |= value << PDEC_CTRLA_SWAP_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PEREN; - tmp |= value << PDEC_CTRLA_PEREN_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN0; - tmp |= value << PDEC_CTRLA_PINEN0_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN1; - tmp |= value << PDEC_CTRLA_PINEN1_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN2; - tmp |= value << PDEC_CTRLA_PINEN2_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN0; - tmp |= value << PDEC_CTRLA_PINVEN0_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN1; - tmp |= value << PDEC_CTRLA_PINVEN1_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN2; - tmp |= value << PDEC_CTRLA_PINVEN2_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_MODE_Msk; - tmp |= PDEC_CTRLA_MODE(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_CONF_Msk; - tmp |= PDEC_CTRLA_CONF(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ANGULAR_Msk; - tmp |= PDEC_CTRLA_ANGULAR(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_MAXCMP_Msk; - tmp |= PDEC_CTRLA_MAXCMP(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - return ((Pdec *)hw)->CTRLA.reg; -} - -static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_OVFEO; - tmp |= value << PDEC_EVCTRL_OVFEO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_ERREO; - tmp |= value << PDEC_EVCTRL_ERREO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_DIREO; - tmp |= value << PDEC_EVCTRL_DIREO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_VLCEO; - tmp |= value << PDEC_EVCTRL_VLCEO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_MCEO0; - tmp |= value << PDEC_EVCTRL_MCEO0_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_MCEO1; - tmp |= value << PDEC_EVCTRL_MCEO1_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVACT_Msk; - tmp |= PDEC_EVCTRL_EVACT(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVINV_Msk; - tmp |= PDEC_EVCTRL_EVINV(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVEI_Msk; - tmp |= PDEC_EVCTRL_EVEI(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) -{ - return ((Pdec *)hw)->EVCTRL.reg; -} - -static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp &= ~PDEC_DBGCTRL_DBGRUN; - tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; - ((Pdec *)hw)->DBGCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) -{ - return ((Pdec *)hw)->DBGCTRL.reg; -} - -static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp &= ~PDEC_PRESC_PRESC_Msk; - tmp |= PDEC_PRESC_PRESC(data); - ((Pdec *)hw)->PRESC.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - return ((Pdec *)hw)->PRESC.reg; -} - -static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; - return tmp; -} - -static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp &= ~PDEC_FILTER_FILTER_Msk; - tmp |= PDEC_FILTER_FILTER(data); - ((Pdec *)hw)->FILTER.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; - return tmp; -} - -static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - return ((Pdec *)hw)->FILTER.reg; -} - -static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, - hri_pdec_prescbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; - tmp |= PDEC_PRESCBUF_PRESCBUF(data); - ((Pdec *)hw)->PRESCBUF.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->PRESCBUF.reg; -} - -static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, - hri_pdec_filterbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; - tmp |= PDEC_FILTERBUF_FILTERBUF(data); - ((Pdec *)hw)->FILTERBUF.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->FILTERBUF.reg; -} - -static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp &= ~PDEC_COUNT_COUNT_Msk; - tmp |= PDEC_COUNT_COUNT(data); - ((Pdec *)hw)->COUNT.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - return ((Pdec *)hw)->COUNT.reg; -} - -static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; - return tmp; -} - -static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp &= ~PDEC_CC_CC_Msk; - tmp |= PDEC_CC_CC(data); - ((Pdec *)hw)->CC[index].reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; - return tmp; -} - -static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - return ((Pdec *)hw)->CC[index].reg; -} - -static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_pdec_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp &= ~PDEC_CCBUF_CCBUF_Msk; - tmp |= PDEC_CCBUF_CCBUF(data); - ((Pdec *)hw)->CCBUF[index].reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_pdec_ccbuf_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->CCBUF[index].reg; -} - -static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; -} - -static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; -} - -static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; -} - -static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; -} - -static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) -{ - uint16_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PDEC_E54_H_INCLUDED */ -#endif /* _SAME54_PDEC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_pm_e54.h b/software/firmware/project_oracle_base/hri/hri_pm_e54.h deleted file mode 100644 index 0b91bee..0000000 --- a/software/firmware/project_oracle_base/hri/hri_pm_e54.h +++ /dev/null @@ -1,820 +0,0 @@ -/** - * \file - * - * \brief SAM PM - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PM_COMPONENT_ -#ifndef _HRI_PM_E54_H_INCLUDED_ -#define _HRI_PM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PM_CRITICAL_SECTIONS) -#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PM_CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_pm_bkupcfg_reg_t; -typedef uint8_t hri_pm_ctrla_reg_t; -typedef uint8_t hri_pm_hibcfg_reg_t; -typedef uint8_t hri_pm_intenset_reg_t; -typedef uint8_t hri_pm_intflag_reg_t; -typedef uint8_t hri_pm_pwsakdly_reg_t; -typedef uint8_t hri_pm_sleepcfg_reg_t; -typedef uint8_t hri_pm_stdbycfg_reg_t; - -static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; -} - -static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; -} - -static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; -} - -static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; -} - -static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) -{ - return ((Pm *)hw)->INTFLAG.reg; -} - -static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - ((Pm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; -} - -static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; -} - -static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; - } else { - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; - } -} - -static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; -} - -static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENSET.reg = mask; -} - -static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) -{ - return ((Pm *)hw)->INTENSET.reg; -} - -static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) -{ - ((Pm *)hw)->INTENSET.reg = data; - ((Pm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= ~PM_CTRLA_IORET; - tmp |= value << PM_CTRLA_IORET_Pos; - ((Pm *)hw)->CTRLA.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) -{ - return ((Pm *)hw)->CTRLA.reg; -} - -static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; - tmp |= PM_SLEEPCFG_SLEEPMODE(data); - ((Pm *)hw)->SLEEPCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->SLEEPCFG.reg; -} - -static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_RAMCFG_Msk; - tmp |= PM_STDBYCFG_RAMCFG(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; - tmp |= PM_STDBYCFG_FASTWKUP(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->STDBYCFG.reg; -} - -static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= ~PM_HIBCFG_RAMCFG_Msk; - tmp |= PM_HIBCFG_RAMCFG(data); - ((Pm *)hw)->HIBCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= ~PM_HIBCFG_BRAMCFG_Msk; - tmp |= PM_HIBCFG_BRAMCFG(data); - ((Pm *)hw)->HIBCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->HIBCFG.reg; -} - -static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; - tmp |= PM_BKUPCFG_BRAMCFG(data); - ((Pm *)hw)->BKUPCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->BKUPCFG.reg; -} - -static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= ~PM_PWSAKDLY_IGNACK; - tmp |= value << PM_PWSAKDLY_IGNACK_Pos; - ((Pm *)hw)->PWSAKDLY.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; - return tmp; -} - -static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; - tmp |= PM_PWSAKDLY_DLYVAL(data); - ((Pm *)hw)->PWSAKDLY.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; - return tmp; -} - -static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) -{ - return ((Pm *)hw)->PWSAKDLY.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PM_E54_H_INCLUDED */ -#endif /* _SAME54_PM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_port_e54.h b/software/firmware/project_oracle_base/hri/hri_port_e54.h deleted file mode 100644 index 261fcf5..0000000 --- a/software/firmware/project_oracle_base/hri/hri_port_e54.h +++ /dev/null @@ -1,2528 +0,0 @@ -/** - * \file - * - * \brief SAM PORT - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PORT_COMPONENT_ -#ifndef _HRI_PORT_E54_H_INCLUDED_ -#define _HRI_PORT_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PORT_CRITICAL_SECTIONS) -#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PORT_CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_port_ctrl_reg_t; -typedef uint32_t hri_port_dir_reg_t; -typedef uint32_t hri_port_evctrl_reg_t; -typedef uint32_t hri_port_in_reg_t; -typedef uint32_t hri_port_out_reg_t; -typedef uint32_t hri_port_wrconfig_reg_t; -typedef uint32_t hri_portgroup_ctrl_reg_t; -typedef uint32_t hri_portgroup_dir_reg_t; -typedef uint32_t hri_portgroup_evctrl_reg_t; -typedef uint32_t hri_portgroup_in_reg_t; -typedef uint32_t hri_portgroup_out_reg_t; -typedef uint32_t hri_portgroup_wrconfig_reg_t; -typedef uint8_t hri_port_pincfg_reg_t; -typedef uint8_t hri_port_pmux_reg_t; -typedef uint8_t hri_portgroup_pincfg_reg_t; -typedef uint8_t hri_portgroup_pmux_reg_t; - -static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); - ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) -{ - return ((PortGroup *)hw)->DIR.reg; -} - -static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = data; - ((PortGroup *)hw)->DIRCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = mask; -} - -static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); - ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) -{ - return ((PortGroup *)hw)->OUT.reg; -} - -static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = data; - ((PortGroup *)hw)->OUTCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = mask; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) -{ - return ((PortGroup *)hw)->IN.reg; -} - -static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((PortGroup *)hw)->CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->CTRL.reg; -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->EVCTRL.reg; -} - -static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PMUX[index].reg; -} - -static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PINCFG[index].reg; -} - -static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].DIR.reg; -} - -static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; -} - -static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; -} - -static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; -} - -static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].OUT.reg; -} - -static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; -} - -static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; -} - -static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; -} - -static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].IN.reg; -} - -static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].CTRL.reg; -} - -static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; -} - -static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; -} - -static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; -} - -static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, - hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PORT_E54_H_INCLUDED */ -#endif /* _SAME54_PORT_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_qspi_e54.h b/software/firmware/project_oracle_base/hri/hri_qspi_e54.h deleted file mode 100644 index 23742bc..0000000 --- a/software/firmware/project_oracle_base/hri/hri_qspi_e54.h +++ /dev/null @@ -1,2058 +0,0 @@ -/** - * \file - * - * \brief SAM QSPI - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_QSPI_COMPONENT_ -#ifndef _HRI_QSPI_E54_H_INCLUDED_ -#define _HRI_QSPI_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) -#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define QSPI_CRITICAL_SECTION_ENTER() -#define QSPI_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_qspi_baud_reg_t; -typedef uint32_t hri_qspi_ctrla_reg_t; -typedef uint32_t hri_qspi_ctrlb_reg_t; -typedef uint32_t hri_qspi_instraddr_reg_t; -typedef uint32_t hri_qspi_instrctrl_reg_t; -typedef uint32_t hri_qspi_instrframe_reg_t; -typedef uint32_t hri_qspi_intenset_reg_t; -typedef uint32_t hri_qspi_intflag_reg_t; -typedef uint32_t hri_qspi_rxdata_reg_t; -typedef uint32_t hri_qspi_scrambctrl_reg_t; -typedef uint32_t hri_qspi_scrambkey_reg_t; -typedef uint32_t hri_qspi_status_reg_t; -typedef uint32_t hri_qspi_txdata_reg_t; - -static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; -} - -static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; -} - -static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; -} - -static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; -} - -static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; -} - -static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; -} - -static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; -} - -static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; -} - -static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; -} - -static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; -} - -static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; -} - -static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; -} - -static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; -} - -static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; -} - -static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; -} - -static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; -} - -static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; -} - -static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Qspi *)hw)->INTFLAG.reg; -} - -static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) -{ - ((Qspi *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; -} - -static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; -} - -static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; - } -} - -static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; -} - -static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; -} - -static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; -} - -static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; - } -} - -static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; -} - -static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; -} - -static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; -} - -static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; - } -} - -static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; -} - -static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; -} - -static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; -} - -static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; - } -} - -static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; -} - -static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; -} - -static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; -} - -static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; - } -} - -static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; -} - -static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; -} - -static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; -} - -static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; - } -} - -static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; -} - -static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - ((Qspi *)hw)->INTENSET.reg = mask; -} - -static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) -{ - return ((Qspi *)hw)->INTENSET.reg; -} - -static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) -{ - ((Qspi *)hw)->INTENSET.reg = data; - ((Qspi *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - ((Qspi *)hw)->INTENCLR.reg = mask; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) -{ - return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) -{ - return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->RXDATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) -{ - return ((Qspi *)hw)->RXDATA.reg; -} - -static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) -{ - return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; -} - -static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) -{ - return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; -} - -static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) -{ - return ((Qspi *)hw)->STATUS.reg; -} - -static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= ~QSPI_CTRLA_ENABLE; - tmp |= value << QSPI_CTRLA_ENABLE_Pos; - ((Qspi *)hw)->CTRLA.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= ~QSPI_CTRLA_LASTXFER; - tmp |= value << QSPI_CTRLA_LASTXFER_Pos; - ((Qspi *)hw)->CTRLA.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) -{ - return ((Qspi *)hw)->CTRLA.reg; -} - -static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_MODE; - tmp |= value << QSPI_CTRLB_MODE_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_LOOPEN; - tmp |= value << QSPI_CTRLB_LOOPEN_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_WDRBT; - tmp |= value << QSPI_CTRLB_WDRBT_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_SMEMREG; - tmp |= value << QSPI_CTRLB_SMEMREG_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_CSMODE_Msk; - tmp |= QSPI_CTRLB_CSMODE(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DATALEN_Msk; - tmp |= QSPI_CTRLB_DATALEN(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DLYBCT_Msk; - tmp |= QSPI_CTRLB_DLYBCT(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DLYCS_Msk; - tmp |= QSPI_CTRLB_DLYCS(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) -{ - return ((Qspi *)hw)->CTRLB.reg; -} - -static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_CPOL; - tmp |= value << QSPI_BAUD_CPOL_Pos; - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_CPHA; - tmp |= value << QSPI_BAUD_CPHA_Pos; - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_BAUD_Msk; - tmp |= QSPI_BAUD_BAUD(data); - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; - return tmp; -} - -static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_DLYBS_Msk; - tmp |= QSPI_BAUD_DLYBS(data); - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; - return tmp; -} - -static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) -{ - return ((Qspi *)hw)->BAUD.reg; -} - -static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, - hri_qspi_instraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp &= ~QSPI_INSTRADDR_ADDR_Msk; - tmp |= QSPI_INSTRADDR_ADDR(data); - ((Qspi *)hw)->INSTRADDR.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRADDR.reg; -} - -static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, - hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; - tmp |= QSPI_INSTRCTRL_INSTR(data); - ((Qspi *)hw)->INSTRCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, - hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; - tmp |= QSPI_INSTRCTRL_OPTCODE(data); - ((Qspi *)hw)->INSTRCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRCTRL.reg; -} - -static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_INSTREN; - tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_ADDREN; - tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; - tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DATAEN; - tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_ADDRLEN; - tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_CRMODE; - tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DDREN; - tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; - tmp |= QSPI_INSTRFRAME_WIDTH(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; - tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; - tmp |= QSPI_INSTRFRAME_TFRTYPE(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; - tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRFRAME.reg; -} - -static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= ~QSPI_SCRAMBCTRL_ENABLE; - tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; - ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; - tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; - ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, - hri_qspi_scrambctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) -{ - return ((Qspi *)hw)->SCRAMBCTRL.reg; -} - -static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->TXDATA.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBKEY.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_QSPI_E54_H_INCLUDED */ -#endif /* _SAME54_QSPI_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_ramecc_e54.h b/software/firmware/project_oracle_base/hri/hri_ramecc_e54.h deleted file mode 100644 index 6031cce..0000000 --- a/software/firmware/project_oracle_base/hri/hri_ramecc_e54.h +++ /dev/null @@ -1,362 +0,0 @@ -/** - * \file - * - * \brief SAM RAMECC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_RAMECC_COMPONENT_ -#ifndef _HRI_RAMECC_E54_H_INCLUDED_ -#define _HRI_RAMECC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) -#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RAMECC_CRITICAL_SECTION_ENTER() -#define RAMECC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_ramecc_erraddr_reg_t; -typedef uint8_t hri_ramecc_dbgctrl_reg_t; -typedef uint8_t hri_ramecc_intenset_reg_t; -typedef uint8_t hri_ramecc_intflag_reg_t; -typedef uint8_t hri_ramecc_status_reg_t; - -static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; -} - -static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; -} - -static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; -} - -static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; -} - -static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; -} - -static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; -} - -static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; -} - -static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; -} - -static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) -{ - return ((Ramecc *)hw)->INTFLAG.reg; -} - -static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) -{ - ((Ramecc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; -} - -static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; -} - -static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; - } else { - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; - } -} - -static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; -} - -static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; -} - -static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; -} - -static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; - } else { - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; - } -} - -static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; -} - -static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - ((Ramecc *)hw)->INTENSET.reg = mask; -} - -static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) -{ - return ((Ramecc *)hw)->INTENSET.reg; -} - -static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) -{ - ((Ramecc *)hw)->INTENSET.reg = data; - ((Ramecc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - ((Ramecc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) -{ - return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; -} - -static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) -{ - return ((Ramecc *)hw)->STATUS.reg; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, - hri_ramecc_erraddr_reg_t mask) -{ - return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) -{ - return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ramecc *)hw)->ERRADDR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) -{ - return ((Ramecc *)hw)->ERRADDR.reg; -} - -static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RAMECC_CRITICAL_SECTION_ENTER(); - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= ~RAMECC_DBGCTRL_ECCDIS; - tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; - ((Ramecc *)hw)->DBGCTRL.reg = tmp; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; - return (bool)tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RAMECC_CRITICAL_SECTION_ENTER(); - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= ~RAMECC_DBGCTRL_ECCELOG; - tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; - ((Ramecc *)hw)->DBGCTRL.reg = tmp; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg = data; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Ramecc *)hw)->DBGCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RAMECC_E54_H_INCLUDED */ -#endif /* _SAME54_RAMECC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_rstc_e54.h b/software/firmware/project_oracle_base/hri/hri_rstc_e54.h deleted file mode 100644 index bf5592a..0000000 --- a/software/firmware/project_oracle_base/hri/hri_rstc_e54.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief SAM RSTC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_RSTC_COMPONENT_ -#ifndef _HRI_RSTC_E54_H_INCLUDED_ -#define _HRI_RSTC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) -#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RSTC_CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_rstc_bkupexit_reg_t; -typedef uint8_t hri_rstc_rcause_reg_t; - -static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->RCAUSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) -{ - return ((Rstc *)hw)->RCAUSE.reg; -} - -static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; -} - -static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; -} - -static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->BKUPEXIT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) -{ - return ((Rstc *)hw)->BKUPEXIT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RSTC_E54_H_INCLUDED */ -#endif /* _SAME54_RSTC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_rtc_e54.h b/software/firmware/project_oracle_base/hri/hri_rtc_e54.h deleted file mode 100644 index 2f2fa3b..0000000 --- a/software/firmware/project_oracle_base/hri/hri_rtc_e54.h +++ /dev/null @@ -1,10139 +0,0 @@ -/** - * \file - * - * \brief SAM RTC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_RTC_COMPONENT_ -#ifndef _HRI_RTC_E54_H_INCLUDED_ -#define _HRI_RTC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RTC_CRITICAL_SECTIONS) -#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RTC_CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_rtcmode0_ctrla_reg_t; -typedef uint16_t hri_rtcmode0_ctrlb_reg_t; -typedef uint16_t hri_rtcmode0_intenset_reg_t; -typedef uint16_t hri_rtcmode0_intflag_reg_t; -typedef uint16_t hri_rtcmode1_comp_reg_t; -typedef uint16_t hri_rtcmode1_count_reg_t; -typedef uint16_t hri_rtcmode1_ctrla_reg_t; -typedef uint16_t hri_rtcmode1_ctrlb_reg_t; -typedef uint16_t hri_rtcmode1_intenset_reg_t; -typedef uint16_t hri_rtcmode1_intflag_reg_t; -typedef uint16_t hri_rtcmode1_per_reg_t; -typedef uint16_t hri_rtcmode2_ctrla_reg_t; -typedef uint16_t hri_rtcmode2_ctrlb_reg_t; -typedef uint16_t hri_rtcmode2_intenset_reg_t; -typedef uint16_t hri_rtcmode2_intflag_reg_t; -typedef uint32_t hri_rtc_bkup_reg_t; -typedef uint32_t hri_rtc_gp_reg_t; -typedef uint32_t hri_rtc_tampctrl_reg_t; -typedef uint32_t hri_rtc_tampid_reg_t; -typedef uint32_t hri_rtcalarm_alarm_reg_t; -typedef uint32_t hri_rtcmode0_comp_reg_t; -typedef uint32_t hri_rtcmode0_count_reg_t; -typedef uint32_t hri_rtcmode0_evctrl_reg_t; -typedef uint32_t hri_rtcmode0_syncbusy_reg_t; -typedef uint32_t hri_rtcmode0_timestamp_reg_t; -typedef uint32_t hri_rtcmode1_evctrl_reg_t; -typedef uint32_t hri_rtcmode1_syncbusy_reg_t; -typedef uint32_t hri_rtcmode1_timestamp_reg_t; -typedef uint32_t hri_rtcmode2_alarm_reg_t; -typedef uint32_t hri_rtcmode2_clock_reg_t; -typedef uint32_t hri_rtcmode2_evctrl_reg_t; -typedef uint32_t hri_rtcmode2_syncbusy_reg_t; -typedef uint32_t hri_rtcmode2_timestamp_reg_t; -typedef uint8_t hri_rtc_dbgctrl_reg_t; -typedef uint8_t hri_rtc_freqcorr_reg_t; -typedef uint8_t hri_rtcalarm_mask_reg_t; -typedef uint8_t hri_rtcmode2_mask_reg_t; - -static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; -} - -static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, - hri_rtcmode0_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTFLAG.reg; -} - -static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; -} - -static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; -} - -static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, - hri_rtcmode1_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTFLAG.reg; -} - -static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; -} - -static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; -} - -static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, - hri_rtcmode2_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTFLAG.reg; -} - -static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; -} - -static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; - } -} - -static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = mask; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, - hri_rtcmode0_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTENSET.reg; -} - -static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = data; - ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; -} - -static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; -} - -static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; -} - -static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; - } -} - -static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = mask; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, - hri_rtcmode1_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTENSET.reg; -} - -static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = data; - ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; -} - -static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; -} - -static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; - } -} - -static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = mask; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, - hri_rtcmode2_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTENSET.reg; -} - -static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = data; - ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode0_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode1_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode2_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; -} - -static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_ENABLE; - tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_BKTRST; - tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_GPTRST; - tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; - tmp |= RTC_MODE0_CTRLA_MODE(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE0_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - return ((Rtc *)hw)->MODE0.CTRLA.reg; -} - -static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_ENABLE; - tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_BKTRST; - tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_GPTRST; - tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; - tmp |= RTC_MODE1_CTRLA_MODE(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE1_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - return ((Rtc *)hw)->MODE1.CTRLA.reg; -} - -static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_ENABLE; - tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLKREP; - tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_BKTRST; - tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_GPTRST; - tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; - tmp |= RTC_MODE2_CTRLA_MODE(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE2_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg = data; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - return ((Rtc *)hw)->MODE2.CTRLA.reg; -} - -static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_GP0EN; - tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_GP2EN; - tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_RTCOUT; - tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DMAEN; - tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; - tmp |= RTC_MODE0_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; - tmp |= RTC_MODE0_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.CTRLB.reg; -} - -static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_GP0EN; - tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_GP2EN; - tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_RTCOUT; - tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DMAEN; - tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; - tmp |= RTC_MODE1_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; - tmp |= RTC_MODE1_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.CTRLB.reg; -} - -static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_GP0EN; - tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_GP2EN; - tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_RTCOUT; - tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DMAEN; - tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; - tmp |= RTC_MODE2_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; - tmp |= RTC_MODE2_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CTRLB.reg; -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO0; - tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO1; - tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO2; - tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO3; - tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO4; - tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO5; - tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO6; - tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO7; - tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_OVFEO; - tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, - hri_rtcmode0_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.EVCTRL.reg; -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO0; - tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO1; - tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO2; - tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO3; - tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO4; - tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO5; - tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO6; - tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO7; - tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_OVFEO; - tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, - hri_rtcmode1_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.EVCTRL.reg; -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO0; - tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO1; - tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO2; - tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO3; - tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO4; - tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO5; - tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO6; - tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO7; - tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_OVFEO; - tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, - hri_rtcmode2_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.EVCTRL.reg; -} - -static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.DBGCTRL.reg; -} - -static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - uint8_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - return ((Rtc *)hw)->MODE0.FREQCORR.reg; -} - -static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; - tmp |= RTC_MODE0_COUNT_COUNT(data); - ((Rtc *)hw)->MODE0.COUNT.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE0.COUNT.reg; -} - -static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; - tmp |= RTC_MODE1_COUNT_COUNT(data); - ((Rtc *)hw)->MODE1.COUNT.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE1.COUNT.reg; -} - -static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; - tmp |= RTC_MODE2_CLOCK_SECOND(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; - tmp |= RTC_MODE2_CLOCK_MINUTE(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; - tmp |= RTC_MODE2_CLOCK_HOUR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; - tmp |= RTC_MODE2_CLOCK_DAY(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; - tmp |= RTC_MODE2_CLOCK_MONTH(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; - tmp |= RTC_MODE2_CLOCK_YEAR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg = data; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return ((Rtc *)hw)->MODE2.CLOCK.reg; -} - -static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= ~RTC_MODE1_PER_PER_Msk; - tmp |= RTC_MODE1_PER_PER(data); - ((Rtc *)hw)->MODE1.PER.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - return ((Rtc *)hw)->MODE1.PER.reg; -} - -static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= ~RTC_MODE0_COMP_COMP_Msk; - tmp |= RTC_MODE0_COMP_COMP(data); - ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - return ((Rtc *)hw)->MODE0.COMP[index].reg; -} - -static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= ~RTC_MODE1_COMP_COMP_Msk; - tmp |= RTC_MODE1_COMP_COMP(data); - ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg = data; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - return ((Rtc *)hw)->MODE1.COMP[index].reg; -} - -static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= ~RTC_GP_GP_Msk; - tmp |= RTC_GP_GP(data); - ((Rtc *)hw)->MODE0.GP[index].reg = tmp; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg |= mask; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg = data; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - return ((Rtc *)hw)->MODE0.GP[index].reg; -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL0; - tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL1; - tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL2; - tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL3; - tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL4; - tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC0; - tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC1; - tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC2; - tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC3; - tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC4; - tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; - tmp |= RTC_TAMPCTRL_IN0ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; - tmp |= RTC_TAMPCTRL_IN1ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; - tmp |= RTC_TAMPCTRL_IN2ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; - tmp |= RTC_TAMPCTRL_IN3ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; - tmp |= RTC_TAMPCTRL_IN4ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; -} - -static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID0; - tmp |= value << RTC_TAMPID_TAMPID0_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID1; - tmp |= value << RTC_TAMPID_TAMPID1_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID2; - tmp |= value << RTC_TAMPID_TAMPID2_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID3; - tmp |= value << RTC_TAMPID_TAMPID3_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID4; - tmp |= value << RTC_TAMPID_TAMPID4_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPEVT; - tmp |= value << RTC_TAMPID_TAMPEVT_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPID.reg; -} - -static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= ~RTC_BKUP_BKUP_Msk; - tmp |= RTC_BKUP_BKUP(data); - ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE0.BKUP[index].reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) -#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) -#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) -#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) -#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) -#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) -#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) -#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) -#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) -#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) -#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) -#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) -#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) -#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) -#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) -#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) -#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) -#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) -#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) -#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) -#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) -#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) -#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) -#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) -#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) -#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) -#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) -#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) -#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) -#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) -#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) -#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) -#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) -#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) -#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) -#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) -#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) -#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) -#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) -#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) -#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) -#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) -#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) -#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) -#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) -#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) -#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) -#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) -#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) -#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) -#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) -#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) -#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) -#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) -#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) -#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) -#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) -#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) -#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) -#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) -#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) -#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) -#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) -#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) -#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) -#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) -#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) -#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) -#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) -#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) -#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) -#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) -#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) -#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) -#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) -#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) -#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) -#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) -#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) -#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) -#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) -#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) -#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) -#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) -#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) -#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) -#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) -#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) -#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) -#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) -#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) -#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) -#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) -#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) -#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) -#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) -#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) -#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) -#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) -#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) -#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) -#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) -#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) -#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) -#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) -#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) -#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) -#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) -#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) -#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) -#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) -#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) -#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) -#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) -#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) -#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) -#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) -#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) -#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) -#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RTC_E54_H_INCLUDED */ -#endif /* _SAME54_RTC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_sdhc_e54.h b/software/firmware/project_oracle_base/hri/hri_sdhc_e54.h deleted file mode 100644 index 0b7f609..0000000 --- a/software/firmware/project_oracle_base/hri/hri_sdhc_e54.h +++ /dev/null @@ -1,7477 +0,0 @@ -/** - * \file - * - * \brief SAM SDHC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_SDHC_COMPONENT_ -#ifndef _HRI_SDHC_E54_H_INCLUDED_ -#define _HRI_SDHC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) -#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SDHC_CRITICAL_SECTION_ENTER() -#define SDHC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sdhc_acesr_reg_t; -typedef uint16_t hri_sdhc_bcr_reg_t; -typedef uint16_t hri_sdhc_bsr_reg_t; -typedef uint16_t hri_sdhc_ccr_reg_t; -typedef uint16_t hri_sdhc_cr_reg_t; -typedef uint16_t hri_sdhc_eisier_reg_t; -typedef uint16_t hri_sdhc_eister_reg_t; -typedef uint16_t hri_sdhc_eistr_reg_t; -typedef uint16_t hri_sdhc_feraces_reg_t; -typedef uint16_t hri_sdhc_fereis_reg_t; -typedef uint16_t hri_sdhc_hc2r_reg_t; -typedef uint16_t hri_sdhc_hcvr_reg_t; -typedef uint16_t hri_sdhc_nisier_reg_t; -typedef uint16_t hri_sdhc_nister_reg_t; -typedef uint16_t hri_sdhc_nistr_reg_t; -typedef uint16_t hri_sdhc_pvr_reg_t; -typedef uint16_t hri_sdhc_sisr_reg_t; -typedef uint16_t hri_sdhc_tmr_reg_t; -typedef uint32_t hri_sdhc_acr_reg_t; -typedef uint32_t hri_sdhc_arg1r_reg_t; -typedef uint32_t hri_sdhc_asar_reg_t; -typedef uint32_t hri_sdhc_bdpr_reg_t; -typedef uint32_t hri_sdhc_ca0r_reg_t; -typedef uint32_t hri_sdhc_ca1r_reg_t; -typedef uint32_t hri_sdhc_cacr_reg_t; -typedef uint32_t hri_sdhc_cc2r_reg_t; -typedef uint32_t hri_sdhc_mccar_reg_t; -typedef uint32_t hri_sdhc_psr_reg_t; -typedef uint32_t hri_sdhc_rr_reg_t; -typedef uint32_t hri_sdhc_ssar_reg_t; -typedef uint8_t hri_sdhc_aesr_reg_t; -typedef uint8_t hri_sdhc_bgcr_reg_t; -typedef uint8_t hri_sdhc_dbgr_reg_t; -typedef uint8_t hri_sdhc_hc1r_reg_t; -typedef uint8_t hri_sdhc_mc1r_reg_t; -typedef uint8_t hri_sdhc_mc2r_reg_t; -typedef uint8_t hri_sdhc_pcr_reg_t; -typedef uint8_t hri_sdhc_srr_reg_t; -typedef uint8_t hri_sdhc_tcr_reg_t; -typedef uint8_t hri_sdhc_wcr_reg_t; - -static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) -{ - return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) -{ - return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->RR[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->RR[index].reg; -} - -static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; -} - -static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; -} - -static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; -} - -static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; -} - -static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; -} - -static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; -} - -static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->PSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->PSR.reg; -} - -static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; -} - -static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; -} - -static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->ACESR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ACESR.reg; -} - -static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CA0R.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CA0R.reg; -} - -static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CA1R.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CA1R.reg; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->MCCAR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->MCCAR.reg; -} - -static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->AESR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->AESR.reg; -} - -static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; -} - -static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->SISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SISR.reg; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HCVR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HCVR.reg; -} - -static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= ~SDHC_SSAR_ADDR_Msk; - tmp |= SDHC_SSAR_ADDR(data); - ((Sdhc *)hw)->SSAR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; - return tmp; -} - -static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; - tmp |= SDHC_SSAR_CMD23_ARG2(data); - ((Sdhc *)hw)->SSAR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; - return tmp; -} - -static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SSAR.reg; -} - -static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; - tmp |= SDHC_BSR_BLOCKSIZE(data); - ((Sdhc *)hw)->BSR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= ~SDHC_BSR_BOUNDARY_Msk; - tmp |= SDHC_BSR_BOUNDARY(data); - ((Sdhc *)hw)->BSR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BSR.reg; -} - -static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BCR.reg; - tmp &= ~SDHC_BCR_BCNT_Msk; - tmp |= SDHC_BCR_BCNT(data); - ((Sdhc *)hw)->BCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BCR.reg; -} - -static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp &= ~SDHC_ARG1R_ARG_Msk; - tmp |= SDHC_ARG1R_ARG(data); - ((Sdhc *)hw)->ARG1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ARG1R.reg; -} - -static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_DMAEN; - tmp |= value << SDHC_TMR_DMAEN_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_BCEN; - tmp |= value << SDHC_TMR_BCEN_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_DTDSEL; - tmp |= value << SDHC_TMR_DTDSEL_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_MSBSEL; - tmp |= value << SDHC_TMR_MSBSEL_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; - return tmp; -} - -static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_ACMDEN_Msk; - tmp |= SDHC_TMR_ACMDEN(data); - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; - return tmp; -} - -static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->TMR.reg; -} - -static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDCCEN; - tmp |= value << SDHC_CR_CMDCCEN_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDICEN; - tmp |= value << SDHC_CR_CMDICEN_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_DPSEL; - tmp |= value << SDHC_CR_DPSEL_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_RESPTYP_Msk; - tmp |= SDHC_CR_RESPTYP(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDTYP_Msk; - tmp |= SDHC_CR_CMDTYP(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDIDX_Msk; - tmp |= SDHC_CR_CMDIDX(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CR.reg; -} - -static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp &= ~SDHC_BDPR_BUFDATA_Msk; - tmp |= SDHC_BDPR_BUFDATA(data); - ((Sdhc *)hw)->BDPR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BDPR.reg; -} - -static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_LEDCTRL; - tmp |= value << SDHC_HC1R_LEDCTRL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_DW; - tmp |= value << SDHC_HC1R_DW_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_HSEN; - tmp |= value << SDHC_HC1R_HSEN_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_CARDDTL; - tmp |= value << SDHC_HC1R_CARDDTL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_CARDDSEL; - tmp |= value << SDHC_HC1R_CARDDSEL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_DMASEL_Msk; - tmp |= SDHC_HC1R_DMASEL(data); - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC1R.reg; -} - -static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= ~SDHC_PCR_SDBPWR; - tmp |= value << SDHC_PCR_SDBPWR_Pos; - ((Sdhc *)hw)->PCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= ~SDHC_PCR_SDBVSEL_Msk; - tmp |= SDHC_PCR_SDBVSEL(data); - ((Sdhc *)hw)->PCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->PCR.reg; -} - -static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_STPBGR; - tmp |= value << SDHC_BGCR_STPBGR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_CONTR; - tmp |= value << SDHC_BGCR_CONTR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_RWCTRL; - tmp |= value << SDHC_BGCR_RWCTRL_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_INTBG; - tmp |= value << SDHC_BGCR_INTBG_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BGCR.reg; -} - -static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCINT; - tmp |= value << SDHC_WCR_WKENCINT_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCINS; - tmp |= value << SDHC_WCR_WKENCINS_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCREM; - tmp |= value << SDHC_WCR_WKENCREM_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->WCR.reg; -} - -static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_INTCLKEN; - tmp |= value << SDHC_CCR_INTCLKEN_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_INTCLKS; - tmp |= value << SDHC_CCR_INTCLKS_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_SDCLKEN; - tmp |= value << SDHC_CCR_SDCLKEN_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_CLKGSEL; - tmp |= value << SDHC_CCR_CLKGSEL_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; - tmp |= SDHC_CCR_USDCLKFSEL(data); - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; - tmp |= SDHC_CCR_SDCLKFSEL(data); - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CCR.reg; -} - -static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TCR.reg; - tmp &= ~SDHC_TCR_DTCVAL_Msk; - tmp |= SDHC_TCR_DTCVAL(data); - ((Sdhc *)hw)->TCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->TCR.reg; -} - -static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTALL; - tmp |= value << SDHC_SRR_SWRSTALL_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTCMD; - tmp |= value << SDHC_SRR_SWRSTCMD_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTDAT; - tmp |= value << SDHC_SRR_SWRSTDAT_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SRR.reg; -} - -static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CMDC; - tmp |= value << SDHC_NISTR_CMDC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_TRFC; - tmp |= value << SDHC_NISTR_TRFC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BLKGE; - tmp |= value << SDHC_NISTR_BLKGE_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_DMAINT; - tmp |= value << SDHC_NISTR_DMAINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BWRRDY; - tmp |= value << SDHC_NISTR_BWRRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BRDRDY; - tmp |= value << SDHC_NISTR_BRDRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CINS; - tmp |= value << SDHC_NISTR_CINS_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CREM; - tmp |= value << SDHC_NISTR_CREM_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CINT; - tmp |= value << SDHC_NISTR_CINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_BOOTAR; - tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_ERRINT; - tmp |= value << SDHC_NISTR_ERRINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTR.reg; -} - -static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDTEO; - tmp |= value << SDHC_EISTR_CMDTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDCRC; - tmp |= value << SDHC_EISTR_CMDCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDEND; - tmp |= value << SDHC_EISTR_CMDEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDIDX; - tmp |= value << SDHC_EISTR_CMDIDX_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATTEO; - tmp |= value << SDHC_EISTR_DATTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATCRC; - tmp |= value << SDHC_EISTR_DATCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATEND; - tmp |= value << SDHC_EISTR_DATEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CURLIM; - tmp |= value << SDHC_EISTR_CURLIM_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_ACMD; - tmp |= value << SDHC_EISTR_ACMD_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_ADMA; - tmp |= value << SDHC_EISTR_ADMA_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_BOOTAE; - tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTR.reg; -} - -static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CMDC; - tmp |= value << SDHC_NISTER_CMDC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_TRFC; - tmp |= value << SDHC_NISTER_TRFC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BLKGE; - tmp |= value << SDHC_NISTER_BLKGE_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_DMAINT; - tmp |= value << SDHC_NISTER_DMAINT_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BWRRDY; - tmp |= value << SDHC_NISTER_BWRRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BRDRDY; - tmp |= value << SDHC_NISTER_BRDRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CINS; - tmp |= value << SDHC_NISTER_CINS_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CREM; - tmp |= value << SDHC_NISTER_CREM_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CINT; - tmp |= value << SDHC_NISTER_CINT_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_BOOTAR; - tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTER.reg; -} - -static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDTEO; - tmp |= value << SDHC_EISTER_CMDTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDCRC; - tmp |= value << SDHC_EISTER_CMDCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDEND; - tmp |= value << SDHC_EISTER_CMDEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDIDX; - tmp |= value << SDHC_EISTER_CMDIDX_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATTEO; - tmp |= value << SDHC_EISTER_DATTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATCRC; - tmp |= value << SDHC_EISTER_DATCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATEND; - tmp |= value << SDHC_EISTER_DATEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CURLIM; - tmp |= value << SDHC_EISTER_CURLIM_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_ACMD; - tmp |= value << SDHC_EISTER_ACMD_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_ADMA; - tmp |= value << SDHC_EISTER_ADMA_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_BOOTAE; - tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTER.reg; -} - -static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CMDC; - tmp |= value << SDHC_NISIER_CMDC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_TRFC; - tmp |= value << SDHC_NISIER_TRFC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BLKGE; - tmp |= value << SDHC_NISIER_BLKGE_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_DMAINT; - tmp |= value << SDHC_NISIER_DMAINT_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BWRRDY; - tmp |= value << SDHC_NISIER_BWRRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BRDRDY; - tmp |= value << SDHC_NISIER_BRDRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CINS; - tmp |= value << SDHC_NISIER_CINS_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CREM; - tmp |= value << SDHC_NISIER_CREM_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CINT; - tmp |= value << SDHC_NISIER_CINT_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_BOOTAR; - tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISIER.reg; -} - -static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDTEO; - tmp |= value << SDHC_EISIER_CMDTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDCRC; - tmp |= value << SDHC_EISIER_CMDCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDEND; - tmp |= value << SDHC_EISIER_CMDEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDIDX; - tmp |= value << SDHC_EISIER_CMDIDX_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATTEO; - tmp |= value << SDHC_EISIER_DATTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATCRC; - tmp |= value << SDHC_EISIER_DATCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATEND; - tmp |= value << SDHC_EISIER_DATEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CURLIM; - tmp |= value << SDHC_EISIER_CURLIM_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_ACMD; - tmp |= value << SDHC_EISIER_ACMD_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_ADMA; - tmp |= value << SDHC_EISIER_ADMA_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_BOOTAE; - tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISIER.reg; -} - -static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_VS18EN; - tmp |= value << SDHC_HC2R_VS18EN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EXTUN; - tmp |= value << SDHC_HC2R_EXTUN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_SLCKSEL; - tmp |= value << SDHC_HC2R_SLCKSEL_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_ASINTEN; - tmp |= value << SDHC_HC2R_ASINTEN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_PVALEN; - tmp |= value << SDHC_HC2R_PVALEN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_UHSMS_Msk; - tmp |= SDHC_HC2R_UHSMS(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; - tmp |= SDHC_HC2R_EMMC_HS200EN(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_DRVSEL_Msk; - tmp |= SDHC_HC2R_DRVSEL(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC2R.reg; -} - -static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, - hri_sdhc_asar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp &= ~SDHC_ASAR_ADMASA_Msk; - tmp |= SDHC_ASAR_ADMASA(data); - ((Sdhc *)hw)->ASAR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->ASAR[index].reg; -} - -static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_CLKGSEL; - tmp |= value << SDHC_PVR_CLKGSEL_Pos; - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, - hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; - tmp |= SDHC_PVR_SDCLKFSEL(data); - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, - hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_DRVSEL_Msk; - tmp |= SDHC_PVR_DRVSEL(data); - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->PVR[index].reg; -} - -static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_DDR; - tmp |= value << SDHC_MC1R_DDR_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_OPD; - tmp |= value << SDHC_MC1R_OPD_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_BOOTA; - tmp |= value << SDHC_MC1R_BOOTA_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_RSTN; - tmp |= value << SDHC_MC1R_RSTN_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_FCD; - tmp |= value << SDHC_MC1R_FCD_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_CMDTYP_Msk; - tmp |= SDHC_MC1R_CMDTYP(data); - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->MC1R.reg; -} - -static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ACR.reg; - tmp &= ~SDHC_ACR_BMAX_Msk; - tmp |= SDHC_ACR_BMAX(data); - ((Sdhc *)hw)->ACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ACR.reg; -} - -static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp &= ~SDHC_CC2R_FSDCLKD; - tmp |= value << SDHC_CC2R_FSDCLKD_Pos; - ((Sdhc *)hw)->CC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CC2R.reg; -} - -static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= ~SDHC_CACR_CAPWREN; - tmp |= value << SDHC_CACR_CAPWREN_Pos; - ((Sdhc *)hw)->CACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= ~SDHC_CACR_KEY_Msk; - tmp |= SDHC_CACR_KEY(data); - ((Sdhc *)hw)->CACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CACR.reg; -} - -static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp &= ~SDHC_DBGR_NIDBG; - tmp |= value << SDHC_DBGR_NIDBG_Pos; - ((Sdhc *)hw)->DBGR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->DBGR.reg; -} - -static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->FERACES.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->FEREIS.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b) -#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b) -#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b) -#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b) -#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b) -#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a) -#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a) -#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a) -#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b) -#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a) -#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a) -#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a) -#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a) -#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b) -#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a) -#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a) -#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a) -#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b) -#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b) -#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b) -#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b) -#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b) -#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a) -#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a) -#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a) -#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b) -#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a) -#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a) -#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a) -#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a) -#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b) -#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a) -#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a) -#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b) -#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b) -#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b) -#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b) -#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b) -#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a) -#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a) -#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a) -#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a) -#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a) -#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a) -#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a) -#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a) -#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a) -#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a) -#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a) -#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a) -#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a) -#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a) -#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a) -#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a) -#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a) -#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a) -#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a) -#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a) -#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a) -#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a) -#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b) -#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b) -#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b) -#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b) -#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b) -#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a) -#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a) -#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a) -#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a) -#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a) -#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a) -#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a) -#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a) -#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a) -#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a) -#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a) -#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a) -#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a) -#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a) -#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a) -#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a) -#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a) -#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b) -#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b) -#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b) -#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b) -#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b) -#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a) -#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a) -#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a) -#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a) -#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a) -#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a) -#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a) -#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a) -#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a) -#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a) -#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a) -#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a) -#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a) -#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a) -#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a) -#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a) -#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a) -#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a) -#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a) -#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b) -#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b) -#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b) -#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b) -#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b) -#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a) -#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a) -#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a) -#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a) -#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a) -#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a) -#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a) -#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a) -#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a) -#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a) -#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a) -#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a) -#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a) -#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a) -#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a) -#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a) -#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a) -#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b) -#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b) -#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b) -#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b) -#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b) -#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a) -#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a) -#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a) -#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a) -#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a) -#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a) -#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a) -#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a) -#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a) -#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a) -#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a) -#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a) -#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a) -#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a) -#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a) -#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a) -#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a) -#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a) -#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a) -#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b) -#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b) -#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b) -#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b) -#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b) -#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a) -#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a) -#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a) -#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a) -#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a) -#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a) -#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a) -#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a) -#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a) -#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a) -#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a) -#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a) -#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a) -#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a) -#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a) -#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a) -#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a) -#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b) -#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b) -#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b) -#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b) -#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b) -#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a) -#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a) -#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a) -#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b) -#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a) -#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a) -#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b) -#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a) -#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a) -#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b) -#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a) -#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a) -#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a) -#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b) -#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b) -#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b) -#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b) -#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b) -#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SDHC_E54_H_INCLUDED */ -#endif /* _SAME54_SDHC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_sercom_e54.h b/software/firmware/project_oracle_base/hri/hri_sercom_e54.h deleted file mode 100644 index fed00ff..0000000 --- a/software/firmware/project_oracle_base/hri/hri_sercom_e54.h +++ /dev/null @@ -1,8892 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM - * - * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_SERCOM_COMPONENT_ -#ifndef _HRI_SERCOM_E54_H_INCLUDED_ -#define _HRI_SERCOM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) -#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SERCOM_CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sercomi2cm_status_reg_t; -typedef uint16_t hri_sercomi2cs_length_reg_t; -typedef uint16_t hri_sercomi2cs_status_reg_t; -typedef uint16_t hri_sercomspi_length_reg_t; -typedef uint16_t hri_sercomspi_status_reg_t; -typedef uint16_t hri_sercomusart_baud_reg_t; -typedef uint16_t hri_sercomusart_length_reg_t; -typedef uint16_t hri_sercomusart_status_reg_t; -typedef uint32_t hri_sercomi2cm_addr_reg_t; -typedef uint32_t hri_sercomi2cm_baud_reg_t; -typedef uint32_t hri_sercomi2cm_ctrla_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; -typedef uint32_t hri_sercomi2cm_data_reg_t; -typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; -typedef uint32_t hri_sercomi2cs_addr_reg_t; -typedef uint32_t hri_sercomi2cs_ctrla_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; -typedef uint32_t hri_sercomi2cs_data_reg_t; -typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; -typedef uint32_t hri_sercomspi_addr_reg_t; -typedef uint32_t hri_sercomspi_ctrla_reg_t; -typedef uint32_t hri_sercomspi_ctrlb_reg_t; -typedef uint32_t hri_sercomspi_ctrlc_reg_t; -typedef uint32_t hri_sercomspi_data_reg_t; -typedef uint32_t hri_sercomspi_syncbusy_reg_t; -typedef uint32_t hri_sercomusart_ctrla_reg_t; -typedef uint32_t hri_sercomusart_ctrlb_reg_t; -typedef uint32_t hri_sercomusart_ctrlc_reg_t; -typedef uint32_t hri_sercomusart_data_reg_t; -typedef uint32_t hri_sercomusart_syncbusy_reg_t; -typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; -typedef uint8_t hri_sercomi2cm_intenset_reg_t; -typedef uint8_t hri_sercomi2cm_intflag_reg_t; -typedef uint8_t hri_sercomi2cs_intenset_reg_t; -typedef uint8_t hri_sercomi2cs_intflag_reg_t; -typedef uint8_t hri_sercomspi_baud_reg_t; -typedef uint8_t hri_sercomspi_dbgctrl_reg_t; -typedef uint8_t hri_sercomspi_intenset_reg_t; -typedef uint8_t hri_sercomspi_intflag_reg_t; -typedef uint8_t hri_sercomusart_dbgctrl_reg_t; -typedef uint8_t hri_sercomusart_intenset_reg_t; -typedef uint8_t hri_sercomusart_intflag_reg_t; -typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; -typedef uint8_t hri_sercomusart_rxpl_reg_t; - -static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTFLAG.reg; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cs_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTFLAG.reg; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; -} - -static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, - hri_sercomspi_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTFLAG.reg; -} - -static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = mask; -} - -static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, - hri_sercomusart_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTFLAG.reg; -} - -static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = mask; -} - -static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = mask; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, - hri_sercomi2cm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTENSET.reg; -} - -static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = data; - ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; -} - -static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = mask; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, - hri_sercomi2cs_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTENSET.reg; -} - -static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = data; - ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; -} - -static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; -} - -static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; - } -} - -static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; -} - -static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; - } -} - -static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; - } -} - -static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = mask; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, - hri_sercomspi_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTENSET.reg; -} - -static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = data; - ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; -} - -static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = mask; -} - -static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; -} - -static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; - } -} - -static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; - } -} - -static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; - } -} - -static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENSET.reg = mask; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, - hri_sercomusart_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTENSET.reg; -} - -static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) -{ - ((Sercom *)hw)->USART.INTENSET.reg = data; - ((Sercom *)hw)->USART.INTENCLR.reg = ~data; -} - -static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = mask; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cs_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, - hri_sercomspi_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, - hri_sercomusart_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, - hri_sercomusart_rxerrcnt_reg_t mask) -{ - uint8_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - return ((Sercom *)hw)->USART.RXERRCNT.reg; -} - -static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CM_CTRLA_MODE(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CM_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; - tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->I2CM.CTRLA.reg; -} - -static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CS_CTRLA_MODE(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CS_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg = data; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) -{ - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->I2CS.CTRLA.reg; -} - -static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_ENABLE; - tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_IBON; - tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPHA; - tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPOL; - tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DORD; - tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; - tmp |= SERCOM_SPI_CTRLA_MODE(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DOPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DIPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; - tmp |= SERCOM_SPI_CTRLA_FORM(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->SPI.CTRLA.reg; -} - -static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_ENABLE; - tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_IBON; - tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXINV; - tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXINV; - tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CMODE; - tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CPOL; - tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_DORD; - tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; - tmp |= SERCOM_USART_CTRLA_MODE(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPR(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; - tmp |= SERCOM_USART_CTRLA_TXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; - tmp |= SERCOM_USART_CTRLA_RXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPA(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; - tmp |= SERCOM_USART_CTRLA_FORM(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->USART.CTRLA.reg; -} - -static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_SMEN; - tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_QCEN; - tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CM_CTRLB_CMD(data); - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.CTRLB.reg; -} - -static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_SMEN; - tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_GCMD; - tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; - tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; - tmp |= SERCOM_I2CS_CTRLB_AMODE(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CS_CTRLB_CMD(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLB.reg; -} - -static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; - tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_SSDE; - tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_MSSEN; - tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_RXEN; - tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; - tmp |= SERCOM_SPI_CTRLB_AMODE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - return ((Sercom *)hw)->SPI.CTRLB.reg; -} - -static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SBMODE; - tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_COLDEN; - tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SFDE; - tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_ENC; - tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_PMODE; - tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_TXEN; - tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_RXEN; - tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_USART_CTRLB_CHSIZE(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; - tmp |= SERCOM_USART_CTRLB_LINCMD(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - return ((Sercom *)hw)->USART.CTRLB.reg; -} - -static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; - tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, - hri_sercomi2cm_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.CTRLC.reg; -} - -static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; - tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, - hri_sercomi2cs_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; - tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); - ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, - hri_sercomi2cs_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLC.reg; -} - -static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= ~SERCOM_SPI_CTRLC_DATA32B; - tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->SPI.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, - hri_sercomspi_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; - tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); - ((Sercom *)hw)->SPI.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, - hri_sercomspi_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.CTRLC.reg; -} - -static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_INACK; - tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_DSNACK; - tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; - tmp |= SERCOM_USART_CTRLC_GTIME(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; - tmp |= SERCOM_USART_CTRLC_BRKLEN(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; - tmp |= SERCOM_USART_CTRLC_HDRDLY(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; - tmp |= SERCOM_USART_CTRLC_MAXITER(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; - tmp |= SERCOM_USART_CTRLC_DATA32B(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLC.reg; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.BAUD.reg; -} - -static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; - tmp |= SERCOM_SPI_BAUD_BAUD(data); - ((Sercom *)hw)->SPI.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRAC_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; - tmp |= SERCOM_USART_RXPL_RXPL(data); - ((Sercom *)hw)->USART.RXPL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.RXPL.reg; -} - -static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= ~SERCOM_I2CS_LENGTH_LENEN; - tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; - ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomi2cs_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; - tmp |= SERCOM_I2CS_LENGTH_LEN(data); - ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, - hri_sercomi2cs_length_reg_t mask) -{ - uint16_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg = data; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) -{ - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - return ((Sercom *)hw)->I2CS.LENGTH.reg; -} - -static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= ~SERCOM_SPI_LENGTH_LENEN; - tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; - ((Sercom *)hw)->SPI.LENGTH.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomspi_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; - tmp |= SERCOM_SPI_LENGTH_LEN(data); - ((Sercom *)hw)->SPI.LENGTH.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, - hri_sercomspi_length_reg_t mask) -{ - uint16_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - return ((Sercom *)hw)->SPI.LENGTH.reg; -} - -static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; - tmp |= SERCOM_USART_LENGTH_LEN(data); - ((Sercom *)hw)->USART.LENGTH.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; - tmp |= SERCOM_USART_LENGTH_LENEN(data); - ((Sercom *)hw)->USART.LENGTH.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - return ((Sercom *)hw)->USART.LENGTH.reg; -} - -static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LENEN; - tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_HS; - tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CM_ADDR_ADDR(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; - tmp |= SERCOM_I2CM_ADDR_LEN(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.ADDR.reg; -} - -static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_GENCEN; - tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDR(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.ADDR.reg; -} - -static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; - tmp |= SERCOM_SPI_ADDR_ADDR(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.ADDR.reg; -} - -static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, - hri_sercomi2cm_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; - tmp |= SERCOM_I2CM_DATA_DATA(data); - ((Sercom *)hw)->I2CM.DATA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, - hri_sercomi2cm_data_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.DATA.reg; -} - -static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, - hri_sercomi2cs_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; - tmp |= SERCOM_I2CS_DATA_DATA(data); - ((Sercom *)hw)->I2CS.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, - hri_sercomi2cs_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.DATA.reg; -} - -static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, - hri_sercomspi_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp &= ~SERCOM_SPI_DATA_DATA_Msk; - tmp |= SERCOM_SPI_DATA_DATA(data); - ((Sercom *)hw)->SPI.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DATA.reg; -} - -static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, - hri_sercomusart_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp &= ~SERCOM_USART_DATA_DATA_Msk; - tmp |= SERCOM_USART_DATA_DATA(data); - ((Sercom *)hw)->USART.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, - hri_sercomusart_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DATA.reg; -} - -static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, - hri_sercomi2cm_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.DBGCTRL.reg; -} - -static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, - hri_sercomspi_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DBGCTRL.reg; -} - -static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, - hri_sercomusart_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DBGCTRL.reg; -} - -static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, - hri_sercomi2cs_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.STATUS.reg; -} - -static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, - hri_sercomspi_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.STATUS.reg; -} - -static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, - hri_sercomusart_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.STATUS.reg; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSERR; - tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; - tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_RXNACK; - tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; - tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; - tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LENERR; - tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; - tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - uint16_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - ((Sercom *)hw)->I2CM.STATUS.reg |= mask; -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.STATUS.reg; -} - -static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - ((Sercom *)hw)->I2CM.STATUS.reg = data; -} - -static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; -} - -static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) -#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) -#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) -#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) -#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) -#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) -#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) -#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) -#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) -#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) -#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) -#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) -#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) -#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) -#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) -#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) -#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) -#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SERCOM_E54_H_INCLUDED */ -#endif /* _SAME54_SERCOM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_supc_e54.h b/software/firmware/project_oracle_base/hri/hri_supc_e54.h deleted file mode 100644 index 501c36f..0000000 --- a/software/firmware/project_oracle_base/hri/hri_supc_e54.h +++ /dev/null @@ -1,1769 +0,0 @@ -/** - * \file - * - * \brief SAM SUPC - * - * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_SUPC_COMPONENT_ -#ifndef _HRI_SUPC_E54_H_INCLUDED_ -#define _HRI_SUPC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) -#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SUPC_CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_supc_bbps_reg_t; -typedef uint32_t hri_supc_bkin_reg_t; -typedef uint32_t hri_supc_bkout_reg_t; -typedef uint32_t hri_supc_bod33_reg_t; -typedef uint32_t hri_supc_intenset_reg_t; -typedef uint32_t hri_supc_intflag_reg_t; -typedef uint32_t hri_supc_status_reg_t; -typedef uint32_t hri_supc_vref_reg_t; -typedef uint32_t hri_supc_vreg_reg_t; - -static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) -{ - return ((Supc *)hw)->INTFLAG.reg; -} - -static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - ((Supc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; - } -} - -static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; -} - -static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; - } -} - -static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; -} - -static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; -} - -static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; -} - -static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; - } -} - -static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; -} - -static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; -} - -static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; -} - -static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; - } -} - -static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; -} - -static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; -} - -static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; -} - -static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; - } -} - -static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; -} - -static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENSET.reg = mask; -} - -static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) -{ - return ((Supc *)hw)->INTENSET.reg; -} - -static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) -{ - ((Supc *)hw)->INTENSET.reg = data; - ((Supc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; -} - -static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; -} - -static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) -{ - return ((Supc *)hw)->STATUS.reg; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKIN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) -{ - return ((Supc *)hw)->BKIN.reg; -} - -static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ENABLE; - tmp |= value << SUPC_BOD33_ENABLE_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_STDBYCFG; - tmp |= value << SUPC_BOD33_STDBYCFG_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNSTDBY; - tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNHIB; - tmp |= value << SUPC_BOD33_RUNHIB_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNBKUP; - tmp |= value << SUPC_BOD33_RUNBKUP_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ACTION_Msk; - tmp |= SUPC_BOD33_ACTION(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_HYST_Msk; - tmp |= SUPC_BOD33_HYST(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_PSEL_Msk; - tmp |= SUPC_BOD33_PSEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_LEVEL_Msk; - tmp |= SUPC_BOD33_LEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; - tmp |= SUPC_BOD33_VBATLEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) -{ - return ((Supc *)hw)->BOD33.reg; -} - -static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_ENABLE; - tmp |= value << SUPC_VREG_ENABLE_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_SEL; - tmp |= value << SUPC_VREG_SEL_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_RUNBKUP; - tmp |= value << SUPC_VREG_RUNBKUP_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSEN; - tmp |= value << SUPC_VREG_VSEN_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSPER_Msk; - tmp |= SUPC_VREG_VSPER(data); - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) -{ - return ((Supc *)hw)->VREG.reg; -} - -static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSEN; - tmp |= value << SUPC_VREF_TSEN_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_VREFOE; - tmp |= value << SUPC_VREF_VREFOE_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSSEL; - tmp |= value << SUPC_VREF_TSSEL_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_RUNSTDBY; - tmp |= value << SUPC_VREF_RUNSTDBY_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_ONDEMAND; - tmp |= value << SUPC_VREF_ONDEMAND_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_SEL_Msk; - tmp |= SUPC_VREF_SEL(data); - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) -{ - return ((Supc *)hw)->VREF.reg; -} - -static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_CONF; - tmp |= value << SUPC_BBPS_CONF_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_WAKEEN; - tmp |= value << SUPC_BBPS_WAKEEN_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) -{ - return ((Supc *)hw)->BBPS.reg; -} - -static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_EN_Msk; - tmp |= SUPC_BKOUT_EN(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_CLR_Msk; - tmp |= SUPC_BKOUT_CLR(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_SET_Msk; - tmp |= SUPC_BKOUT_SET(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_RTCTGL_Msk; - tmp |= SUPC_BKOUT_RTCTGL(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) -{ - return ((Supc *)hw)->BKOUT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SUPC_E54_H_INCLUDED */ -#endif /* _SAME54_SUPC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_tc_e54.h b/software/firmware/project_oracle_base/hri/hri_tc_e54.h deleted file mode 100644 index a31cb2c..0000000 --- a/software/firmware/project_oracle_base/hri/hri_tc_e54.h +++ /dev/null @@ -1,3003 +0,0 @@ -/** - * \file - * - * \brief SAM TC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_TC_COMPONENT_ -#ifndef _HRI_TC_E54_H_INCLUDED_ -#define _HRI_TC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TC_CRITICAL_SECTIONS) -#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TC_CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tc_evctrl_reg_t; -typedef uint16_t hri_tccount16_cc_reg_t; -typedef uint16_t hri_tccount16_ccbuf_reg_t; -typedef uint16_t hri_tccount16_count_reg_t; -typedef uint32_t hri_tc_ctrla_reg_t; -typedef uint32_t hri_tc_syncbusy_reg_t; -typedef uint32_t hri_tccount32_cc_reg_t; -typedef uint32_t hri_tccount32_ccbuf_reg_t; -typedef uint32_t hri_tccount32_count_reg_t; -typedef uint8_t hri_tc_ctrlbset_reg_t; -typedef uint8_t hri_tc_dbgctrl_reg_t; -typedef uint8_t hri_tc_drvctrl_reg_t; -typedef uint8_t hri_tc_intenset_reg_t; -typedef uint8_t hri_tc_intflag_reg_t; -typedef uint8_t hri_tc_status_reg_t; -typedef uint8_t hri_tc_wave_reg_t; -typedef uint8_t hri_tccount8_cc_reg_t; -typedef uint8_t hri_tccount8_ccbuf_reg_t; -typedef uint8_t hri_tccount8_count_reg_t; -typedef uint8_t hri_tccount8_per_reg_t; -typedef uint8_t hri_tccount8_perbuf_reg_t; - -static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; -} - -static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.INTFLAG.reg; -} - -static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; -} - -static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; -} - -static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; - } -} - -static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; -} - -static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; -} - -static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; - } -} - -static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; -} - -static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; -} - -static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); -} - -static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); -} - -static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.CTRLBSET.reg; -} - -static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; -} - -static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; -} - -static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; -} - -static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; -} - -static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; - } -} - -static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; -} - -static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; -} - -static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; -} - -static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; - } -} - -static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; -} - -static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; -} - -static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; -} - -static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; - } -} - -static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; -} - -static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; -} - -static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; -} - -static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; - } -} - -static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; -} - -static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = mask; -} - -static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.INTENSET.reg; -} - -static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = data; - ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; -} - -static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; -} - -static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; -} - -static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ENABLE; - tmp |= value << TC_CTRLA_ENABLE_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_RUNSTDBY; - tmp |= value << TC_CTRLA_RUNSTDBY_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ONDEMAND; - tmp |= value << TC_CTRLA_ONDEMAND_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ALOCK; - tmp |= value << TC_CTRLA_ALOCK_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN0; - tmp |= value << TC_CTRLA_CAPTEN0_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN1; - tmp |= value << TC_CTRLA_CAPTEN1_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN0; - tmp |= value << TC_CTRLA_COPEN0_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN1; - tmp |= value << TC_CTRLA_COPEN1_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_MODE_Msk; - tmp |= TC_CTRLA_MODE(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCSYNC_Msk; - tmp |= TC_CTRLA_PRESCSYNC(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCALER_Msk; - tmp |= TC_CTRLA_PRESCALER(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTMODE0_Msk; - tmp |= TC_CTRLA_CAPTMODE0(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTMODE1_Msk; - tmp |= TC_CTRLA_CAPTMODE1(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - return ((Tc *)hw)->COUNT16.CTRLA.reg; -} - -static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCINV; - tmp |= value << TC_EVCTRL_TCINV_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCEI; - tmp |= value << TC_EVCTRL_TCEI_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_OVFEO; - tmp |= value << TC_EVCTRL_OVFEO_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO0; - tmp |= value << TC_EVCTRL_MCEO0_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO1; - tmp |= value << TC_EVCTRL_MCEO1_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_EVACT_Msk; - tmp |= TC_EVCTRL_EVACT(data); - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.EVCTRL.reg; -} - -static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp &= ~TC_WAVE_WAVEGEN_Msk; - tmp |= TC_WAVE_WAVEGEN(data); - ((Tc *)hw)->COUNT16.WAVE.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.WAVE.reg; -} - -static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN0; - tmp |= value << TC_DRVCTRL_INVEN0_Pos; - ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN1; - tmp |= value << TC_DRVCTRL_INVEN1_Pos; - ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.DRVCTRL.reg; -} - -static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp &= ~TC_DBGCTRL_DBGRUN; - tmp |= value << TC_DBGCTRL_DBGRUN_Pos; - ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.DBGCTRL.reg; -} - -static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount8_count_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; - tmp |= TC_COUNT8_COUNT_COUNT(data); - ((Tc *)hw)->COUNT8.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT8.COUNT.reg; -} - -static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount16_count_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; - tmp |= TC_COUNT16_COUNT_COUNT(data); - ((Tc *)hw)->COUNT16.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, - hri_tccount16_count_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT16.COUNT.reg; -} - -static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount32_count_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; - tmp |= TC_COUNT32_COUNT_COUNT(data); - ((Tc *)hw)->COUNT32.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, - hri_tccount32_count_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT32.COUNT.reg; -} - -static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= ~TC_COUNT8_PER_PER_Msk; - tmp |= TC_COUNT8_PER_PER(data); - ((Tc *)hw)->COUNT8.PER.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - return ((Tc *)hw)->COUNT8.PER.reg; -} - -static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount8_cc_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= ~TC_COUNT8_CC_CC_Msk; - tmp |= TC_COUNT8_CC_CC(data); - ((Tc *)hw)->COUNT8.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount8_cc_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT8.CC[index].reg; -} - -static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount16_cc_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= ~TC_COUNT16_CC_CC_Msk; - tmp |= TC_COUNT16_CC_CC(data); - ((Tc *)hw)->COUNT16.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount16_cc_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT16.CC[index].reg; -} - -static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount32_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= ~TC_COUNT32_CC_CC_Msk; - tmp |= TC_COUNT32_CC_CC(data); - ((Tc *)hw)->COUNT32.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount32_cc_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT32.CC[index].reg; -} - -static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, - hri_tccount8_perbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; - tmp |= TC_COUNT8_PERBUF_PERBUF(data); - ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, - hri_tccount8_perbuf_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT8.PERBUF.reg; -} - -static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT8_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT8.CCBUF[index].reg; -} - -static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT16_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT16.CCBUF[index].reg; -} - -static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT32_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT32.CCBUF[index].reg; -} - -static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; -} - -static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; -} - -static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT16.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT16.STATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) -#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) -#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) -#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) -#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) -#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) -#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) -#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) -#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) -#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) -#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) -#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) -#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) -#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) -#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) -#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) -#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) -#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) -#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) -#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) -#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) -#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) -#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) -#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TC_E54_H_INCLUDED */ -#endif /* _SAME54_TC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_tcc_e54.h b/software/firmware/project_oracle_base/hri/hri_tcc_e54.h deleted file mode 100644 index 55f46bd..0000000 --- a/software/firmware/project_oracle_base/hri/hri_tcc_e54.h +++ /dev/null @@ -1,9992 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_TCC_COMPONENT_ -#ifndef _HRI_TCC_E54_H_INCLUDED_ -#define _HRI_TCC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TCC_CRITICAL_SECTIONS) -#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TCC_CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tcc_patt_reg_t; -typedef uint16_t hri_tcc_pattbuf_reg_t; -typedef uint32_t hri_tcc_cc_reg_t; -typedef uint32_t hri_tcc_ccbuf_reg_t; -typedef uint32_t hri_tcc_count_reg_t; -typedef uint32_t hri_tcc_ctrla_reg_t; -typedef uint32_t hri_tcc_drvctrl_reg_t; -typedef uint32_t hri_tcc_evctrl_reg_t; -typedef uint32_t hri_tcc_fctrla_reg_t; -typedef uint32_t hri_tcc_fctrlb_reg_t; -typedef uint32_t hri_tcc_intenset_reg_t; -typedef uint32_t hri_tcc_intflag_reg_t; -typedef uint32_t hri_tcc_per_reg_t; -typedef uint32_t hri_tcc_perbuf_reg_t; -typedef uint32_t hri_tcc_status_reg_t; -typedef uint32_t hri_tcc_syncbusy_reg_t; -typedef uint32_t hri_tcc_wave_reg_t; -typedef uint32_t hri_tcc_wexctrl_reg_t; -typedef uint8_t hri_tcc_ctrlbset_reg_t; -typedef uint8_t hri_tcc_dbgctrl_reg_t; - -static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - while (((Tcc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - return ((Tcc *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; -} - -static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; -} - -static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; -} - -static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTFLAG.reg; -} - -static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - ((Tcc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; -} - -static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; - } -} - -static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; -} - -static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; -} - -static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; - } -} - -static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; -} - -static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); -} - -static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); -} - -static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->CTRLBSET.reg; -} - -static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = data; - ((Tcc *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; -} - -static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; -} - -static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; - } -} - -static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; -} - -static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; -} - -static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; -} - -static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; - } -} - -static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; -} - -static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; -} - -static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; -} - -static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; - } -} - -static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; -} - -static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; -} - -static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; -} - -static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; - } -} - -static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; -} - -static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; -} - -static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; -} - -static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; - } -} - -static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; -} - -static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; -} - -static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; -} - -static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; - } -} - -static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; -} - -static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; -} - -static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; -} - -static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; -} - -static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; -} - -static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; -} - -static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; -} - -static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; -} - -static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; -} - -static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; -} - -static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; -} - -static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; - } -} - -static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; -} - -static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; -} - -static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; -} - -static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; - } -} - -static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; -} - -static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; -} - -static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; -} - -static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; - } -} - -static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; -} - -static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; -} - -static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; -} - -static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; - } -} - -static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; -} - -static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; -} - -static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; -} - -static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; - } -} - -static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; -} - -static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; -} - -static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; -} - -static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; - } -} - -static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; -} - -static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENSET.reg = mask; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTENSET.reg; -} - -static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) -{ - ((Tcc *)hw)->INTENSET.reg = data; - ((Tcc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tcc *)hw)->SYNCBUSY.reg; -} - -static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ENABLE; - tmp |= value << TCC_CTRLA_ENABLE_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RUNSTDBY; - tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ALOCK; - tmp |= value << TCC_CTRLA_ALOCK_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_MSYNC; - tmp |= value << TCC_CTRLA_MSYNC_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_DMAOS; - tmp |= value << TCC_CTRLA_DMAOS_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN0; - tmp |= value << TCC_CTRLA_CPTEN0_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN1; - tmp |= value << TCC_CTRLA_CPTEN1_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN2; - tmp |= value << TCC_CTRLA_CPTEN2_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN3; - tmp |= value << TCC_CTRLA_CPTEN3_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN4; - tmp |= value << TCC_CTRLA_CPTEN4_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN5; - tmp |= value << TCC_CTRLA_CPTEN5_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RESOLUTION_Msk; - tmp |= TCC_CTRLA_RESOLUTION(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCALER_Msk; - tmp |= TCC_CTRLA_PRESCALER(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; - tmp |= TCC_CTRLA_PRESCSYNC(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - return ((Tcc *)hw)->CTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_KEEP; - tmp |= value << TCC_FCTRLA_KEEP_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_QUAL; - tmp |= value << TCC_FCTRLA_QUAL_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_RESTART; - tmp |= value << TCC_FCTRLA_RESTART_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKPRESC; - tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_SRC_Msk; - tmp |= TCC_FCTRLA_SRC(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANK_Msk; - tmp |= TCC_FCTRLA_BLANK(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_HALT_Msk; - tmp |= TCC_FCTRLA_HALT(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CHSEL_Msk; - tmp |= TCC_FCTRLA_CHSEL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CAPTURE_Msk; - tmp |= TCC_FCTRLA_CAPTURE(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; - tmp |= TCC_FCTRLA_BLANKVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; - tmp |= TCC_FCTRLA_FILTERVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_KEEP; - tmp |= value << TCC_FCTRLB_KEEP_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_QUAL; - tmp |= value << TCC_FCTRLB_QUAL_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_RESTART; - tmp |= value << TCC_FCTRLB_RESTART_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKPRESC; - tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_SRC_Msk; - tmp |= TCC_FCTRLB_SRC(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANK_Msk; - tmp |= TCC_FCTRLB_BLANK(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_HALT_Msk; - tmp |= TCC_FCTRLB_HALT(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CHSEL_Msk; - tmp |= TCC_FCTRLB_CHSEL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CAPTURE_Msk; - tmp |= TCC_FCTRLB_CAPTURE(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; - tmp |= TCC_FCTRLB_BLANKVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; - tmp |= TCC_FCTRLB_FILTERVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLB.reg; -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN0; - tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN1; - tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN2; - tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN3; - tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_OTMX_Msk; - tmp |= TCC_WEXCTRL_OTMX(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTLS_Msk; - tmp |= TCC_WEXCTRL_DTLS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTHS_Msk; - tmp |= TCC_WEXCTRL_DTHS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->WEXCTRL.reg; -} - -static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE0; - tmp |= value << TCC_DRVCTRL_NRE0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE1; - tmp |= value << TCC_DRVCTRL_NRE1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE2; - tmp |= value << TCC_DRVCTRL_NRE2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE3; - tmp |= value << TCC_DRVCTRL_NRE3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE4; - tmp |= value << TCC_DRVCTRL_NRE4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE5; - tmp |= value << TCC_DRVCTRL_NRE5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE6; - tmp |= value << TCC_DRVCTRL_NRE6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE7; - tmp |= value << TCC_DRVCTRL_NRE7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV0; - tmp |= value << TCC_DRVCTRL_NRV0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV1; - tmp |= value << TCC_DRVCTRL_NRV1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV2; - tmp |= value << TCC_DRVCTRL_NRV2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV3; - tmp |= value << TCC_DRVCTRL_NRV3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV4; - tmp |= value << TCC_DRVCTRL_NRV4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV5; - tmp |= value << TCC_DRVCTRL_NRV5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV6; - tmp |= value << TCC_DRVCTRL_NRV6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV7; - tmp |= value << TCC_DRVCTRL_NRV7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN0; - tmp |= value << TCC_DRVCTRL_INVEN0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN1; - tmp |= value << TCC_DRVCTRL_INVEN1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN2; - tmp |= value << TCC_DRVCTRL_INVEN2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN3; - tmp |= value << TCC_DRVCTRL_INVEN3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN4; - tmp |= value << TCC_DRVCTRL_INVEN4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN5; - tmp |= value << TCC_DRVCTRL_INVEN5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN6; - tmp |= value << TCC_DRVCTRL_INVEN6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN7; - tmp |= value << TCC_DRVCTRL_INVEN7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL0(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL1(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DRVCTRL.reg; -} - -static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_DBGRUN; - tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_FDDBD; - tmp |= value << TCC_DBGCTRL_FDDBD_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DBGCTRL.reg; -} - -static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_OVFEO; - tmp |= value << TCC_EVCTRL_OVFEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TRGEO; - tmp |= value << TCC_EVCTRL_TRGEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTEO; - tmp |= value << TCC_EVCTRL_CNTEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV0; - tmp |= value << TCC_EVCTRL_TCINV0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV1; - tmp |= value << TCC_EVCTRL_TCINV1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI0; - tmp |= value << TCC_EVCTRL_TCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI1; - tmp |= value << TCC_EVCTRL_TCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI0; - tmp |= value << TCC_EVCTRL_MCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI1; - tmp |= value << TCC_EVCTRL_MCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI2; - tmp |= value << TCC_EVCTRL_MCEI2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI3; - tmp |= value << TCC_EVCTRL_MCEI3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI4; - tmp |= value << TCC_EVCTRL_MCEI4_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI5; - tmp |= value << TCC_EVCTRL_MCEI5_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO0; - tmp |= value << TCC_EVCTRL_MCEO0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO1; - tmp |= value << TCC_EVCTRL_MCEO1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO2; - tmp |= value << TCC_EVCTRL_MCEO2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO3; - tmp |= value << TCC_EVCTRL_MCEO3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO4; - tmp |= value << TCC_EVCTRL_MCEO4_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO5; - tmp |= value << TCC_EVCTRL_MCEO5_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT0_Msk; - tmp |= TCC_EVCTRL_EVACT0(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT1_Msk; - tmp |= TCC_EVCTRL_EVACT1(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTSEL_Msk; - tmp |= TCC_EVCTRL_CNTSEL(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->EVCTRL.reg; -} - -static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE0; - tmp |= value << TCC_PATT_PGE0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE1; - tmp |= value << TCC_PATT_PGE1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE2; - tmp |= value << TCC_PATT_PGE2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE3; - tmp |= value << TCC_PATT_PGE3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE4; - tmp |= value << TCC_PATT_PGE4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE5; - tmp |= value << TCC_PATT_PGE5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE6; - tmp |= value << TCC_PATT_PGE6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE7; - tmp |= value << TCC_PATT_PGE7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV0; - tmp |= value << TCC_PATT_PGV0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV1; - tmp |= value << TCC_PATT_PGV1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV2; - tmp |= value << TCC_PATT_PGV2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV3; - tmp |= value << TCC_PATT_PGV3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV4; - tmp |= value << TCC_PATT_PGV4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV5; - tmp |= value << TCC_PATT_PGV5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV6; - tmp |= value << TCC_PATT_PGV6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV7; - tmp |= value << TCC_PATT_PGV7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - uint16_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->PATT.reg; -} - -static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CIPEREN; - tmp |= value << TCC_WAVE_CIPEREN_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN0; - tmp |= value << TCC_WAVE_CICCEN0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN1; - tmp |= value << TCC_WAVE_CICCEN1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN2; - tmp |= value << TCC_WAVE_CICCEN2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN3; - tmp |= value << TCC_WAVE_CICCEN3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL0; - tmp |= value << TCC_WAVE_POL0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL1; - tmp |= value << TCC_WAVE_POL1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL2; - tmp |= value << TCC_WAVE_POL2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL3; - tmp |= value << TCC_WAVE_POL3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL4; - tmp |= value << TCC_WAVE_POL4_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL5; - tmp |= value << TCC_WAVE_POL5_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP0; - tmp |= value << TCC_WAVE_SWAP0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP1; - tmp |= value << TCC_WAVE_SWAP1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP2; - tmp |= value << TCC_WAVE_SWAP2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP3; - tmp |= value << TCC_WAVE_SWAP3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_WAVEGEN_Msk; - tmp |= TCC_WAVE_WAVEGEN(data); - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_RAMP_Msk; - tmp |= TCC_WAVE_RAMP(data); - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->WAVE.reg; -} - -static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH4_DITHER_Msk; - tmp |= TCC_PER_DITH4_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH5_DITHER_Msk; - tmp |= TCC_PER_DITH5_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH6_DITHER_Msk; - tmp |= TCC_PER_DITH6_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH4_DITHER_Msk; - tmp |= TCC_CC_DITH4_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH5_DITHER_Msk; - tmp |= TCC_CC_DITH5_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH6_DITHER_Msk; - tmp |= TCC_CC_DITH6_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB0; - tmp |= value << TCC_PATTBUF_PGEB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB1; - tmp |= value << TCC_PATTBUF_PGEB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB2; - tmp |= value << TCC_PATTBUF_PGEB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB3; - tmp |= value << TCC_PATTBUF_PGEB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB4; - tmp |= value << TCC_PATTBUF_PGEB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB5; - tmp |= value << TCC_PATTBUF_PGEB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB6; - tmp |= value << TCC_PATTBUF_PGEB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB7; - tmp |= value << TCC_PATTBUF_PGEB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB0; - tmp |= value << TCC_PATTBUF_PGVB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB1; - tmp |= value << TCC_PATTBUF_PGVB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB2; - tmp |= value << TCC_PATTBUF_PGVB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB3; - tmp |= value << TCC_PATTBUF_PGVB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB4; - tmp |= value << TCC_PATTBUF_PGVB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB5; - tmp |= value << TCC_PATTBUF_PGVB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB6; - tmp |= value << TCC_PATTBUF_PGVB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB7; - tmp |= value << TCC_PATTBUF_PGVB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PATTBUF.reg; -} - -static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERBUF.reg; -} - -static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCBUF[index].reg; -} - -static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; -} - -static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; -} - -static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; -} - -static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->STATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) -#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) -#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TCC_E54_H_INCLUDED */ -#endif /* _SAME54_TCC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_trng_e54.h b/software/firmware/project_oracle_base/hri/hri_trng_e54.h deleted file mode 100644 index e42caab..0000000 --- a/software/firmware/project_oracle_base/hri/hri_trng_e54.h +++ /dev/null @@ -1,380 +0,0 @@ -/** - * \file - * - * \brief SAM TRNG - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_TRNG_COMPONENT_ -#ifndef _HRI_TRNG_E54_H_INCLUDED_ -#define _HRI_TRNG_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) -#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TRNG_CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_trng_data_reg_t; -typedef uint8_t hri_trng_ctrla_reg_t; -typedef uint8_t hri_trng_evctrl_reg_t; -typedef uint8_t hri_trng_intenset_reg_t; -typedef uint8_t hri_trng_intflag_reg_t; - -static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) -{ - return ((Trng *)hw)->INTFLAG.reg; -} - -static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - ((Trng *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; -} - -static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; -} - -static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; - } else { - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; - } -} - -static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; -} - -static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENSET.reg = mask; -} - -static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) -{ - return ((Trng *)hw)->INTENSET.reg; -} - -static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) -{ - ((Trng *)hw)->INTENSET.reg = data; - ((Trng *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENCLR.reg = mask; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Trng *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) -{ - return ((Trng *)hw)->DATA.reg; -} - -static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_ENABLE; - tmp |= value << TRNG_CTRLA_ENABLE_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_RUNSTDBY; - tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) -{ - return ((Trng *)hw)->CTRLA.reg; -} - -static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= ~TRNG_EVCTRL_DATARDYEO; - tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; - ((Trng *)hw)->EVCTRL.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) -{ - return ((Trng *)hw)->EVCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TRNG_E54_H_INCLUDED */ -#endif /* _SAME54_TRNG_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_usb_e54.h b/software/firmware/project_oracle_base/hri/hri_usb_e54.h deleted file mode 100644 index 34b5e02..0000000 --- a/software/firmware/project_oracle_base/hri/hri_usb_e54.h +++ /dev/null @@ -1,9335 +0,0 @@ -/** - * \file - * - * \brief SAM USB - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_USB_COMPONENT_ -#ifndef _HRI_USB_E54_H_INCLUDED_ -#define _HRI_USB_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_USB_CRITICAL_SECTIONS) -#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define USB_CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_usb_padcal_reg_t; -typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; -typedef uint16_t hri_usbdesc_bank_extreg_reg_t; -typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; -typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; -typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; -typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; -typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; -typedef uint16_t hri_usbdevice_ctrlb_reg_t; -typedef uint16_t hri_usbdevice_epintsmry_reg_t; -typedef uint16_t hri_usbdevice_fnum_reg_t; -typedef uint16_t hri_usbdevice_intenset_reg_t; -typedef uint16_t hri_usbdevice_intflag_reg_t; -typedef uint16_t hri_usbhost_ctrlb_reg_t; -typedef uint16_t hri_usbhost_fnum_reg_t; -typedef uint16_t hri_usbhost_intenset_reg_t; -typedef uint16_t hri_usbhost_intflag_reg_t; -typedef uint16_t hri_usbhost_pintsmry_reg_t; -typedef uint32_t hri_usb_descadd_reg_t; -typedef uint32_t hri_usbdesc_bank_addr_reg_t; -typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; -typedef uint32_t hri_usbdescriptordevice_addr_reg_t; -typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; -typedef uint32_t hri_usbdescriptorhost_addr_reg_t; -typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; -typedef uint8_t hri_usb_ctrla_reg_t; -typedef uint8_t hri_usb_fsmstatus_reg_t; -typedef uint8_t hri_usb_qosctrl_reg_t; -typedef uint8_t hri_usb_syncbusy_reg_t; -typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; -typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; -typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; -typedef uint8_t hri_usbdevice_dadd_reg_t; -typedef uint8_t hri_usbdevice_epcfg_reg_t; -typedef uint8_t hri_usbdevice_epintenset_reg_t; -typedef uint8_t hri_usbdevice_epintflag_reg_t; -typedef uint8_t hri_usbdevice_epstatus_reg_t; -typedef uint8_t hri_usbdevice_status_reg_t; -typedef uint8_t hri_usbendpoint_epcfg_reg_t; -typedef uint8_t hri_usbendpoint_epintenset_reg_t; -typedef uint8_t hri_usbendpoint_epintflag_reg_t; -typedef uint8_t hri_usbendpoint_epstatus_reg_t; -typedef uint8_t hri_usbhost_binterval_reg_t; -typedef uint8_t hri_usbhost_flenhigh_reg_t; -typedef uint8_t hri_usbhost_hsofc_reg_t; -typedef uint8_t hri_usbhost_pcfg_reg_t; -typedef uint8_t hri_usbhost_pintenset_reg_t; -typedef uint8_t hri_usbhost_pintflag_reg_t; -typedef uint8_t hri_usbhost_pstatus_reg_t; -typedef uint8_t hri_usbhost_status_reg_t; -typedef uint8_t hri_usbpipe_binterval_reg_t; -typedef uint8_t hri_usbpipe_pcfg_reg_t; -typedef uint8_t hri_usbpipe_pintenset_reg_t; -typedef uint8_t hri_usbpipe_pintflag_reg_t; -typedef uint8_t hri_usbpipe_pstatus_reg_t; - -static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) -{ - while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->EXTREG.reg; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_BK.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; -} - -static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t -hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t -hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) - >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) - >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_bk_reg_t -hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) - >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) - >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) - >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbendpoint_epintflag_reg_t -hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintflag_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbendpoint_epstatus_reg_t -hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbendpoint_epintenset_reg_t -hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbdevice_epintflag_reg_t -hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbdevice_epintenset_reg_t -hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, - hri_usbdevice_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTFLAG.reg; -} - -static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; -} - -static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, - hri_usbhost_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTFLAG.reg; -} - -static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; - } -} - -static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; - } -} - -static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; - } -} - -static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = mask; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, - hri_usbdevice_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTENSET.reg; -} - -static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = data; - ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; -} - -static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; -} - -static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; -} - -static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; - } -} - -static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; -} - -static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; -} - -static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; -} - -static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; - } -} - -static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; -} - -static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; - } -} - -static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; - } -} - -static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; -} - -static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; -} - -static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; - } -} - -static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; -} - -static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; -} - -static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; -} - -static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; - } -} - -static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; -} - -static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENSET.reg = mask; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, - hri_usbhost_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTENSET.reg; -} - -static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) -{ - ((Usb *)hw)->HOST.INTENSET.reg = data; - ((Usb *)hw)->HOST.INTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = mask; -} - -static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.SYNCBUSY.reg; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.STATUS.reg; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, - hri_usb_fsmstatus_reg_t mask) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FSMSTATUS.reg; -} - -static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FNUM.reg; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FLENHIGH.reg; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, - hri_usbdevice_epintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, - hri_usbhost_pintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PINTSMRY.reg; -} - -static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_ENABLE; - tmp |= value << USB_CTRLA_ENABLE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_RUNSTDBY; - tmp |= value << USB_CTRLA_RUNSTDBY_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_MODE; - tmp |= value << USB_CTRLA_MODE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg = data; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) -{ - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - return ((Usb *)hw)->HOST.CTRLA.reg; -} - -static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_CQOS_Msk; - tmp |= USB_QOSCTRL_CQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_DQOS_Msk; - tmp |= USB_QOSCTRL_DQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.QOSCTRL.reg; -} - -static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_DETACH; - tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_UPRSM; - tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_NREPLY; - tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTJ; - tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTK; - tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; - tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_OPMODE2; - tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_GNAK; - tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; - tmp |= USB_DEVICE_CTRLB_SPDCONF(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; - tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.CTRLB.reg; -} - -static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_RESUME; - tmp |= value << USB_HOST_CTRLB_RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_AUTORESUME; - tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTJ; - tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTK; - tmp |= value << USB_HOST_CTRLB_TSTK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SOFE; - tmp |= value << USB_HOST_CTRLB_SOFE_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_BUSRESET; - tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_VBUSOK; - tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_L1RESUME; - tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; - tmp |= USB_HOST_CTRLB_SPDCONF(data); - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.CTRLB.reg; -} - -static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_ADDEN; - tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, - hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_DADD_Msk; - tmp |= USB_DEVICE_DADD_DADD(data); - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DADD.reg; -} - -static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENCE; - tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENC_Msk; - tmp |= USB_HOST_HSOFC_FLENC(data); - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.HSOFC.reg; -} - -static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_MFNUM_Msk; - tmp |= USB_HOST_FNUM_MFNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_FNUM_Msk; - tmp |= USB_HOST_FNUM_FNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FNUM.reg; -} - -static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= ~USB_DESCADD_DESCADD_Msk; - tmp |= USB_DESCADD_DESCADD(data); - ((Usb *)hw)->HOST.DESCADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.DESCADD.reg; -} - -static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSP_Msk; - tmp |= USB_PADCAL_TRANSP(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSN_Msk; - tmp |= USB_PADCAL_TRANSN(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRIM_Msk; - tmp |= USB_PADCAL_TRIM(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PADCAL.reg; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.STATUS.reg; -} - -static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->EXTREG.reg; -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, - hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void -hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) - >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_status_bk_reg_t -hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_status_bk_reg_t -hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) -#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) -#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) -#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) -#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) -#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) -#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) -#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) -#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) -#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) -#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) -#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) -#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) -#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) -#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) -#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) -#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) -#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) -#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) -#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) -#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) -#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) -#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) -#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) -#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) -#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) -#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) -#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) -#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) -#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) -#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) -#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) -#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) -#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) -#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) -#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) -#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) -#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) -#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) -#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) -#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) -#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) -#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) -#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) -#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) -#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) -#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) -#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) -#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) -#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) -#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) -#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) -#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) -#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) -#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) -#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) -#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) -#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) -#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) -#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) -#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) -#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) -#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) -#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) -#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) -#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) -#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) -#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) -#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) -#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) -#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) -#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) -#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) -#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) -#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) -#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) -#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) -#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) -#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) -#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) -#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) -#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) -#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) -#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) -#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) -#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) -#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) -#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) -#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) -#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) -#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) -#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) -#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) -#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) -#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) -#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) -#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) -#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) -#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) -#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) -#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) -#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_USB_E54_H_INCLUDED */ -#endif /* _SAME54_USB_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/hri/hri_wdt_e54.h b/software/firmware/project_oracle_base/hri/hri_wdt_e54.h deleted file mode 100644 index 3549e2f..0000000 --- a/software/firmware/project_oracle_base/hri/hri_wdt_e54.h +++ /dev/null @@ -1,617 +0,0 @@ -/** - * \file - * - * \brief SAM WDT - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_WDT_COMPONENT_ -#ifndef _HRI_WDT_E54_H_INCLUDED_ -#define _HRI_WDT_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_WDT_CRITICAL_SECTIONS) -#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define WDT_CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_wdt_syncbusy_reg_t; -typedef uint8_t hri_wdt_clear_reg_t; -typedef uint8_t hri_wdt_config_reg_t; -typedef uint8_t hri_wdt_ctrla_reg_t; -typedef uint8_t hri_wdt_ewctrl_reg_t; -typedef uint8_t hri_wdt_intenset_reg_t; -typedef uint8_t hri_wdt_intflag_reg_t; - -static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - while (((Wdt *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - return ((Wdt *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTFLAG.reg; -} - -static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - ((Wdt *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; -} - -static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; -} - -static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; - } else { - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; - } -} - -static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; -} - -static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENSET.reg = mask; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTENSET.reg; -} - -static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) -{ - ((Wdt *)hw)->INTENSET.reg = data; - ((Wdt *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Wdt *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Wdt *)hw)->SYNCBUSY.reg; -} - -static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ENABLE; - tmp |= value << WDT_CTRLA_ENABLE_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_WEN; - tmp |= value << WDT_CTRLA_WEN_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ALWAYSON; - tmp |= value << WDT_CTRLA_ALWAYSON_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg = data; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) -{ - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - return ((Wdt *)hw)->CTRLA.reg; -} - -static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_PER_Msk; - tmp |= WDT_CONFIG_PER(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_WINDOW_Msk; - tmp |= WDT_CONFIG_WINDOW(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) -{ - return ((Wdt *)hw)->CONFIG.reg; -} - -static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; - tmp |= WDT_EWCTRL_EWOFFSET(data); - ((Wdt *)hw)->EWCTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) -{ - return ((Wdt *)hw)->EWCTRL.reg; -} - -static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CLEAR.reg = data; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); - WDT_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_WDT_E54_H_INCLUDED */ -#endif /* _SAME54_WDT_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component-version.h b/software/firmware/project_oracle_base/include/component-version.h deleted file mode 100644 index d786d20..0000000 --- a/software/firmware/project_oracle_base/include/component-version.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 1 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version. -// -#define COMPONENT_VERSION 10001 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 134 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.1" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2019-04-09 08:16:19" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - diff --git a/software/firmware/project_oracle_base/include/component/ac.h b/software/firmware/project_oracle_base/include/component/ac.h deleted file mode 100644 index e8a9fc4..0000000 --- a/software/firmware/project_oracle_base/include/component/ac.h +++ /dev/null @@ -1,598 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_AC_COMPONENT_ -#define _SAME54_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAME54_AC Analog Comparators */ -/*@{*/ - -#define AC_U2501 -#define REV_AC 0x100 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ -#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ - -/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ - uint16_t :14; /*!< bit: 2..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} AC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ -#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ - -#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ -#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) -#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) -#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ - __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component/adc.h b/software/firmware/project_oracle_base/include/component/adc.h deleted file mode 100644 index b2fee11..0000000 --- a/software/firmware/project_oracle_base/include/component/adc.h +++ /dev/null @@ -1,871 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_ADC_COMPONENT_ -#define _SAME54_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAME54_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2500 -#define REV_ADC 0x100 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t :1; /*!< bit: 2 Reserved */ - uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ - uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :4; /*!< bit: 11..14 Reserved */ - uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ -#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) -#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ -#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ -#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ -#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) -#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ -#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ -#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ -#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ -#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ -#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ -#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ -#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ -#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ -#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) -#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :2; /*!< bit: 5.. 6 Reserved */ - uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :2; /*!< bit: 13..14 Reserved */ - uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ -#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ -#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) -#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ -#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ -#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) -#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ -#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ -#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ -#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) -#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ -#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) -#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ -#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) -#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) -#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ - uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ - uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ - uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ - uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ - uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ - uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ - uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ - uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) -#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ -#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ -#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ - -#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ -#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) -#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) -#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ - -/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ -#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ - -#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ -#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) -#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ -#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) -#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ -#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) -#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ -#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) -#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ -#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) -#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ -#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) -#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ -#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) -#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ -#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) -#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ -#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) -#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ -#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) -#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ - -/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQSTAT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ -#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ - -#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ -#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) -#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ -#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) -#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ -#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) -#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ -#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) -#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ -#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) -#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ -#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) -#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ -#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) -#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ -#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) -#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ -#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) -#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ -#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) -#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ -#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ -#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ - -#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ -#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) -#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) -#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ -#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) -#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ - RoReg8 Reserved1[0x1]; - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x17]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ - __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ - __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ - __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ - RoReg8 Reserved3[0x2]; - __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ - RoReg8 Reserved4[0x2]; - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component/aes.h b/software/firmware/project_oracle_base/include/component/aes.h deleted file mode 100644 index 2831d0d..0000000 --- a/software/firmware/project_oracle_base/include/component/aes.h +++ /dev/null @@ -1,375 +0,0 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_AES_COMPONENT_ -#define _SAME54_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAME54_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x220 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ - uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ - uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ - uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ -#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ -#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ -#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ -#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ -#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ -#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ -#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ -#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ -#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ -#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ -#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ -#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ -#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ -#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ -#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ -#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ -#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ -#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ -#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ -#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ -#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ -#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ -#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ -#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ -#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component/can.h b/software/firmware/project_oracle_base/include/component/can.h deleted file mode 100644 index 48b3cab..0000000 --- a/software/firmware/project_oracle_base/include/component/can.h +++ /dev/null @@ -1,3187 +0,0 @@ -/** - * \file - * - * \brief Component description for CAN - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_CAN_COMPONENT_ -#define _SAME54_CAN_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CAN */ -/* ========================================================================== */ -/** \addtogroup SAME54_CAN Control Area Network */ -/*@{*/ - -#define CAN_U2003 -#define REV_CAN 0x321 - -/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :20; /*!< bit: 0..19 Reserved */ - uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ - uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ - uint32_t REL:4; /*!< bit: 28..31 Core Release */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_CREL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ -#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */ - -#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ -#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) -#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) -#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ -#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) -#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) -#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ -#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) -#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) -#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */ - -/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ENDN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ -#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */ - -#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ -#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) -#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) -#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */ - -/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_MRCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ -#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ - -#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ -#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) -#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ -#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ -#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */ -#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */ -#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */ - -/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ - uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ - uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ - uint32_t :2; /*!< bit: 21..22 Reserved */ - uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_DBTP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ -#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ - -#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ -#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) -#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) -#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ -#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) -#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) -#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ -#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) -#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) -#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ -#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) -#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) -#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ -#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos) -#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */ - -/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ - uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ - uint32_t RX:1; /*!< bit: 7 Receive Pin */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TEST_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ -#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */ - -#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ -#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos) -#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ -#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) -#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) -#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */ -#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */ -#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ -#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ -#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ -#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos) -#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */ - -/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ - uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RWD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ -#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */ - -#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ -#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) -#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) -#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ -#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) -#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) -#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */ - -/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INIT:1; /*!< bit: 0 Initialization */ - uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ - uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ - uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ - uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ - uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ - uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ - uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ - uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ - uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ - uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ - uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ - uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_CCCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ -#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */ - -#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ -#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos) -#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ -#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos) -#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ -#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos) -#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ -#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos) -#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ -#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos) -#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ -#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos) -#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ -#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos) -#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ -#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos) -#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ -#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos) -#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ -#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos) -#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ -#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos) -#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ -#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos) -#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ -#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos) -#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ -#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos) -#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */ - -/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ - uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ - uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NBTP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ -#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ - -#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ -#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) -#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) -#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ -#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) -#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) -#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ -#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) -#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) -#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ -#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) -#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) -#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */ - -/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ - uint32_t :14; /*!< bit: 2..15 Reserved */ - uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TSCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ -#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ - -#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ -#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) -#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ -#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ -#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */ -#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ -#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) -#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) -#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */ - -/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TSCV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ -#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ - -#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ -#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) -#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) -#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */ - -/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ - uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TOCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ -#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ - -#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ -#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos) -#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ -#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) -#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */ -#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ -#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ -#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ -#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ -#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) -#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) -#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */ - -/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TOCV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ -#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ - -#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ -#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) -#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) -#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */ - -/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ - uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ - uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ - uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ECR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ -#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */ - -#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ -#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) -#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) -#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ -#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) -#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) -#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ -#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos) -#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ -#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) -#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) -#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */ - -/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ - uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ - uint32_t EP:1; /*!< bit: 5 Error Passive */ - uint32_t EW:1; /*!< bit: 6 Warning Status */ - uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ - uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ - uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ - uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ - uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ - uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_PSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ -#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */ - -#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ -#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) -#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ -#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ -#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ -#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ -#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ -#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ -#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ -#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ -#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ -#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) -#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ -#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ -#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */ -#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */ -#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ -#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos) -#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ -#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos) -#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ -#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos) -#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ -#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) -#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ -#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ -#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ -#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ -#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ -#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ -#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ -#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ -#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ -#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos) -#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ -#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos) -#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ -#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos) -#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ -#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos) -#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ -#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) -#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) -#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */ - -/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ - uint32_t :17; /*!< bit: 15..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TDCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ -#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ - -#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ -#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) -#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) -#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ -#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) -#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) -#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */ - -/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ - uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ - uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ - uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ - uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ - uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ - uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ - uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ - uint32_t HPM:1; /*!< bit: 8 High Priority Message */ - uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ - uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ - uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ - uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ - uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ - uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ - uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ - uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ - uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ - uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ - uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ - uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ - uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ - uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ - uint32_t EP:1; /*!< bit: 23 Error Passive */ - uint32_t EW:1; /*!< bit: 24 Warning Status */ - uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ - uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ - uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ - uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ - uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_IR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ -#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */ - -#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ -#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos) -#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ -#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos) -#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ -#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos) -#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ -#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos) -#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ -#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos) -#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ -#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos) -#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ -#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos) -#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ -#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos) -#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ -#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos) -#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ -#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos) -#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ -#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos) -#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ -#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos) -#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ -#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos) -#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ -#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos) -#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ -#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos) -#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ -#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos) -#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ -#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos) -#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ -#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos) -#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ -#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos) -#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ -#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos) -#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ -#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos) -#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ -#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos) -#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ -#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos) -#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ -#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos) -#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ -#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos) -#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ -#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos) -#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ -#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos) -#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ -#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos) -#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ -#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos) -#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ -#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos) -#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */ - -/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ - uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ - uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ - uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ - uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ - uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ - uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ - uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ - uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ - uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ - uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ - uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ - uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ - uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ - uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ - uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ - uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ - uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ - uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ - uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ - uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ - uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ - uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ - uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ - uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ - uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ - uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ - uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ - uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ - uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_IE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ -#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */ - -#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ -#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos) -#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ -#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos) -#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ -#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos) -#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ -#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos) -#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ -#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos) -#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ -#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos) -#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ -#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos) -#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ -#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos) -#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ -#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos) -#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ -#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos) -#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ -#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos) -#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ -#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos) -#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ -#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos) -#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ -#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos) -#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ -#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos) -#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ -#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos) -#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ -#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos) -#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ -#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos) -#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ -#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos) -#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ -#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos) -#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ -#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos) -#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ -#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos) -#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ -#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos) -#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ -#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos) -#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ -#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos) -#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ -#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos) -#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ -#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos) -#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ -#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos) -#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ -#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos) -#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ -#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos) -#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */ - -/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ - uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ - uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ - uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ - uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ - uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ - uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ - uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ - uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ - uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ - uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ - uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ - uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ - uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ - uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ - uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ - uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ - uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ - uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ - uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ - uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ - uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ - uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ - uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ - uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ - uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ - uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ - uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ - uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ - uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ILS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ -#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ - -#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ -#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos) -#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ -#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos) -#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ -#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos) -#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ -#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos) -#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ -#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos) -#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ -#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos) -#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ -#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos) -#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ -#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos) -#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ -#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos) -#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ -#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos) -#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ -#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos) -#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ -#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos) -#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ -#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos) -#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ -#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos) -#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ -#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos) -#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ -#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos) -#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ -#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos) -#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ -#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos) -#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ -#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos) -#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ -#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos) -#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ -#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos) -#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ -#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos) -#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ -#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos) -#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ -#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos) -#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ -#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos) -#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ -#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos) -#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ -#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos) -#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ -#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos) -#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ -#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos) -#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ -#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos) -#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */ - -/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ - uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ILE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ -#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ - -#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ -#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos) -#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ -#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos) -#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */ - -/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ - uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ - uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ - uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_GFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ -#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ - -#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ -#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos) -#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ -#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos) -#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ -#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) -#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ -#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ -#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) -#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ -#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */ - -/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ - uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_SIDFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ -#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ - -#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ -#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) -#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) -#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ -#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) -#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) -#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */ - -/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ - uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ -#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ - -#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ -#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) -#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) -#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ -#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) -#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) -#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */ - -/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ - uint32_t :3; /*!< bit: 29..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDAM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ -#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ - -#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ -#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) -#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) -#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */ - -/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ - uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ - uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ - uint32_t FLST:1; /*!< bit: 15 Filter List */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_HPMS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ -#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ - -#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ -#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) -#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) -#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ -#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) -#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */ -#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */ -#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ -#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ -#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ -#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) -#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) -#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ -#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos) -#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */ - -/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ND0:1; /*!< bit: 0 New Data 0 */ - uint32_t ND1:1; /*!< bit: 1 New Data 1 */ - uint32_t ND2:1; /*!< bit: 2 New Data 2 */ - uint32_t ND3:1; /*!< bit: 3 New Data 3 */ - uint32_t ND4:1; /*!< bit: 4 New Data 4 */ - uint32_t ND5:1; /*!< bit: 5 New Data 5 */ - uint32_t ND6:1; /*!< bit: 6 New Data 6 */ - uint32_t ND7:1; /*!< bit: 7 New Data 7 */ - uint32_t ND8:1; /*!< bit: 8 New Data 8 */ - uint32_t ND9:1; /*!< bit: 9 New Data 9 */ - uint32_t ND10:1; /*!< bit: 10 New Data 10 */ - uint32_t ND11:1; /*!< bit: 11 New Data 11 */ - uint32_t ND12:1; /*!< bit: 12 New Data 12 */ - uint32_t ND13:1; /*!< bit: 13 New Data 13 */ - uint32_t ND14:1; /*!< bit: 14 New Data 14 */ - uint32_t ND15:1; /*!< bit: 15 New Data 15 */ - uint32_t ND16:1; /*!< bit: 16 New Data 16 */ - uint32_t ND17:1; /*!< bit: 17 New Data 17 */ - uint32_t ND18:1; /*!< bit: 18 New Data 18 */ - uint32_t ND19:1; /*!< bit: 19 New Data 19 */ - uint32_t ND20:1; /*!< bit: 20 New Data 20 */ - uint32_t ND21:1; /*!< bit: 21 New Data 21 */ - uint32_t ND22:1; /*!< bit: 22 New Data 22 */ - uint32_t ND23:1; /*!< bit: 23 New Data 23 */ - uint32_t ND24:1; /*!< bit: 24 New Data 24 */ - uint32_t ND25:1; /*!< bit: 25 New Data 25 */ - uint32_t ND26:1; /*!< bit: 26 New Data 26 */ - uint32_t ND27:1; /*!< bit: 27 New Data 27 */ - uint32_t ND28:1; /*!< bit: 28 New Data 28 */ - uint32_t ND29:1; /*!< bit: 29 New Data 29 */ - uint32_t ND30:1; /*!< bit: 30 New Data 30 */ - uint32_t ND31:1; /*!< bit: 31 New Data 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NDAT1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ -#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ - -#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ -#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos) -#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ -#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos) -#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ -#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos) -#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ -#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos) -#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ -#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos) -#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ -#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos) -#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ -#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos) -#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ -#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos) -#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ -#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos) -#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ -#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos) -#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ -#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos) -#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ -#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos) -#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ -#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos) -#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ -#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos) -#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ -#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos) -#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ -#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos) -#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ -#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos) -#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ -#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos) -#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ -#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos) -#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ -#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos) -#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ -#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos) -#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ -#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos) -#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ -#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos) -#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ -#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos) -#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ -#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos) -#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ -#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos) -#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ -#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos) -#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ -#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos) -#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ -#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos) -#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ -#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos) -#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ -#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos) -#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ -#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos) -#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */ - -/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ND32:1; /*!< bit: 0 New Data 32 */ - uint32_t ND33:1; /*!< bit: 1 New Data 33 */ - uint32_t ND34:1; /*!< bit: 2 New Data 34 */ - uint32_t ND35:1; /*!< bit: 3 New Data 35 */ - uint32_t ND36:1; /*!< bit: 4 New Data 36 */ - uint32_t ND37:1; /*!< bit: 5 New Data 37 */ - uint32_t ND38:1; /*!< bit: 6 New Data 38 */ - uint32_t ND39:1; /*!< bit: 7 New Data 39 */ - uint32_t ND40:1; /*!< bit: 8 New Data 40 */ - uint32_t ND41:1; /*!< bit: 9 New Data 41 */ - uint32_t ND42:1; /*!< bit: 10 New Data 42 */ - uint32_t ND43:1; /*!< bit: 11 New Data 43 */ - uint32_t ND44:1; /*!< bit: 12 New Data 44 */ - uint32_t ND45:1; /*!< bit: 13 New Data 45 */ - uint32_t ND46:1; /*!< bit: 14 New Data 46 */ - uint32_t ND47:1; /*!< bit: 15 New Data 47 */ - uint32_t ND48:1; /*!< bit: 16 New Data 48 */ - uint32_t ND49:1; /*!< bit: 17 New Data 49 */ - uint32_t ND50:1; /*!< bit: 18 New Data 50 */ - uint32_t ND51:1; /*!< bit: 19 New Data 51 */ - uint32_t ND52:1; /*!< bit: 20 New Data 52 */ - uint32_t ND53:1; /*!< bit: 21 New Data 53 */ - uint32_t ND54:1; /*!< bit: 22 New Data 54 */ - uint32_t ND55:1; /*!< bit: 23 New Data 55 */ - uint32_t ND56:1; /*!< bit: 24 New Data 56 */ - uint32_t ND57:1; /*!< bit: 25 New Data 57 */ - uint32_t ND58:1; /*!< bit: 26 New Data 58 */ - uint32_t ND59:1; /*!< bit: 27 New Data 59 */ - uint32_t ND60:1; /*!< bit: 28 New Data 60 */ - uint32_t ND61:1; /*!< bit: 29 New Data 61 */ - uint32_t ND62:1; /*!< bit: 30 New Data 62 */ - uint32_t ND63:1; /*!< bit: 31 New Data 63 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NDAT2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ -#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ - -#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ -#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos) -#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ -#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos) -#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ -#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos) -#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ -#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos) -#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ -#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos) -#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ -#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos) -#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ -#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos) -#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ -#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos) -#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ -#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos) -#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ -#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos) -#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ -#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos) -#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ -#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos) -#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ -#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos) -#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ -#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos) -#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ -#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos) -#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ -#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos) -#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ -#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos) -#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ -#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos) -#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ -#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos) -#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ -#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos) -#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ -#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos) -#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ -#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos) -#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ -#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos) -#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ -#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos) -#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ -#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos) -#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ -#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos) -#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ -#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos) -#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ -#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos) -#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ -#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos) -#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ -#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos) -#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ -#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos) -#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ -#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos) -#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */ - -/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ - uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ - uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0C_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ -#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ - -#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ -#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) -#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) -#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ -#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) -#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) -#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ -#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) -#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) -#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ -#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos) -#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */ - -/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ - uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0S_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ -#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ - -#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ -#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) -#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) -#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ -#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) -#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) -#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ -#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) -#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) -#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ -#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos) -#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ -#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos) -#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */ - -/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0A_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ -#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ - -#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ -#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) -#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) -#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */ - -/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ -#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ - -#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ -#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) -#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) -#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */ - -/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ - uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ - uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1C_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ -#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ - -#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ -#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) -#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) -#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ -#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) -#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) -#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ -#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) -#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) -#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ -#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos) -#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */ - -/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ - uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ - uint32_t :4; /*!< bit: 26..29 Reserved */ - uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1S_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ -#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ - -#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ -#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) -#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) -#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ -#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) -#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) -#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ -#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) -#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) -#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ -#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos) -#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ -#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos) -#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ -#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) -#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */ -#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */ -#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */ -#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ -#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */ - -/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1A_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ -#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ - -#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ -#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) -#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) -#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */ - -/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ - uint32_t :21; /*!< bit: 11..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXESC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ -#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ - -#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ -#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) -#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ -#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) -#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ -#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) -#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */ - -/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ - uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ - uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ -#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ - -#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ -#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) -#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) -#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ -#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) -#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) -#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ -#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) -#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) -#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ -#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos) -#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */ - -/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ - uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXFQS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ -#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ - -#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ -#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) -#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) -#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ -#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) -#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) -#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ -#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) -#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) -#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ -#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos) -#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */ - -/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXESC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ -#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ - -#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ -#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) -#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */ -#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */ -#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */ -#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */ -#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */ -#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */ -#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */ -#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */ -#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */ - -/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ - uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ - uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ - uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ - uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ - uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ - uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ - uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ - uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ - uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ - uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ - uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ - uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ - uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ - uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ - uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ - uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ - uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ - uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ - uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ - uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ - uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ - uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ - uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ - uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ - uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ - uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ - uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ - uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ - uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ - uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ - uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBRP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ -#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ - -#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ -#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos) -#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ -#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos) -#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ -#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos) -#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ -#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos) -#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ -#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos) -#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ -#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos) -#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ -#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos) -#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ -#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos) -#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ -#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos) -#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ -#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos) -#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ -#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos) -#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ -#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos) -#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ -#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos) -#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ -#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos) -#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ -#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos) -#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ -#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos) -#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ -#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos) -#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ -#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos) -#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ -#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos) -#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ -#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos) -#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ -#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos) -#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ -#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos) -#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ -#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos) -#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ -#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos) -#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ -#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos) -#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ -#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos) -#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ -#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos) -#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ -#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos) -#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ -#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos) -#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ -#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos) -#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ -#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos) -#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ -#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos) -#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */ - -/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ - uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ - uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ - uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ - uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ - uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ - uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ - uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ - uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ - uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ - uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ - uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ - uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ - uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ - uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ - uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ - uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ - uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ - uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ - uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ - uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ - uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ - uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ - uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ - uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ - uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ - uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ - uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ - uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ - uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ - uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ - uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBAR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ -#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ - -#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ -#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos) -#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ -#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos) -#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ -#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos) -#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ -#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos) -#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ -#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos) -#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ -#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos) -#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ -#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos) -#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ -#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos) -#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ -#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos) -#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ -#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos) -#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ -#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos) -#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ -#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos) -#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ -#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos) -#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ -#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos) -#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ -#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos) -#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ -#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos) -#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ -#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos) -#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ -#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos) -#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ -#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos) -#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ -#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos) -#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ -#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos) -#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ -#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos) -#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ -#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos) -#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ -#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos) -#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ -#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos) -#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ -#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos) -#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ -#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos) -#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ -#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos) -#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ -#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos) -#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ -#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos) -#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ -#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos) -#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ -#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos) -#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */ - -/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ - uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ - uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ - uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ - uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ - uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ - uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ - uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ - uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ - uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ - uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ - uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ - uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ - uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ - uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ - uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ - uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ - uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ - uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ - uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ - uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ - uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ - uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ - uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ - uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ - uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ - uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ - uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ - uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ - uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ - uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ - uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ -#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ - -#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ -#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos) -#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ -#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos) -#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ -#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos) -#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ -#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos) -#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ -#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos) -#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ -#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos) -#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ -#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos) -#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ -#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos) -#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ -#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos) -#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ -#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos) -#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ -#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos) -#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ -#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos) -#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ -#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos) -#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ -#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos) -#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ -#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos) -#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ -#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos) -#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ -#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos) -#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ -#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos) -#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ -#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos) -#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ -#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos) -#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ -#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos) -#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ -#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos) -#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ -#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos) -#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ -#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos) -#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ -#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos) -#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ -#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos) -#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ -#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos) -#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ -#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos) -#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ -#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos) -#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ -#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos) -#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ -#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos) -#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ -#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos) -#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */ - -/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ - uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ - uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ - uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ - uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ - uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ - uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ - uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ - uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ - uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ - uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ - uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ - uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ - uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ - uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ - uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ - uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ - uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ - uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ - uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ - uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ - uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ - uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ - uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ - uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ - uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ - uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ - uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ - uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ - uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ - uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ - uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBTO_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ -#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ - -#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ -#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos) -#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ -#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos) -#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ -#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos) -#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ -#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos) -#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ -#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos) -#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ -#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos) -#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ -#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos) -#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ -#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos) -#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ -#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos) -#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ -#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos) -#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ -#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos) -#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ -#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos) -#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ -#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos) -#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ -#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos) -#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ -#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos) -#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ -#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos) -#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ -#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos) -#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ -#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos) -#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ -#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos) -#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ -#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos) -#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ -#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos) -#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ -#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos) -#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ -#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos) -#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ -#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos) -#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ -#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos) -#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ -#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos) -#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ -#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos) -#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ -#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos) -#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ -#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos) -#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ -#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos) -#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ -#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos) -#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ -#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos) -#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */ - -/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ - uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ - uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ - uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ - uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ - uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ - uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ - uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ - uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ - uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ - uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ - uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ - uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ - uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ - uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ - uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ - uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ - uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ - uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ - uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ - uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ - uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ - uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ - uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ - uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ - uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ - uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ - uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ - uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ - uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ - uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ - uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ -#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ - -#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ -#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos) -#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ -#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos) -#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ -#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos) -#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ -#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos) -#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ -#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos) -#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ -#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos) -#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ -#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos) -#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ -#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos) -#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ -#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos) -#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ -#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos) -#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ -#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos) -#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ -#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos) -#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ -#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos) -#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ -#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos) -#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ -#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos) -#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ -#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos) -#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ -#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos) -#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ -#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos) -#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ -#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos) -#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ -#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos) -#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ -#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos) -#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ -#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos) -#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ -#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos) -#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ -#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos) -#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ -#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos) -#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ -#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos) -#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ -#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos) -#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ -#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos) -#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ -#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos) -#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ -#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos) -#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ -#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos) -#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ -#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos) -#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */ - -/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ - uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ - uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ - uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ - uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ - uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ - uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ - uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ - uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ - uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ - uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ - uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ - uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ - uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ - uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ - uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ - uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ - uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ - uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ - uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ - uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ - uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ - uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ - uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ - uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ - uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ - uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ - uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ - uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ - uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ - uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ - uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBTIE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ -#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ - -#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ -#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) -#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ -#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) -#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ -#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) -#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ -#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) -#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ -#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) -#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ -#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) -#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ -#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) -#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ -#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) -#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ -#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) -#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ -#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) -#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ -#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) -#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ -#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) -#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ -#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) -#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ -#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) -#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ -#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) -#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ -#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) -#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ -#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) -#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ -#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) -#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ -#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) -#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ -#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) -#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ -#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) -#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ -#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) -#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ -#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) -#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ -#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) -#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ -#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) -#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ -#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) -#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ -#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) -#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ -#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) -#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ -#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) -#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ -#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) -#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ -#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) -#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ -#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) -#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */ - -/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ - uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ - uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ - uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ - uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ - uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ - uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ - uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ - uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ - uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ - uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ - uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ - uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ - uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ - uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ - uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ - uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ - uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ - uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ - uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ - uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ - uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ - uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ - uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ - uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ - uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ - uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ - uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ - uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ - uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ - uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ - uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCIE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ -#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ - -#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ -#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) -#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ -#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) -#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ -#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) -#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ -#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) -#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ -#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) -#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ -#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) -#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ -#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) -#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ -#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) -#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ -#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) -#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ -#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) -#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ -#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) -#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ -#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) -#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ -#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) -#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ -#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) -#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ -#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) -#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ -#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) -#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ -#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) -#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ -#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) -#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ -#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) -#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ -#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) -#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ -#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) -#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ -#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) -#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ -#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) -#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ -#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) -#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ -#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) -#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ -#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) -#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ -#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) -#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ -#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) -#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ -#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) -#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ -#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) -#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ -#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) -#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ -#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) -#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */ - -/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ - uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ -#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ - -#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ -#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) -#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) -#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ -#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) -#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) -#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ -#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) -#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) -#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */ - -/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ - uint32_t :3; /*!< bit: 21..23 Reserved */ - uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ - uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ -#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ - -#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ -#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) -#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) -#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ -#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) -#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) -#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ -#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) -#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) -#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ -#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos) -#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ -#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos) -#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */ - -/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ -#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ - -#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ -#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) -#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) -#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */ - -/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ -#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ - -#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ -#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) -#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) -#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ -#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos) -#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ -#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos) -#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ -#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos) -#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */ - -/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ -#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ - -#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ -#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) -#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) -#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ -#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) -#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) -#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ -#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos) -#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ -#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos) -#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ -#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) -#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) -#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ -#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) -#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */ - -/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ -#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ - -#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ -#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) -#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) -#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ -#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) -#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) -#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ -#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) -#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) -#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ -#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) -#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) -#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */ - -/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ -#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ - -#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ -#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) -#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) -#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ -#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) -#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ -#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) -#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ -#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) -#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */ - -/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ -#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ - -#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ -#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) -#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) -#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ -#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) -#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) -#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ -#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) -#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ -#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) -#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ -#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) -#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) -#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ -#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) -#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */ - -/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ -#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ - -#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ -#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) -#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) -#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ -#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) -#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) -#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ -#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) -#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) -#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ -#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) -#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) -#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */ - -/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ -#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ - -#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ -#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) -#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) -#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ -#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) -#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ -#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) -#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ -#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) -#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */ - -/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ -#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ - -#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ -#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) -#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) -#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ -#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) -#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) -#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ -#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) -#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ -#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) -#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ -#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) -#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) -#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ -#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) -#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */ - -/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ -#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ - -#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ -#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) -#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) -#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ -#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) -#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) -#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ -#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) -#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) -#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ -#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) -#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) -#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */ - -/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ - uint32_t :5; /*!< bit: 11..15 Reserved */ - uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ - uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ - uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_SIDFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ -#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ - -#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ -#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) -#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) -#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ -#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) -#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) -#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ -#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) -#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */ -#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ -#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ -#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ -#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) -#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ -#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ -#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */ -#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */ - -/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ -#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ - -#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ -#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) -#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) -#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ -#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos) -#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ -#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos) -#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ -#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos) -#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */ - -/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t DLC:4; /*!< bit: 16..19 Identifier */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ - uint32_t MM:8; /*!< bit: 24..31 Message Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ -#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ - -#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ -#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) -#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) -#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ -#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos) -#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ -#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos) -#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ -#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos) -#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ -#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) -#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) -#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */ - -/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ -#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ - -#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ -#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) -#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) -#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ -#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) -#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) -#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ -#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) -#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) -#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ -#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) -#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) -#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */ - -/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ -#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ - -#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ -#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) -#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) -#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ -#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) -#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ -#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) -#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ -#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) -#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */ - -/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t ET:2; /*!< bit: 22..23 Event Type */ - uint32_t MM:8; /*!< bit: 24..31 Message Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ -#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ - -#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ -#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) -#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) -#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ -#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) -#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) -#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ -#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) -#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ -#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) -#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ -#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) -#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */ -#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ -#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ -#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) -#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) -#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */ - -/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ - uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ -#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ - -#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ -#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) -#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) -#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ -#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) -#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */ -#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ -#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ -#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */ - -/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ -#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ - -#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ -#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) -#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) -#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ -#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) -#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ -#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ -#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */ -#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ -#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */ - -/** \brief CAN APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ - __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ - __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ - __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ - __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ - __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ - __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ - __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ - __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ - __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ - __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ - __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ - RoReg8 Reserved1[0x10]; - __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ - __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ - __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ - RoReg8 Reserved2[0x4]; - __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ - __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ - __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ - __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ - RoReg8 Reserved3[0x20]; - __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ - __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ - __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ - RoReg8 Reserved4[0x4]; - __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ - __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ - __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ - __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ - __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ - __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ - __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ - __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ - __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ - __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ - __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ - __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ - __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ - __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ - __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ - __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ - __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ - __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ - __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ - __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ - __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ - __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ - RoReg8 Reserved5[0x8]; - __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ - __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ - __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ -} Can; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxbe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ - __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ - __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ -} CanMramRxbe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxf0e hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ - __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ - __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ -} CanMramRxf0e -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxf1e hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ - __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ - __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ -} CanMramRxf1e -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_sidfe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ -} CanMramSidfe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_txbe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ - __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ - __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ -} CanMramTxbe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_txefe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ - __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ -} CanMramTxefe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_xifde hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ - __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ -} CanMramXifde -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SECTION_CAN_MRAM_RXBE -#define SECTION_CAN_MRAM_RXF0E -#define SECTION_CAN_MRAM_RXF1E -#define SECTION_CAN_MRAM_SIDFE -#define SECTION_CAN_MRAM_TXBE -#define SECTION_CAN_MRAM_TXEFE -#define SECTION_CAN_MRAM_XIFDE - -/*@}*/ - -#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component/ccl.h b/software/firmware/project_oracle_base/include/component/ccl.h deleted file mode 100644 index b5dbb9a..0000000 --- a/software/firmware/project_oracle_base/include/component/ccl.h +++ /dev/null @@ -1,228 +0,0 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_CCL_COMPONENT_ -#define _SAME54_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAME54_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x110 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ -#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ - uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ -#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component/cmcc.h b/software/firmware/project_oracle_base/include/component/cmcc.h deleted file mode 100644 index 55799b5..0000000 --- a/software/firmware/project_oracle_base/include/component/cmcc.h +++ /dev/null @@ -1,357 +0,0 @@ -/** - * \file - * - * \brief Component description for CMCC - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_CMCC_COMPONENT_ -#define _SAME54_CMCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CMCC */ -/* ========================================================================== */ -/** \addtogroup SAME54_CMCC Cortex M Cache Controller */ -/*@{*/ - -#define CMCC_U2015 -#define REV_CMCC 0x600 - -/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ - uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ - uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ - uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ - uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ - uint32_t :18; /*!< bit: 14..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_TYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ -#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ - -#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ -#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) -#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ -#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) -#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ -#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) -#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ -#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ -#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) -#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ -#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) -#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ -#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) -#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ - -/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ - uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ -#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ - -#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ -#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) -#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ -#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) -#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ -#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ - -/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ -#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ - -#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ -#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) -#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ - -/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_SR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ -#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ - -#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ -#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) -#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ - -/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_LCKWAY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ -#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ - -#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ -#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) -#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) -#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ - -/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ -#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ - -#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ -#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) -#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ - -/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ - uint32_t :16; /*!< bit: 12..27 Reserved */ - uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ -#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ - -#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ -#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) -#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) -#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ -#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) -#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ - -/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ -#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ - -#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ -#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) -#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ -#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ - -/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ -#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ - -#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ -#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) -#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ - -/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ -#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ - -#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ -#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) -#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ - -/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ -#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ - -#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ -#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) -#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) -#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ - -/** \brief CMCC APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ - __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ - __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ - __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ - __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ - RoReg8 Reserved1[0xC]; - __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ - __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ - __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ - __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ - __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ - __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ -} Cmcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component/dac.h b/software/firmware/project_oracle_base/include/component/dac.h deleted file mode 100644 index 60f28c0..0000000 --- a/software/firmware/project_oracle_base/include/component/dac.h +++ /dev/null @@ -1,544 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_DAC_COMPONENT_ -#define _SAME54_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAME54_DAC Digital-to-Analog Converter */ -/*@{*/ - -#define DAC_U2502 -#define REV_DAC 0x100 - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ - uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) -#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ - uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ - uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ - uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ - uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ - uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ - uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ - uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ - uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ - uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ - uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ -#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) -#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ -#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) -#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ -#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) -#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ -#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) -#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ -#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) -#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ -#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) -#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) -#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ -#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) -#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ -#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) -#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ -#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) -#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) -#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) -#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) -#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) -#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) -#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) -#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) -#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) -#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) -#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) -#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) -#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) -#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) -#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) -#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) -#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) -#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) -#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) -#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) -#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) -#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) -#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) -#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) -#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) -#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) -#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ -#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) -#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) -#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ - __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ - __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ - __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ - __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ - __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ - __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ - __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ - __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ - __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ - __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ -#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) -#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ -#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) -#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ -#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) -#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ -#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) -#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) -#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ -#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) -#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ -#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) -#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ -#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) -#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) -#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ -#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) -#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ -#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) -#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ -#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) -#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) -#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ - uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ - uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ - uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ - uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ -#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) -#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ -#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) -#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) -#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ -#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) -#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ -#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) -#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) -#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) -#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ - uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ - uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ - uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ - uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ - uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DAC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ - -#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) -#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) -#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ -#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) -#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ -#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) -#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) -#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ -#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) -#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ -#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) -#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) -#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ - uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ - uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ - uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ - uint16_t :1; /*!< bit: 12 Reserved */ - uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DACCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ -#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ - -#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) -#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) -#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ -#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ -#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ -#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ -#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) -#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ -#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) -#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ -#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) -#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ -#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) -#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) -#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ -#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) -#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) -#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ -#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ -#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ - -/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ -#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ - -#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ -#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) -#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ - -/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ -#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ - -#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ -#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) -#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) -#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ - __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ - __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ - __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ - __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x3]; - __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_base/include/component/dmac.h b/software/firmware/project_oracle_base/include/component/dmac.h deleted file mode 100644 index a611b79..0000000 --- a/software/firmware/project_oracle_base/include/component/dmac.h +++ /dev/null @@ -1,1416 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_DMAC_COMPONENT_ -#define _SAME54_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAME54_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2503 -#define REV_DMAC 0x101 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t :6; /*!< bit: 2.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ -#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) -#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ -#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ -#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) -#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ - uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ - uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ - uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ - uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ - uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ - uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ - uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ - uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ - uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ - uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ - uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ - uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ - uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ - uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ - uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ - uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ - uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ - uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ - uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ - uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ - uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ - uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ - uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ -#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) -#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ -#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) -#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ -#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) -#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ -#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) -#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ -#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ - uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ - uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ - uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ - uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ - uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ - uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ - uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ - uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ - uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ - uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ - uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ - uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ - uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ - uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ - uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ - uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ - uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ - uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ - uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) -#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) -#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) -#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) -#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos) -#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos) -#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos) -#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos) -#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos) -#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos) -#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos) -#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos) -#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos) -#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos) -#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos) -#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos) -#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos) -#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos) -#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos) -#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ - uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ - uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ - uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ - uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ - uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ - uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ - uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ - uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ - uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ - uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ - uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ - uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ - uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ - uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ - uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ - uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ - uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ - uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ - uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ -#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) -#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ -#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) -#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ -#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) -#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ -#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) -#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */ -#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos) -#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */ -#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos) -#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */ -#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos) -#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */ -#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos) -#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */ -#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos) -#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */ -#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos) -#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */ -#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos) -#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */ -#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos) -#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */ -#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos) -#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */ -#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos) -#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */ -#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos) -#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */ -#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos) -#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */ -#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos) -#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */ -#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos) -#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */ -#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos) -#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ -#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ - uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ - uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ - uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ - uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ - uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ - uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ - uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ - uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ - uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ - uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ - uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ - uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ - uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ - uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ - uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ - uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ - uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ - uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ - uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ -#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) -#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ -#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) -#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ -#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) -#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ -#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) -#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */ -#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos) -#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */ -#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos) -#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */ -#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos) -#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */ -#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos) -#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */ -#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos) -#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */ -#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos) -#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */ -#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos) -#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */ -#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos) -#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */ -#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos) -#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */ -#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos) -#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */ -#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos) -#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */ -#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos) -#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */ -#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos) -#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */ -#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos) -#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */ -#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos) -#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ -#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ - uint32_t :5; /*!< bit: 15..19 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ - uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ -#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) -#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ -#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) -#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ -#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ -#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) -#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ -#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ -#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ -#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) -#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ -#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ -#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) -#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ -#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ - -#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHPRILVL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ -#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ - -#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ -#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) -#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ -#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ -#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ -#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ -#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ -#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ -#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ - -/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ - uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ - uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHEVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ -#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ - -#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ -#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) -#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ -#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ -#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ -#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ -#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ -#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ -#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ -#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ -#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos) -#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ -#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos) -#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ -#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ -#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos) -#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ -#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits -#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 10 // Index of Generic Clock -#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value -#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value -#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented -#define USB_PIPE_NUM 8 // Number of USB pipes -#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system -#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) -#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode -#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested -#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode - -#endif /* _SAME54_USB_INSTANCE_ */ diff --git a/software/firmware/project_oracle_base/include/instance/wdt.h b/software/firmware/project_oracle_base/include/instance/wdt.h deleted file mode 100644 index c96d770..0000000 --- a/software/firmware/project_oracle_base/include/instance/wdt.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_WDT_INSTANCE_ -#define _SAME54_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAME54_WDT_INSTANCE_ */ diff --git a/software/firmware/project_oracle_base/include/pio/same54n19a.h b/software/firmware/project_oracle_base/include/pio/same54n19a.h deleted file mode 100644 index 8d51a31..0000000 --- a/software/firmware/project_oracle_base/include/pio/same54n19a.h +++ /dev/null @@ -1,2688 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAME54N19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54N19A_PIO_ -#define _SAME54N19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ -#define MUX_PA23I_CAN0_RX _L_(8) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) -#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ -#define MUX_PA25I_CAN0_RX _L_(8) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) -#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ -#define MUX_PA22I_CAN0_TX _L_(8) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) -#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ -#define MUX_PA24I_CAN0_TX _L_(8) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ -#define MUX_PB13H_CAN1_RX _L_(7) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) -#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ -#define MUX_PB15H_CAN1_RX _L_(7) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) -#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ -#define MUX_PB12H_CAN1_TX _L_(7) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) -#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ -#define MUX_PB14H_CAN1_TX _L_(7) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ -#define MUX_PC21L_GMAC_GCOL _L_(11) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) -#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ -#define MUX_PA16L_GMAC_GCRS _L_(11) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) -#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ -#define MUX_PA20L_GMAC_GMDC _L_(11) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) -#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ -#define MUX_PB14L_GMAC_GMDC _L_(11) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) -#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ -#define MUX_PC11L_GMAC_GMDC _L_(11) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) -#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ -#define MUX_PA21L_GMAC_GMDIO _L_(11) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) -#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ -#define MUX_PB15L_GMAC_GMDIO _L_(11) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) -#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ -#define MUX_PC12L_GMAC_GMDIO _L_(11) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) -#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ -#define MUX_PA13L_GMAC_GRX0 _L_(11) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) -#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ -#define MUX_PA12L_GMAC_GRX1 _L_(11) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) -#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ -#define MUX_PC15L_GMAC_GRX2 _L_(11) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) -#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ -#define MUX_PC14L_GMAC_GRX3 _L_(11) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) -#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ -#define MUX_PC18L_GMAC_GRXCK _L_(11) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) -#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ -#define MUX_PC20L_GMAC_GRXDV _L_(11) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) -#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ -#define MUX_PA15L_GMAC_GRXER _L_(11) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) -#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ -#define MUX_PA18L_GMAC_GTX0 _L_(11) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) -#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ -#define MUX_PA19L_GMAC_GTX1 _L_(11) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) -#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ -#define MUX_PC16L_GMAC_GTX2 _L_(11) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) -#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ -#define MUX_PC17L_GMAC_GTX3 _L_(11) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) -#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ -#define MUX_PA14L_GMAC_GTXCK _L_(11) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) -#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ -#define MUX_PA17L_GMAC_GTXEN _L_(11) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) -#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ -#define MUX_PC19L_GMAC_GTXER _L_(11) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAME54N19A_PIO_ */ diff --git a/software/firmware/project_oracle_base/include/pio/same54n20a.h b/software/firmware/project_oracle_base/include/pio/same54n20a.h deleted file mode 100644 index d8a7ac4..0000000 --- a/software/firmware/project_oracle_base/include/pio/same54n20a.h +++ /dev/null @@ -1,2688 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAME54N20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54N20A_PIO_ -#define _SAME54N20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ -#define MUX_PA23I_CAN0_RX _L_(8) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) -#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ -#define MUX_PA25I_CAN0_RX _L_(8) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) -#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ -#define MUX_PA22I_CAN0_TX _L_(8) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) -#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ -#define MUX_PA24I_CAN0_TX _L_(8) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ -#define MUX_PB13H_CAN1_RX _L_(7) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) -#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ -#define MUX_PB15H_CAN1_RX _L_(7) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) -#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ -#define MUX_PB12H_CAN1_TX _L_(7) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) -#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ -#define MUX_PB14H_CAN1_TX _L_(7) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ -#define MUX_PC21L_GMAC_GCOL _L_(11) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) -#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ -#define MUX_PA16L_GMAC_GCRS _L_(11) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) -#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ -#define MUX_PA20L_GMAC_GMDC _L_(11) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) -#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ -#define MUX_PB14L_GMAC_GMDC _L_(11) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) -#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ -#define MUX_PC11L_GMAC_GMDC _L_(11) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) -#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ -#define MUX_PA21L_GMAC_GMDIO _L_(11) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) -#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ -#define MUX_PB15L_GMAC_GMDIO _L_(11) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) -#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ -#define MUX_PC12L_GMAC_GMDIO _L_(11) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) -#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ -#define MUX_PA13L_GMAC_GRX0 _L_(11) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) -#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ -#define MUX_PA12L_GMAC_GRX1 _L_(11) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) -#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ -#define MUX_PC15L_GMAC_GRX2 _L_(11) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) -#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ -#define MUX_PC14L_GMAC_GRX3 _L_(11) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) -#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ -#define MUX_PC18L_GMAC_GRXCK _L_(11) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) -#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ -#define MUX_PC20L_GMAC_GRXDV _L_(11) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) -#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ -#define MUX_PA15L_GMAC_GRXER _L_(11) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) -#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ -#define MUX_PA18L_GMAC_GTX0 _L_(11) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) -#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ -#define MUX_PA19L_GMAC_GTX1 _L_(11) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) -#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ -#define MUX_PC16L_GMAC_GTX2 _L_(11) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) -#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ -#define MUX_PC17L_GMAC_GTX3 _L_(11) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) -#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ -#define MUX_PA14L_GMAC_GTXCK _L_(11) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) -#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ -#define MUX_PA17L_GMAC_GTXEN _L_(11) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) -#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ -#define MUX_PC19L_GMAC_GTXER _L_(11) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAME54N20A_PIO_ */ diff --git a/software/firmware/project_oracle_base/include/pio/same54p19a.h b/software/firmware/project_oracle_base/include/pio/same54p19a.h deleted file mode 100644 index 93afbcc..0000000 --- a/software/firmware/project_oracle_base/include/pio/same54p19a.h +++ /dev/null @@ -1,3010 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAME54P19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54P19A_PIO_ -#define _SAME54P19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ -#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ -#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ -#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ -#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ -#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ -#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ -#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ -#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ -#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ -#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ -#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ -#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ -#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ -#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ -#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ -#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ -#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ -#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ -#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ -#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ -#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ -#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ -#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ -#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ -#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ -#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ -#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ -#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ -#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ -#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ -#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ -#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ -#define MUX_PD00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ -#define MUX_PD01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ -#define MUX_PD08A_EIC_EXTINT3 _L_(0) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ -#define MUX_PC04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ -#define MUX_PD09A_EIC_EXTINT4 _L_(0) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ -#define MUX_PD10A_EIC_EXTINT5 _L_(0) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ -#define MUX_PC22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ -#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ -#define MUX_PD11A_EIC_EXTINT6 _L_(0) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ -#define MUX_PC23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ -#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ -#define MUX_PD12A_EIC_EXTINT7 _L_(0) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ -#define MUX_PD20A_EIC_EXTINT10 _L_(0) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ -#define MUX_PD21A_EIC_EXTINT11 _L_(0) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ -#define MUX_PB26A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ -#define MUX_PB27A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ -#define MUX_PB28A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ -#define MUX_PC30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ -#define MUX_PB29A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ -#define MUX_PC31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ -#define MUX_PC22C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ -#define MUX_PC23C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ -#define MUX_PD20C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ -#define MUX_PD21C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ -#define MUX_PB26C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ -#define MUX_PB27C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ -#define MUX_PB28C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ -#define MUX_PB29C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ -#define MUX_PC23D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ -#define MUX_PC22D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ -#define MUX_PD20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ -#define MUX_PD21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ -#define MUX_PC04F_TCC0_WO0 _L_(5) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ -#define MUX_PD08F_TCC0_WO1 _L_(5) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ -#define MUX_PD09F_TCC0_WO2 _L_(5) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ -#define MUX_PD10F_TCC0_WO3 _L_(5) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ -#define MUX_PD11F_TCC0_WO4 _L_(5) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ -#define MUX_PD12F_TCC0_WO5 _L_(5) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ -#define MUX_PC22F_TCC0_WO6 _L_(5) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ -#define MUX_PC23F_TCC0_WO7 _L_(5) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ -#define MUX_PD20F_TCC1_WO0 _L_(5) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ -#define MUX_PD21F_TCC1_WO1 _L_(5) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ -#define MUX_PB26F_TCC1_WO2 _L_(5) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ -#define MUX_PB27F_TCC1_WO3 _L_(5) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ -#define MUX_PB28F_TCC1_WO4 _L_(5) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ -#define MUX_PB29F_TCC1_WO5 _L_(5) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ -#define MUX_PA23I_CAN0_RX _L_(8) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) -#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ -#define MUX_PA25I_CAN0_RX _L_(8) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) -#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ -#define MUX_PA22I_CAN0_TX _L_(8) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) -#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ -#define MUX_PA24I_CAN0_TX _L_(8) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ -#define MUX_PB13H_CAN1_RX _L_(7) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) -#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ -#define MUX_PB15H_CAN1_RX _L_(7) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) -#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ -#define MUX_PB12H_CAN1_TX _L_(7) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) -#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ -#define MUX_PB14H_CAN1_TX _L_(7) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ -#define MUX_PC21L_GMAC_GCOL _L_(11) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) -#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ -#define MUX_PA16L_GMAC_GCRS _L_(11) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) -#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ -#define MUX_PA20L_GMAC_GMDC _L_(11) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) -#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ -#define MUX_PB14L_GMAC_GMDC _L_(11) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) -#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ -#define MUX_PC11L_GMAC_GMDC _L_(11) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) -#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ -#define MUX_PC22L_GMAC_GMDC _L_(11) -#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) -#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) -#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ -#define MUX_PA21L_GMAC_GMDIO _L_(11) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) -#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ -#define MUX_PB15L_GMAC_GMDIO _L_(11) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) -#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ -#define MUX_PC12L_GMAC_GMDIO _L_(11) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) -#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ -#define MUX_PC23L_GMAC_GMDIO _L_(11) -#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) -#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) -#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ -#define MUX_PA13L_GMAC_GRX0 _L_(11) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) -#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ -#define MUX_PA12L_GMAC_GRX1 _L_(11) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) -#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ -#define MUX_PC15L_GMAC_GRX2 _L_(11) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) -#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ -#define MUX_PC14L_GMAC_GRX3 _L_(11) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) -#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ -#define MUX_PC18L_GMAC_GRXCK _L_(11) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) -#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ -#define MUX_PC20L_GMAC_GRXDV _L_(11) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) -#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ -#define MUX_PA15L_GMAC_GRXER _L_(11) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) -#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ -#define MUX_PA18L_GMAC_GTX0 _L_(11) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) -#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ -#define MUX_PA19L_GMAC_GTX1 _L_(11) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) -#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ -#define MUX_PC16L_GMAC_GTX2 _L_(11) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) -#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ -#define MUX_PC17L_GMAC_GTX3 _L_(11) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) -#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ -#define MUX_PA14L_GMAC_GTXCK _L_(11) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) -#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ -#define MUX_PA17L_GMAC_GTXEN _L_(11) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) -#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ -#define MUX_PC19L_GMAC_GTXER _L_(11) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ -#define MUX_PB27D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ -#define MUX_PB26D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ -#define MUX_PB28D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ -#define MUX_PB29D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ -#define MUX_PD09D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ -#define MUX_PC04C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ -#define MUX_PD08D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ -#define MUX_PD10D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ -#define MUX_PD11D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ -#define MUX_PD08C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ -#define MUX_PD09C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ -#define MUX_PD10C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ -#define MUX_PD11C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ -#define MUX_PC30B_ADC1_AIN12 _L_(1) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) -#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ -#define MUX_PC31B_ADC1_AIN13 _L_(1) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) -#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ -#define MUX_PD00B_ADC1_AIN14 _L_(1) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) -#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ -#define MUX_PD01B_ADC1_AIN15 _L_(1) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ -#define MUX_PB29J_I2S_MCK1 _L_(9) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ -#define MUX_PB28J_I2S_SCK1 _L_(9) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ -#define MUX_PD20I_SDHC1_SDCD _L_(8) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) -#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ -#define MUX_PD21I_SDHC1_SDWP _L_(8) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAME54P19A_PIO_ */ diff --git a/software/firmware/project_oracle_base/include/pio/same54p20a.h b/software/firmware/project_oracle_base/include/pio/same54p20a.h deleted file mode 100644 index cc04680..0000000 --- a/software/firmware/project_oracle_base/include/pio/same54p20a.h +++ /dev/null @@ -1,3010 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAME54P20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54P20A_PIO_ -#define _SAME54P20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ -#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ -#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ -#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ -#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ -#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ -#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ -#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ -#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ -#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ -#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ -#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ -#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ -#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ -#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ -#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ -#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ -#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ -#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ -#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ -#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ -#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ -#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ -#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ -#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ -#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ -#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ -#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ -#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ -#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ -#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ -#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ -#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ -#define MUX_PD00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ -#define MUX_PD01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ -#define MUX_PD08A_EIC_EXTINT3 _L_(0) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ -#define MUX_PC04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ -#define MUX_PD09A_EIC_EXTINT4 _L_(0) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ -#define MUX_PD10A_EIC_EXTINT5 _L_(0) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ -#define MUX_PC22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ -#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ -#define MUX_PD11A_EIC_EXTINT6 _L_(0) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ -#define MUX_PC23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ -#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ -#define MUX_PD12A_EIC_EXTINT7 _L_(0) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ -#define MUX_PD20A_EIC_EXTINT10 _L_(0) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ -#define MUX_PD21A_EIC_EXTINT11 _L_(0) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ -#define MUX_PB26A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ -#define MUX_PB27A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ -#define MUX_PB28A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ -#define MUX_PC30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ -#define MUX_PB29A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ -#define MUX_PC31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ -#define MUX_PC22C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ -#define MUX_PC23C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ -#define MUX_PD20C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ -#define MUX_PD21C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ -#define MUX_PB26C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ -#define MUX_PB27C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ -#define MUX_PB28C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ -#define MUX_PB29C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ -#define MUX_PC23D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ -#define MUX_PC22D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ -#define MUX_PD20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ -#define MUX_PD21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ -#define MUX_PC04F_TCC0_WO0 _L_(5) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ -#define MUX_PD08F_TCC0_WO1 _L_(5) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ -#define MUX_PD09F_TCC0_WO2 _L_(5) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ -#define MUX_PD10F_TCC0_WO3 _L_(5) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ -#define MUX_PD11F_TCC0_WO4 _L_(5) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ -#define MUX_PD12F_TCC0_WO5 _L_(5) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ -#define MUX_PC22F_TCC0_WO6 _L_(5) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ -#define MUX_PC23F_TCC0_WO7 _L_(5) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ -#define MUX_PD20F_TCC1_WO0 _L_(5) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ -#define MUX_PD21F_TCC1_WO1 _L_(5) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ -#define MUX_PB26F_TCC1_WO2 _L_(5) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ -#define MUX_PB27F_TCC1_WO3 _L_(5) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ -#define MUX_PB28F_TCC1_WO4 _L_(5) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ -#define MUX_PB29F_TCC1_WO5 _L_(5) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ -#define MUX_PA23I_CAN0_RX _L_(8) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) -#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ -#define MUX_PA25I_CAN0_RX _L_(8) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) -#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ -#define MUX_PA22I_CAN0_TX _L_(8) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) -#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ -#define MUX_PA24I_CAN0_TX _L_(8) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ -#define MUX_PB13H_CAN1_RX _L_(7) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) -#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ -#define MUX_PB15H_CAN1_RX _L_(7) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) -#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ -#define MUX_PB12H_CAN1_TX _L_(7) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) -#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ -#define MUX_PB14H_CAN1_TX _L_(7) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ -#define MUX_PC21L_GMAC_GCOL _L_(11) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) -#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ -#define MUX_PA16L_GMAC_GCRS _L_(11) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) -#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ -#define MUX_PA20L_GMAC_GMDC _L_(11) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) -#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ -#define MUX_PB14L_GMAC_GMDC _L_(11) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) -#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ -#define MUX_PC11L_GMAC_GMDC _L_(11) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) -#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ -#define MUX_PC22L_GMAC_GMDC _L_(11) -#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) -#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) -#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ -#define MUX_PA21L_GMAC_GMDIO _L_(11) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) -#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ -#define MUX_PB15L_GMAC_GMDIO _L_(11) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) -#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ -#define MUX_PC12L_GMAC_GMDIO _L_(11) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) -#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ -#define MUX_PC23L_GMAC_GMDIO _L_(11) -#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) -#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) -#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ -#define MUX_PA13L_GMAC_GRX0 _L_(11) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) -#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ -#define MUX_PA12L_GMAC_GRX1 _L_(11) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) -#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ -#define MUX_PC15L_GMAC_GRX2 _L_(11) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) -#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ -#define MUX_PC14L_GMAC_GRX3 _L_(11) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) -#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ -#define MUX_PC18L_GMAC_GRXCK _L_(11) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) -#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ -#define MUX_PC20L_GMAC_GRXDV _L_(11) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) -#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ -#define MUX_PA15L_GMAC_GRXER _L_(11) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) -#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ -#define MUX_PA18L_GMAC_GTX0 _L_(11) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) -#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ -#define MUX_PA19L_GMAC_GTX1 _L_(11) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) -#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ -#define MUX_PC16L_GMAC_GTX2 _L_(11) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) -#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ -#define MUX_PC17L_GMAC_GTX3 _L_(11) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) -#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ -#define MUX_PA14L_GMAC_GTXCK _L_(11) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) -#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ -#define MUX_PA17L_GMAC_GTXEN _L_(11) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) -#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ -#define MUX_PC19L_GMAC_GTXER _L_(11) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ -#define MUX_PB27D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ -#define MUX_PB26D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ -#define MUX_PB28D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ -#define MUX_PB29D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ -#define MUX_PD09D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ -#define MUX_PC04C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ -#define MUX_PD08D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ -#define MUX_PD10D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ -#define MUX_PD11D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ -#define MUX_PD08C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ -#define MUX_PD09C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ -#define MUX_PD10C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ -#define MUX_PD11C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ -#define MUX_PC30B_ADC1_AIN12 _L_(1) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) -#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ -#define MUX_PC31B_ADC1_AIN13 _L_(1) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) -#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ -#define MUX_PD00B_ADC1_AIN14 _L_(1) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) -#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ -#define MUX_PD01B_ADC1_AIN15 _L_(1) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ -#define MUX_PB29J_I2S_MCK1 _L_(9) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ -#define MUX_PB28J_I2S_SCK1 _L_(9) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ -#define MUX_PD20I_SDHC1_SDCD _L_(8) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) -#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ -#define MUX_PD21I_SDHC1_SDWP _L_(8) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAME54P20A_PIO_ */ diff --git a/software/firmware/project_oracle_base/include/sam.h b/software/firmware/project_oracle_base/include/sam.h deleted file mode 100644 index 3fa3b5f..0000000 --- a/software/firmware/project_oracle_base/include/sam.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * \file - * - * \brief Top level header file - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _SAM_ -#define _SAM_ - -#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) -#include "same54n19a.h" -#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) -#include "same54n20a.h" -#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) -#include "same54p19a.h" -#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) -#include "same54p20a.h" -#else -#error Library does not support the specified device -#endif - -#endif /* _SAM_ */ diff --git a/software/firmware/project_oracle_base/include/same54.h b/software/firmware/project_oracle_base/include/same54.h deleted file mode 100644 index 7da756e..0000000 --- a/software/firmware/project_oracle_base/include/same54.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAME54 - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54_ -#define _SAME54_ - -/** - * \defgroup SAME54_definitions SAME54 Device Definitions - * \brief SAME54 CMSIS Definitions. - */ - -#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) - #include "same54n19a.h" -#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) - #include "same54n20a.h" -#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) - #include "same54p19a.h" -#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) - #include "same54p20a.h" -#else - #error Library does not support the specified device. -#endif - -#endif /* _SAME54_ */ diff --git a/software/firmware/project_oracle_base/include/same54n19a.h b/software/firmware/project_oracle_base/include/same54n19a.h deleted file mode 100644 index cb183bb..0000000 --- a/software/firmware/project_oracle_base/include/same54n19a.h +++ /dev/null @@ -1,1085 +0,0 @@ -/** - * \file - * - * \brief Header file for SAME54N19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54N19A_ -#define _SAME54N19A_ - -/** - * \ingroup SAME54_definitions - * \addtogroup SAME54N19A_definitions SAME54N19A definitions - * This file defines all structures and symbols for SAME54N19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -/** \defgroup SAME54N19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAME54N19A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAME54N19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAME54N19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL) IRQ 0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL) IRQ 1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL) IRQ 2 */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL) IRQ 3 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL) IRQ 4 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAME54N19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC) IRQ 0 */ - SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC) IRQ 1 */ - WDT_IRQn = 10, /**< 10 SAME54N19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAME54N19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC) IRQ 0 */ - EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC) IRQ 1 */ - EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC) IRQ 2 */ - EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC) IRQ 3 */ - EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC) IRQ 4 */ - EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC) IRQ 5 */ - EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC) IRQ 6 */ - EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC) IRQ 7 */ - EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC) IRQ 8 */ - EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC) IRQ 9 */ - EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC) IRQ 10 */ - EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC) IRQ 11 */ - EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC) IRQ 12 */ - EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC) IRQ 13 */ - EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC) IRQ 14 */ - EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC) IRQ 15 */ - FREQM_IRQn = 28, /**< 28 SAME54N19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ - DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 4 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS) IRQ 0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS) IRQ 1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS) IRQ 2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS) IRQ 3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS) IRQ 4 */ - PAC_IRQn = 41, /**< 41 SAME54N19A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAME54N19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ - CAN0_IRQn = 78, /**< 78 SAME54N19A Control Area Network 0 (CAN0) */ - CAN1_IRQn = 79, /**< 79 SAME54N19A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB) IRQ 0 */ - USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB) IRQ 1 */ - USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB) IRQ 2 */ - USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB) IRQ 3 */ - GMAC_IRQn = 84, /**< 84 SAME54N19A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 0 */ - TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 1 */ - TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 2 */ - TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 3 */ - TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 4 */ - TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 5 */ - TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 6 */ - TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 0 */ - TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 1 */ - TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 2 */ - TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 3 */ - TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 4 */ - TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 0 */ - TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 1 */ - TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 2 */ - TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 3 */ - TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 0 */ - TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 1 */ - TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 2 */ - TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 0 */ - TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 1 */ - TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 2 */ - TC0_IRQn = 107, /**< 107 SAME54N19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAME54N19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAME54N19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAME54N19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAME54N19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAME54N19A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAME54N19A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAME54N19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC) IRQ 0 */ - PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC) IRQ 1 */ - PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC) IRQ 2 */ - ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 0 */ - ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 1 */ - ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 0 */ - ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 1 */ - AC_IRQn = 122, /**< 122 SAME54N19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 0 */ - DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 1 */ - DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 2 */ - DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 3 */ - DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 4 */ - I2S_IRQn = 128, /**< 128 SAME54N19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAME54N19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAME54N19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAME54N19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAME54N19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAME54N19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAME54N19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAME54N19A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAME54N19A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ - void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC */ - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_same54.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */ -/* ************************************************************************** */ -/** \defgroup SAME54N19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -/** \defgroup SAME54N19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/gmac.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -/** \defgroup SAME54N19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ -#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ -#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -/** \defgroup SAME54N19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ -#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ -#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ -#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ -#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ -#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ -#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -/** \defgroup SAME54N19A_port PORT Definitions */ -/*@{*/ - -#include "pio/same54n19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x61840303) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAME54N19A_H */ diff --git a/software/firmware/project_oracle_base/include/same54n20a.h b/software/firmware/project_oracle_base/include/same54n20a.h deleted file mode 100644 index 4d4e23d..0000000 --- a/software/firmware/project_oracle_base/include/same54n20a.h +++ /dev/null @@ -1,1085 +0,0 @@ -/** - * \file - * - * \brief Header file for SAME54N20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54N20A_ -#define _SAME54N20A_ - -/** - * \ingroup SAME54_definitions - * \addtogroup SAME54N20A_definitions SAME54N20A definitions - * This file defines all structures and symbols for SAME54N20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -/** \defgroup SAME54N20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAME54N20A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAME54N20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAME54N20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54N20A Oscillators Control (OSCCTRL) IRQ 0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54N20A Oscillators Control (OSCCTRL) IRQ 1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54N20A Oscillators Control (OSCCTRL) IRQ 2 */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54N20A Oscillators Control (OSCCTRL) IRQ 3 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54N20A Oscillators Control (OSCCTRL) IRQ 4 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAME54N20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54N20A Supply Controller (SUPC) IRQ 0 */ - SUPC_1_IRQn = 9, /**< 9 SAME54N20A Supply Controller (SUPC) IRQ 1 */ - WDT_IRQn = 10, /**< 10 SAME54N20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAME54N20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54N20A External Interrupt Controller (EIC) IRQ 0 */ - EIC_1_IRQn = 13, /**< 13 SAME54N20A External Interrupt Controller (EIC) IRQ 1 */ - EIC_2_IRQn = 14, /**< 14 SAME54N20A External Interrupt Controller (EIC) IRQ 2 */ - EIC_3_IRQn = 15, /**< 15 SAME54N20A External Interrupt Controller (EIC) IRQ 3 */ - EIC_4_IRQn = 16, /**< 16 SAME54N20A External Interrupt Controller (EIC) IRQ 4 */ - EIC_5_IRQn = 17, /**< 17 SAME54N20A External Interrupt Controller (EIC) IRQ 5 */ - EIC_6_IRQn = 18, /**< 18 SAME54N20A External Interrupt Controller (EIC) IRQ 6 */ - EIC_7_IRQn = 19, /**< 19 SAME54N20A External Interrupt Controller (EIC) IRQ 7 */ - EIC_8_IRQn = 20, /**< 20 SAME54N20A External Interrupt Controller (EIC) IRQ 8 */ - EIC_9_IRQn = 21, /**< 21 SAME54N20A External Interrupt Controller (EIC) IRQ 9 */ - EIC_10_IRQn = 22, /**< 22 SAME54N20A External Interrupt Controller (EIC) IRQ 10 */ - EIC_11_IRQn = 23, /**< 23 SAME54N20A External Interrupt Controller (EIC) IRQ 11 */ - EIC_12_IRQn = 24, /**< 24 SAME54N20A External Interrupt Controller (EIC) IRQ 12 */ - EIC_13_IRQn = 25, /**< 25 SAME54N20A External Interrupt Controller (EIC) IRQ 13 */ - EIC_14_IRQn = 26, /**< 26 SAME54N20A External Interrupt Controller (EIC) IRQ 14 */ - EIC_15_IRQn = 27, /**< 27 SAME54N20A External Interrupt Controller (EIC) IRQ 15 */ - FREQM_IRQn = 28, /**< 28 SAME54N20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ - DMAC_0_IRQn = 31, /**< 31 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 4 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54N20A Event System Interface (EVSYS) IRQ 0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54N20A Event System Interface (EVSYS) IRQ 1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54N20A Event System Interface (EVSYS) IRQ 2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54N20A Event System Interface (EVSYS) IRQ 3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54N20A Event System Interface (EVSYS) IRQ 4 */ - PAC_IRQn = 41, /**< 41 SAME54N20A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAME54N20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ - CAN0_IRQn = 78, /**< 78 SAME54N20A Control Area Network 0 (CAN0) */ - CAN1_IRQn = 79, /**< 79 SAME54N20A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54N20A Universal Serial Bus (USB) IRQ 0 */ - USB_1_IRQn = 81, /**< 81 SAME54N20A Universal Serial Bus (USB) IRQ 1 */ - USB_2_IRQn = 82, /**< 82 SAME54N20A Universal Serial Bus (USB) IRQ 2 */ - USB_3_IRQn = 83, /**< 83 SAME54N20A Universal Serial Bus (USB) IRQ 3 */ - GMAC_IRQn = 84, /**< 84 SAME54N20A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 0 */ - TCC0_1_IRQn = 86, /**< 86 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 1 */ - TCC0_2_IRQn = 87, /**< 87 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 2 */ - TCC0_3_IRQn = 88, /**< 88 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 3 */ - TCC0_4_IRQn = 89, /**< 89 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 4 */ - TCC0_5_IRQn = 90, /**< 90 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 5 */ - TCC0_6_IRQn = 91, /**< 91 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 6 */ - TCC1_0_IRQn = 92, /**< 92 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 0 */ - TCC1_1_IRQn = 93, /**< 93 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 1 */ - TCC1_2_IRQn = 94, /**< 94 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 2 */ - TCC1_3_IRQn = 95, /**< 95 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 3 */ - TCC1_4_IRQn = 96, /**< 96 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 4 */ - TCC2_0_IRQn = 97, /**< 97 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 0 */ - TCC2_1_IRQn = 98, /**< 98 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 1 */ - TCC2_2_IRQn = 99, /**< 99 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 2 */ - TCC2_3_IRQn = 100, /**< 100 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 3 */ - TCC3_0_IRQn = 101, /**< 101 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 0 */ - TCC3_1_IRQn = 102, /**< 102 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 1 */ - TCC3_2_IRQn = 103, /**< 103 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 2 */ - TCC4_0_IRQn = 104, /**< 104 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 0 */ - TCC4_1_IRQn = 105, /**< 105 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 1 */ - TCC4_2_IRQn = 106, /**< 106 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 2 */ - TC0_IRQn = 107, /**< 107 SAME54N20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAME54N20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAME54N20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAME54N20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAME54N20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAME54N20A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAME54N20A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAME54N20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54N20A Quadrature Decodeur (PDEC) IRQ 0 */ - PDEC_1_IRQn = 116, /**< 116 SAME54N20A Quadrature Decodeur (PDEC) IRQ 1 */ - PDEC_2_IRQn = 117, /**< 117 SAME54N20A Quadrature Decodeur (PDEC) IRQ 2 */ - ADC0_0_IRQn = 118, /**< 118 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 0 */ - ADC0_1_IRQn = 119, /**< 119 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 1 */ - ADC1_0_IRQn = 120, /**< 120 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 0 */ - ADC1_1_IRQn = 121, /**< 121 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 1 */ - AC_IRQn = 122, /**< 122 SAME54N20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 0 */ - DAC_1_IRQn = 124, /**< 124 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 1 */ - DAC_2_IRQn = 125, /**< 125 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 2 */ - DAC_3_IRQn = 126, /**< 126 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 3 */ - DAC_4_IRQn = 127, /**< 127 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 4 */ - I2S_IRQn = 128, /**< 128 SAME54N20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAME54N20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAME54N20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAME54N20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAME54N20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAME54N20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAME54N20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAME54N20A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAME54N20A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ - void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC */ - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_same54.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */ -/* ************************************************************************** */ -/** \defgroup SAME54N20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -/** \defgroup SAME54N20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/gmac.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -/** \defgroup SAME54N20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ -#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ -#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -/** \defgroup SAME54N20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ -#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ -#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ -#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ -#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ -#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ -#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -/** \defgroup SAME54N20A_port PORT Definitions */ -/*@{*/ - -#include "pio/same54n20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x61840302) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAME54N20A_H */ diff --git a/software/firmware/project_oracle_base/include/same54p19a.h b/software/firmware/project_oracle_base/include/same54p19a.h deleted file mode 100644 index ed3ae04..0000000 --- a/software/firmware/project_oracle_base/include/same54p19a.h +++ /dev/null @@ -1,1085 +0,0 @@ -/** - * \file - * - * \brief Header file for SAME54P19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54P19A_ -#define _SAME54P19A_ - -/** - * \ingroup SAME54_definitions - * \addtogroup SAME54P19A_definitions SAME54P19A definitions - * This file defines all structures and symbols for SAME54P19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -/** \defgroup SAME54P19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAME54P19A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAME54P19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAME54P19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54P19A Oscillators Control (OSCCTRL) IRQ 0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54P19A Oscillators Control (OSCCTRL) IRQ 1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54P19A Oscillators Control (OSCCTRL) IRQ 2 */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54P19A Oscillators Control (OSCCTRL) IRQ 3 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54P19A Oscillators Control (OSCCTRL) IRQ 4 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAME54P19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54P19A Supply Controller (SUPC) IRQ 0 */ - SUPC_1_IRQn = 9, /**< 9 SAME54P19A Supply Controller (SUPC) IRQ 1 */ - WDT_IRQn = 10, /**< 10 SAME54P19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAME54P19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54P19A External Interrupt Controller (EIC) IRQ 0 */ - EIC_1_IRQn = 13, /**< 13 SAME54P19A External Interrupt Controller (EIC) IRQ 1 */ - EIC_2_IRQn = 14, /**< 14 SAME54P19A External Interrupt Controller (EIC) IRQ 2 */ - EIC_3_IRQn = 15, /**< 15 SAME54P19A External Interrupt Controller (EIC) IRQ 3 */ - EIC_4_IRQn = 16, /**< 16 SAME54P19A External Interrupt Controller (EIC) IRQ 4 */ - EIC_5_IRQn = 17, /**< 17 SAME54P19A External Interrupt Controller (EIC) IRQ 5 */ - EIC_6_IRQn = 18, /**< 18 SAME54P19A External Interrupt Controller (EIC) IRQ 6 */ - EIC_7_IRQn = 19, /**< 19 SAME54P19A External Interrupt Controller (EIC) IRQ 7 */ - EIC_8_IRQn = 20, /**< 20 SAME54P19A External Interrupt Controller (EIC) IRQ 8 */ - EIC_9_IRQn = 21, /**< 21 SAME54P19A External Interrupt Controller (EIC) IRQ 9 */ - EIC_10_IRQn = 22, /**< 22 SAME54P19A External Interrupt Controller (EIC) IRQ 10 */ - EIC_11_IRQn = 23, /**< 23 SAME54P19A External Interrupt Controller (EIC) IRQ 11 */ - EIC_12_IRQn = 24, /**< 24 SAME54P19A External Interrupt Controller (EIC) IRQ 12 */ - EIC_13_IRQn = 25, /**< 25 SAME54P19A External Interrupt Controller (EIC) IRQ 13 */ - EIC_14_IRQn = 26, /**< 26 SAME54P19A External Interrupt Controller (EIC) IRQ 14 */ - EIC_15_IRQn = 27, /**< 27 SAME54P19A External Interrupt Controller (EIC) IRQ 15 */ - FREQM_IRQn = 28, /**< 28 SAME54P19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ - DMAC_0_IRQn = 31, /**< 31 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 4 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54P19A Event System Interface (EVSYS) IRQ 0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54P19A Event System Interface (EVSYS) IRQ 1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54P19A Event System Interface (EVSYS) IRQ 2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54P19A Event System Interface (EVSYS) IRQ 3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54P19A Event System Interface (EVSYS) IRQ 4 */ - PAC_IRQn = 41, /**< 41 SAME54P19A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAME54P19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ - CAN0_IRQn = 78, /**< 78 SAME54P19A Control Area Network 0 (CAN0) */ - CAN1_IRQn = 79, /**< 79 SAME54P19A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54P19A Universal Serial Bus (USB) IRQ 0 */ - USB_1_IRQn = 81, /**< 81 SAME54P19A Universal Serial Bus (USB) IRQ 1 */ - USB_2_IRQn = 82, /**< 82 SAME54P19A Universal Serial Bus (USB) IRQ 2 */ - USB_3_IRQn = 83, /**< 83 SAME54P19A Universal Serial Bus (USB) IRQ 3 */ - GMAC_IRQn = 84, /**< 84 SAME54P19A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 0 */ - TCC0_1_IRQn = 86, /**< 86 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 1 */ - TCC0_2_IRQn = 87, /**< 87 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 2 */ - TCC0_3_IRQn = 88, /**< 88 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 3 */ - TCC0_4_IRQn = 89, /**< 89 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 4 */ - TCC0_5_IRQn = 90, /**< 90 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 5 */ - TCC0_6_IRQn = 91, /**< 91 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 6 */ - TCC1_0_IRQn = 92, /**< 92 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 0 */ - TCC1_1_IRQn = 93, /**< 93 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 1 */ - TCC1_2_IRQn = 94, /**< 94 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 2 */ - TCC1_3_IRQn = 95, /**< 95 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 3 */ - TCC1_4_IRQn = 96, /**< 96 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 4 */ - TCC2_0_IRQn = 97, /**< 97 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 0 */ - TCC2_1_IRQn = 98, /**< 98 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 1 */ - TCC2_2_IRQn = 99, /**< 99 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 2 */ - TCC2_3_IRQn = 100, /**< 100 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 3 */ - TCC3_0_IRQn = 101, /**< 101 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 0 */ - TCC3_1_IRQn = 102, /**< 102 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 1 */ - TCC3_2_IRQn = 103, /**< 103 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 2 */ - TCC4_0_IRQn = 104, /**< 104 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 0 */ - TCC4_1_IRQn = 105, /**< 105 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 1 */ - TCC4_2_IRQn = 106, /**< 106 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 2 */ - TC0_IRQn = 107, /**< 107 SAME54P19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAME54P19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAME54P19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAME54P19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAME54P19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAME54P19A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAME54P19A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAME54P19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54P19A Quadrature Decodeur (PDEC) IRQ 0 */ - PDEC_1_IRQn = 116, /**< 116 SAME54P19A Quadrature Decodeur (PDEC) IRQ 1 */ - PDEC_2_IRQn = 117, /**< 117 SAME54P19A Quadrature Decodeur (PDEC) IRQ 2 */ - ADC0_0_IRQn = 118, /**< 118 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 0 */ - ADC0_1_IRQn = 119, /**< 119 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 1 */ - ADC1_0_IRQn = 120, /**< 120 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 0 */ - ADC1_1_IRQn = 121, /**< 121 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 1 */ - AC_IRQn = 122, /**< 122 SAME54P19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 0 */ - DAC_1_IRQn = 124, /**< 124 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 1 */ - DAC_2_IRQn = 125, /**< 125 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 2 */ - DAC_3_IRQn = 126, /**< 126 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 3 */ - DAC_4_IRQn = 127, /**< 127 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 4 */ - I2S_IRQn = 128, /**< 128 SAME54P19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAME54P19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAME54P19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAME54P19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAME54P19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAME54P19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAME54P19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAME54P19A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAME54P19A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ - void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC */ - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_same54.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */ -/* ************************************************************************** */ -/** \defgroup SAME54P19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -/** \defgroup SAME54P19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/gmac.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -/** \defgroup SAME54P19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ -#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ -#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -/** \defgroup SAME54P19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ -#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ -#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ -#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ -#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ -#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ -#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -/** \defgroup SAME54P19A_port PORT Definitions */ -/*@{*/ - -#include "pio/same54p19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x61840301) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 4 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAME54P19A_H */ diff --git a/software/firmware/project_oracle_base/include/same54p20a.h b/software/firmware/project_oracle_base/include/same54p20a.h deleted file mode 100644 index 2446095..0000000 --- a/software/firmware/project_oracle_base/include/same54p20a.h +++ /dev/null @@ -1,1085 +0,0 @@ -/** - * \file - * - * \brief Header file for SAME54P20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAME54P20A_ -#define _SAME54P20A_ - -/** - * \ingroup SAME54_definitions - * \addtogroup SAME54P20A_definitions SAME54P20A definitions - * This file defines all structures and symbols for SAME54P20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -/** \defgroup SAME54P20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAME54P20A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAME54P20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAME54P20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54P20A Oscillators Control (OSCCTRL) IRQ 0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54P20A Oscillators Control (OSCCTRL) IRQ 1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54P20A Oscillators Control (OSCCTRL) IRQ 2 */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54P20A Oscillators Control (OSCCTRL) IRQ 3 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54P20A Oscillators Control (OSCCTRL) IRQ 4 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAME54P20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54P20A Supply Controller (SUPC) IRQ 0 */ - SUPC_1_IRQn = 9, /**< 9 SAME54P20A Supply Controller (SUPC) IRQ 1 */ - WDT_IRQn = 10, /**< 10 SAME54P20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAME54P20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54P20A External Interrupt Controller (EIC) IRQ 0 */ - EIC_1_IRQn = 13, /**< 13 SAME54P20A External Interrupt Controller (EIC) IRQ 1 */ - EIC_2_IRQn = 14, /**< 14 SAME54P20A External Interrupt Controller (EIC) IRQ 2 */ - EIC_3_IRQn = 15, /**< 15 SAME54P20A External Interrupt Controller (EIC) IRQ 3 */ - EIC_4_IRQn = 16, /**< 16 SAME54P20A External Interrupt Controller (EIC) IRQ 4 */ - EIC_5_IRQn = 17, /**< 17 SAME54P20A External Interrupt Controller (EIC) IRQ 5 */ - EIC_6_IRQn = 18, /**< 18 SAME54P20A External Interrupt Controller (EIC) IRQ 6 */ - EIC_7_IRQn = 19, /**< 19 SAME54P20A External Interrupt Controller (EIC) IRQ 7 */ - EIC_8_IRQn = 20, /**< 20 SAME54P20A External Interrupt Controller (EIC) IRQ 8 */ - EIC_9_IRQn = 21, /**< 21 SAME54P20A External Interrupt Controller (EIC) IRQ 9 */ - EIC_10_IRQn = 22, /**< 22 SAME54P20A External Interrupt Controller (EIC) IRQ 10 */ - EIC_11_IRQn = 23, /**< 23 SAME54P20A External Interrupt Controller (EIC) IRQ 11 */ - EIC_12_IRQn = 24, /**< 24 SAME54P20A External Interrupt Controller (EIC) IRQ 12 */ - EIC_13_IRQn = 25, /**< 25 SAME54P20A External Interrupt Controller (EIC) IRQ 13 */ - EIC_14_IRQn = 26, /**< 26 SAME54P20A External Interrupt Controller (EIC) IRQ 14 */ - EIC_15_IRQn = 27, /**< 27 SAME54P20A External Interrupt Controller (EIC) IRQ 15 */ - FREQM_IRQn = 28, /**< 28 SAME54P20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ - DMAC_0_IRQn = 31, /**< 31 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 4 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54P20A Event System Interface (EVSYS) IRQ 0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54P20A Event System Interface (EVSYS) IRQ 1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54P20A Event System Interface (EVSYS) IRQ 2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54P20A Event System Interface (EVSYS) IRQ 3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54P20A Event System Interface (EVSYS) IRQ 4 */ - PAC_IRQn = 41, /**< 41 SAME54P20A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAME54P20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ - CAN0_IRQn = 78, /**< 78 SAME54P20A Control Area Network 0 (CAN0) */ - CAN1_IRQn = 79, /**< 79 SAME54P20A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54P20A Universal Serial Bus (USB) IRQ 0 */ - USB_1_IRQn = 81, /**< 81 SAME54P20A Universal Serial Bus (USB) IRQ 1 */ - USB_2_IRQn = 82, /**< 82 SAME54P20A Universal Serial Bus (USB) IRQ 2 */ - USB_3_IRQn = 83, /**< 83 SAME54P20A Universal Serial Bus (USB) IRQ 3 */ - GMAC_IRQn = 84, /**< 84 SAME54P20A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 0 */ - TCC0_1_IRQn = 86, /**< 86 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 1 */ - TCC0_2_IRQn = 87, /**< 87 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 2 */ - TCC0_3_IRQn = 88, /**< 88 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 3 */ - TCC0_4_IRQn = 89, /**< 89 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 4 */ - TCC0_5_IRQn = 90, /**< 90 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 5 */ - TCC0_6_IRQn = 91, /**< 91 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 6 */ - TCC1_0_IRQn = 92, /**< 92 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 0 */ - TCC1_1_IRQn = 93, /**< 93 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 1 */ - TCC1_2_IRQn = 94, /**< 94 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 2 */ - TCC1_3_IRQn = 95, /**< 95 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 3 */ - TCC1_4_IRQn = 96, /**< 96 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 4 */ - TCC2_0_IRQn = 97, /**< 97 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 0 */ - TCC2_1_IRQn = 98, /**< 98 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 1 */ - TCC2_2_IRQn = 99, /**< 99 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 2 */ - TCC2_3_IRQn = 100, /**< 100 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 3 */ - TCC3_0_IRQn = 101, /**< 101 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 0 */ - TCC3_1_IRQn = 102, /**< 102 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 1 */ - TCC3_2_IRQn = 103, /**< 103 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 2 */ - TCC4_0_IRQn = 104, /**< 104 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 0 */ - TCC4_1_IRQn = 105, /**< 105 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 1 */ - TCC4_2_IRQn = 106, /**< 106 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 2 */ - TC0_IRQn = 107, /**< 107 SAME54P20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAME54P20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAME54P20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAME54P20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAME54P20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAME54P20A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAME54P20A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAME54P20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54P20A Quadrature Decodeur (PDEC) IRQ 0 */ - PDEC_1_IRQn = 116, /**< 116 SAME54P20A Quadrature Decodeur (PDEC) IRQ 1 */ - PDEC_2_IRQn = 117, /**< 117 SAME54P20A Quadrature Decodeur (PDEC) IRQ 2 */ - ADC0_0_IRQn = 118, /**< 118 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 0 */ - ADC0_1_IRQn = 119, /**< 119 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 1 */ - ADC1_0_IRQn = 120, /**< 120 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 0 */ - ADC1_1_IRQn = 121, /**< 121 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 1 */ - AC_IRQn = 122, /**< 122 SAME54P20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 0 */ - DAC_1_IRQn = 124, /**< 124 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 1 */ - DAC_2_IRQn = 125, /**< 125 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 2 */ - DAC_3_IRQn = 126, /**< 126 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 3 */ - DAC_4_IRQn = 127, /**< 127 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 4 */ - I2S_IRQn = 128, /**< 128 SAME54P20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAME54P20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAME54P20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAME54P20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAME54P20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAME54P20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAME54P20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAME54P20A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAME54P20A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ - void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC */ - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_same54.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */ -/* ************************************************************************** */ -/** \defgroup SAME54P20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -/** \defgroup SAME54P20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/gmac.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -/** \defgroup SAME54P20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ -#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ -#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -/** \defgroup SAME54P20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ -#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ -#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ -#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ -#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ -#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ -#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -/** \defgroup SAME54P20A_port PORT Definitions */ -/*@{*/ - -#include "pio/same54p20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x61840300) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 4 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAME54P20A_H */ diff --git a/software/firmware/project_oracle_base/include/system_same54.h b/software/firmware/project_oracle_base/include/system_same54.h deleted file mode 100644 index e4535de..0000000 --- a/software/firmware/project_oracle_base/include/system_same54.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAME54_H_INCLUDED_ -#define _SYSTEM_SAME54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAME54_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/.vs/project_oracle_test_prj/v14/.atsuo b/software/firmware/project_oracle_test_prj/.vs/project_oracle_test_prj/v14/.atsuo new file mode 100644 index 0000000..0adfae4 Binary files /dev/null and b/software/firmware/project_oracle_test_prj/.vs/project_oracle_test_prj/v14/.atsuo differ diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20.atsln b/software/firmware/project_oracle_test_prj/project_oracle_test_prj.atsln similarity index 80% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20.atsln rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj.atsln index 88185cb..9f7e75e 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20.atsln +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj.atsln @@ -3,7 +3,7 @@ Microsoft Visual Studio Solution File, Format Version 12.00 # Atmel Studio Solution File, Format Version 11.00 VisualStudioVersion = 14.0.23107.0 MinimumVisualStudioVersion = 10.0.40219.1 -Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "same54_gfx_4_19_20", "same54_gfx_4_19_20\same54_gfx_4_19_20.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "project_oracle_test_prj", "project_oracle_test_prj\project_oracle_test_prj.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/AtmelStart.env_conf b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/AtmelStart.env_conf rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/AtmelStart.gpdsc b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc similarity index 92% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/AtmelStart.gpdsc rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc index dc4b169..a891ba7 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/.atmelstart/AtmelStart.gpdsc +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc @@ -42,12 +42,16 @@ Atmel Start Framework #define ATMEL_START + + - + + + @@ -55,6 +59,7 @@ + @@ -72,6 +77,7 @@ + @@ -84,9 +90,11 @@ + + @@ -134,7 +142,7 @@ - + @@ -146,14 +154,16 @@ + - + + @@ -170,6 +180,7 @@ + @@ -186,6 +197,7 @@ + diff --git a/software/firmware/project_oracle_base/atmel_start_config.atstart b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart similarity index 90% rename from software/firmware/project_oracle_base/atmel_start_config.atstart rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart index 1db4532..71e239f 100644 --- a/software/firmware/project_oracle_base/atmel_start_config.atstart +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart @@ -2,27 +2,27 @@ format_version: '2' name: My Project versions: api: '1.0' - backend: 1.7.301 + backend: 1.7.303 commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 content: unknown content_pack_name: unknown format: '2' - frontend: 1.7.301 - packs_version_avr8: 1.0.1408 + frontend: 1.7.303 + packs_version_avr8: 1.0.1410 packs_version_qtouch: unknown - packs_version_sam: 1.0.1373 - version_backend: 1.7.301 + packs_version_sam: 1.0.1554 + version_backend: 1.7.303 version_frontend: '' board: - identifier: CustomBoard - device: SAME54P20A-AF + identifier: SAME54XplainedPro + device: SAME54P20A-AU details: null application: null middlewares: {} drivers: CMCC: user_label: CMCC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC functionality: System api: HAL:HPL:CMCC configuration: @@ -38,7 +38,7 @@ drivers: domain_group: null DMAC: user_label: DMAC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC functionality: System api: HAL:HPL:DMAC configuration: @@ -574,7 +574,7 @@ drivers: domain_group: null EXTERNAL_IRQ_0: user_label: EXTERNAL_IRQ_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ functionality: External_IRQ api: HAL:Driver:Ext_IRQ configuration: @@ -697,7 +697,7 @@ drivers: eic_gclk_selection: Generic clock generator 0 GCLK: user_label: GCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK functionality: System api: HAL:HPL:GCLK configuration: @@ -711,7 +711,7 @@ drivers: enable_gclk_gen_1__externalclock: 1000000 enable_gclk_gen_2: false enable_gclk_gen_2__externalclock: 1000000 - enable_gclk_gen_3: true + enable_gclk_gen_3: false enable_gclk_gen_3__externalclock: 1000000 enable_gclk_gen_4: false enable_gclk_gen_4__externalclock: 1000000 @@ -750,7 +750,7 @@ drivers: gclk_arch_gen_2_oe: false gclk_arch_gen_2_oov: false gclk_arch_gen_2_runstdby: false - gclk_arch_gen_3_enable: true + gclk_arch_gen_3_enable: false gclk_arch_gen_3_idc: false gclk_arch_gen_3_oe: false gclk_arch_gen_3_oov: false @@ -827,7 +827,7 @@ drivers: domain_group: null MCLK: user_label: MCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK functionality: System api: HAL:HPL:MCLK configuration: @@ -850,7 +850,7 @@ drivers: configuration: {} OSC32KCTRL: user_label: OSC32KCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL functionality: System api: HAL:HPL:OSC32KCTRL configuration: @@ -878,7 +878,7 @@ drivers: domain_group: null OSCCTRL: user_label: OSCCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL functionality: System api: HAL:HPL:OSCCTRL configuration: @@ -959,7 +959,7 @@ drivers: domain_group: null PORT: user_label: PORT - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::PORT::driver_config_definition::PORT::HAL:HPL:PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT functionality: System api: HAL:HPL:PORT configuration: @@ -1019,26 +1019,9 @@ drivers: variant: null clocks: domain_group: null - QUAD_SPI_0: - user_label: QUAD_SPI_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.Sync - functionality: Quad_SPI - api: HAL:Driver:QSPI_Sync - configuration: - qspi_advanced: false - qspi_baud_rate: 375000 - qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following - edge of SPCK. - qspi_cpol: The inactive state value of SPCK is logic level zero. - qspi_dlybs: 0 - qspi_dlycs: 0 - optional_signals: [] - variant: null - clocks: - domain_group: null RAMECC: user_label: RAMECC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC functionality: System api: HAL:HPL:RAMECC configuration: {} @@ -1046,67 +1029,11 @@ drivers: variant: null clocks: domain_group: null - TIMER_0: - user_label: TIMER_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::RTC::driver_config_definition::Timer::HAL:Driver:Timer - functionality: Timer - api: HAL:Driver:Timer - configuration: - rtc_arch_comp_val: 32 - rtc_arch_init_reset: true - rtc_arch_prescaler: OFF(Peripheral clock divided by 1) - rtc_cmpeo0: false - rtc_cmpeo1: false - rtc_event_control: false - rtc_ovfeo: false - rtc_pereo0: false - rtc_pereo1: false - rtc_pereo2: false - rtc_pereo3: false - rtc_pereo4: false - rtc_pereo5: false - rtc_pereo6: false - rtc_pereo7: false - rtc_tamper_active_layer_frequency_prescalar: DIV2 CLK_RTC_OUT is CLK_RTC /2 - rtc_tamper_debounce_frequency_prescalar: DIV2 CLK_RTC_DEB is CLK_RTC /2 - rtc_tamper_input_action_0: OFF(Disabled) - rtc_tamper_input_action_1: OFF(Disabled) - rtc_tamper_input_action_2: OFF(Disabled) - rtc_tamper_input_action_3: OFF(Disabled) - rtc_tamper_input_action_4: OFF(Disabled) - rtc_tampereo: false - rtc_tampevei: false - tamper_debounce_enable_0: false - tamper_debounce_enable_1: false - tamper_debounce_enable_2: false - tamper_debounce_enable_3: false - tamper_debounce_enable_4: false - tamper_input_0_settings: false - tamper_input_1_settings: false - tamper_input_2_settings: false - tamper_input_3_settings: false - tamper_input_4_settings: false - tamper_level_0: false - tamper_level_1: false - tamper_level_2: false - tamper_level_3: false - tamper_level_4: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: RTC - input: RTC source - external: false - external_frequency: 0 - configuration: - rtc_clk_selection: RTC source USART_0: user_label: USART_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SERCOM0::driver_config_definition::UART::HAL:Driver:USART.Sync + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async functionality: USART - api: HAL:Driver:USART_Sync + api: HAL:Driver:USART_Async configuration: usart_advanced: false usart_arch_clock_mode: USART with internal clock @@ -1121,7 +1048,7 @@ drivers: usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) usart_arch_sampr: 16x arithmetic usart_arch_sfde: false - usart_baud_rate: 9600 + usart_baud_rate: 115200 usart_character_size: 8 bits usart_parity: No parity usart_rx_enable: true @@ -1131,11 +1058,11 @@ drivers: variant: specification: TXPO=0, RXPO=1, CMODE=0 required_signals: - - name: SERCOM0/PAD/0 - pad: PA04 + - name: SERCOM2/PAD/0 + pad: PB25 label: TX - - name: SERCOM0/PAD/1 - pad: PA05 + - name: SERCOM2/PAD/1 + pad: PB24 label: RX clocks: domain_group: @@ -1153,7 +1080,7 @@ drivers: slow_gclk_selection: Generic clock generator 3 I2C_0: user_label: I2C_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM3::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync functionality: I2C api: HAL:Driver:I2C_Master_Sync configuration: @@ -1171,11 +1098,11 @@ drivers: variant: specification: SDA=0, SCL=1 required_signals: - - name: SERCOM1/PAD/0 - pad: PA16 + - name: SERCOM3/PAD/0 + pad: PA22 label: SDA - - name: SERCOM1/PAD/1 - pad: PA17 + - name: SERCOM3/PAD/1 + pad: PA23 label: SCL clocks: domain_group: @@ -1191,20 +1118,9 @@ drivers: configuration: core_gclk_selection: Generic clock generator 0 slow_gclk_selection: Generic clock generator 3 - DELAY_0: - user_label: DELAY_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay - functionality: Delay - api: HAL:Driver:Delay - configuration: - systick_arch_tickint: false - optional_signals: [] - variant: null - clocks: - domain_group: null - TIMER_1: - user_label: TIMER_1 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::TC0::driver_config_definition::Timer::HAL:Driver:Timer + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer functionality: Timer api: HAL:Driver:Timer configuration: @@ -1234,28 +1150,28 @@ drivers: configuration: tc_gclk_selection: Generic clock generator 0 pads: - PA04: - name: PA04 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA04 - mode: Peripheral IO - user_label: PA04 - configuration: null - PA05: - name: PA05 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA05 - mode: Peripheral IO - user_label: PA05 - configuration: null - PA16: - name: PA16 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA16 + PA22: + name: PA22 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA22 mode: I2C - user_label: PA16 + user_label: PA22 configuration: null - PA17: - name: PA17 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA17 + PA23: + name: PA23 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA23 mode: I2C - user_label: PA17 + user_label: PA23 + configuration: null + PB24: + name: PB24 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 + mode: Peripheral IO + user_label: PB24 + configuration: null + PB25: + name: PB25 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 + mode: Peripheral IO + user_label: PB25 configuration: null toolchain_options: [] diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/RTE_Components.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/RTE_Components.h similarity index 95% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/RTE_Components.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/RTE_Components.h index 5911be2..d7183e6 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/RTE_Components.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/RTE_Components.h @@ -39,7 +39,7 @@ * * \acme_license_stop * - * Project: same54_gfx_4_19_20 + * Project: project_oracle_test_prj * Target: ATSAME54P20A * **/ diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_cmcc_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_cmcc_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_dmac_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_dmac_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h diff --git a/software/firmware/project_oracle_base/config/hpl_eic_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_eic_config.h similarity index 100% rename from software/firmware/project_oracle_base/config/hpl_eic_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_eic_config.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_gclk_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_gclk_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_gclk_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_gclk_config.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_mclk_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_mclk_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_osc32kctrl_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_osc32kctrl_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_oscctrl_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_oscctrl_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_oscctrl_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_oscctrl_config.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_port_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_port_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_port_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_port_config.h diff --git a/software/firmware/project_oracle_base/config/hpl_sercom_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h similarity index 54% rename from software/firmware/project_oracle_base/config/hpl_sercom_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h index 87f2e5d..68ce64c 100644 --- a/software/firmware/project_oracle_base/config/hpl_sercom_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h @@ -6,8 +6,8 @@ #include -#ifndef CONF_SERCOM_0_USART_ENABLE -#define CONF_SERCOM_0_USART_ENABLE 1 +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 #endif // Basic Configuration @@ -15,15 +15,15 @@ // Receive buffer enable // Enable input buffer in SERCOM module // usart_rx_enable -#ifndef CONF_SERCOM_0_USART_RXEN -#define CONF_SERCOM_0_USART_RXEN 1 +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 #endif // Transmitt buffer enable // Enable output buffer in SERCOM module // usart_tx_enable -#ifndef CONF_SERCOM_0_USART_TXEN -#define CONF_SERCOM_0_USART_TXEN 1 +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 #endif // Frame parity @@ -32,8 +32,8 @@ // <0x2=>Odd parity // Parity bit mode for USART frame // usart_parity -#ifndef CONF_SERCOM_0_USART_PARITY -#define CONF_SERCOM_0_USART_PARITY 0x0 +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 #endif // Character Size @@ -44,8 +44,8 @@ // <0x7=>7 bits // Data character size in USART frame // usart_character_size -#ifndef CONF_SERCOM_0_USART_CHSIZE -#define CONF_SERCOM_0_USART_CHSIZE 0x0 +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 #endif // Stop Bit @@ -53,51 +53,51 @@ // <1=>Two stop bits // Number of stop bits in USART frame // usart_stop_bit -#ifndef CONF_SERCOM_0_USART_SBMODE -#define CONF_SERCOM_0_USART_SBMODE 0 +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 #endif // Baud rate <1-6250000> // USART baud rate setting // usart_baud_rate -#ifndef CONF_SERCOM_0_USART_BAUD -#define CONF_SERCOM_0_USART_BAUD 9600 +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 115200 #endif // // Advanced configuration // usart_advanced -#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG -#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0 +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 #endif // Run in stand-by // Keep the module running in standby sleep mode // usart_arch_runstdby -#ifndef CONF_SERCOM_0_USART_RUNSTDBY -#define CONF_SERCOM_0_USART_RUNSTDBY 0 +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 #endif // Immediate Buffer Overflow Notification // Controls when the BUFOVF status bit is asserted // usart_arch_ibon -#ifndef CONF_SERCOM_0_USART_IBON -#define CONF_SERCOM_0_USART_IBON 0 +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 #endif // Start of Frame Detection Enable // Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) // usart_arch_sfde -#ifndef CONF_SERCOM_0_USART_SFDE -#define CONF_SERCOM_0_USART_SFDE 0 +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 #endif // Collision Detection Enable // Collision detection enable // usart_arch_cloden -#ifndef CONF_SERCOM_0_USART_CLODEN -#define CONF_SERCOM_0_USART_CLODEN 0 +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 #endif // Operating Mode @@ -105,8 +105,8 @@ // <0x1=>USART with internal clock // Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. // usart_arch_clock_mode -#ifndef CONF_SERCOM_0_USART_MODE -#define CONF_SERCOM_0_USART_MODE 0x1 +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 #endif // Sample Rate @@ -117,8 +117,8 @@ // <0x4=>3x arithmetic // How many over-sampling bits used when sampling data state // usart_arch_sampr -#ifndef CONF_SERCOM_0_USART_SAMPR -#define CONF_SERCOM_0_USART_SAMPR 0x0 +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 #endif // Sample Adjustment @@ -128,15 +128,15 @@ // <0x3=>13-14-15 (6-7-8 8-bit over-sampling) // Adjust which samples to use for data sampling in asynchronous mode // usart_arch_sampa -#ifndef CONF_SERCOM_0_USART_SAMPA -#define CONF_SERCOM_0_USART_SAMPA 0x0 +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 #endif // Fractional Part <0-7> // Fractional part of the baud rate if baud rate generator is in fractional mode // usart_arch_fractional -#ifndef CONF_SERCOM_0_USART_FRACTIONAL -#define CONF_SERCOM_0_USART_FRACTIONAL 0x0 +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 #endif // Data Order @@ -144,19 +144,19 @@ // <1=>LSB is transmitted first // Data order of the data bits in the frame // usart_arch_dord -#ifndef CONF_SERCOM_0_USART_DORD -#define CONF_SERCOM_0_USART_DORD 1 +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 #endif // Does not do anything in UART mode -#define CONF_SERCOM_0_USART_CPOL 0 +#define CONF_SERCOM_2_USART_CPOL 0 // Encoding Format // <0=>No encoding // <1=>IrDA encoded // usart_arch_enc -#ifndef CONF_SERCOM_0_USART_ENC -#define CONF_SERCOM_0_USART_ENC 0 +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 #endif // LIN Slave Enable @@ -165,8 +165,8 @@ // <0=>Disable // <1=>Enable // usart_arch_lin_slave_enable -#ifndef CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE -#define CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE 0 +#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 #endif // Debug Stop Mode @@ -174,102 +174,102 @@ // <0=>Keep running // <1=>Halt // usart_arch_dbgstop -#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE -#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0 +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 #endif // -#ifndef CONF_SERCOM_0_USART_INACK -#define CONF_SERCOM_0_USART_INACK 0x0 +#ifndef CONF_SERCOM_2_USART_INACK +#define CONF_SERCOM_2_USART_INACK 0x0 #endif -#ifndef CONF_SERCOM_0_USART_DSNACK -#define CONF_SERCOM_0_USART_DSNACK 0x0 +#ifndef CONF_SERCOM_2_USART_DSNACK +#define CONF_SERCOM_2_USART_DSNACK 0x0 #endif -#ifndef CONF_SERCOM_0_USART_MAXITER -#define CONF_SERCOM_0_USART_MAXITER 0x7 +#ifndef CONF_SERCOM_2_USART_MAXITER +#define CONF_SERCOM_2_USART_MAXITER 0x7 #endif -#ifndef CONF_SERCOM_0_USART_GTIME -#define CONF_SERCOM_0_USART_GTIME 0x2 +#ifndef CONF_SERCOM_2_USART_GTIME +#define CONF_SERCOM_2_USART_GTIME 0x2 #endif -#define CONF_SERCOM_0_USART_RXINV 0x0 -#define CONF_SERCOM_0_USART_TXINV 0x0 +#define CONF_SERCOM_2_USART_RXINV 0x0 +#define CONF_SERCOM_2_USART_TXINV 0x0 -#ifndef CONF_SERCOM_0_USART_CMODE -#define CONF_SERCOM_0_USART_CMODE 0 +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 #endif -#ifndef CONF_SERCOM_0_USART_RXPO -#define CONF_SERCOM_0_USART_RXPO 1 /* RX is on PIN_PA05 */ +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */ #endif -#ifndef CONF_SERCOM_0_USART_TXPO -#define CONF_SERCOM_0_USART_TXPO 0 /* TX is on PIN_PA04 */ +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */ #endif /* Set correct parity settings in register interface based on PARITY setting */ -#if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 1 -#if CONF_SERCOM_0_USART_PARITY == 0 -#define CONF_SERCOM_0_USART_PMODE 0 -#define CONF_SERCOM_0_USART_FORM 4 +#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 4 #else -#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 -#define CONF_SERCOM_0_USART_FORM 5 +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 5 #endif -#else /* #if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 0 */ -#if CONF_SERCOM_0_USART_PARITY == 0 -#define CONF_SERCOM_0_USART_PMODE 0 -#define CONF_SERCOM_0_USART_FORM 0 +#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 #else -#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 -#define CONF_SERCOM_0_USART_FORM 1 +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 #endif #endif // Calculate BAUD register value in UART mode -#if CONF_SERCOM_0_USART_SAMPR == 0 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_0_USART_SAMPR == 1 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_0_USART_SAMPR == 2 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_0_USART_SAMPR == 3 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_0_USART_SAMPR == 4 -#ifndef CONF_SERCOM_0_USART_BAUD_RATE -#define CONF_SERCOM_0_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif -#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 #endif #endif @@ -279,8 +279,8 @@ #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) #endif -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 1 +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 1 #endif // Basic @@ -288,16 +288,16 @@ // I2C Bus clock speed (Hz) <1-400000> // I2C Bus clock (SCL) speed measured in Hz // i2c_master_baud_rate -#ifndef CONF_SERCOM_1_I2CM_BAUD -#define CONF_SERCOM_1_I2CM_BAUD 100000 +#ifndef CONF_SERCOM_3_I2CM_BAUD +#define CONF_SERCOM_3_I2CM_BAUD 100000 #endif // // Advanced // i2c_master_advanced -#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG -#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 +#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0 #endif // TRise (ns) <0-300> @@ -307,29 +307,29 @@ // High Speed Mode: typical 20ns, max 40ns // i2c_master_arch_trise -#ifndef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215 +#ifndef CONF_SERCOM_3_I2CM_TRISE +#define CONF_SERCOM_3_I2CM_TRISE 215 #endif // Master SCL Low Extended Time-Out (MEXTTOEN) // This enables the master SCL low extend time-out // i2c_master_arch_mexttoen -#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN -#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 +#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN +#define CONF_SERCOM_3_I2CM_MEXTTOEN 0 #endif // Slave SCL Low Extend Time-Out (SEXTTOEN) // Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine // i2c_master_arch_sexttoen -#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN -#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 +#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN +#define CONF_SERCOM_3_I2CM_SEXTTOEN 0 #endif // SCL Low Time-Out (LOWTOUT) // Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold // i2c_master_arch_lowtout -#ifndef CONF_SERCOM_1_I2CM_LOWTOUT -#define CONF_SERCOM_1_I2CM_LOWTOUT 0 +#ifndef CONF_SERCOM_3_I2CM_LOWTOUT +#define CONF_SERCOM_3_I2CM_LOWTOUT 0 #endif // Inactive Time-Out (INACTOUT) @@ -339,8 +339,8 @@ // <0x3=>20-21 SCL cycle time-out(200-210us) // Defines if inactivity time-out should be enabled, and how long the time-out should be // i2c_master_arch_inactout -#ifndef CONF_SERCOM_1_I2CM_INACTOUT -#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 +#ifndef CONF_SERCOM_3_I2CM_INACTOUT +#define CONF_SERCOM_3_I2CM_INACTOUT 0x0 #endif // SDA Hold Time (SDAHOLD) @@ -350,15 +350,15 @@ // <3=>400-800ns hold time // Defines the SDA hold time with respect to the negative edge of SCL // i2c_master_arch_sdahold -#ifndef CONF_SERCOM_1_I2CM_SDAHOLD -#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 +#ifndef CONF_SERCOM_3_I2CM_SDAHOLD +#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2 #endif // Run in stand-by // Determine if the module shall run in standby sleep mode // i2c_master_arch_runstdby -#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY -#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 +#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY +#define CONF_SERCOM_3_I2CM_RUNSTDBY 0 #endif // Debug Stop Mode @@ -366,19 +366,19 @@ // <0=>Keep running // <1=>Halt // i2c_master_arch_dbgstop -#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE -#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 +#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0 #endif // -#ifndef CONF_SERCOM_1_I2CM_SPEED -#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#ifndef CONF_SERCOM_3_I2CM_SPEED +#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode #endif -#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 +#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300 #warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns -#undef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215U +#undef CONF_SERCOM_3_I2CM_TRISE +#define CONF_SERCOM_3_I2CM_TRISE 215U #endif // gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) @@ -386,25 +386,25 @@ // i2c_scl_freq // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW -#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ +#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \ / 1000U)) \ * 10U \ + 5U) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10U)) -#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE -#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) + / (CONF_SERCOM_3_I2CM_BAUD * 10U)) +#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE +#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF -#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 +#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1 #warning Requested I2C baudrate too high, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 +#define CONF_SERCOM_3_I2CM_BAUD_RATE 1 #else -#define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) +#define CONF_SERCOM_3_I2CM_BAUD_RATE \ + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2)) #endif #endif diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_tc_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Config/hpl_tc_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h diff --git a/software/firmware/project_oracle_base/config/peripheral_clk_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h similarity index 80% rename from software/firmware/project_oracle_base/config/peripheral_clk_config.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h index 05d93a6..74141bb 100644 --- a/software/firmware/project_oracle_base/config/peripheral_clk_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h @@ -52,22 +52,6 @@ #define CONF_CPU_FREQUENCY 119997440 #endif -// RTC Clock Source -// rtc_clk_selection -// RTC source -// Select the clock source for RTC. -#ifndef CONF_GCLK_RTC_SRC -#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE -#endif - -/** - * \def CONF_GCLK_RTC_FREQUENCY - * \brief RTC's Clock frequency - */ -#ifndef CONF_GCLK_RTC_FREQUENCY -#define CONF_GCLK_RTC_FREQUENCY 32768 -#endif - // Core Clock Source // core_gclk_selection @@ -96,8 +80,8 @@ // Generic clock generator 11 // Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM0_CORE_SRC -#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val #endif // Slow Clock Source @@ -128,24 +112,24 @@ // Generic clock generator 11 // Select the slow clock source. -#ifndef CONF_GCLK_SERCOM0_SLOW_SRC -#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #endif /** - * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY - * \brief SERCOM0's Core Clock frequency + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency */ -#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY -#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 119997440 +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440 #endif /** - * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY - * \brief SERCOM0's Slow Clock frequency + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency */ -#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 #endif // Core Clock Source @@ -176,8 +160,8 @@ // Generic clock generator 11 // Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM1_CORE_SRC -#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val #endif // Slow Clock Source @@ -208,24 +192,24 @@ // Generic clock generator 11 // Select the slow clock source. -#ifndef CONF_GCLK_SERCOM1_SLOW_SRC -#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #endif /** - * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY - * \brief SERCOM1's Core Clock frequency + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency */ -#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY -#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 119997440 +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440 #endif /** - * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY - * \brief SERCOM1's Slow Clock frequency + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency */ -#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 #endif // TC Clock Source diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Default.xml b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Default.xml similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Default.xml rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Default.xml diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/same54p20a_flash.ld b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/same54p20a_flash.ld similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/same54p20a_flash.ld rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/same54p20a_flash.ld diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/same54p20a_sram.ld b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/same54p20a_sram.ld similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/same54p20a_sram.ld rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/same54p20a_sram.ld diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/startup_same54.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/startup_same54.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/startup_same54.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/startup_same54.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/system_same54.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/system_same54.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/Device_Startup/system_same54.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/Device_Startup/system_same54.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/atmel_start.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/atmel_start.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/atmel_start.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/atmel_start.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/atmel_start_pins.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h similarity index 85% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/atmel_start_pins.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h index b4f267b..44a1c39 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/atmel_start_pins.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h @@ -27,7 +27,9 @@ #define GPIO_PIN_FUNCTION_M 12 #define GPIO_PIN_FUNCTION_N 13 -#define PA04 GPIO(GPIO_PORTA, 4) -#define PA05 GPIO(GPIO_PORTA, 5) +#define PA22 GPIO(GPIO_PORTA, 22) +#define PA23 GPIO(GPIO_PORTA, 23) +#define PB24 GPIO(GPIO_PORTB, 24) +#define PB25 GPIO(GPIO_PORTB, 25) #endif // ATMEL_START_PINS_H_INCLUDED diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c new file mode 100644 index 0000000..9bda34f --- /dev/null +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c @@ -0,0 +1,134 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +/*! The buffer size for USART */ +#define USART_0_BUFFER_SIZE 16 + +struct usart_async_descriptor USART_0; +struct timer_descriptor TIMER_0; + +static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE]; + +struct i2c_m_sync_desc I2C_0; + +void EXTERNAL_IRQ_0_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_mclk_set_APBAMASK_EIC_bit(MCLK); + + ext_irq_init(); +} + +/** + * \brief USART Clock initialization function + * + * Enables register interface and peripheral clock + */ +void USART_0_CLOCK_init() +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); +} + +/** + * \brief USART pinmux initialization function + * + * Set each required pin to USART functionality + */ +void USART_0_PORT_init() +{ + + gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); + + gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); +} + +/** + * \brief USART initialization function + * + * Enables USART peripheral, clocks and initializes USART driver + */ +void USART_0_init(void) +{ + USART_0_CLOCK_init(); + usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); + USART_0_PORT_init(); +} + +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_pull_mode(PA22, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0); + + gpio_set_pin_pull_mode(PA23, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM3); + I2C_0_PORT_init(); +} + +/** + * \brief Timer initialization function + * + * Enables Timer peripheral, clocks and initializes Timer driver + */ +static void TIMER_0_init(void) +{ + hri_mclk_set_APBAMASK_TC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + timer_init(&TIMER_0, TC0, _tc_get_timer()); +} + +void system_init(void) +{ + init_mcu(); + + EXTERNAL_IRQ_0_init(); + + USART_0_init(); + + I2C_0_init(); + + TIMER_0_init(); +} diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/driver_init.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.h similarity index 73% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/driver_init.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.h index 6a792b9..16d4f9f 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/driver_init.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.h @@ -21,17 +21,27 @@ extern "C" { #include #include -#include +#include + +#include + +#include #include #include -extern struct usart_sync_descriptor USART_0; -extern struct timer_descriptor TIMER_0; +extern struct usart_async_descriptor USART_0; + +extern struct i2c_m_sync_desc I2C_0; +extern struct timer_descriptor TIMER_0; void USART_0_PORT_init(void); void USART_0_CLOCK_init(void); void USART_0_init(void); +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + /** * \brief Perform system initialization, initialize pins and clocks for * peripherals diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.c new file mode 100644 index 0000000..7cf9ca8 --- /dev/null +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.c @@ -0,0 +1,84 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using EXTERNAL_IRQ_0 + */ +void EXTERNAL_IRQ_0_example(void) +{ +} + +/** + * Example of using USART_0 to write "Hello World" using the IO abstraction. + * + * Since the driver is asynchronous we need to use statically allocated memory for string + * because driver initiates transfer and then returns before the transmission is completed. + * + * Once transfer has been completed the tx_cb function will be called. + */ + +static uint8_t example_USART_0[12] = "Hello World!"; + +static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr) +{ + /* Transfer completed */ +} + +void USART_0_example(void) +{ + struct io_descriptor *io; + + usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0); + /*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb); + usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/ + usart_async_get_io_descriptor(&USART_0, &io); + usart_async_enable(&USART_0); + + io_write(io, example_USART_0, 12); +} + +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + +static struct timer_task TIMER_0_task1, TIMER_0_task2; + +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + TIMER_0_task2.interval = 200; + TIMER_0_task2.cb = TIMER_0_task2_cb; + TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_add_task(&TIMER_0, &TIMER_0_task2); + timer_start(&TIMER_0); +} diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/examples/driver_examples.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.h similarity index 88% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/examples/driver_examples.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.h index 3480b4d..8e0cea1 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/examples/driver_examples.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.h @@ -12,8 +12,12 @@ extern "C" { #endif +void EXTERNAL_IRQ_0_example(void); + void USART_0_example(void); +void I2C_0_example(void); + void TIMER_0_example(void); #ifdef __cplusplus diff --git a/software/firmware/project_oracle_base/hal/documentation/ext_irq.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/ext_irq.rst similarity index 100% rename from software/firmware/project_oracle_base/hal/documentation/ext_irq.rst rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/ext_irq.rst diff --git a/software/firmware/project_oracle_base/hal/documentation/i2c_master_sync.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/i2c_master_sync.rst similarity index 100% rename from software/firmware/project_oracle_base/hal/documentation/i2c_master_sync.rst rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/i2c_master_sync.rst diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/documentation/timer.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/timer.rst similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/documentation/timer.rst rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/timer.rst diff --git a/software/firmware/project_oracle_base/hal/documentation/usart_sync.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/usart_async.rst similarity index 62% rename from software/firmware/project_oracle_base/hal/documentation/usart_sync.rst rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/usart_async.rst index 15e4b13..6bf4a23 100644 --- a/software/firmware/project_oracle_base/hal/documentation/usart_sync.rst +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/usart_async.rst @@ -1,9 +1,20 @@ -The USART Synchronous Driver -============================ +The USART Asynchronous Driver +============================= The universal synchronous and asynchronous receiver and transmitter (USART) is usually used to transfer data from one device to the other. +The USART driver use a ring buffer to store received data. When the USART +raise the data received interrupt, this data will be stored in the ring buffer +at the next free location. When the ring buffer is full, the next reception +will overwrite the oldest data stored in the ring buffer. There is one +USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro +is called SERCOM0_USART_BUFFER_SIZE. + +On the other hand, when sending data over USART, the data is not copied to an +internal buffer, but the data buffer supplied by the user is used. The callback +will only be generated at the end of the buffer and not for each byte. + User can set action for flow control pins by function usart_set_flow_control, if the flow control is enabled. All the available states are defined in union usart_flow_control_state. @@ -24,6 +35,8 @@ Features * Data order * Flow control * Data transfer: transmission, reception +* Notifications about transfer done or error case via callbacks +* Status information with busy state and transfer count Applications ------------ @@ -34,7 +47,8 @@ between devices. Dependencies ------------ -USART capable hardware. +USART capable hardware, with interrupt on each character is sent or +received. Concurrency ----------- diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_atomic.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_atomic.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_atomic.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_atomic.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_cache.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_cache.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_delay.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_delay.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h diff --git a/software/firmware/project_oracle_base/hal/include/hal_ext_irq.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_ext_irq.h similarity index 100% rename from software/firmware/project_oracle_base/hal/include/hal_ext_irq.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_ext_irq.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_gpio.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_gpio.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_gpio.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_gpio.h diff --git a/software/firmware/project_oracle_base/hal/include/hal_i2c_m_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_i2c_m_sync.h similarity index 100% rename from software/firmware/project_oracle_base/hal/include/hal_i2c_m_sync.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_i2c_m_sync.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_init.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_init.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_init.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_init.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_io.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_io.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_io.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_io.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_sleep.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_sleep.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_sleep.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_sleep.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_timer.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_timer.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hal_timer.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_timer.h diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_usart_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_usart_async.h new file mode 100644 index 0000000..3a6de39 --- /dev/null +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_usart_async.h @@ -0,0 +1,339 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_USART_ASYNC_H_INCLUDED +#define _HAL_USART_ASYNC_H_INCLUDED + +#include "hal_io.h" +#include +#include + +/** + * \addtogroup doc_driver_hal_usart_async + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor + * + * The USART descriptor forward declaration. + */ +struct usart_async_descriptor; + +/** + * \brief USART callback type + */ +typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr); + +/** + * \brief USART callback types + */ +enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB }; + +/** + * \brief USART callbacks + */ +struct usart_async_callbacks { + usart_cb_t tx_done; + usart_cb_t rx_done; + usart_cb_t error; +}; + +/** \brief USART status + * Status descriptor holds the current status of transfer. + */ +struct usart_async_status { + /** Status flags */ + uint32_t flags; + /** Number of characters transmitted */ + uint16_t txcnt; + /** Number of characters receviced */ + uint16_t rxcnt; +}; + +/** + * \brief Asynchronous USART descriptor structure + */ +struct usart_async_descriptor { + struct io_descriptor io; + struct _usart_async_device device; + struct usart_async_callbacks usart_cb; + uint32_t stat; + + struct ringbuffer rx; + uint16_t tx_por; + uint8_t * tx_buffer; + uint16_t tx_buffer_length; +}; + +/** USART write busy */ +#define USART_ASYNC_STATUS_BUSY 0x0001 + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used as USART + * interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via the USART + * \param[in] hw The pointer to the hardware instance + * \param[in] rx_buffer An RX buffer + * \param[in] rx_buffer_length The length of the buffer above + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + * \retval -1 Passed parameters were invalid or the interface is already + * initialized + * \retval 0 The initialization is completed successfully + */ +int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer, + const uint16_t rx_buffer_length, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware + * is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_async_deinit(struct usart_async_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_async_enable(struct usart_async_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_async_disable(struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of I/O descriptor retrieving. + */ +int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Register USART callback + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] type Callback type + * \param[in] cb A callback function + * + * \return The status of callback assignment. + * \retval -1 Passed parameters were invalid or the interface is not initialized + * \retval 0 A callback is registered successfully + */ +int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, + const enum usart_async_callback_type type, usart_cb_t cb); + +/** + * \brief Specify action for flow control pins + * + * This function sets action (or state) for flow control pins if + * the flow control is enabled. + * It sets state of flow control pins only if automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, + const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the flow control pins + * if the flow control is enabled. + * + * The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of the USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve the current interface status + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] status The state of USART + * + * \return The status of USART status retrieving. + */ +int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status); + +/** + * \brief flush USART ringbuf + * + * This function flush USART RX ringbuf. + * + * \param[in] descr The pointer to USART descriptor + * + * \return ERR_NONE + */ +int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_async_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_USART_ASYNC_H_INCLUDED */ diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_cmcc.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_cmcc.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_cmcc.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_cmcc.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_core.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_core.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_core.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_core.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_delay.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_delay.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_delay.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_delay.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_dma.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_dma.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_dma.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_dma.h diff --git a/software/firmware/project_oracle_base/hal/include/hpl_ext_irq.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ext_irq.h similarity index 100% rename from software/firmware/project_oracle_base/hal/include/hpl_ext_irq.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ext_irq.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_gpio.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_gpio.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_gpio.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_gpio.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_m_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_async.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_m_async.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_async.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_m_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_sync.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_m_sync.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_sync.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_s_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_async.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_s_async.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_async.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_s_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_sync.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_i2c_s_sync.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_sync.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_init.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_init.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_init.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_init.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_irq.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_irq.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_irq.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_irq.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_missing_features.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_missing_features.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_missing_features.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_missing_features.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_pwm.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_pwm.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_pwm.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_pwm.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_ramecc.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ramecc.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_ramecc.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ramecc.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_reset.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_reset.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_reset.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_reset.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_sleep.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_sleep.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_sleep.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_sleep.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_async.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_async.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_async.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_m_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_async.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_m_async.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_async.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_m_dma.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_dma.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_m_dma.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_dma.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_m_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_sync.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_m_sync.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_sync.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_s_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_async.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_s_async.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_async.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_s_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_sync.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_s_sync.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_sync.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_sync.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_spi_sync.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_sync.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_timer.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_timer.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_timer.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_timer.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_usart.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_usart.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_usart_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_async.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_usart_async.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_async.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_usart_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_sync.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/include/hpl_usart_sync.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_sync.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_atomic.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_atomic.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_atomic.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_atomic.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_cache.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_cache.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_cache.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_cache.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_delay.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_delay.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_delay.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_delay.c diff --git a/software/firmware/project_oracle_base/hal/src/hal_ext_irq.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_ext_irq.c similarity index 100% rename from software/firmware/project_oracle_base/hal/src/hal_ext_irq.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_ext_irq.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_gpio.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_gpio.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_gpio.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_gpio.c diff --git a/software/firmware/project_oracle_base/hal/src/hal_i2c_m_sync.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_i2c_m_sync.c similarity index 100% rename from software/firmware/project_oracle_base/hal/src/hal_i2c_m_sync.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_i2c_m_sync.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_init.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_init.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_init.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_init.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_io.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_io.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_io.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_io.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_sleep.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_sleep.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_sleep.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_sleep.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_timer.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_timer.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/src/hal_timer.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_timer.c diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_usart_async.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_usart_async.c new file mode 100644 index 0000000..f07b266 --- /dev/null +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_usart_async.c @@ -0,0 +1,420 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_async.h" +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); +static void usart_process_byte_sent(struct _usart_async_device *device); +static void usart_transmission_complete(struct _usart_async_device *device); +static void usart_error(struct _usart_async_device *device); +static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data); + +/** + * \brief Initialize usart interface + */ +int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *rx_buffer, + uint16_t rx_buffer_length, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw && rx_buffer && rx_buffer_length); + + if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) { + return ERR_INVALID_ARG; + } + init_status = _usart_async_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_async_read; + descr->io.write = usart_async_write; + + descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent; + descr->device.usart_cb.rx_done_cb = usart_fill_rx_buffer; + descr->device.usart_cb.tx_done_cb = usart_transmission_complete; + descr->device.usart_cb.error_cb = usart_error; + + return ERR_NONE; +} + +/** + * \brief Deinitialize usart interface + */ +int32_t usart_async_deinit(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_deinit(&descr->device); + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_async_enable(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_async_disable(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Register usart callback + */ +int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, + const enum usart_async_callback_type type, usart_cb_t cb) +{ + ASSERT(descr); + + switch (type) { + case USART_ASYNC_RXC_CB: + descr->usart_cb.rx_done = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_RX_DONE, NULL != cb); + break; + case USART_ASYNC_TXC_CB: + descr->usart_cb.tx_done = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_TX_DONE, NULL != cb); + break; + case USART_ASYNC_ERROR_CB: + descr->usart_cb.error = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_ERROR, NULL != cb); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_async_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_async_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_async_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_async_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_async_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_async_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_async_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_async_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + return _usart_async_is_byte_sent(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + + return ringbuffer_num(&descr->rx) > 0; +} + +/** + * \brief Retrieve the current interface status + */ +int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status) +{ + ASSERT(descr); + + volatile uint32_t *tmp_stat = &(descr->stat); + volatile uint16_t *tmp_txcnt = &(descr->tx_por); + + if (status) { + status->flags = *tmp_stat; + status->txcnt = *tmp_txcnt; + status->rxcnt = ringbuffer_num(&descr->rx); + } + if (*tmp_stat & USART_ASYNC_STATUS_BUSY) { + return ERR_BUSY; + } + + return ERR_NONE; +} + +/** + * \brief flush usart rx ringbuf + */ +int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + + return ringbuffer_flush(&descr->rx); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_async_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); + + ASSERT(descr && buf && length); + + if (descr->tx_por != descr->tx_buffer_length) { + return ERR_NO_RESOURCE; + } + descr->tx_buffer = (uint8_t *)buf; + descr->tx_buffer_length = length; + descr->tx_por = 0; + descr->stat = USART_ASYNC_STATUS_BUSY; + _usart_async_enable_byte_sent_irq(&descr->device); + + return (int32_t)length; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint16_t was_read = 0; + uint32_t num; + struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); + + ASSERT(descr && buf && length); + + CRITICAL_SECTION_ENTER() + num = ringbuffer_num(&descr->rx); + CRITICAL_SECTION_LEAVE() + + while ((was_read < num) && (was_read < length)) { + ringbuffer_get(&descr->rx, &buf[was_read++]); + } + + return (int32_t)was_read; +} + +/** + * \brief Process "byte is sent" interrupt + * + * \param[in] device The pointer to device structure + */ +static void usart_process_byte_sent(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + if (descr->tx_por != descr->tx_buffer_length) { + _usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]); + _usart_async_enable_byte_sent_irq(&descr->device); + } else { + _usart_async_enable_tx_done_irq(&descr->device); + } +} + +/** + * \brief Process completion of data sending + * + * \param[in] device The pointer to device structure + */ +static void usart_transmission_complete(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + if (descr->usart_cb.tx_done) { + descr->usart_cb.tx_done(descr); + } +} + +/** + * \brief Process byte reception + * + * \param[in] device The pointer to device structure + * \param[in] data Data read + */ +static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + ringbuffer_put(&descr->rx, data); + + if (descr->usart_cb.rx_done) { + descr->usart_cb.rx_done(descr); + } +} + +/** + * \brief Process error interrupt + * + * \param[in] device The pointer to device structure + */ +static void usart_error(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + if (descr->usart_cb.error) { + descr->usart_cb.error(descr); + } +} + +//@} diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/compiler.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/compiler.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/compiler.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/compiler.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/err_codes.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/err_codes.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/err_codes.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/err_codes.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/events.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/events.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/events.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/events.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/parts.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/parts.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/parts.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/parts.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_assert.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_assert.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_assert.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_assert.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_event.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_event.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_event.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_event.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_increment_macro.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_increment_macro.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_increment_macro.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_increment_macro.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_list.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_list.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_list.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_list.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_repeat_macro.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_repeat_macro.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/include/utils_repeat_macro.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_repeat_macro.h diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_ringbuffer.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_ringbuffer.h new file mode 100644 index 0000000..401d557 --- /dev/null +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_ringbuffer.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief Ringbuffer declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _UTILS_RINGBUFFER_H_INCLUDED +#define _UTILS_RINGBUFFER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_ringbuffer + * + * @{ + */ + +#include "compiler.h" +#include "utils_assert.h" + +/** + * \brief Ring buffer element type + */ +struct ringbuffer { + uint8_t *buf; /** Buffer base address */ + uint32_t size; /** Buffer size */ + uint32_t read_index; /** Buffer read index */ + uint32_t write_index; /** Buffer write index */ +}; + +/** + * \brief Ring buffer init + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] buf Space to store the data + * \param[in] size The buffer length, must be aligned with power of 2 + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size); + +/** + * \brief Get one byte from ring buffer, the user needs to handle the concurrent + * access on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte space to store the read data + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data); + +/** + * \brief Put one byte to ring buffer, the user needs to handle the concurrent access + * on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte data to be put into ring buffer + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data); + +/** + * \brief Return the element number of ring buffer + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return The number of elements in ring buffer [0, rb->size] + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb); + +/** + * \brief Flush ring buffer, the user needs to handle the concurrent access on buffer + * via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return ERR_NONE on success, or an error code on failure. + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_RINGBUFFER_H_INCLUDED */ diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_assert.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_assert.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_assert.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_assert.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_event.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_event.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_event.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_event.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_list.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_list.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_list.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_list.c diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_ringbuffer.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_ringbuffer.c new file mode 100644 index 0000000..45cac83 --- /dev/null +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_ringbuffer.c @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief Ringbuffer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include "utils_ringbuffer.h" + +/** + * \brief Ringbuffer init + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) +{ + ASSERT(rb && buf && size); + + /* + * buf size must be aligned to power of 2 + */ + if ((size & (size - 1)) != 0) { + return ERR_INVALID_ARG; + } + + /* size - 1 is faster in calculation */ + rb->size = size - 1; + rb->read_index = 0; + rb->write_index = rb->read_index; + rb->buf = (uint8_t *)buf; + + return ERR_NONE; +} + +/** + * \brief Get one byte from ringbuffer + * + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) +{ + ASSERT(rb && data); + + if (rb->write_index != rb->read_index) { + *data = rb->buf[rb->read_index & rb->size]; + rb->read_index++; + return ERR_NONE; + } + + return ERR_NOT_FOUND; +} + +/** + * \brief Put one byte to ringbuffer + * + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) +{ + ASSERT(rb); + + rb->buf[rb->write_index & rb->size] = data; + + /* + * buffer full strategy: new data will overwrite the oldest data in + * the buffer + */ + if ((rb->write_index - rb->read_index) > rb->size) { + rb->read_index = rb->write_index - rb->size; + } + + rb->write_index++; + + return ERR_NONE; +} + +/** + * \brief Return the element number of ringbuffer + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb) +{ + ASSERT(rb); + + return rb->write_index - rb->read_index; +} + +/** + * \brief Flush ringbuffer + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb) +{ + ASSERT(rb); + + rb->read_index = rb->write_index; + + return ERR_NONE; +} diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_syscalls.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_syscalls.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hal/utils/src/utils_syscalls.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_syscalls.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/cmcc/hpl_cmcc.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/cmcc/hpl_cmcc.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/cmcc/hpl_cmcc.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/cmcc/hpl_cmcc.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/core/hpl_core_m4.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_m4.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/core/hpl_core_m4.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_m4.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/core/hpl_core_port.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_port.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/core/hpl_core_port.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_port.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/core/hpl_init.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_init.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/core/hpl_init.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_init.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/dmac/hpl_dmac.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/dmac/hpl_dmac.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/dmac/hpl_dmac.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/dmac/hpl_dmac.c diff --git a/software/firmware/project_oracle_base/hpl/eic/hpl_eic.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/eic/hpl_eic.c similarity index 100% rename from software/firmware/project_oracle_base/hpl/eic/hpl_eic.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/eic/hpl_eic.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/gclk/hpl_gclk.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/gclk/hpl_gclk.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/gclk/hpl_gclk_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk_base.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/gclk/hpl_gclk_base.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk_base.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/mclk/hpl_mclk.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/mclk/hpl_mclk.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/mclk/hpl_mclk.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/mclk/hpl_mclk.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/osc32kctrl/hpl_osc32kctrl.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/osc32kctrl/hpl_osc32kctrl.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/osc32kctrl/hpl_osc32kctrl.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/osc32kctrl/hpl_osc32kctrl.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/oscctrl/hpl_oscctrl.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/oscctrl/hpl_oscctrl.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/oscctrl/hpl_oscctrl.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/oscctrl/hpl_oscctrl.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/pm/hpl_pm.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/pm/hpl_pm.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/pm/hpl_pm_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm_base.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/pm/hpl_pm_base.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm_base.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/port/hpl_gpio_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/port/hpl_gpio_base.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/port/hpl_gpio_base.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/port/hpl_gpio_base.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/ramecc/hpl_ramecc.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/ramecc/hpl_ramecc.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/ramecc/hpl_ramecc.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/ramecc/hpl_ramecc.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/sercom/hpl_sercom.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/sercom/hpl_sercom.c similarity index 97% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/sercom/hpl_sercom.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/sercom/hpl_sercom.c index a1db100..306c99b 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/sercom/hpl_sercom.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/sercom/hpl_sercom.c @@ -163,6 +163,8 @@ static struct usart_configuration _usarts[] = { }; #endif +static struct _usart_async_device *_sercom2_dev = NULL; + static uint8_t _get_sercom_index(const void *const hw); static uint8_t _sercom_get_irq_num(const void *const hw); static void _sercom_init_irq_param(const void *const hw, void *dev); @@ -562,6 +564,40 @@ void _usart_async_set_irq_state(struct _usart_async_device *const device, const } } +/** + * \internal Sercom interrupt handler + * + * \param[in] p The pointer to interrupt parameter + */ +static void _sercom_usart_interrupt_handler(struct _usart_async_device *device) +{ + void *hw = device->hw; + + if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) { + hri_sercomusart_clear_INTEN_DRE_bit(hw); + device->usart_cb.tx_byte_sent(device); + } else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) { + hri_sercomusart_clear_INTEN_TXC_bit(hw); + device->usart_cb.tx_done_cb(device); + } else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) { + if (hri_sercomusart_read_STATUS_reg(hw) + & (SERCOM_USART_STATUS_PERR | SERCOM_USART_STATUS_FERR | SERCOM_USART_STATUS_BUFOVF + | SERCOM_USART_STATUS_ISF | SERCOM_USART_STATUS_COLL)) { + hri_sercomusart_clear_STATUS_reg(hw, SERCOM_USART_STATUS_MASK); + return; + } + + device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); + } else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) { + uint32_t status; + + hri_sercomusart_clear_interrupt_ERROR_bit(hw); + device->usart_cb.error_cb(device); + status = hri_sercomusart_read_STATUS_reg(hw); + hri_sercomusart_clear_STATUS_reg(hw, status); + } +} + /** * \internal Retrieve ordinal number of the given sercom hardware instance * @@ -589,6 +625,10 @@ static uint8_t _get_sercom_index(const void *const hw) */ static void _sercom_init_irq_param(const void *const hw, void *dev) { + + if (hw == SERCOM2) { + _sercom2_dev = (struct _usart_async_device *)dev; + } } /** @@ -2357,6 +2397,35 @@ static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_a return NULL; } +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_0_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_1_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_2_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_3_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} + int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) { const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/tc/hpl_tc.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc.c similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/tc/hpl_tc.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/tc/hpl_tc_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc_base.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hpl/tc/hpl_tc_base.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc_base.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_ac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ac_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_ac_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ac_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_adc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_adc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_adc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_adc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_aes_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_aes_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_aes_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_aes_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_can_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_can_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_can_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_can_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_ccl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ccl_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_ccl_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ccl_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_cmcc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_cmcc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_cmcc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_cmcc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_dac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dac_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_dac_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dac_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_dmac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dmac_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_dmac_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dmac_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_dsu_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dsu_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_dsu_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dsu_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_eic_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_eic_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_eic_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_eic_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_evsys_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_evsys_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_evsys_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_evsys_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_freqm_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_freqm_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_freqm_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_freqm_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_gclk_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gclk_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_gclk_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gclk_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_gmac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gmac_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_gmac_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gmac_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_hmatrixb_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_hmatrixb_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_hmatrixb_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_hmatrixb_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_i2s_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_i2s_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_i2s_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_i2s_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_icm_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_icm_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_icm_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_icm_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_mclk_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_mclk_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_mclk_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_mclk_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_nvmctrl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_nvmctrl_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_nvmctrl_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_nvmctrl_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_osc32kctrl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_osc32kctrl_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_osc32kctrl_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_osc32kctrl_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_oscctrl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_oscctrl_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_oscctrl_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_oscctrl_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pac_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pac_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pac_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pcc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pcc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pcc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pcc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pdec_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pdec_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pdec_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pdec_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pm_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pm_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_pm_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pm_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_port_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_port_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_port_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_port_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_qspi_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_qspi_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_qspi_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_qspi_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_ramecc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ramecc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_ramecc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ramecc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_rstc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rstc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_rstc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rstc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_rtc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rtc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_rtc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rtc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_sdhc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sdhc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_sdhc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sdhc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_sercom_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sercom_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_sercom_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sercom_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_supc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_supc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_supc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_supc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_tc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_tc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_tcc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tcc_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_tcc_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tcc_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_trng_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_trng_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_trng_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_trng_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_usb_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_usb_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_usb_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_usb_e54.h diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_wdt_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_wdt_e54.h similarity index 100% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/hri/hri_wdt_e54.h rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_wdt_e54.h diff --git a/software/firmware/project_oracle_base/main.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/main.c similarity index 100% rename from software/firmware/project_oracle_base/main.c rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/main.c diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/same54_gfx_4_19_20.componentinfo.xml b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/project_oracle_test_prj.componentinfo.xml similarity index 96% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/same54_gfx_4_19_20.componentinfo.xml rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/project_oracle_test_prj.componentinfo.xml index f72709b..b90e72c 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/same54_gfx_4_19_20.componentinfo.xml +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/project_oracle_test_prj.componentinfo.xml @@ -91,7 +91,7 @@ template source C Exe - Ly2UrrHBiH0fCOfkTk+KRA== + fp3ibDoBFJ1tq/lNIqyyJA== templates/main.c Main file (.c) diff --git a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/same54_gfx_4_19_20.cproj b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/project_oracle_test_prj.cproj similarity index 90% rename from software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/same54_gfx_4_19_20.cproj rename to software/firmware/project_oracle_test_prj/project_oracle_test_prj/project_oracle_test_prj.cproj index 69de6e2..8008062 100644 --- a/software/firmware/e54_xplained_testing/same54_gfx_4_19_20/same54_gfx_4_19_20/same54_gfx_4_19_20.cproj +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/project_oracle_test_prj.cproj @@ -12,9 +12,9 @@ $(MSBuildProjectName) .elf $(MSBuildProjectDirectory)\$(Configuration) - same54_gfx_4_19_20 - same54_gfx_4_19_20 - same54_gfx_4_19_20 + project_oracle_test_prj + project_oracle_test_prj + project_oracle_test_prj Native true false @@ -30,15 +30,15 @@ - - - - - - - - - + + + + + + + + + .atmelstart\atmel_start_config.atstart .atmelstart\AtmelStart.gpdsc @@ -53,7 +53,9 @@ + + @@ -61,6 +63,7 @@ + @@ -78,6 +81,7 @@ + @@ -90,9 +94,11 @@ + + @@ -134,13 +140,13 @@ - - - - - + + + + + - + @@ -152,14 +158,16 @@ + - + + @@ -169,21 +177,22 @@ - + + - + - + @@ -213,6 +222,7 @@ ../hpl/cmcc ../hpl/core ../hpl/dmac + ../hpl/eic ../hpl/gclk ../hpl/mclk ../hpl/osc32kctrl @@ -254,6 +264,7 @@ ../hpl/cmcc ../hpl/core ../hpl/dmac + ../hpl/eic ../hpl/gclk ../hpl/mclk ../hpl/osc32kctrl @@ -278,6 +289,7 @@ ../hpl/cmcc ../hpl/core ../hpl/dmac + ../hpl/eic ../hpl/gclk ../hpl/mclk ../hpl/osc32kctrl @@ -318,6 +330,7 @@ ../hpl/cmcc ../hpl/core ../hpl/dmac + ../hpl/eic ../hpl/gclk ../hpl/mclk ../hpl/osc32kctrl @@ -360,6 +373,7 @@ ../hpl/cmcc ../hpl/core ../hpl/dmac + ../hpl/eic ../hpl/gclk ../hpl/mclk ../hpl/osc32kctrl @@ -385,6 +399,7 @@ ../hpl/cmcc ../hpl/core ../hpl/dmac + ../hpl/eic ../hpl/gclk ../hpl/mclk ../hpl/osc32kctrl @@ -418,6 +433,9 @@ compile + + compile + compile @@ -472,9 +490,15 @@ compile + + compile + compile + + compile + compile @@ -487,7 +511,7 @@ compile - + compile @@ -502,6 +526,9 @@ compile + + compile + compile @@ -583,9 +610,15 @@ compile + + compile + compile + + compile + compile @@ -598,7 +631,7 @@ compile - + compile @@ -631,6 +664,9 @@ compile + + compile + compile @@ -640,6 +676,9 @@ compile + + compile + compile @@ -658,6 +697,9 @@ compile + + compile + compile @@ -830,6 +872,7 @@ + @@ -848,10 +891,16 @@ compile + + compile + + + compile + compile - + compile