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150 lines
3.8 KiB
C
150 lines
3.8 KiB
C
/**
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* \file
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*
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* \brief Quad SPI related functionality declaration.
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _HPL_QSPI_H_INCLUDED
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#define _HPL_QSPI_H_INCLUDED
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#include "compiler.h"
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/**
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* \addtogroup hpl_qspi HPL QSPI
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*
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*@{
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \brief Qspi access modes
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*/
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enum qspi_access {
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/* Read access */
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QSPI_READ_ACCESS = 0,
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/* Read memory access */
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QSPI_READMEM_ACCESS,
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/* Write access */
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QSPI_WRITE_ACCESS,
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/* Write memory access */
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QSPI_WRITEMEM_ACCESS
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};
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/**
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* \brief QSPI command instruction/address/data width
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*/
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enum qspi_cmd_width {
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/** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */
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QSPI_INST1_ADDR1_DATA1,
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/** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */
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QSPI_INST1_ADDR1_DATA2,
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/** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */
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QSPI_INST1_ADDR1_DATA4,
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/** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */
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QSPI_INST1_ADDR2_DATA2,
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/** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */
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QSPI_INST1_ADDR4_DATA4,
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/** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */
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QSPI_INST2_ADDR2_DATA2,
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/** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */
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QSPI_INST4_ADDR4_DATA4
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};
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/**
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* \brief QSPI command option code length in bits
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*/
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enum qspi_cmd_opt_len {
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/** The option code is 1 bit long */
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QSPI_OPT_1BIT,
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/** The option code is 2 bits long */
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QSPI_OPT_2BIT,
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/** The option code is 4 bits long */
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QSPI_OPT_4BIT,
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/** The option code is 8 bits long */
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QSPI_OPT_8BIT
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};
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/**
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* \brief Qspi command structure
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*/
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struct _qspi_command {
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union {
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struct {
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/* Width of QSPI Addr , inst data */
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uint32_t width : 3;
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/* Reserved */
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uint32_t reserved0 : 1;
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/* Enable Instruction */
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uint32_t inst_en : 1;
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/* Enable Address */
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uint32_t addr_en : 1;
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/* Enable Option */
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uint32_t opt_en : 1;
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/* Enable Data */
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uint32_t data_en : 1;
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/* Option Length */
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uint32_t opt_len : 2;
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/* Address Length */
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uint32_t addr_len : 1;
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/* Option Length */
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uint32_t reserved1 : 1;
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/* Transfer type */
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uint32_t tfr_type : 2;
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/* Continuous read mode */
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uint32_t continues_read : 1;
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/* Enable Double Data Rate */
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uint32_t ddr_enable : 1;
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/* Dummy Cycles Length */
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uint32_t dummy_cycles : 5;
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/* Reserved */
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uint32_t reserved3 : 11;
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} bits;
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uint32_t word;
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} inst_frame;
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uint8_t instruction;
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uint8_t option;
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uint32_t address;
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size_t buf_len;
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const void *tx_buf;
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void * rx_buf;
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};
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#ifdef __cplusplus
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}
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#endif
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/**@}*/
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#endif /* ifndef _HPL_QSPI_H_INCLUDED */
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