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85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/* Auto-generated config file hpl_qspi_config.h */
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#ifndef HPL_QSPI_CONFIG_H
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#define HPL_QSPI_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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// <h> Basic settings
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#ifndef CONF_CONF_QSPI_ENABLE
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#define CONF_CONF_QSPI_ENABLE 1
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#endif
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// <o> Baud rate <1-150000000>
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// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
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// <id> qspi_baud_rate
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#ifndef CONF_QSPI_BAUD
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#define CONF_QSPI_BAUD 375000
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#endif
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// <o> Clock Polarity
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// <0x0=>The inactive state value of SPCK is logic level zero.
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// <0x1=>The inactive state value of SPCK is logic level one.
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// <i> Determines the inactive state value of the serial clock (SPCK).
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// <id> qspi_cpol
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#ifndef CONF_QSPI_CPOL
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#define CONF_QSPI_CPOL 0x0
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#endif
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// <o> Clock Phase
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// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
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// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
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// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
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// <id> qspi_cpha
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#ifndef CONF_QSPI_CPHA
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#define CONF_QSPI_CPHA 0x0
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#endif
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// </h>
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// <e> Advanced Configuration
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// <id> qspi_advanced
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#ifndef CONF_QSPI_ADVANCED
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#define CONF_QSPI_ADVANCED 0
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#endif
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// <o> Delay Before QSCK (ns) <0-255000>
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// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
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// <id> qspi_dlybs
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#ifndef CONF_QSPI_DLY_BS
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#define CONF_QSPI_DLY_BS 0
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#endif
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// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
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// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
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// <id> qspi_dlycs
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#ifndef CONF_QSPI_DLY_CS
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#define CONF_QSPI_DLY_CS 0
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#endif
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// </e>
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/* Calculate baud register value from requested baudrate value */
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#ifndef CONF_QSPI_BAUD_RATE
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#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
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#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
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#warning Invalid baudrate, please check.
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#endif
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#endif
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/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
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#ifndef CONF_QSPI_DLYCS
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#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
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#endif
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/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
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#ifndef CONF_QSPI_DLYBS
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#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_QSPI_CONFIG_H
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