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299 lines
7.7 KiB
C
299 lines
7.7 KiB
C
/**
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* \file
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*
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* \brief SAM PCC
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAME54_PCC_COMPONENT_
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#ifndef _HRI_PCC_E54_H_INCLUDED_
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#define _HRI_PCC_E54_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_PCC_CRITICAL_SECTIONS)
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#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define PCC_CRITICAL_SECTION_ENTER()
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#define PCC_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_pcc_imr_reg_t;
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typedef uint32_t hri_pcc_isr_reg_t;
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typedef uint32_t hri_pcc_mr_reg_t;
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typedef uint32_t hri_pcc_rhr_reg_t;
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typedef uint32_t hri_pcc_wpmr_reg_t;
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typedef uint32_t hri_pcc_wpsr_reg_t;
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static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw)
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{
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((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
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}
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static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw)
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{
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return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos;
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}
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static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
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} else {
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((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
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}
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}
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static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw)
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{
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((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
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}
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static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw)
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{
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((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
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}
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static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw)
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{
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return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos;
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}
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static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
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} else {
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((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
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}
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}
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static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw)
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{
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((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
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}
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static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
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{
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((Pcc *)hw)->IER.reg = mask;
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}
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static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Pcc *)hw)->IMR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw)
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{
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return ((Pcc *)hw)->IMR.reg;
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}
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static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data)
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{
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((Pcc *)hw)->IER.reg = data;
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((Pcc *)hw)->IDR.reg = ~data;
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}
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static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
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{
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((Pcc *)hw)->IDR.reg = mask;
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}
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static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw)
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{
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return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos;
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}
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static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw)
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{
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return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos;
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}
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static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Pcc *)hw)->ISR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw)
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{
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return ((Pcc *)hw)->ISR.reg;
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}
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static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask)
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{
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return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos;
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}
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static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw)
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{
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return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos;
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}
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static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Pcc *)hw)->RHR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw)
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{
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return ((Pcc *)hw)->RHR.reg;
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}
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static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw)
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{
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return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos;
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}
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static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask)
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{
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return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos;
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}
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static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw)
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{
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return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos;
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}
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static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Pcc *)hw)->WPSR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw)
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{
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return ((Pcc *)hw)->WPSR.reg;
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}
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static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->MR.reg |= mask;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Pcc *)hw)->MR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->MR.reg = data;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->MR.reg &= ~mask;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->MR.reg ^= mask;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw)
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{
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return ((Pcc *)hw)->MR.reg;
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}
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static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->WPMR.reg |= mask;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Pcc *)hw)->WPMR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->WPMR.reg = data;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->WPMR.reg &= ~mask;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
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{
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PCC_CRITICAL_SECTION_ENTER();
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((Pcc *)hw)->WPMR.reg ^= mask;
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PCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw)
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{
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return ((Pcc *)hw)->WPMR.reg;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HRI_PCC_E54_H_INCLUDED */
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#endif /* _SAME54_PCC_COMPONENT_ */
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