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stable
Penguin 5 years ago
parent 554184343e
commit 8d8856f22e
180 changed files with 237998 additions and 237998 deletions
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2
README.md
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# Embedded-Graphics-Learning
# Embedded-Graphics-Learning

1124
electrical/same54_dev_board/BRAIN.sch
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1124
electrical/same54_dev_board/BRAIN.sch-bak
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6
electrical/same54_dev_board/NCP349MNAETBG.dcm
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library

44
electrical/same54_dev_board/NCP349MNAETBG.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# NCP349MNAETBG
#
DEF NCP349MNAETBG U 0 40 Y Y 1 F N
F0 "U" 0 -200 50 H V C CNN
F1 "NCP349MNAETBG" 0 350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -300 250 300 -150 0 1 0 f
X VIN 1 -400 150 100 R 50 50 1 1 I
X GND 2 -400 50 100 R 50 50 1 1 I
X ~FLAG 3 400 150 100 L 50 50 1 1 I
X ~EN 4 -400 -50 100 R 50 50 1 1 I
X OUT 5 400 50 100 L 50 50 1 1 I
X OUT 6 400 -50 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# NCP349MNAETBG
#
DEF NCP349MNAETBG U 0 40 Y Y 1 F N
F0 "U" 0 -200 50 H V C CNN
F1 "NCP349MNAETBG" 0 350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -300 250 300 -150 0 1 0 f
X VIN 1 -400 150 100 R 50 50 1 1 I
X GND 2 -400 50 100 R 50 50 1 1 I
X ~FLAG 3 400 150 100 L 50 50 1 1 I
X ~EN 4 -400 -50 100 R 50 50 1 1 I
X OUT 5 400 50 100 L 50 50 1 1 I
X OUT 6 400 -50 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library

802
electrical/same54_dev_board/Power.sch
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC

802
electrical/same54_dev_board/Power.sch-bak
Unescape Escape View File

@ -1,401 +1,401 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC

1312
electrical/same54_dev_board/SCREEN_INTF.sch
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1312
electrical/same54_dev_board/SCREEN_INTF.sch-bak
View File

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564
electrical/same54_dev_board/USB_INTF.sch
Unescape Escape View File

@ -1,282 +1,282 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC

564
electrical/same54_dev_board/USB_INTF.sch-bak
Unescape Escape View File

@ -1,282 +1,282 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC

157530
electrical/same54_dev_board/fp-info-cache
View File

File diff suppressed because it is too large Load Diff

6
electrical/same54_dev_board/fp-lib-table
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(fp_lib_table
(lib (name proj_modules)(type KiCad)(uri ${KIPRJMOD}/modules/proj_modules.pretty)(options "")(descr ""))
)
(fp_lib_table
(lib (name proj_modules)(type KiCad)(uri ${KIPRJMOD}/modules/proj_modules.pretty)(options "")(descr ""))
)

18
electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.bck
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EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library

18
electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.dcm
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EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library

198
electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Conn_02x20_Odd_Even_LCD_INTF
#
DEF Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N
F0 "J" 0 -1100 50 H V C CNN
F1 "Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN
F2 "" -400 0 50 H I C CNN
F3 "" -400 0 50 H I C CNN
$FPLIST
Connector*:*_2x??-1MP*
$ENDFPLIST
DRAW
S -450 -995 -400 -1005 1 1 6 N
S -450 -895 -400 -905 1 1 6 N
S -450 -795 -400 -805 1 1 6 N
S -450 -695 -400 -705 1 1 6 N
S -450 -595 -400 -605 1 1 6 N
S -450 -495 -400 -505 1 1 6 N
S -450 -395 -400 -405 1 1 6 N
S -450 -295 -400 -305 1 1 6 N
S -450 -195 -400 -205 1 1 6 N
S -450 -95 -400 -105 1 1 6 N
S -450 5 -400 -5 1 1 6 N
S -450 105 -400 95 1 1 6 N
S -450 205 -400 195 1 1 6 N
S -450 305 -400 295 1 1 6 N
S -450 405 -400 395 1 1 6 N
S -450 505 -400 495 1 1 6 N
S -450 605 -400 595 1 1 6 N
S -450 705 -400 695 1 1 6 N
S -450 805 -400 795 1 1 6 N
S -450 905 -400 895 1 1 6 N
S -450 950 450 -1050 1 1 10 f
S 450 -995 400 -1005 1 1 6 N
S 450 -895 400 -905 1 1 6 N
S 450 -795 400 -805 1 1 6 N
S 450 -695 400 -705 1 1 6 N
S 450 -595 400 -605 1 1 6 N
S 450 -495 400 -505 1 1 6 N
S 450 -395 400 -405 1 1 6 N
S 450 -295 400 -305 1 1 6 N
S 450 -195 400 -205 1 1 6 N
S 450 -95 400 -105 1 1 6 N
S 450 5 400 -5 1 1 6 N
S 450 105 400 95 1 1 6 N
S 450 205 400 195 1 1 6 N
S 450 305 400 295 1 1 6 N
S 450 405 400 395 1 1 6 N
S 450 505 400 495 1 1 6 N
S 450 605 400 595 1 1 6 N
S 450 705 400 695 1 1 6 N
S 450 805 400 795 1 1 6 N
S 450 905 400 895 1 1 6 N
X VCC 1 -600 900 150 R 50 50 1 1 W
X ~TFT_WR 10 600 500 150 L 50 50 1 1 P
X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P
X TFT_TE 12 600 400 150 L 50 50 1 1 I
X TFT_D0 13 -600 300 150 R 50 50 1 1 P
X TFT_D1 14 600 300 150 L 50 50 1 1 P
X TFT_D2 15 -600 200 150 R 50 50 1 1 P
X TFT_D3 16 600 200 150 L 50 50 1 1 P
X TFT_D4 17 -600 100 150 R 50 50 1 1 P
X TFT_D5 18 600 100 150 L 50 50 1 1 P
X TFT_D6 19 -600 0 150 R 50 50 1 1 P
X GND 2 600 900 150 L 50 50 1 1 P
X TFT_D7 20 600 0 150 L 50 50 1 1 P
X TFT_D8 21 -600 -100 150 R 50 50 1 1 P
X TFT_D9 22 600 -100 150 L 50 50 1 1 P
X TFT_D10 23 -600 -200 150 R 50 50 1 1 P
X TFT_D11 24 600 -200 150 L 50 50 1 1 P
X TFT_D12 25 -600 -300 150 R 50 50 1 1 P
X TFT_D13 26 600 -300 150 L 50 50 1 1 P
X TFT_D14 27 -600 -400 150 R 50 50 1 1 P
X TFT_D15 28 600 -400 150 L 50 50 1 1 P
X TFT_D16 29 -600 -500 150 R 50 50 1 1 P
X CPT_SCL 3 -600 800 150 R 50 50 1 1 P
X TFT_D17 30 600 -500 150 L 50 50 1 1 P
X TFT_D18 31 -600 -600 150 R 50 50 1 1 P
X TFT_D19 32 600 -600 150 L 50 50 1 1 P
X TFT_D20 33 -600 -700 150 R 50 50 1 1 P
X TFT_D21 34 600 -700 150 L 50 50 1 1 P
X TFT_D22 35 -600 -800 150 R 50 50 1 1 P
X TFT_D23 36 600 -800 150 L 50 50 1 1 P
X TFT_STB 37 -600 -900 150 R 50 50 1 1 P
X NC 38 600 -900 150 L 50 50 1 1 N
X Pin_39 39 -600 -1000 150 R 50 50 1 1 P
X CPT_SDA 4 600 800 150 L 50 50 1 1 P
X NC 40 600 -1000 150 L 50 50 1 1 N
X CPT_INT 5 -600 700 150 R 50 50 1 1 P
X TFT_GPO 6 600 700 150 L 50 50 1 1 O
X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P
X TFT_D/C 8 600 600 150 L 50 50 1 1 P
X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Conn_02x20_Odd_Even_LCD_INTF
#
DEF Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N
F0 "J" 0 -1100 50 H V C CNN
F1 "Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN
F2 "" -400 0 50 H I C CNN
F3 "" -400 0 50 H I C CNN
$FPLIST
Connector*:*_2x??-1MP*
$ENDFPLIST
DRAW
S -450 -995 -400 -1005 1 1 6 N
S -450 -895 -400 -905 1 1 6 N
S -450 -795 -400 -805 1 1 6 N
S -450 -695 -400 -705 1 1 6 N
S -450 -595 -400 -605 1 1 6 N
S -450 -495 -400 -505 1 1 6 N
S -450 -395 -400 -405 1 1 6 N
S -450 -295 -400 -305 1 1 6 N
S -450 -195 -400 -205 1 1 6 N
S -450 -95 -400 -105 1 1 6 N
S -450 5 -400 -5 1 1 6 N
S -450 105 -400 95 1 1 6 N
S -450 205 -400 195 1 1 6 N
S -450 305 -400 295 1 1 6 N
S -450 405 -400 395 1 1 6 N
S -450 505 -400 495 1 1 6 N
S -450 605 -400 595 1 1 6 N
S -450 705 -400 695 1 1 6 N
S -450 805 -400 795 1 1 6 N
S -450 905 -400 895 1 1 6 N
S -450 950 450 -1050 1 1 10 f
S 450 -995 400 -1005 1 1 6 N
S 450 -895 400 -905 1 1 6 N
S 450 -795 400 -805 1 1 6 N
S 450 -695 400 -705 1 1 6 N
S 450 -595 400 -605 1 1 6 N
S 450 -495 400 -505 1 1 6 N
S 450 -395 400 -405 1 1 6 N
S 450 -295 400 -305 1 1 6 N
S 450 -195 400 -205 1 1 6 N
S 450 -95 400 -105 1 1 6 N
S 450 5 400 -5 1 1 6 N
S 450 105 400 95 1 1 6 N
S 450 205 400 195 1 1 6 N
S 450 305 400 295 1 1 6 N
S 450 405 400 395 1 1 6 N
S 450 505 400 495 1 1 6 N
S 450 605 400 595 1 1 6 N
S 450 705 400 695 1 1 6 N
S 450 805 400 795 1 1 6 N
S 450 905 400 895 1 1 6 N
X VCC 1 -600 900 150 R 50 50 1 1 W
X ~TFT_WR 10 600 500 150 L 50 50 1 1 P
X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P
X TFT_TE 12 600 400 150 L 50 50 1 1 I
X TFT_D0 13 -600 300 150 R 50 50 1 1 P
X TFT_D1 14 600 300 150 L 50 50 1 1 P
X TFT_D2 15 -600 200 150 R 50 50 1 1 P
X TFT_D3 16 600 200 150 L 50 50 1 1 P
X TFT_D4 17 -600 100 150 R 50 50 1 1 P
X TFT_D5 18 600 100 150 L 50 50 1 1 P
X TFT_D6 19 -600 0 150 R 50 50 1 1 P
X GND 2 600 900 150 L 50 50 1 1 P
X TFT_D7 20 600 0 150 L 50 50 1 1 P
X TFT_D8 21 -600 -100 150 R 50 50 1 1 P
X TFT_D9 22 600 -100 150 L 50 50 1 1 P
X TFT_D10 23 -600 -200 150 R 50 50 1 1 P
X TFT_D11 24 600 -200 150 L 50 50 1 1 P
X TFT_D12 25 -600 -300 150 R 50 50 1 1 P
X TFT_D13 26 600 -300 150 L 50 50 1 1 P
X TFT_D14 27 -600 -400 150 R 50 50 1 1 P
X TFT_D15 28 600 -400 150 L 50 50 1 1 P
X TFT_D16 29 -600 -500 150 R 50 50 1 1 P
X CPT_SCL 3 -600 800 150 R 50 50 1 1 P
X TFT_D17 30 600 -500 150 L 50 50 1 1 P
X TFT_D18 31 -600 -600 150 R 50 50 1 1 P
X TFT_D19 32 600 -600 150 L 50 50 1 1 P
X TFT_D20 33 -600 -700 150 R 50 50 1 1 P
X TFT_D21 34 600 -700 150 L 50 50 1 1 P
X TFT_D22 35 -600 -800 150 R 50 50 1 1 P
X TFT_D23 36 600 -800 150 L 50 50 1 1 P
X TFT_STB 37 -600 -900 150 R 50 50 1 1 P
X NC 38 600 -900 150 L 50 50 1 1 N
X Pin_39 39 -600 -1000 150 R 50 50 1 1 P
X CPT_SDA 4 600 800 150 L 50 50 1 1 P
X NC 40 600 -1000 150 L 50 50 1 1 N
X CPT_INT 5 -600 700 150 R 50 50 1 1 P
X TFT_GPO 6 600 700 150 L 50 50 1 1 O
X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P
X TFT_D/C 8 600 600 150 L 50 50 1 1 P
X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

6
electrical/same54_dev_board/libraries/MAX7301AAX_.dcm
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library

120
electrical/same54_dev_board/libraries/MAX7301AAX_.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# MAX7301AAX+
#
DEF MAX7301AAX+ U 0 40 Y Y 1 L N
F0 "U" -500 1339 50 H V L BNN
F1 "MAX7301AAX+" -500 -1457 50 H V L BNN
F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN
F3 "Maxim Integrated" 0 0 50 H I L BNN
F4 "None" 0 0 50 H I L BNN
F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN
F6 "SSOP-36 Maxim" 0 0 50 H I L BNN
F7 "Unavailable" 0 0 50 H I L BNN
F8 "MAX7301AAX+" 0 0 50 H I L BNN
DRAW
P 2 0 0 16 -500 -1300 -500 1300 N
P 2 0 0 16 -500 1300 500 1300 N
P 2 0 0 16 500 -1300 -500 -1300 N
P 2 0 0 16 500 1300 500 -1300 N
X ISET 1 -700 1000 200 R 40 40 0 0 I
X P9 10 -700 0 200 R 40 40 0 0 B
X P10 11 -700 -100 200 R 40 40 0 0 B
X P11 12 -700 -200 200 R 40 40 0 0 B
X P12 13 -700 -300 200 R 40 40 0 0 B
X P13 14 -700 -400 200 R 40 40 0 0 B
X P14 15 -700 -500 200 R 40 40 0 0 B
X P15 16 -700 -600 200 R 40 40 0 0 B
X P16 17 -700 -700 200 R 40 40 0 0 B
X P17 18 -700 -800 200 R 40 40 0 0 B
X P18 19 700 500 200 L 40 40 0 0 B
X GND 2 700 -1100 200 L 40 40 0 0 W
X P19 20 700 400 200 L 40 40 0 0 B
X P20 21 700 300 200 L 40 40 0 0 B
X P21 22 700 200 200 L 40 40 0 0 B
X P22 23 700 100 200 L 40 40 0 0 B
X P23 24 700 0 200 L 40 40 0 0 B
X P24 25 700 -100 200 L 40 40 0 0 B
X P25 26 700 -200 200 L 40 40 0 0 B
X P26 27 700 -300 200 L 40 40 0 0 B
X P27 28 700 -400 200 L 40 40 0 0 B
X P28 29 700 -500 200 L 40 40 0 0 B
X GND 3 700 -1000 200 L 40 40 0 0 W
X P29 30 700 -600 200 L 40 40 0 0 B
X P30 31 700 -700 200 L 40 40 0 0 B
X P31 32 700 -800 200 L 40 40 0 0 B
X SCLK 33 700 900 200 L 40 40 0 0 I C
X DIN 34 700 800 200 L 40 40 0 0 I
X CS 35 700 1000 200 L 40 40 0 0 I
X V+ 36 700 1200 200 L 40 40 0 0 W
X DOUT 4 700 700 200 L 40 40 0 0 O
X P4 5 -700 500 200 R 40 40 0 0 B
X P5 6 -700 400 200 R 40 40 0 0 B
X P6 7 -700 300 200 R 40 40 0 0 B
X P7 8 -700 200 200 R 40 40 0 0 B
X P8 9 -700 100 200 R 40 40 0 0 B
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# MAX7301AAX+
#
DEF MAX7301AAX+ U 0 40 Y Y 1 L N
F0 "U" -500 1339 50 H V L BNN
F1 "MAX7301AAX+" -500 -1457 50 H V L BNN
F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN
F3 "Maxim Integrated" 0 0 50 H I L BNN
F4 "None" 0 0 50 H I L BNN
F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN
F6 "SSOP-36 Maxim" 0 0 50 H I L BNN
F7 "Unavailable" 0 0 50 H I L BNN
F8 "MAX7301AAX+" 0 0 50 H I L BNN
DRAW
P 2 0 0 16 -500 -1300 -500 1300 N
P 2 0 0 16 -500 1300 500 1300 N
P 2 0 0 16 500 -1300 -500 -1300 N
P 2 0 0 16 500 1300 500 -1300 N
X ISET 1 -700 1000 200 R 40 40 0 0 I
X P9 10 -700 0 200 R 40 40 0 0 B
X P10 11 -700 -100 200 R 40 40 0 0 B
X P11 12 -700 -200 200 R 40 40 0 0 B
X P12 13 -700 -300 200 R 40 40 0 0 B
X P13 14 -700 -400 200 R 40 40 0 0 B
X P14 15 -700 -500 200 R 40 40 0 0 B
X P15 16 -700 -600 200 R 40 40 0 0 B
X P16 17 -700 -700 200 R 40 40 0 0 B
X P17 18 -700 -800 200 R 40 40 0 0 B
X P18 19 700 500 200 L 40 40 0 0 B
X GND 2 700 -1100 200 L 40 40 0 0 W
X P19 20 700 400 200 L 40 40 0 0 B
X P20 21 700 300 200 L 40 40 0 0 B
X P21 22 700 200 200 L 40 40 0 0 B
X P22 23 700 100 200 L 40 40 0 0 B
X P23 24 700 0 200 L 40 40 0 0 B
X P24 25 700 -100 200 L 40 40 0 0 B
X P25 26 700 -200 200 L 40 40 0 0 B
X P26 27 700 -300 200 L 40 40 0 0 B
X P27 28 700 -400 200 L 40 40 0 0 B
X P28 29 700 -500 200 L 40 40 0 0 B
X GND 3 700 -1000 200 L 40 40 0 0 W
X P29 30 700 -600 200 L 40 40 0 0 B
X P30 31 700 -700 200 L 40 40 0 0 B
X P31 32 700 -800 200 L 40 40 0 0 B
X SCLK 33 700 900 200 L 40 40 0 0 I C
X DIN 34 700 800 200 L 40 40 0 0 I
X CS 35 700 1000 200 L 40 40 0 0 I
X V+ 36 700 1200 200 L 40 40 0 0 W
X DOUT 4 700 700 200 L 40 40 0 0 O
X P4 5 -700 500 200 R 40 40 0 0 B
X P5 6 -700 400 200 R 40 40 0 0 B
X P6 7 -700 300 200 R 40 40 0 0 B
X P7 8 -700 200 200 R 40 40 0 0 B
X P8 9 -700 100 200 R 40 40 0 0 B
ENDDRAW
ENDDEF
#
#End Library

6
electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.dcm
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library

30
electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# TPS73733QDRBRQ1
#
DEF TPS73733QDRBRQ1 U 0 40 Y Y 1 F N
F0 "U" 0 -400 50 H V C CNN
F1 "TPS73733QDRBRQ1" 0 450 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# TPS73733QDRBRQ1
#
DEF TPS73733QDRBRQ1 U 0 40 Y Y 1 F N
F0 "U" 0 -400 50 H V C CNN
F1 "TPS73733QDRBRQ1" 0 450 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
ENDDRAW
ENDDEF
#
#End Library

114
electrical/same54_dev_board/modules/proj_modules.pretty/SOP80P1030X264-36N.kicad_mod
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(module SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418)
(descr "")
(fp_text reference REF** (at -2.415 -8.587 0) (layer F.SilkS)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_text value SOP80P1030X264-36N (at 5.84 8.587 0) (layer F.Fab)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2))
(fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2))
(fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127))
(fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127))
(fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127))
(fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127))
(fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127))
(fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127))
(fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 2 smd rect (at -4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 7 smd rect (at -4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 12 smd rect (at -4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 17 smd rect (at -4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 20 smd rect (at 4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 25 smd rect (at 4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 30 smd rect (at 4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 35 smd rect (at 4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(module SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418)
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electrical/same54_dev_board/same54_dev_board-cache.lib
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electrical/same54_dev_board/same54_dev_board.kicad_pcb
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electrical/same54_dev_board/same54_dev_board.pro
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@ -1,43 +1,43 @@
update=Sun 19 Apr 2020 04:53:03 PM CDT
version=1
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update=Sun 19 Apr 2020 04:53:03 PM CDT
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[general]
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456
electrical/same54_dev_board/same54_dev_board.sch
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@ -1,228 +1,228 @@
EESchema Schematic File Version 4
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Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain.
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456
electrical/same54_dev_board/same54_dev_board.sch-bak
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Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain.
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A 11000 8500
encoding utf-8
Sheet 1 5
Title "Project Oracle"
Date "2020-03-16"
Rev "v0.1"
Comp ""
Comment1 ""
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Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain.
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12
electrical/same54_dev_board/sym-lib-table
Unescape Escape View File

@ -1,6 +1,6 @@
(sym_lib_table
(lib (name same54_dev_board-rescue)(type Legacy)(uri ${KIPRJMOD}/same54_dev_board-rescue.lib)(options "")(descr ""))
(lib (name Conn_02x20_LCD_INTF)(type Legacy)(uri ${KIPRJMOD}/libraries/Conn_02x20_LCD_INTF.lib)(options "")(descr ""))
(lib (name MAX7301AAX_)(type Legacy)(uri ${KIPRJMOD}/libraries/MAX7301AAX_.lib)(options "")(descr ""))
(lib (name TPS73733QDRBRQ1)(type Legacy)(uri ${KIPRJMOD}/libraries/TPS73733QDRBRQ1.lib)(options "")(descr ""))
)
(sym_lib_table
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(lib (name Conn_02x20_LCD_INTF)(type Legacy)(uri ${KIPRJMOD}/libraries/Conn_02x20_LCD_INTF.lib)(options "")(descr ""))
(lib (name MAX7301AAX_)(type Legacy)(uri ${KIPRJMOD}/libraries/MAX7301AAX_.lib)(options "")(descr ""))
(lib (name TPS73733QDRBRQ1)(type Legacy)(uri ${KIPRJMOD}/libraries/TPS73733QDRBRQ1.lib)(options "")(descr ""))
)

34
software/README.md
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@ -1,17 +1,17 @@
# Software Readme
## Goals
- Fish Tank Controller that will monitor and send updates via wifi (or ethernet idk yet???)
## To Do
- PCB
- Decide on core reqs (ex: do i want wifi or NOT)
- map pins
- create bare software for pin mappings
- fix asf4 vomit <<<emoji here>>>
- Get make based asf4 project to compile (i have toolchains wtf why no work)
## Info
# Software Readme
## Goals
- Fish Tank Controller that will monitor and send updates via wifi (or ethernet idk yet???)
## To Do
- PCB
- Decide on core reqs (ex: do i want wifi or NOT)
- map pins
- create bare software for pin mappings
- fix asf4 vomit <<<emoji here>>>
- Get make based asf4 project to compile (i have toolchains wtf why no work)
## Info

2354
software/conf/project_oractle_config.atstart
View File

File diff suppressed because it is too large Load Diff

12
software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf
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@ -1,6 +1,6 @@
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
</device-packs>
</environment>
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
</device-packs>
</environment>

430
software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc
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@ -1,215 +1,215 @@
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
<vendor>Atmel</vendor>
<name>My Project</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
<releases>
<release version="1.0.1">Initial version</release>
</releases>
<taxonomy>
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
</taxonomy>
<generators>
<generator id="AtmelStart">
<description>Atmel Start</description>
<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
<command>http://start.atmel.com/</command>
<files>
<file category="generator" name="atmel_start_config.atstart"/>
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
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</generator>
</generators>
<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
</condition>
<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="GCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
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</package>
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<name>My Project</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
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<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
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<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
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<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="GCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
</files>
</component>
</components>
</package>

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart
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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h
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/* Auto-generated config file hpl_cmcc_config.h */
#ifndef HPL_CMCC_CONFIG_H
#define HPL_CMCC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Configuration
// <q> Cache enable
//<i> Defines the cache should be enabled or not.
// <id> cmcc_enable
#ifndef CONF_CMCC_ENABLE
#define CONF_CMCC_ENABLE 0x0
#endif
// <o> Cache Size
//<i> Defines the cache memory size to be configured.
// <0x0=>1 KB
// <0x1=>2 KB
// <0x2=>4 KB
// <id> cache_size
#ifndef CONF_CMCC_CACHE_SIZE
#define CONF_CMCC_CACHE_SIZE 0x2
#endif
// <e> Advanced Configuration
// <id> cmcc_advanced_configuration
// <q> Data cache disable
//<i> Defines the data cache should be disabled or not.
// <id> cmcc_data_cache_disable
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
#endif
// <q> Instruction cache disable
//<i> Defines the Instruction cache should be disabled or not.
// <id> cmcc_inst_cache_disable
#ifndef CONF_CMCC_INST_CACHE_DISABLE
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
#endif
// <q> Clock Gating disable
//<i> Defines the clock gating should be disabled or not.
// <id> cmcc_clock_gating_disable
#ifndef CONF_CMCC_CLK_GATING_DISABLE
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_CMCC_CONFIG_H
/* Auto-generated config file hpl_cmcc_config.h */
#ifndef HPL_CMCC_CONFIG_H
#define HPL_CMCC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Configuration
// <q> Cache enable
//<i> Defines the cache should be enabled or not.
// <id> cmcc_enable
#ifndef CONF_CMCC_ENABLE
#define CONF_CMCC_ENABLE 0x0
#endif
// <o> Cache Size
//<i> Defines the cache memory size to be configured.
// <0x0=>1 KB
// <0x1=>2 KB
// <0x2=>4 KB
// <id> cache_size
#ifndef CONF_CMCC_CACHE_SIZE
#define CONF_CMCC_CACHE_SIZE 0x2
#endif
// <e> Advanced Configuration
// <id> cmcc_advanced_configuration
// <q> Data cache disable
//<i> Defines the data cache should be disabled or not.
// <id> cmcc_data_cache_disable
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
#endif
// <q> Instruction cache disable
//<i> Defines the Instruction cache should be disabled or not.
// <id> cmcc_inst_cache_disable
#ifndef CONF_CMCC_INST_CACHE_DISABLE
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
#endif
// <q> Clock Gating disable
//<i> Defines the clock gating should be disabled or not.
// <id> cmcc_clock_gating_disable
#ifndef CONF_CMCC_CLK_GATING_DISABLE
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_CMCC_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h
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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h
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/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
#endif
// <y> Low Power Clock Division
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_lpdiv
#ifndef CONF_MCLK_LPDIV
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
#endif
// <y> High-Speed Clock Division
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
// <id> mclk_arch_hsdiv
#ifndef CONF_MCLK_HSDIV
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 5
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H
/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
#endif
// <y> Low Power Clock Division
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_lpdiv
#ifndef CONF_MCLK_LPDIV
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
#endif
// <y> High-Speed Clock Division
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
// <id> mclk_arch_hsdiv
#ifndef CONF_MCLK_HSDIV
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 5
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h
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/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 0
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x3
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 1
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// <o> Control Gain Mode
// <0x0=>Low Power mode
// <0x1=>Standard mode
// <0x2=>High Speed mode
// <id> xosc32k_arch_cgm
#ifndef CONF_XOSC32K_CGM
#define CONF_XOSC32K_CGM 0x1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x3F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H
/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 0
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x3
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 1
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// <o> Control Gain Mode
// <0x0=>Low Power mode
// <0x1=>Standard mode
// <0x2=>High Speed mode
// <id> xosc32k_arch_cgm
#ifndef CONF_XOSC32K_CGM
#define CONF_XOSC32K_CGM 0x1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x3F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h
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/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef CONF_SERCOM_2_USART_ENABLE
#define CONF_SERCOM_2_USART_ENABLE 1
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
#ifndef CONF_SERCOM_2_USART_RXEN
#define CONF_SERCOM_2_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
#ifndef CONF_SERCOM_2_USART_TXEN
#define CONF_SERCOM_2_USART_TXEN 1
#endif
// <o> Frame parity
// <0x0=>No parity
// <0x1=>Even parity
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
#ifndef CONF_SERCOM_2_USART_PARITY
#define CONF_SERCOM_2_USART_PARITY 0x0
#endif
// <o> Character Size
// <0x0=>8 bits
// <0x1=>9 bits
// <0x5=>5 bits
// <0x6=>6 bits
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
#ifndef CONF_SERCOM_2_USART_CHSIZE
#define CONF_SERCOM_2_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
// <0=>One stop bit
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
#ifndef CONF_SERCOM_2_USART_SBMODE
#define CONF_SERCOM_2_USART_SBMODE 0
#endif
// <o> Baud rate <1-6250000>
// <i> USART baud rate setting
// <id> usart_baud_rate
#ifndef CONF_SERCOM_2_USART_BAUD
#define CONF_SERCOM_2_USART_BAUD 115200
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
#define CONF_SERCOM_2_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
#ifndef CONF_SERCOM_2_USART_IBON
#define CONF_SERCOM_2_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
#ifndef CONF_SERCOM_2_USART_SFDE
#define CONF_SERCOM_2_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
#ifndef CONF_SERCOM_2_USART_CLODEN
#define CONF_SERCOM_2_USART_CLODEN 0
#endif
// <o> Operating Mode
// <0x0=>USART with external clock
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
#ifndef CONF_SERCOM_2_USART_MODE
#define CONF_SERCOM_2_USART_MODE 0x1
#endif
// <o> Sample Rate
// <0x0=>16x arithmetic
// <0x1=>16x fractional
// <0x2=>8x arithmetic
// <0x3=>8x fractional
// <0x4=>3x arithmetic
// <i> How many over-sampling bits used when sampling data state
// <id> usart_arch_sampr
#ifndef CONF_SERCOM_2_USART_SAMPR
#define CONF_SERCOM_2_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
#ifndef CONF_SERCOM_2_USART_SAMPA
#define CONF_SERCOM_2_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
// <0=>MSB is transmitted first
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
#ifndef CONF_SERCOM_2_USART_DORD
#define CONF_SERCOM_2_USART_DORD 1
#endif
// Does not do anything in UART mode
#define CONF_SERCOM_2_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
#ifndef CONF_SERCOM_2_USART_ENC
#define CONF_SERCOM_2_USART_ENC 0
#endif
// <o> LIN Slave Enable
// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
// <0=>Disable
// <1=>Enable
// <id> usart_arch_lin_slave_enable
#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_2_USART_INACK
#define CONF_SERCOM_2_USART_INACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_DSNACK
#define CONF_SERCOM_2_USART_DSNACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_MAXITER
#define CONF_SERCOM_2_USART_MAXITER 0x7
#endif
#ifndef CONF_SERCOM_2_USART_GTIME
#define CONF_SERCOM_2_USART_GTIME 0x2
#endif
#define CONF_SERCOM_2_USART_RXINV 0x0
#define CONF_SERCOM_2_USART_TXINV 0x0
#ifndef CONF_SERCOM_2_USART_CMODE
#define CONF_SERCOM_2_USART_CMODE 0
#endif
#ifndef CONF_SERCOM_2_USART_RXPO
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
#endif
#ifndef CONF_SERCOM_2_USART_TXPO
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 4
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 5
#endif
#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 0
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 1
#endif
#endif
// Calculate BAUD register value in UART mode
#if CONF_SERCOM_2_USART_SAMPR == 0
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 1
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 2
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 3
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 4
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_3_I2CM_ENABLE
#define CONF_SERCOM_3_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_3_I2CM_BAUD
#define CONF_SERCOM_3_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN
#define CONF_SERCOM_3_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN
#define CONF_SERCOM_3_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_3_I2CM_LOWTOUT
#define CONF_SERCOM_3_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_3_I2CM_INACTOUT
#define CONF_SERCOM_3_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_3_I2CM_SDAHOLD
#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY
#define CONF_SERCOM_3_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_3_I2CM_SPEED
#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215U
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \
- (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \
/ 1000U)) \
* 10U \
+ 5U) \
/ (CONF_SERCOM_3_I2CM_BAUD * 10U))
#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE
#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_3_I2CM_BAUD_RATE \
((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H
/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef CONF_SERCOM_2_USART_ENABLE
#define CONF_SERCOM_2_USART_ENABLE 1
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
#ifndef CONF_SERCOM_2_USART_RXEN
#define CONF_SERCOM_2_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
#ifndef CONF_SERCOM_2_USART_TXEN
#define CONF_SERCOM_2_USART_TXEN 1
#endif
// <o> Frame parity
// <0x0=>No parity
// <0x1=>Even parity
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
#ifndef CONF_SERCOM_2_USART_PARITY
#define CONF_SERCOM_2_USART_PARITY 0x0
#endif
// <o> Character Size
// <0x0=>8 bits
// <0x1=>9 bits
// <0x5=>5 bits
// <0x6=>6 bits
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
#ifndef CONF_SERCOM_2_USART_CHSIZE
#define CONF_SERCOM_2_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
// <0=>One stop bit
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
#ifndef CONF_SERCOM_2_USART_SBMODE
#define CONF_SERCOM_2_USART_SBMODE 0
#endif
// <o> Baud rate <1-6250000>
// <i> USART baud rate setting
// <id> usart_baud_rate
#ifndef CONF_SERCOM_2_USART_BAUD
#define CONF_SERCOM_2_USART_BAUD 115200
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
#define CONF_SERCOM_2_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
#ifndef CONF_SERCOM_2_USART_IBON
#define CONF_SERCOM_2_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
#ifndef CONF_SERCOM_2_USART_SFDE
#define CONF_SERCOM_2_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
#ifndef CONF_SERCOM_2_USART_CLODEN
#define CONF_SERCOM_2_USART_CLODEN 0
#endif
// <o> Operating Mode
// <0x0=>USART with external clock
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
#ifndef CONF_SERCOM_2_USART_MODE
#define CONF_SERCOM_2_USART_MODE 0x1
#endif
// <o> Sample Rate
// <0x0=>16x arithmetic
// <0x1=>16x fractional
// <0x2=>8x arithmetic
// <0x3=>8x fractional
// <0x4=>3x arithmetic
// <i> How many over-sampling bits used when sampling data state
// <id> usart_arch_sampr
#ifndef CONF_SERCOM_2_USART_SAMPR
#define CONF_SERCOM_2_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
#ifndef CONF_SERCOM_2_USART_SAMPA
#define CONF_SERCOM_2_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
// <0=>MSB is transmitted first
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
#ifndef CONF_SERCOM_2_USART_DORD
#define CONF_SERCOM_2_USART_DORD 1
#endif
// Does not do anything in UART mode
#define CONF_SERCOM_2_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
#ifndef CONF_SERCOM_2_USART_ENC
#define CONF_SERCOM_2_USART_ENC 0
#endif
// <o> LIN Slave Enable
// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
// <0=>Disable
// <1=>Enable
// <id> usart_arch_lin_slave_enable
#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_2_USART_INACK
#define CONF_SERCOM_2_USART_INACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_DSNACK
#define CONF_SERCOM_2_USART_DSNACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_MAXITER
#define CONF_SERCOM_2_USART_MAXITER 0x7
#endif
#ifndef CONF_SERCOM_2_USART_GTIME
#define CONF_SERCOM_2_USART_GTIME 0x2
#endif
#define CONF_SERCOM_2_USART_RXINV 0x0
#define CONF_SERCOM_2_USART_TXINV 0x0
#ifndef CONF_SERCOM_2_USART_CMODE
#define CONF_SERCOM_2_USART_CMODE 0
#endif
#ifndef CONF_SERCOM_2_USART_RXPO
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
#endif
#ifndef CONF_SERCOM_2_USART_TXPO
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 4
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 5
#endif
#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 0
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 1
#endif
#endif
// Calculate BAUD register value in UART mode
#if CONF_SERCOM_2_USART_SAMPR == 0
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 1
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 2
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 3
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 4
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_3_I2CM_ENABLE
#define CONF_SERCOM_3_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_3_I2CM_BAUD
#define CONF_SERCOM_3_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN
#define CONF_SERCOM_3_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN
#define CONF_SERCOM_3_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_3_I2CM_LOWTOUT
#define CONF_SERCOM_3_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_3_I2CM_INACTOUT
#define CONF_SERCOM_3_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_3_I2CM_SDAHOLD
#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY
#define CONF_SERCOM_3_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_3_I2CM_SPEED
#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215U
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \
- (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \
/ 1000U)) \
* 10U \
+ 5U) \
/ (CONF_SERCOM_3_I2CM_BAUD * 10U))
#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE
#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_3_I2CM_BAUD_RATE \
((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h
Unescape Escape View File

@ -1,180 +1,180 @@
/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 1
#endif
#include "peripheral_clk_config.h"
// <h> Basic configuration
// <o> Prescaler
// <0x0=> No division
// <0x1=> Divide by 2
// <0x2=> Divide by 4
// <0x3=> Divide by 8
// <0x4=> Divide by 16
// <0x5=> Divide by 64
// <0x6=> Divide by 256
// <0x7=> Divide by 1024
// <i> This defines the prescaler value
// <id> timer_prescaler
#ifndef CONF_TC0_PRESCALER
#define CONF_TC0_PRESCALER 0x3
#endif
// <o> Length of one timer tick in uS <0-4294967295>
// <id> timer_tick
#ifndef CONF_TC0_TIMER_TICK
#define CONF_TC0_TIMER_TICK 1000
#endif
// </h>
// <e> Advanced configuration
// <id> timer_advanced_configuration
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC0_PRESCSYNC
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <q> Run in standby
// <i> Indicates whether the module will continue to run in standby sleep mode
// <id> tc_arch_runstdby
#ifndef CONF_TC0_RUNSTDBY
#define CONF_TC0_RUNSTDBY 0
#endif
// <q> Run in debug mode
// <i> Indicates whether the module will run in debug mode
// <id> tc_arch_dbgrun
#ifndef CONF_TC0_DBGRUN
#define CONF_TC0_DBGRUN 0
#endif
// <q> Run on demand
// <i> Run if requested by some other peripheral in the device
// <id> tc_arch_ondemand
#ifndef CONF_TC0_ONDEMAND
#define CONF_TC0_ONDEMAND 0
#endif
// </e>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
#endif
// <q> Output Event On Match or Capture on Channel 0
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo0
#ifndef CONF_TC0_MCEO0
#define CONF_TC0_MCEO0 0
#endif
// <q> Output Event On Match or Capture on Channel 1
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo1
#ifndef CONF_TC0_MCEO1
#define CONF_TC0_MCEO1 0
#endif
// <q> Output Event On Timer Tick
// <i> Enable output of event on timer tick
// <id> tc_arch_ovfeo
#ifndef CONF_TC0_OVFEO
#define CONF_TC0_OVFEO 0
#endif
// <q> Event Input
// <i> Enable asynchronous input events
// <id> tc_arch_tcei
#ifndef CONF_TC0_TCEI
#define CONF_TC0_TCEI 0
#endif
// <q> Inverted Event Input
// <i> Invert the asynchronous input events
// <id> tc_arch_tcinv
#ifndef CONF_TC0_TCINV
#define CONF_TC0_TCINV 0
#endif
// <o> Event action
// <0=> Event action disabled
// <1=> Start, restart or re-trigger TC on event
// <2=> Count on event
// <3=> Start on event
// <4=> Time stamp capture
// <5=> Period captured in CC0, pulse width in CC1
// <6=> Period captured in CC1, pulse width in CC0
// <7=> Pulse width capture
// <i> Event which will be performed on an event
//<id> tc_arch_evact
#ifndef CONF_TC0_EVACT
#define CONF_TC0_EVACT 0
#endif
// </e>
// Default values which the driver needs in order to work correctly
// Mode set to 32-bit
#ifndef CONF_TC0_MODE
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
#endif
// CC 1 register set to 0
#ifndef CONF_TC0_CC1
#define CONF_TC0_CC1 0
#endif
#ifndef CONF_TC0_ALOCK
#define CONF_TC0_ALOCK 0
#endif
// Not used in 32-bit mode
#define CONF_TC0_PER 0
// Calculating correct top value based on requested tick interval.
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
// Prescaler set to 64
#if CONF_TC0_PRESCALER > 0x4
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 64
#endif
// Prescaler set to 256
#if CONF_TC0_PRESCALER > 0x5
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 256
#endif
// Prescaler set to 1024
#if CONF_TC0_PRESCALER > 0x6
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 1024
#endif
#ifndef CONF_TC0_CC0
#define CONF_TC0_CC0 \
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
#endif
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H
/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 1
#endif
#include "peripheral_clk_config.h"
// <h> Basic configuration
// <o> Prescaler
// <0x0=> No division
// <0x1=> Divide by 2
// <0x2=> Divide by 4
// <0x3=> Divide by 8
// <0x4=> Divide by 16
// <0x5=> Divide by 64
// <0x6=> Divide by 256
// <0x7=> Divide by 1024
// <i> This defines the prescaler value
// <id> timer_prescaler
#ifndef CONF_TC0_PRESCALER
#define CONF_TC0_PRESCALER 0x3
#endif
// <o> Length of one timer tick in uS <0-4294967295>
// <id> timer_tick
#ifndef CONF_TC0_TIMER_TICK
#define CONF_TC0_TIMER_TICK 1000
#endif
// </h>
// <e> Advanced configuration
// <id> timer_advanced_configuration
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC0_PRESCSYNC
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <q> Run in standby
// <i> Indicates whether the module will continue to run in standby sleep mode
// <id> tc_arch_runstdby
#ifndef CONF_TC0_RUNSTDBY
#define CONF_TC0_RUNSTDBY 0
#endif
// <q> Run in debug mode
// <i> Indicates whether the module will run in debug mode
// <id> tc_arch_dbgrun
#ifndef CONF_TC0_DBGRUN
#define CONF_TC0_DBGRUN 0
#endif
// <q> Run on demand
// <i> Run if requested by some other peripheral in the device
// <id> tc_arch_ondemand
#ifndef CONF_TC0_ONDEMAND
#define CONF_TC0_ONDEMAND 0
#endif
// </e>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
#endif
// <q> Output Event On Match or Capture on Channel 0
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo0
#ifndef CONF_TC0_MCEO0
#define CONF_TC0_MCEO0 0
#endif
// <q> Output Event On Match or Capture on Channel 1
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo1
#ifndef CONF_TC0_MCEO1
#define CONF_TC0_MCEO1 0
#endif
// <q> Output Event On Timer Tick
// <i> Enable output of event on timer tick
// <id> tc_arch_ovfeo
#ifndef CONF_TC0_OVFEO
#define CONF_TC0_OVFEO 0
#endif
// <q> Event Input
// <i> Enable asynchronous input events
// <id> tc_arch_tcei
#ifndef CONF_TC0_TCEI
#define CONF_TC0_TCEI 0
#endif
// <q> Inverted Event Input
// <i> Invert the asynchronous input events
// <id> tc_arch_tcinv
#ifndef CONF_TC0_TCINV
#define CONF_TC0_TCINV 0
#endif
// <o> Event action
// <0=> Event action disabled
// <1=> Start, restart or re-trigger TC on event
// <2=> Count on event
// <3=> Start on event
// <4=> Time stamp capture
// <5=> Period captured in CC0, pulse width in CC1
// <6=> Period captured in CC1, pulse width in CC0
// <7=> Pulse width capture
// <i> Event which will be performed on an event
//<id> tc_arch_evact
#ifndef CONF_TC0_EVACT
#define CONF_TC0_EVACT 0
#endif
// </e>
// Default values which the driver needs in order to work correctly
// Mode set to 32-bit
#ifndef CONF_TC0_MODE
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
#endif
// CC 1 register set to 0
#ifndef CONF_TC0_CC1
#define CONF_TC0_CC1 0
#endif
#ifndef CONF_TC0_ALOCK
#define CONF_TC0_ALOCK 0
#endif
// Not used in 32-bit mode
#define CONF_TC0_PER 0
// Calculating correct top value based on requested tick interval.
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
// Prescaler set to 64
#if CONF_TC0_PRESCALER > 0x4
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 64
#endif
// Prescaler set to 256
#if CONF_TC0_PRESCALER > 0x5
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 256
#endif
// Prescaler set to 1024
#if CONF_TC0_PRESCALER > 0x6
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 1024
#endif
#ifndef CONF_TC0_CC0
#define CONF_TC0_CC0 \
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
#endif
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H

514
software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h
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/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> EIC Clock Source
// <id> eic_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for EIC.
#ifndef CONF_GCLK_EIC_SRC
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_EIC_FREQUENCY
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 119997440
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 119997440
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
* \brief SERCOM2's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM3_CORE_SRC
#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
* \brief SERCOM3's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
* \brief SERCOM3's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC0_SRC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC0_FREQUENCY
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 119997440
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H
/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> EIC Clock Source
// <id> eic_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for EIC.
#ifndef CONF_GCLK_EIC_SRC
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_EIC_FREQUENCY
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 119997440
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 119997440
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
* \brief SERCOM2's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM3_CORE_SRC
#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
* \brief SERCOM3's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
* \brief SERCOM3's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC0_SRC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC0_FREQUENCY
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 119997440
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

18
software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c
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@ -1,9 +1,9 @@
#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
}
#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
}

36
software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h
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#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif
#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif

24
software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h
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@ -1,12 +1,12 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#endif // ATMEL_START_PINS_H_INCLUDED
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#endif // ATMEL_START_PINS_H_INCLUDED

268
software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c
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@ -1,134 +1,134 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
/*! The buffer size for USART */
#define USART_0_BUFFER_SIZE 16
struct usart_async_descriptor USART_0;
struct timer_descriptor TIMER_0;
static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE];
struct i2c_m_sync_desc I2C_0;
void EXTERNAL_IRQ_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
ext_irq_init();
}
/**
* \brief USART Clock initialization function
*
* Enables register interface and peripheral clock
*/
void USART_0_CLOCK_init()
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
/**
* \brief USART pinmux initialization function
*
* Set each required pin to USART functionality
*/
void USART_0_PORT_init()
{
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
/**
* \brief USART initialization function
*
* Enables USART peripheral, clocks and initializes USART driver
*/
void USART_0_init(void)
{
USART_0_CLOCK_init();
usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL);
USART_0_PORT_init();
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_pull_mode(PA22,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0);
gpio_set_pin_pull_mode(PA23,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1);
}
void I2C_0_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, SERCOM3);
I2C_0_PORT_init();
}
/**
* \brief Timer initialization function
*
* Enables Timer peripheral, clocks and initializes Timer driver
*/
static void TIMER_0_init(void)
{
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
timer_init(&TIMER_0, TC0, _tc_get_timer());
}
void system_init(void)
{
init_mcu();
EXTERNAL_IRQ_0_init();
USART_0_init();
I2C_0_init();
TIMER_0_init();
}
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
/*! The buffer size for USART */
#define USART_0_BUFFER_SIZE 16
struct usart_async_descriptor USART_0;
struct timer_descriptor TIMER_0;
static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE];
struct i2c_m_sync_desc I2C_0;
void EXTERNAL_IRQ_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
ext_irq_init();
}
/**
* \brief USART Clock initialization function
*
* Enables register interface and peripheral clock
*/
void USART_0_CLOCK_init()
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
/**
* \brief USART pinmux initialization function
*
* Set each required pin to USART functionality
*/
void USART_0_PORT_init()
{
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
/**
* \brief USART initialization function
*
* Enables USART peripheral, clocks and initializes USART driver
*/
void USART_0_init(void)
{
USART_0_CLOCK_init();
usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL);
USART_0_PORT_init();
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_pull_mode(PA22,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0);
gpio_set_pin_pull_mode(PA23,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1);
}
void I2C_0_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, SERCOM3);
I2C_0_PORT_init();
}
/**
* \brief Timer initialization function
*
* Enables Timer peripheral, clocks and initializes Timer driver
*/
static void TIMER_0_init(void)
{
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
timer_init(&TIMER_0, TC0, _tc_get_timer());
}
void system_init(void)
{
init_mcu();
EXTERNAL_IRQ_0_init();
USART_0_init();
I2C_0_init();
TIMER_0_init();
}

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_ext_irq.h>
#include <hal_usart_async.h>
#include <hal_i2c_m_sync.h>
#include <hal_timer.h>
#include <hpl_tc_base.h>
extern struct usart_async_descriptor USART_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct timer_descriptor TIMER_0;
void USART_0_PORT_init(void);
void USART_0_CLOCK_init(void);
void USART_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_ext_irq.h>
#include <hal_usart_async.h>
#include <hal_i2c_m_sync.h>
#include <hal_timer.h>
#include <hpl_tc_base.h>
extern struct usart_async_descriptor USART_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct timer_descriptor TIMER_0;
void USART_0_PORT_init(void);
void USART_0_CLOCK_init(void);
void USART_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using EXTERNAL_IRQ_0
*/
void EXTERNAL_IRQ_0_example(void)
{
}
/**
* Example of using USART_0 to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_USART_0[12] = "Hello World!";
static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr)
{
/* Transfer completed */
}
void USART_0_example(void)
{
struct io_descriptor *io;
usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0);
/*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb);
usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/
usart_async_get_io_descriptor(&USART_0, &io);
usart_async_enable(&USART_0);
io_write(io, example_USART_0, 12);
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
static struct timer_task TIMER_0_task1, TIMER_0_task2;
/**
* Example of using TIMER_0.
*/
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
{
}
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
{
}
void TIMER_0_example(void)
{
TIMER_0_task1.interval = 100;
TIMER_0_task1.cb = TIMER_0_task1_cb;
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
TIMER_0_task2.interval = 200;
TIMER_0_task2.cb = TIMER_0_task2_cb;
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
timer_add_task(&TIMER_0, &TIMER_0_task1);
timer_add_task(&TIMER_0, &TIMER_0_task2);
timer_start(&TIMER_0);
}
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using EXTERNAL_IRQ_0
*/
void EXTERNAL_IRQ_0_example(void)
{
}
/**
* Example of using USART_0 to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_USART_0[12] = "Hello World!";
static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr)
{
/* Transfer completed */
}
void USART_0_example(void)
{
struct io_descriptor *io;
usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0);
/*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb);
usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/
usart_async_get_io_descriptor(&USART_0, &io);
usart_async_enable(&USART_0);
io_write(io, example_USART_0, 12);
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
static struct timer_task TIMER_0_task1, TIMER_0_task2;
/**
* Example of using TIMER_0.
*/
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
{
}
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
{
}
void TIMER_0_example(void)
{
TIMER_0_task1.interval = 100;
TIMER_0_task1.cb = TIMER_0_task1_cb;
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
TIMER_0_task2.interval = 200;
TIMER_0_task2.cb = TIMER_0_task2_cb;
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
timer_add_task(&TIMER_0, &TIMER_0_task1);
timer_add_task(&TIMER_0, &TIMER_0_task2);
timer_start(&TIMER_0);
}

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void EXTERNAL_IRQ_0_example(void);
void USART_0_example(void);
void I2C_0_example(void);
void TIMER_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void EXTERNAL_IRQ_0_example(void);
void USART_0_example(void);
void I2C_0_example(void);
void TIMER_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED

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==============
EXT IRQ driver
==============
The External Interrupt driver allows external pins to be
configured as interrupt lines. Each interrupt line can be
individually masked and can generate an interrupt on rising,
falling or both edges, or on high or low levels. Some of
external pin can also be configured to wake up the device
from sleep modes where all clocks have been disabled.
External pins can also generate an event.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Detect external pins interrupt
Applications
------------
* Generate an interrupt on rising, falling or both edges,
or on high or low levels.
Dependencies
------------
* GPIO hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A
==============
EXT IRQ driver
==============
The External Interrupt driver allows external pins to be
configured as interrupt lines. Each interrupt line can be
individually masked and can generate an interrupt on rising,
falling or both edges, or on high or low levels. Some of
external pin can also be configured to wake up the device
from sleep modes where all clocks have been disabled.
External pins can also generate an event.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Detect external pins interrupt
Applications
------------
* Generate an interrupt on rising, falling or both edges,
or on high or low levels.
Dependencies
------------
* GPIO hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

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=============================
I2C Master synchronous driver
=============================
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
for on-board low-speed bi-directional communication between controllers and
peripherals. The master device is responsible for initiating and controlling
all transfers on the I2C bus. Only one master device can be active on the I2C
bus at the time, but the master role can be transferred between devices on the
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
resistors.
The stop condition is automatically controlled by the driver if the I/O write and
read functions are used, but can be manually controlled by using the
i2c_m_sync_transfer function.
Often a master accesses different information in the slave by accessing
different registers in the slave. This is done by first sending a message to
the target slave containing the register address, followed by a repeated start
condition (no stop condition between) ending with transferring register data.
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
function, but limited to 8-bit register addresses.
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
stick within the SCL clock frequency range supported by the selected mode.
The requested SCL clock frequency is not validated by the
i2c_m_sync_set_baudrate function against the selected I2C mode.
Features
--------
* I2C Master support
* Initialization and de-initialization
* Enabling and disabling
* Run-time bus speed configuration
* Write and read I2C messages
* Slave register access functions (limited to 8-bit address)
* Manual or automatic stop condition generation
* 10- and 7- bit addressing
* I2C Modes supported
+----------------------+-------------------+
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
+----------------------+-------------------+
|* Fastmode+ | (SCL: 1 - 1000kHz)|
+----------------------+-------------------+
|* Highspeed mode | (SCL: 1 - 3400kHz)|
+----------------------+-------------------+
Applications
------------
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
* Data communication between micro controllers
* Controlling displays
Dependencies
------------
* I2C Master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
General
^^^^^^^
* System Managmenet Bus (SMBus) not supported.
* Power Management Bus (PMBus) not supported.
Clock considerations
^^^^^^^^^^^^^^^^^^^^
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
Known issues and workarounds
----------------------------
N/A
=============================
I2C Master synchronous driver
=============================
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
for on-board low-speed bi-directional communication between controllers and
peripherals. The master device is responsible for initiating and controlling
all transfers on the I2C bus. Only one master device can be active on the I2C
bus at the time, but the master role can be transferred between devices on the
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
resistors.
The stop condition is automatically controlled by the driver if the I/O write and
read functions are used, but can be manually controlled by using the
i2c_m_sync_transfer function.
Often a master accesses different information in the slave by accessing
different registers in the slave. This is done by first sending a message to
the target slave containing the register address, followed by a repeated start
condition (no stop condition between) ending with transferring register data.
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
function, but limited to 8-bit register addresses.
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
stick within the SCL clock frequency range supported by the selected mode.
The requested SCL clock frequency is not validated by the
i2c_m_sync_set_baudrate function against the selected I2C mode.
Features
--------
* I2C Master support
* Initialization and de-initialization
* Enabling and disabling
* Run-time bus speed configuration
* Write and read I2C messages
* Slave register access functions (limited to 8-bit address)
* Manual or automatic stop condition generation
* 10- and 7- bit addressing
* I2C Modes supported
+----------------------+-------------------+
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
+----------------------+-------------------+
|* Fastmode+ | (SCL: 1 - 1000kHz)|
+----------------------+-------------------+
|* Highspeed mode | (SCL: 1 - 3400kHz)|
+----------------------+-------------------+
Applications
------------
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
* Data communication between micro controllers
* Controlling displays
Dependencies
------------
* I2C Master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
General
^^^^^^^
* System Managmenet Bus (SMBus) not supported.
* Power Management Bus (PMBus) not supported.
Clock considerations
^^^^^^^^^^^^^^^^^^^^
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
Known issues and workarounds
----------------------------
N/A

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============================
The Timer driver (bare-bone)
============================
The Timer driver provides means for delayed and periodical function invocation.
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
changes execution delays and periods for all tasks in the timers task queue.
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
the period set in the task configuration.
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
reuse the memory of expired task in the callback.
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Starting and stopping
* Timer tasks - periodical invocation of functions
* Changing and obtaining of the period of a timer
Applications
------------
* Delayed and periodical function execution for middle-ware stacks and applications.
Dependencies
------------
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
Concurrency
-----------
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
until the task adding or removing is complete.
The task queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
Limitations
-----------
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
Knows issues and workarounds
----------------------------
Not applicable
============================
The Timer driver (bare-bone)
============================
The Timer driver provides means for delayed and periodical function invocation.
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
changes execution delays and periods for all tasks in the timers task queue.
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
the period set in the task configuration.
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
reuse the memory of expired task in the callback.
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Starting and stopping
* Timer tasks - periodical invocation of functions
* Changing and obtaining of the period of a timer
Applications
------------
* Delayed and periodical function execution for middle-ware stacks and applications.
Dependencies
------------
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
Concurrency
-----------
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
until the task adding or removing is complete.
The task queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
Limitations
-----------
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
Knows issues and workarounds
----------------------------
Not applicable

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The USART Asynchronous Driver
=============================
The universal synchronous and asynchronous receiver and transmitter
(USART) is usually used to transfer data from one device to the other.
The USART driver use a ring buffer to store received data. When the USART
raise the data received interrupt, this data will be stored in the ring buffer
at the next free location. When the ring buffer is full, the next reception
will overwrite the oldest data stored in the ring buffer. There is one
USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
is called SERCOM0_USART_BUFFER_SIZE.
On the other hand, when sending data over USART, the data is not copied to an
internal buffer, but the data buffer supplied by the user is used. The callback
will only be generated at the end of the buffer and not for each byte.
User can set action for flow control pins by function usart_set_flow_control,
if the flow control is enabled. All the available states are defined in union
usart_flow_control_state.
Note that user can set state of flow control pins only if automatic support of
the flow control is not supported by the hardware.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* UART or USRT communication mode
* Character size
* Data order
* Flow control
* Data transfer: transmission, reception
* Notifications about transfer done or error case via callbacks
* Status information with busy state and transfer count
Applications
------------
They are commonly used in a terminal application or low-speed communication
between devices.
Dependencies
------------
USART capable hardware, with interrupt on each character is sent or
received.
Concurrency
-----------
Write buffer should not be changed while data is being sent.
Limitations
-----------
* The driver does not support 9-bit character size.
* The "USART with ISO7816" mode can be only used in ISO7816 capable devices.
And the SCK pin can't be set directly. Application can use a GCLK output PIN
to generate SCK. For example to communicate with a SMARTCARD with ISO7816
(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be
config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification.
Known issues and workarounds
----------------------------
N/A
The USART Asynchronous Driver
=============================
The universal synchronous and asynchronous receiver and transmitter
(USART) is usually used to transfer data from one device to the other.
The USART driver use a ring buffer to store received data. When the USART
raise the data received interrupt, this data will be stored in the ring buffer
at the next free location. When the ring buffer is full, the next reception
will overwrite the oldest data stored in the ring buffer. There is one
USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
is called SERCOM0_USART_BUFFER_SIZE.
On the other hand, when sending data over USART, the data is not copied to an
internal buffer, but the data buffer supplied by the user is used. The callback
will only be generated at the end of the buffer and not for each byte.
User can set action for flow control pins by function usart_set_flow_control,
if the flow control is enabled. All the available states are defined in union
usart_flow_control_state.
Note that user can set state of flow control pins only if automatic support of
the flow control is not supported by the hardware.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* UART or USRT communication mode
* Character size
* Data order
* Flow control
* Data transfer: transmission, reception
* Notifications about transfer done or error case via callbacks
* Status information with busy state and transfer count
Applications
------------
They are commonly used in a terminal application or low-speed communication
between devices.
Dependencies
------------
USART capable hardware, with interrupt on each character is sent or
received.
Concurrency
-----------
Write buffer should not be changed while data is being sent.
Limitations
-----------
* The driver does not support 9-bit character size.
* The "USART with ISO7816" mode can be only used in ISO7816 capable devices.
And the SCK pin can't be set directly. Application can use a GCLK output PIN
to generate SCK. For example to communicate with a SMARTCARD with ISO7816
(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be
config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification.
Known issues and workarounds
----------------------------
N/A

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/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */
/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h
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/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HAL_CACHE_H_
#define HAL_CACHE_H_
#include <hpl_cmcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Enable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_enable(const void *hw);
/**
* \brief Disable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_disable(const void *hw);
/**
* \brief Initialize cache module
*
* This function initialize cache module configuration.
*
* \return status of operation
*/
int32_t cache_init(void);
/**
* \brief Configure cache module
*
* \param[in] pointer pointing to the starting address of cache module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/**
* \brief Invalidate entire cache entries
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_invalidate_all(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HAL_CACHE_H_ */
/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HAL_CACHE_H_
#define HAL_CACHE_H_
#include <hpl_cmcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Enable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_enable(const void *hw);
/**
* \brief Disable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_disable(const void *hw);
/**
* \brief Initialize cache module
*
* This function initialize cache module configuration.
*
* \return status of operation
*/
int32_t cache_init(void);
/**
* \brief Configure cache module
*
* \param[in] pointer pointing to the starting address of cache module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/**
* \brief Invalidate entire cache entries
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_invalidate_all(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HAL_CACHE_H_ */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h
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/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#ifndef _HAL_DELAY_H_INCLUDED
#define _HAL_DELAY_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_delay Delay Driver
*
*@{
*/
/**
* \brief Initialize Delay driver
*
* \param[in] hw The pointer to hardware instance
*/
void delay_init(void *const hw);
/**
* \brief Perform delay in us
*
* This function performs delay for the given amount of microseconds.
*
* \param[in] us The amount delay in us
*/
void delay_us(const uint16_t us);
/**
* \brief Perform delay in ms
*
* This function performs delay for the given amount of milliseconds.
*
* \param[in] ms The amount delay in ms
*/
void delay_ms(const uint16_t ms);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t delay_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_DELAY_H_INCLUDED */
/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT