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stable
Penguin 5 years ago
parent 554184343e
commit 8d8856f22e
180 changed files with 237998 additions and 237998 deletions
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2
README.md
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# Embedded-Graphics-Learning
# Embedded-Graphics-Learning

1124
electrical/same54_dev_board/BRAIN.sch
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1124
electrical/same54_dev_board/BRAIN.sch-bak
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6
electrical/same54_dev_board/NCP349MNAETBG.dcm
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library

44
electrical/same54_dev_board/NCP349MNAETBG.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# NCP349MNAETBG
#
DEF NCP349MNAETBG U 0 40 Y Y 1 F N
F0 "U" 0 -200 50 H V C CNN
F1 "NCP349MNAETBG" 0 350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -300 250 300 -150 0 1 0 f
X VIN 1 -400 150 100 R 50 50 1 1 I
X GND 2 -400 50 100 R 50 50 1 1 I
X ~FLAG 3 400 150 100 L 50 50 1 1 I
X ~EN 4 -400 -50 100 R 50 50 1 1 I
X OUT 5 400 50 100 L 50 50 1 1 I
X OUT 6 400 -50 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# NCP349MNAETBG
#
DEF NCP349MNAETBG U 0 40 Y Y 1 F N
F0 "U" 0 -200 50 H V C CNN
F1 "NCP349MNAETBG" 0 350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -300 250 300 -150 0 1 0 f
X VIN 1 -400 150 100 R 50 50 1 1 I
X GND 2 -400 50 100 R 50 50 1 1 I
X ~FLAG 3 400 150 100 L 50 50 1 1 I
X ~EN 4 -400 -50 100 R 50 50 1 1 I
X OUT 5 400 50 100 L 50 50 1 1 I
X OUT 6 400 -50 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library

802
electrical/same54_dev_board/Power.sch
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC

802
electrical/same54_dev_board/Power.sch-bak
Unescape Escape View File

@ -1,401 +1,401 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5950 4350 5950 4450
Connection ~ 5950 4450
Wire Wire Line
5950 4450 5950 4550
Connection ~ 5950 4550
Wire Wire Line
5950 4550 5950 4650
Connection ~ 5950 4650
Wire Wire Line
5950 4650 5950 4750
Connection ~ 5950 4750
Wire Wire Line
5950 4750 5950 4850
Connection ~ 5950 4850
Wire Wire Line
5950 4850 5950 4950
Connection ~ 5950 4950
Wire Wire Line
5950 4950 5950 5050
Connection ~ 5950 5050
Wire Wire Line
5950 5050 5950 5150
Connection ~ 5950 5150
Wire Wire Line
5950 5150 5950 5250
Wire Wire Line
5950 5500 5950 5600
Text HLabel 950 900 0 50 Input ~ 0
USB_3v3
Text HLabel 950 1050 0 50 Input ~ 0
USB_5v
Text GLabel 950 600 0 50 Input ~ 0
g_3v3
Text GLabel 950 750 0 50 Input ~ 0
g_5v
Wire Wire Line
950 900 1350 900
Text Label 1350 900 0 50 ~ 0
USB_3v3
Wire Wire Line
950 1050 1350 1050
Text Label 1350 1050 0 50 ~ 0
USB_5v
Wire Wire Line
950 600 1350 600
Wire Wire Line
950 750 1350 750
Text Label 1350 600 0 50 ~ 0
3v3Out
Text Label 1350 750 0 50 ~ 0
5vOut
Wire Wire Line
3950 5300 3950 5400
Connection ~ 3950 5400
Wire Wire Line
3950 5400 3950 5500
Connection ~ 3950 5500
Wire Wire Line
3950 5500 3950 5600
Connection ~ 3950 5600
Wire Wire Line
3950 5600 3950 5700
Connection ~ 3950 5700
Wire Wire Line
3950 5700 3950 5800
Connection ~ 3950 5800
Wire Wire Line
3950 5800 3950 5900
Connection ~ 3950 5900
Wire Wire Line
3950 5900 3950 6000
$Comp
L Connector:Barrel_Jack_Switch J4
U 1 1 5E88DD8C
P 950 1500
F 0 "J4" H 1007 1817 50 0000 C CNN
F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN
F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN
F 3 "~" H 1000 1460 50 0001 C CNN
1 950 1500
1 0 0 -1
$EndComp
Wire Wire Line
1250 1400 1350 1400
Text Label 1350 1400 0 50 ~ 0
Wall_5V
NoConn ~ 1250 1500
Wire Wire Line
1250 1600 1350 1600
$Comp
L power:GND #PWR0113
U 1 1 5E8980B4
P 1350 1600
F 0 "#PWR0113" H 1350 1350 50 0001 C CNN
F 1 "GND" H 1355 1427 50 0000 C CNN
F 2 "" H 1350 1600 50 0001 C CNN
F 3 "" H 1350 1600 50 0001 C CNN
1 1350 1600
1 0 0 -1
$EndComp
$Comp
L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1
U 5 1 5E84F3B3
P 4950 5000
F 0 "U1" H 4950 5915 50 0000 C CNN
F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN
F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN
F 3 "" H 3750 6250 50 0001 C CNN
5 4950 5000
1 0 0 -1
$EndComp
Text Notes 3300 2350 0 50 ~ 0
These are dummy loads!!!
Wire Wire Line
4500 1800 3950 1800
$Comp
L Device:R_Small R2
U 1 1 5E8D1249
P 3950 1900
F 0 "R2" H 4009 1946 50 0000 L CNN
F 1 "100k" H 4009 1855 50 0000 L CNN
F 2 "" H 3950 1900 50 0001 C CNN
F 3 "~" H 3950 1900 50 0001 C CNN
1 3950 1900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 5E8D1C92
P 3950 2600
F 0 "R3" H 4009 2646 50 0000 L CNN
F 1 "100k" H 4009 2555 50 0000 L CNN
F 2 "" H 3950 2600 50 0001 C CNN
F 3 "~" H 3950 2600 50 0001 C CNN
1 3950 2600
1 0 0 -1
$EndComp
Wire Wire Line
3950 2000 3950 2050
$Comp
L power:GND #PWR0114
U 1 1 5E8D3DAD
P 3950 2050
F 0 "#PWR0114" H 3950 1800 50 0001 C CNN
F 1 "GND" H 3955 1877 50 0000 C CNN
F 2 "" H 3950 2050 50 0001 C CNN
F 3 "" H 3950 2050 50 0001 C CNN
1 3950 2050
1 0 0 -1
$EndComp
Wire Wire Line
3950 2700 3950 2750
$Comp
L power:GND #PWR0115
U 1 1 5E8D4B47
P 3950 2750
F 0 "#PWR0115" H 3950 2500 50 0001 C CNN
F 1 "GND" H 3955 2577 50 0000 C CNN
F 2 "" H 3950 2750 50 0001 C CNN
F 3 "" H 3950 2750 50 0001 C CNN
1 3950 2750
1 0 0 -1
$EndComp
Wire Wire Line
3950 1800 3550 1800
Connection ~ 3950 1800
Text Label 3550 1800 2 50 ~ 0
USB_5v
Wire Wire Line
3950 2500 3550 2500
Connection ~ 3950 2500
Text Label 3550 2500 2 50 ~ 0
USB_3v3
Wire Wire Line
4900 2500 5800 2500
Wire Wire Line
4500 2500 4350 2500
Wire Wire Line
4900 1800 5350 1800
$Comp
L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4
U 1 1 5E7F2428
P 8100 2250
AR Path="/5E7F2428" Ref="U4" Part="1"
AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1"
F 0 "U4" H 8100 2665 50 0000 C CNN
F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN
F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN
F 3 "" H 8100 2250 50 0001 C CNN
1 8100 2250
1 0 0 -1
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1
U 1 1 5E9B8E9E
P 4700 1800
F 0 "Q1" V 4950 1800 60 0000 C CNN
F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3000 60 0001 L CNN "Status"
1 4700 1800
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3
U 1 1 5E9CBFD6
P 6000 1800
F 0 "Q3" V 6250 1800 60 0000 C CNN
F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3000 60 0001 L CNN "Status"
1 6000 1800
0 -1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2
U 1 1 5E9D56A5
P 4700 2500
F 0 "Q2" V 4950 2500 60 0000 C CNN
F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 4900 3700 60 0001 L CNN "Status"
1 4700 2500
0 1 -1 0
$EndComp
$Comp
L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4
U 1 1 5E9DB598
P 6000 2500
F 0 "Q4" V 6250 2500 60 0000 C CNN
F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN
F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN
F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN
F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN"
F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category"
F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family"
F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description"
F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 6200 3700 60 0001 L CNN "Status"
1 6000 2500
0 -1 -1 0
$EndComp
Wire Wire Line
4600 2800 5350 2800
Wire Wire Line
4600 2100 6100 2100
Wire Wire Line
4600 2100 4350 2100
Wire Wire Line
4350 2100 4350 2500
Connection ~ 4600 2100
Connection ~ 4350 2500
Wire Wire Line
4350 2500 3950 2500
Wire Wire Line
5350 1800 5350 2800
Connection ~ 5350 1800
Wire Wire Line
5350 1800 5800 1800
Connection ~ 5350 2800
Wire Wire Line
5350 2800 6100 2800
Wire Wire Line
5350 2800 5350 2900
$Comp
L Device:R_Small R6
U 1 1 5E9E8F6F
P 5350 3000
F 0 "R6" H 5409 3046 50 0000 L CNN
F 1 "R_Small" H 5409 2955 50 0000 L CNN
F 2 "" H 5350 3000 50 0001 C CNN
F 3 "~" H 5350 3000 50 0001 C CNN
1 5350 3000
1 0 0 -1
$EndComp
Wire Wire Line
5350 3100 5350 3150
$Comp
L power:GND #PWR0117
U 1 1 5E9EA130
P 5350 3150
F 0 "#PWR0117" H 5350 2900 50 0001 C CNN
F 1 "GND" H 5355 2977 50 0000 C CNN
F 2 "" H 5350 3150 50 0001 C CNN
F 3 "" H 5350 3150 50 0001 C CNN
1 5350 3150
1 0 0 -1
$EndComp
Wire Wire Line
6200 1800 6550 1800
Wire Wire Line
6550 2500 6200 2500
Wire Wire Line
6550 1800 6550 2100
Connection ~ 6550 2100
Wire Wire Line
6550 2100 6550 2500
$Comp
L Device:C_Small C10
U 1 1 5E9F5727
P 7050 2200
F 0 "C10" H 7250 2250 50 0000 R CNN
F 1 "100nF" H 7350 2150 50 0000 R CNN
F 2 "" H 7050 2200 50 0001 C CNN
F 3 "~" H 7050 2200 50 0001 C CNN
1 7050 2200
-1 0 0 -1
$EndComp
Wire Wire Line
6550 2100 7050 2100
Wire Wire Line
7050 2100 7200 2100
Connection ~ 7050 2100
$Comp
L Device:C_Small C11
U 1 1 5E9F9ED9
P 7200 2200
F 0 "C11" H 7292 2246 50 0000 L CNN
F 1 "1uF" H 7292 2155 50 0000 L CNN
F 2 "" H 7200 2200 50 0001 C CNN
F 3 "~" H 7200 2200 50 0001 C CNN
1 7200 2200
1 0 0 -1
$EndComp
Connection ~ 7200 2100
Wire Wire Line
7200 2100 7700 2100
Wire Wire Line
7700 2200 7700 2300
Wire Wire Line
7700 2300 7700 2400
Connection ~ 7700 2300
$Comp
L power:GND #PWR0118
U 1 1 5EA05C9E
P 7700 2400
F 0 "#PWR0118" H 7700 2150 50 0001 C CNN
F 1 "GND" H 7705 2227 50 0000 C CNN
F 2 "" H 7700 2400 50 0001 C CNN
F 3 "" H 7700 2400 50 0001 C CNN
1 7700 2400
1 0 0 -1
$EndComp
NoConn ~ 8500 2100
Wire Wire Line
8500 2200 8500 2300
Wire Wire Line
8500 2200 8650 2200
Connection ~ 8500 2200
Wire Wire Line
7050 2300 7200 2300
Wire Wire Line
7200 2300 7700 2300
Connection ~ 7200 2300
$EndSCHEMATC

1312
electrical/same54_dev_board/SCREEN_INTF.sch
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1312
electrical/same54_dev_board/SCREEN_INTF.sch-bak
View File

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564
electrical/same54_dev_board/USB_INTF.sch
Unescape Escape View File

@ -1,282 +1,282 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC

564
electrical/same54_dev_board/USB_INTF.sch-bak
Unescape Escape View File

@ -1,282 +1,282 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:USB_B_Micro J1
U 1 1 5E8480AD
P 6050 1300
F 0 "J1" H 6107 1767 50 0000 C CNN
F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN
F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN
F 3 "~" H 6200 1250 50 0001 C CNN
1 6050 1300
1 0 0 -1
$EndComp
$Comp
L dk_Interface-Controllers:FT232RQ-REEL U2
U 1 1 5E84744C
P 7700 2500
F 0 "U2" H 8000 1100 60 0000 C CNN
F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN
F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN
F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN
F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN"
F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN"
F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category"
F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family"
F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link"
F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page"
F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description"
F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer"
F 12 "Active" H 7900 3700 60 0001 L CNN "Status"
1 7700 2500
1 0 0 -1
$EndComp
Text Notes 650 700 0 50 ~ 0
Power Interface
Wire Wire Line
6350 1300 6400 1300
Text Label 6400 1300 0 50 ~ 0
USB_D+
Wire Wire Line
6350 1400 6400 1400
Text Label 6400 1400 0 50 ~ 0
USB_D-
Wire Wire Line
7000 3400 6900 3400
Wire Wire Line
7000 3500 6900 3500
Text Label 6900 3400 2 50 ~ 0
USB_D+
Text Label 6900 3500 2 50 ~ 0
USB_D-
Wire Wire Line
8000 3000 8100 3000
Text Label 8100 3000 0 50 ~ 0
FTDI_TX
Wire Wire Line
7000 2600 6900 2600
Text Label 6900 2600 2 50 ~ 0
FTDI_RX
Wire Wire Line
7400 4200 7500 4200
Connection ~ 7500 4200
Wire Wire Line
7500 4200 7600 4200
Wire Wire Line
7500 4200 7500 4300
$Comp
L power:GND #PWR0110
U 1 1 5E7B73F2
P 7500 4300
F 0 "#PWR0110" H 7500 4050 50 0001 C CNN
F 1 "GND" H 7505 4127 50 0000 C CNN
F 2 "" H 7500 4300 50 0001 C CNN
F 3 "" H 7500 4300 50 0001 C CNN
1 7500 4300
1 0 0 -1
$EndComp
Wire Wire Line
5950 1700 6050 1700
Wire Wire Line
6050 1700 6050 1800
Connection ~ 6050 1700
$Comp
L power:GND #PWR0111
U 1 1 5E7BED3A
P 6050 1800
F 0 "#PWR0111" H 6050 1550 50 0001 C CNN
F 1 "GND" H 6055 1627 50 0000 C CNN
F 2 "" H 6050 1800 50 0001 C CNN
F 3 "" H 6050 1800 50 0001 C CNN
1 6050 1800
1 0 0 -1
$EndComp
NoConn ~ 6350 1500
Wire Notes Line
600 600 2000 600
Text Label 1350 1950 0 50 ~ 0
FTDI_TX
Wire Wire Line
1100 1950 1350 1950
Text HLabel 1100 1950 0 50 Input ~ 0
DEBUG_RX
Text Label 1350 1850 0 50 ~ 0
FTDI_RX
Wire Wire Line
1100 1850 1350 1850
Text HLabel 1100 1850 0 50 Input ~ 0
DEBUG_TX
Text Notes 700 1750 0 50 ~ 0
USB Interface
Wire Notes Line
2000 1650 600 1650
Wire Notes Line
600 600 600 1650
Wire Wire Line
7500 2300 7500 2400
Wire Wire Line
8000 2800 8500 2800
$Comp
L Device:C_Small C6
U 1 1 5E7E8395
P 8500 2900
F 0 "C6" H 8592 2946 50 0000 L CNN
F 1 "100nF" H 8592 2855 50 0000 L CNN
F 2 "" H 8500 2900 50 0001 C CNN
F 3 "~" H 8500 2900 50 0001 C CNN
1 8500 2900
1 0 0 -1
$EndComp
Wire Wire Line
8500 3000 8500 3100
$Comp
L power:GND #PWR0112
U 1 1 5E7E91F3
P 8500 3100
F 0 "#PWR0112" H 8500 2850 50 0001 C CNN
F 1 "GND" H 8505 2927 50 0000 C CNN
F 2 "" H 8500 3100 50 0001 C CNN
F 3 "" H 8500 3100 50 0001 C CNN
1 8500 3100
1 0 0 -1
$EndComp
NoConn ~ 8000 3100
NoConn ~ 8000 3200
Wire Wire Line
8500 2800 8850 2800
Connection ~ 8500 2800
Text Label 8850 2800 0 50 ~ 0
FTDI_3v3
Text Label 7500 2300 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7000 3100 6900 3100
Text Label 6900 3100 2 50 ~ 0
FTDI_3v3
Wire Wire Line
7600 4200 7700 4200
Connection ~ 7600 4200
Wire Wire Line
7000 3900 6900 3900
Wire Wire Line
6900 3900 6900 4200
Wire Wire Line
6900 4200 7400 4200
Connection ~ 7400 4200
Wire Wire Line
7700 4200 7800 4200
Connection ~ 7700 4200
$Comp
L Device:C_Small C7
U 1 1 5E7F85B7
P 6800 1200
F 0 "C7" H 6892 1246 50 0000 L CNN
F 1 "10nF" H 6892 1155 50 0000 L CNN
F 2 "" H 6800 1200 50 0001 C CNN
F 3 "~" H 6800 1200 50 0001 C CNN
1 6800 1200
1 0 0 -1
$EndComp
Wire Wire Line
6350 1100 6800 1100
Wire Wire Line
6800 1300 6800 1700
Wire Wire Line
6800 1700 6050 1700
Wire Wire Line
6800 1100 7050 1100
Connection ~ 6800 1100
$Comp
L Device:Ferrite_Bead_Small FB1
U 1 1 5E7FB1E4
P 7150 1100
F 0 "FB1" V 6913 1100 50 0000 C CNN
F 1 "40_Ohm" V 7004 1100 50 0000 C CNN
F 2 "" V 7080 1100 50 0001 C CNN
F 3 "~" H 7150 1100 50 0001 C CNN
1 7150 1100
0 1 1 0
$EndComp
Wire Wire Line
7600 1100 7600 2400
Wire Wire Line
7250 1100 7600 1100
Wire Wire Line
7600 1100 8050 1100
Connection ~ 7600 1100
$Comp
L Device:C_Small C8
U 1 1 5E8424CD
P 8050 1200
F 0 "C8" H 8142 1246 50 0000 L CNN
F 1 "4.7uF" H 8142 1155 50 0000 L CNN
F 2 "" H 8050 1200 50 0001 C CNN
F 3 "~" H 8050 1200 50 0001 C CNN
1 8050 1200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C9
U 1 1 5E844B56
P 8550 1200
F 0 "C9" H 8642 1246 50 0000 L CNN
F 1 "100nF" H 8642 1155 50 0000 L CNN
F 2 "" H 8550 1200 50 0001 C CNN
F 3 "~" H 8550 1200 50 0001 C CNN
1 8550 1200
1 0 0 -1
$EndComp
Wire Wire Line
8050 1100 8550 1100
Connection ~ 8050 1100
Wire Wire Line
8050 1300 8300 1300
Wire Wire Line
8300 1300 8300 1400
Connection ~ 8300 1300
Wire Wire Line
8300 1300 8550 1300
$Comp
L power:GND #PWR0116
U 1 1 5E849ABD
P 8300 1400
F 0 "#PWR0116" H 8300 1150 50 0001 C CNN
F 1 "GND" H 8305 1227 50 0000 C CNN
F 2 "" H 8300 1400 50 0001 C CNN
F 3 "" H 8300 1400 50 0001 C CNN
1 8300 1400
1 0 0 -1
$EndComp
Text Label 8950 1100 0 50 ~ 0
FTDI_5V
Wire Wire Line
8550 1100 8950 1100
Connection ~ 8550 1100
Wire Wire Line
1050 800 1550 800
Text Label 1550 800 0 50 ~ 0
FTDI_5V
Text HLabel 1050 800 0 50 Input ~ 0
FTDI_5V
Text Label 1550 950 0 50 ~ 0
FTDI_3v3
Wire Wire Line
1050 950 1550 950
Wire Notes Line
2000 600 2000 1650
Text HLabel 1050 950 0 50 Input ~ 0
FTDI_3V3
$EndSCHEMATC

157530
electrical/same54_dev_board/fp-info-cache
View File

File diff suppressed because it is too large Load Diff

6
electrical/same54_dev_board/fp-lib-table
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(fp_lib_table
(lib (name proj_modules)(type KiCad)(uri ${KIPRJMOD}/modules/proj_modules.pretty)(options "")(descr ""))
)
(fp_lib_table
(lib (name proj_modules)(type KiCad)(uri ${KIPRJMOD}/modules/proj_modules.pretty)(options "")(descr ""))
)

18
electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.bck
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EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library

18
electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.dcm
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EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
$CMP Conn_02x20_Odd_Even_LCD_INTF
D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)
K connector
F ~
$ENDCMP
#
#End Doc Library

198
electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Conn_02x20_Odd_Even_LCD_INTF
#
DEF Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N
F0 "J" 0 -1100 50 H V C CNN
F1 "Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN
F2 "" -400 0 50 H I C CNN
F3 "" -400 0 50 H I C CNN
$FPLIST
Connector*:*_2x??-1MP*
$ENDFPLIST
DRAW
S -450 -995 -400 -1005 1 1 6 N
S -450 -895 -400 -905 1 1 6 N
S -450 -795 -400 -805 1 1 6 N
S -450 -695 -400 -705 1 1 6 N
S -450 -595 -400 -605 1 1 6 N
S -450 -495 -400 -505 1 1 6 N
S -450 -395 -400 -405 1 1 6 N
S -450 -295 -400 -305 1 1 6 N
S -450 -195 -400 -205 1 1 6 N
S -450 -95 -400 -105 1 1 6 N
S -450 5 -400 -5 1 1 6 N
S -450 105 -400 95 1 1 6 N
S -450 205 -400 195 1 1 6 N
S -450 305 -400 295 1 1 6 N
S -450 405 -400 395 1 1 6 N
S -450 505 -400 495 1 1 6 N
S -450 605 -400 595 1 1 6 N
S -450 705 -400 695 1 1 6 N
S -450 805 -400 795 1 1 6 N
S -450 905 -400 895 1 1 6 N
S -450 950 450 -1050 1 1 10 f
S 450 -995 400 -1005 1 1 6 N
S 450 -895 400 -905 1 1 6 N
S 450 -795 400 -805 1 1 6 N
S 450 -695 400 -705 1 1 6 N
S 450 -595 400 -605 1 1 6 N
S 450 -495 400 -505 1 1 6 N
S 450 -395 400 -405 1 1 6 N
S 450 -295 400 -305 1 1 6 N
S 450 -195 400 -205 1 1 6 N
S 450 -95 400 -105 1 1 6 N
S 450 5 400 -5 1 1 6 N
S 450 105 400 95 1 1 6 N
S 450 205 400 195 1 1 6 N
S 450 305 400 295 1 1 6 N
S 450 405 400 395 1 1 6 N
S 450 505 400 495 1 1 6 N
S 450 605 400 595 1 1 6 N
S 450 705 400 695 1 1 6 N
S 450 805 400 795 1 1 6 N
S 450 905 400 895 1 1 6 N
X VCC 1 -600 900 150 R 50 50 1 1 W
X ~TFT_WR 10 600 500 150 L 50 50 1 1 P
X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P
X TFT_TE 12 600 400 150 L 50 50 1 1 I
X TFT_D0 13 -600 300 150 R 50 50 1 1 P
X TFT_D1 14 600 300 150 L 50 50 1 1 P
X TFT_D2 15 -600 200 150 R 50 50 1 1 P
X TFT_D3 16 600 200 150 L 50 50 1 1 P
X TFT_D4 17 -600 100 150 R 50 50 1 1 P
X TFT_D5 18 600 100 150 L 50 50 1 1 P
X TFT_D6 19 -600 0 150 R 50 50 1 1 P
X GND 2 600 900 150 L 50 50 1 1 P
X TFT_D7 20 600 0 150 L 50 50 1 1 P
X TFT_D8 21 -600 -100 150 R 50 50 1 1 P
X TFT_D9 22 600 -100 150 L 50 50 1 1 P
X TFT_D10 23 -600 -200 150 R 50 50 1 1 P
X TFT_D11 24 600 -200 150 L 50 50 1 1 P
X TFT_D12 25 -600 -300 150 R 50 50 1 1 P
X TFT_D13 26 600 -300 150 L 50 50 1 1 P
X TFT_D14 27 -600 -400 150 R 50 50 1 1 P
X TFT_D15 28 600 -400 150 L 50 50 1 1 P
X TFT_D16 29 -600 -500 150 R 50 50 1 1 P
X CPT_SCL 3 -600 800 150 R 50 50 1 1 P
X TFT_D17 30 600 -500 150 L 50 50 1 1 P
X TFT_D18 31 -600 -600 150 R 50 50 1 1 P
X TFT_D19 32 600 -600 150 L 50 50 1 1 P
X TFT_D20 33 -600 -700 150 R 50 50 1 1 P
X TFT_D21 34 600 -700 150 L 50 50 1 1 P
X TFT_D22 35 -600 -800 150 R 50 50 1 1 P
X TFT_D23 36 600 -800 150 L 50 50 1 1 P
X TFT_STB 37 -600 -900 150 R 50 50 1 1 P
X NC 38 600 -900 150 L 50 50 1 1 N
X Pin_39 39 -600 -1000 150 R 50 50 1 1 P
X CPT_SDA 4 600 800 150 L 50 50 1 1 P
X NC 40 600 -1000 150 L 50 50 1 1 N
X CPT_INT 5 -600 700 150 R 50 50 1 1 P
X TFT_GPO 6 600 700 150 L 50 50 1 1 O
X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P
X TFT_D/C 8 600 600 150 L 50 50 1 1 P
X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Conn_02x20_Odd_Even_LCD_INTF
#
DEF Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N
F0 "J" 0 -1100 50 H V C CNN
F1 "Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN
F2 "" -400 0 50 H I C CNN
F3 "" -400 0 50 H I C CNN
$FPLIST
Connector*:*_2x??-1MP*
$ENDFPLIST
DRAW
S -450 -995 -400 -1005 1 1 6 N
S -450 -895 -400 -905 1 1 6 N
S -450 -795 -400 -805 1 1 6 N
S -450 -695 -400 -705 1 1 6 N
S -450 -595 -400 -605 1 1 6 N
S -450 -495 -400 -505 1 1 6 N
S -450 -395 -400 -405 1 1 6 N
S -450 -295 -400 -305 1 1 6 N
S -450 -195 -400 -205 1 1 6 N
S -450 -95 -400 -105 1 1 6 N
S -450 5 -400 -5 1 1 6 N
S -450 105 -400 95 1 1 6 N
S -450 205 -400 195 1 1 6 N
S -450 305 -400 295 1 1 6 N
S -450 405 -400 395 1 1 6 N
S -450 505 -400 495 1 1 6 N
S -450 605 -400 595 1 1 6 N
S -450 705 -400 695 1 1 6 N
S -450 805 -400 795 1 1 6 N
S -450 905 -400 895 1 1 6 N
S -450 950 450 -1050 1 1 10 f
S 450 -995 400 -1005 1 1 6 N
S 450 -895 400 -905 1 1 6 N
S 450 -795 400 -805 1 1 6 N
S 450 -695 400 -705 1 1 6 N
S 450 -595 400 -605 1 1 6 N
S 450 -495 400 -505 1 1 6 N
S 450 -395 400 -405 1 1 6 N
S 450 -295 400 -305 1 1 6 N
S 450 -195 400 -205 1 1 6 N
S 450 -95 400 -105 1 1 6 N
S 450 5 400 -5 1 1 6 N
S 450 105 400 95 1 1 6 N
S 450 205 400 195 1 1 6 N
S 450 305 400 295 1 1 6 N
S 450 405 400 395 1 1 6 N
S 450 505 400 495 1 1 6 N
S 450 605 400 595 1 1 6 N
S 450 705 400 695 1 1 6 N
S 450 805 400 795 1 1 6 N
S 450 905 400 895 1 1 6 N
X VCC 1 -600 900 150 R 50 50 1 1 W
X ~TFT_WR 10 600 500 150 L 50 50 1 1 P
X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P
X TFT_TE 12 600 400 150 L 50 50 1 1 I
X TFT_D0 13 -600 300 150 R 50 50 1 1 P
X TFT_D1 14 600 300 150 L 50 50 1 1 P
X TFT_D2 15 -600 200 150 R 50 50 1 1 P
X TFT_D3 16 600 200 150 L 50 50 1 1 P
X TFT_D4 17 -600 100 150 R 50 50 1 1 P
X TFT_D5 18 600 100 150 L 50 50 1 1 P
X TFT_D6 19 -600 0 150 R 50 50 1 1 P
X GND 2 600 900 150 L 50 50 1 1 P
X TFT_D7 20 600 0 150 L 50 50 1 1 P
X TFT_D8 21 -600 -100 150 R 50 50 1 1 P
X TFT_D9 22 600 -100 150 L 50 50 1 1 P
X TFT_D10 23 -600 -200 150 R 50 50 1 1 P
X TFT_D11 24 600 -200 150 L 50 50 1 1 P
X TFT_D12 25 -600 -300 150 R 50 50 1 1 P
X TFT_D13 26 600 -300 150 L 50 50 1 1 P
X TFT_D14 27 -600 -400 150 R 50 50 1 1 P
X TFT_D15 28 600 -400 150 L 50 50 1 1 P
X TFT_D16 29 -600 -500 150 R 50 50 1 1 P
X CPT_SCL 3 -600 800 150 R 50 50 1 1 P
X TFT_D17 30 600 -500 150 L 50 50 1 1 P
X TFT_D18 31 -600 -600 150 R 50 50 1 1 P
X TFT_D19 32 600 -600 150 L 50 50 1 1 P
X TFT_D20 33 -600 -700 150 R 50 50 1 1 P
X TFT_D21 34 600 -700 150 L 50 50 1 1 P
X TFT_D22 35 -600 -800 150 R 50 50 1 1 P
X TFT_D23 36 600 -800 150 L 50 50 1 1 P
X TFT_STB 37 -600 -900 150 R 50 50 1 1 P
X NC 38 600 -900 150 L 50 50 1 1 N
X Pin_39 39 -600 -1000 150 R 50 50 1 1 P
X CPT_SDA 4 600 800 150 L 50 50 1 1 P
X NC 40 600 -1000 150 L 50 50 1 1 N
X CPT_INT 5 -600 700 150 R 50 50 1 1 P
X TFT_GPO 6 600 700 150 L 50 50 1 1 O
X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P
X TFT_D/C 8 600 600 150 L 50 50 1 1 P
X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

6
electrical/same54_dev_board/libraries/MAX7301AAX_.dcm
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library

120
electrical/same54_dev_board/libraries/MAX7301AAX_.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# MAX7301AAX+
#
DEF MAX7301AAX+ U 0 40 Y Y 1 L N
F0 "U" -500 1339 50 H V L BNN
F1 "MAX7301AAX+" -500 -1457 50 H V L BNN
F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN
F3 "Maxim Integrated" 0 0 50 H I L BNN
F4 "None" 0 0 50 H I L BNN
F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN
F6 "SSOP-36 Maxim" 0 0 50 H I L BNN
F7 "Unavailable" 0 0 50 H I L BNN
F8 "MAX7301AAX+" 0 0 50 H I L BNN
DRAW
P 2 0 0 16 -500 -1300 -500 1300 N
P 2 0 0 16 -500 1300 500 1300 N
P 2 0 0 16 500 -1300 -500 -1300 N
P 2 0 0 16 500 1300 500 -1300 N
X ISET 1 -700 1000 200 R 40 40 0 0 I
X P9 10 -700 0 200 R 40 40 0 0 B
X P10 11 -700 -100 200 R 40 40 0 0 B
X P11 12 -700 -200 200 R 40 40 0 0 B
X P12 13 -700 -300 200 R 40 40 0 0 B
X P13 14 -700 -400 200 R 40 40 0 0 B
X P14 15 -700 -500 200 R 40 40 0 0 B
X P15 16 -700 -600 200 R 40 40 0 0 B
X P16 17 -700 -700 200 R 40 40 0 0 B
X P17 18 -700 -800 200 R 40 40 0 0 B
X P18 19 700 500 200 L 40 40 0 0 B
X GND 2 700 -1100 200 L 40 40 0 0 W
X P19 20 700 400 200 L 40 40 0 0 B
X P20 21 700 300 200 L 40 40 0 0 B
X P21 22 700 200 200 L 40 40 0 0 B
X P22 23 700 100 200 L 40 40 0 0 B
X P23 24 700 0 200 L 40 40 0 0 B
X P24 25 700 -100 200 L 40 40 0 0 B
X P25 26 700 -200 200 L 40 40 0 0 B
X P26 27 700 -300 200 L 40 40 0 0 B
X P27 28 700 -400 200 L 40 40 0 0 B
X P28 29 700 -500 200 L 40 40 0 0 B
X GND 3 700 -1000 200 L 40 40 0 0 W
X P29 30 700 -600 200 L 40 40 0 0 B
X P30 31 700 -700 200 L 40 40 0 0 B
X P31 32 700 -800 200 L 40 40 0 0 B
X SCLK 33 700 900 200 L 40 40 0 0 I C
X DIN 34 700 800 200 L 40 40 0 0 I
X CS 35 700 1000 200 L 40 40 0 0 I
X V+ 36 700 1200 200 L 40 40 0 0 W
X DOUT 4 700 700 200 L 40 40 0 0 O
X P4 5 -700 500 200 R 40 40 0 0 B
X P5 6 -700 400 200 R 40 40 0 0 B
X P6 7 -700 300 200 R 40 40 0 0 B
X P7 8 -700 200 200 R 40 40 0 0 B
X P8 9 -700 100 200 R 40 40 0 0 B
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# MAX7301AAX+
#
DEF MAX7301AAX+ U 0 40 Y Y 1 L N
F0 "U" -500 1339 50 H V L BNN
F1 "MAX7301AAX+" -500 -1457 50 H V L BNN
F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN
F3 "Maxim Integrated" 0 0 50 H I L BNN
F4 "None" 0 0 50 H I L BNN
F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN
F6 "SSOP-36 Maxim" 0 0 50 H I L BNN
F7 "Unavailable" 0 0 50 H I L BNN
F8 "MAX7301AAX+" 0 0 50 H I L BNN
DRAW
P 2 0 0 16 -500 -1300 -500 1300 N
P 2 0 0 16 -500 1300 500 1300 N
P 2 0 0 16 500 -1300 -500 -1300 N
P 2 0 0 16 500 1300 500 -1300 N
X ISET 1 -700 1000 200 R 40 40 0 0 I
X P9 10 -700 0 200 R 40 40 0 0 B
X P10 11 -700 -100 200 R 40 40 0 0 B
X P11 12 -700 -200 200 R 40 40 0 0 B
X P12 13 -700 -300 200 R 40 40 0 0 B
X P13 14 -700 -400 200 R 40 40 0 0 B
X P14 15 -700 -500 200 R 40 40 0 0 B
X P15 16 -700 -600 200 R 40 40 0 0 B
X P16 17 -700 -700 200 R 40 40 0 0 B
X P17 18 -700 -800 200 R 40 40 0 0 B
X P18 19 700 500 200 L 40 40 0 0 B
X GND 2 700 -1100 200 L 40 40 0 0 W
X P19 20 700 400 200 L 40 40 0 0 B
X P20 21 700 300 200 L 40 40 0 0 B
X P21 22 700 200 200 L 40 40 0 0 B
X P22 23 700 100 200 L 40 40 0 0 B
X P23 24 700 0 200 L 40 40 0 0 B
X P24 25 700 -100 200 L 40 40 0 0 B
X P25 26 700 -200 200 L 40 40 0 0 B
X P26 27 700 -300 200 L 40 40 0 0 B
X P27 28 700 -400 200 L 40 40 0 0 B
X P28 29 700 -500 200 L 40 40 0 0 B
X GND 3 700 -1000 200 L 40 40 0 0 W
X P29 30 700 -600 200 L 40 40 0 0 B
X P30 31 700 -700 200 L 40 40 0 0 B
X P31 32 700 -800 200 L 40 40 0 0 B
X SCLK 33 700 900 200 L 40 40 0 0 I C
X DIN 34 700 800 200 L 40 40 0 0 I
X CS 35 700 1000 200 L 40 40 0 0 I
X V+ 36 700 1200 200 L 40 40 0 0 W
X DOUT 4 700 700 200 L 40 40 0 0 O
X P4 5 -700 500 200 R 40 40 0 0 B
X P5 6 -700 400 200 R 40 40 0 0 B
X P6 7 -700 300 200 R 40 40 0 0 B
X P7 8 -700 200 200 R 40 40 0 0 B
X P8 9 -700 100 200 R 40 40 0 0 B
ENDDRAW
ENDDEF
#
#End Library

6
electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.dcm
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library

30
electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# TPS73733QDRBRQ1
#
DEF TPS73733QDRBRQ1 U 0 40 Y Y 1 F N
F0 "U" 0 -400 50 H V C CNN
F1 "TPS73733QDRBRQ1" 0 450 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
ENDDRAW
ENDDEF
#
#End Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# TPS73733QDRBRQ1
#
DEF TPS73733QDRBRQ1 U 0 40 Y Y 1 F N
F0 "U" 0 -400 50 H V C CNN
F1 "TPS73733QDRBRQ1" 0 450 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
ENDDRAW
ENDDEF
#
#End Library

114
electrical/same54_dev_board/modules/proj_modules.pretty/SOP80P1030X264-36N.kicad_mod
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(module SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418)
(descr "")
(fp_text reference REF** (at -2.415 -8.587 0) (layer F.SilkS)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_text value SOP80P1030X264-36N (at 5.84 8.587 0) (layer F.Fab)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2))
(fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2))
(fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127))
(fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127))
(fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127))
(fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127))
(fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127))
(fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127))
(fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 2 smd rect (at -4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 7 smd rect (at -4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 12 smd rect (at -4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 17 smd rect (at -4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 20 smd rect (at 4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 25 smd rect (at 4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 30 smd rect (at 4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 35 smd rect (at 4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste))
(module SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418)
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electrical/same54_dev_board/same54_dev_board-cache.lib
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electrical/same54_dev_board/same54_dev_board.kicad_pcb
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electrical/same54_dev_board/same54_dev_board.pro
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@ -1,43 +1,43 @@
update=Sun 19 Apr 2020 04:53:03 PM CDT
version=1
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update=Sun 19 Apr 2020 04:53:03 PM CDT
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[general]
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456
electrical/same54_dev_board/same54_dev_board.sch
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@ -1,228 +1,228 @@
EESchema Schematic File Version 4
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Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain.
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456
electrical/same54_dev_board/same54_dev_board.sch-bak
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Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain.
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A 11000 8500
encoding utf-8
Sheet 1 5
Title "Project Oracle"
Date "2020-03-16"
Rev "v0.1"
Comp ""
Comment1 ""
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Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain.
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12
electrical/same54_dev_board/sym-lib-table
Unescape Escape View File

@ -1,6 +1,6 @@
(sym_lib_table
(lib (name same54_dev_board-rescue)(type Legacy)(uri ${KIPRJMOD}/same54_dev_board-rescue.lib)(options "")(descr ""))
(lib (name Conn_02x20_LCD_INTF)(type Legacy)(uri ${KIPRJMOD}/libraries/Conn_02x20_LCD_INTF.lib)(options "")(descr ""))
(lib (name MAX7301AAX_)(type Legacy)(uri ${KIPRJMOD}/libraries/MAX7301AAX_.lib)(options "")(descr ""))
(lib (name TPS73733QDRBRQ1)(type Legacy)(uri ${KIPRJMOD}/libraries/TPS73733QDRBRQ1.lib)(options "")(descr ""))
)
(sym_lib_table
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(lib (name Conn_02x20_LCD_INTF)(type Legacy)(uri ${KIPRJMOD}/libraries/Conn_02x20_LCD_INTF.lib)(options "")(descr ""))
(lib (name MAX7301AAX_)(type Legacy)(uri ${KIPRJMOD}/libraries/MAX7301AAX_.lib)(options "")(descr ""))
(lib (name TPS73733QDRBRQ1)(type Legacy)(uri ${KIPRJMOD}/libraries/TPS73733QDRBRQ1.lib)(options "")(descr ""))
)

34
software/README.md
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@ -1,17 +1,17 @@
# Software Readme
## Goals
- Fish Tank Controller that will monitor and send updates via wifi (or ethernet idk yet???)
## To Do
- PCB
- Decide on core reqs (ex: do i want wifi or NOT)
- map pins
- create bare software for pin mappings
- fix asf4 vomit <<<emoji here>>>
- Get make based asf4 project to compile (i have toolchains wtf why no work)
## Info
# Software Readme
## Goals
- Fish Tank Controller that will monitor and send updates via wifi (or ethernet idk yet???)
## To Do
- PCB
- Decide on core reqs (ex: do i want wifi or NOT)
- map pins
- create bare software for pin mappings
- fix asf4 vomit <<<emoji here>>>
- Get make based asf4 project to compile (i have toolchains wtf why no work)
## Info

2354
software/conf/project_oractle_config.atstart
View File

File diff suppressed because it is too large Load Diff

12
software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf
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@ -1,6 +1,6 @@
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
</device-packs>
</environment>
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
</device-packs>
</environment>

430
software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc
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@ -1,215 +1,215 @@
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
<vendor>Atmel</vendor>
<name>My Project</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
<releases>
<release version="1.0.1">Initial version</release>
</releases>
<taxonomy>
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
</taxonomy>
<generators>
<generator id="AtmelStart">
<description>Atmel Start</description>
<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
<command>http://start.atmel.com/</command>
<files>
<file category="generator" name="atmel_start_config.atstart"/>
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
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</generator>
</generators>
<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
</condition>
<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="GCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
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</package>
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<name>My Project</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
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<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
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<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
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<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="GCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
</files>
</component>
</components>
</package>

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart
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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h
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/* Auto-generated config file hpl_cmcc_config.h */
#ifndef HPL_CMCC_CONFIG_H
#define HPL_CMCC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Configuration
// <q> Cache enable
//<i> Defines the cache should be enabled or not.
// <id> cmcc_enable
#ifndef CONF_CMCC_ENABLE
#define CONF_CMCC_ENABLE 0x0
#endif
// <o> Cache Size
//<i> Defines the cache memory size to be configured.
// <0x0=>1 KB
// <0x1=>2 KB
// <0x2=>4 KB
// <id> cache_size
#ifndef CONF_CMCC_CACHE_SIZE
#define CONF_CMCC_CACHE_SIZE 0x2
#endif
// <e> Advanced Configuration
// <id> cmcc_advanced_configuration
// <q> Data cache disable
//<i> Defines the data cache should be disabled or not.
// <id> cmcc_data_cache_disable
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
#endif
// <q> Instruction cache disable
//<i> Defines the Instruction cache should be disabled or not.
// <id> cmcc_inst_cache_disable
#ifndef CONF_CMCC_INST_CACHE_DISABLE
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
#endif
// <q> Clock Gating disable
//<i> Defines the clock gating should be disabled or not.
// <id> cmcc_clock_gating_disable
#ifndef CONF_CMCC_CLK_GATING_DISABLE
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_CMCC_CONFIG_H
/* Auto-generated config file hpl_cmcc_config.h */
#ifndef HPL_CMCC_CONFIG_H
#define HPL_CMCC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Configuration
// <q> Cache enable
//<i> Defines the cache should be enabled or not.
// <id> cmcc_enable
#ifndef CONF_CMCC_ENABLE
#define CONF_CMCC_ENABLE 0x0
#endif
// <o> Cache Size
//<i> Defines the cache memory size to be configured.
// <0x0=>1 KB
// <0x1=>2 KB
// <0x2=>4 KB
// <id> cache_size
#ifndef CONF_CMCC_CACHE_SIZE
#define CONF_CMCC_CACHE_SIZE 0x2
#endif
// <e> Advanced Configuration
// <id> cmcc_advanced_configuration
// <q> Data cache disable
//<i> Defines the data cache should be disabled or not.
// <id> cmcc_data_cache_disable
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
#endif
// <q> Instruction cache disable
//<i> Defines the Instruction cache should be disabled or not.
// <id> cmcc_inst_cache_disable
#ifndef CONF_CMCC_INST_CACHE_DISABLE
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
#endif
// <q> Clock Gating disable
//<i> Defines the clock gating should be disabled or not.
// <id> cmcc_clock_gating_disable
#ifndef CONF_CMCC_CLK_GATING_DISABLE
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_CMCC_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h
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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h
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/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
#endif
// <y> Low Power Clock Division
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_lpdiv
#ifndef CONF_MCLK_LPDIV
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
#endif
// <y> High-Speed Clock Division
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
// <id> mclk_arch_hsdiv
#ifndef CONF_MCLK_HSDIV
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 5
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H
/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
#endif
// <y> Low Power Clock Division
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_lpdiv
#ifndef CONF_MCLK_LPDIV
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
#endif
// <y> High-Speed Clock Division
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
// <id> mclk_arch_hsdiv
#ifndef CONF_MCLK_HSDIV
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 5
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h
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/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 0
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x3
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 1
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// <o> Control Gain Mode
// <0x0=>Low Power mode
// <0x1=>Standard mode
// <0x2=>High Speed mode
// <id> xosc32k_arch_cgm
#ifndef CONF_XOSC32K_CGM
#define CONF_XOSC32K_CGM 0x1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x3F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H
/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 0
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x3
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 1
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// <o> Control Gain Mode
// <0x0=>Low Power mode
// <0x1=>Standard mode
// <0x2=>High Speed mode
// <id> xosc32k_arch_cgm
#ifndef CONF_XOSC32K_CGM
#define CONF_XOSC32K_CGM 0x1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x3F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h
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/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef CONF_SERCOM_2_USART_ENABLE
#define CONF_SERCOM_2_USART_ENABLE 1
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
#ifndef CONF_SERCOM_2_USART_RXEN
#define CONF_SERCOM_2_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
#ifndef CONF_SERCOM_2_USART_TXEN
#define CONF_SERCOM_2_USART_TXEN 1
#endif
// <o> Frame parity
// <0x0=>No parity
// <0x1=>Even parity
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
#ifndef CONF_SERCOM_2_USART_PARITY
#define CONF_SERCOM_2_USART_PARITY 0x0
#endif
// <o> Character Size
// <0x0=>8 bits
// <0x1=>9 bits
// <0x5=>5 bits
// <0x6=>6 bits
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
#ifndef CONF_SERCOM_2_USART_CHSIZE
#define CONF_SERCOM_2_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
// <0=>One stop bit
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
#ifndef CONF_SERCOM_2_USART_SBMODE
#define CONF_SERCOM_2_USART_SBMODE 0
#endif
// <o> Baud rate <1-6250000>
// <i> USART baud rate setting
// <id> usart_baud_rate
#ifndef CONF_SERCOM_2_USART_BAUD
#define CONF_SERCOM_2_USART_BAUD 115200
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
#define CONF_SERCOM_2_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
#ifndef CONF_SERCOM_2_USART_IBON
#define CONF_SERCOM_2_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
#ifndef CONF_SERCOM_2_USART_SFDE
#define CONF_SERCOM_2_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
#ifndef CONF_SERCOM_2_USART_CLODEN
#define CONF_SERCOM_2_USART_CLODEN 0
#endif
// <o> Operating Mode
// <0x0=>USART with external clock
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
#ifndef CONF_SERCOM_2_USART_MODE
#define CONF_SERCOM_2_USART_MODE 0x1
#endif
// <o> Sample Rate
// <0x0=>16x arithmetic
// <0x1=>16x fractional
// <0x2=>8x arithmetic
// <0x3=>8x fractional
// <0x4=>3x arithmetic
// <i> How many over-sampling bits used when sampling data state
// <id> usart_arch_sampr
#ifndef CONF_SERCOM_2_USART_SAMPR
#define CONF_SERCOM_2_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
#ifndef CONF_SERCOM_2_USART_SAMPA
#define CONF_SERCOM_2_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
// <0=>MSB is transmitted first
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
#ifndef CONF_SERCOM_2_USART_DORD
#define CONF_SERCOM_2_USART_DORD 1
#endif
// Does not do anything in UART mode
#define CONF_SERCOM_2_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
#ifndef CONF_SERCOM_2_USART_ENC
#define CONF_SERCOM_2_USART_ENC 0
#endif
// <o> LIN Slave Enable
// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
// <0=>Disable
// <1=>Enable
// <id> usart_arch_lin_slave_enable
#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_2_USART_INACK
#define CONF_SERCOM_2_USART_INACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_DSNACK
#define CONF_SERCOM_2_USART_DSNACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_MAXITER
#define CONF_SERCOM_2_USART_MAXITER 0x7
#endif
#ifndef CONF_SERCOM_2_USART_GTIME
#define CONF_SERCOM_2_USART_GTIME 0x2
#endif
#define CONF_SERCOM_2_USART_RXINV 0x0
#define CONF_SERCOM_2_USART_TXINV 0x0
#ifndef CONF_SERCOM_2_USART_CMODE
#define CONF_SERCOM_2_USART_CMODE 0
#endif
#ifndef CONF_SERCOM_2_USART_RXPO
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
#endif
#ifndef CONF_SERCOM_2_USART_TXPO
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 4
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 5
#endif
#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 0
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 1
#endif
#endif
// Calculate BAUD register value in UART mode
#if CONF_SERCOM_2_USART_SAMPR == 0
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 1
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 2
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 3
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 4
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_3_I2CM_ENABLE
#define CONF_SERCOM_3_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_3_I2CM_BAUD
#define CONF_SERCOM_3_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN
#define CONF_SERCOM_3_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN
#define CONF_SERCOM_3_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_3_I2CM_LOWTOUT
#define CONF_SERCOM_3_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_3_I2CM_INACTOUT
#define CONF_SERCOM_3_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_3_I2CM_SDAHOLD
#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY
#define CONF_SERCOM_3_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_3_I2CM_SPEED
#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215U
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \
- (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \
/ 1000U)) \
* 10U \
+ 5U) \
/ (CONF_SERCOM_3_I2CM_BAUD * 10U))
#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE
#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_3_I2CM_BAUD_RATE \
((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H
/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef CONF_SERCOM_2_USART_ENABLE
#define CONF_SERCOM_2_USART_ENABLE 1
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
#ifndef CONF_SERCOM_2_USART_RXEN
#define CONF_SERCOM_2_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
#ifndef CONF_SERCOM_2_USART_TXEN
#define CONF_SERCOM_2_USART_TXEN 1
#endif
// <o> Frame parity
// <0x0=>No parity
// <0x1=>Even parity
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
#ifndef CONF_SERCOM_2_USART_PARITY
#define CONF_SERCOM_2_USART_PARITY 0x0
#endif
// <o> Character Size
// <0x0=>8 bits
// <0x1=>9 bits
// <0x5=>5 bits
// <0x6=>6 bits
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
#ifndef CONF_SERCOM_2_USART_CHSIZE
#define CONF_SERCOM_2_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
// <0=>One stop bit
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
#ifndef CONF_SERCOM_2_USART_SBMODE
#define CONF_SERCOM_2_USART_SBMODE 0
#endif
// <o> Baud rate <1-6250000>
// <i> USART baud rate setting
// <id> usart_baud_rate
#ifndef CONF_SERCOM_2_USART_BAUD
#define CONF_SERCOM_2_USART_BAUD 115200
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
#define CONF_SERCOM_2_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
#ifndef CONF_SERCOM_2_USART_IBON
#define CONF_SERCOM_2_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
#ifndef CONF_SERCOM_2_USART_SFDE
#define CONF_SERCOM_2_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
#ifndef CONF_SERCOM_2_USART_CLODEN
#define CONF_SERCOM_2_USART_CLODEN 0
#endif
// <o> Operating Mode
// <0x0=>USART with external clock
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
#ifndef CONF_SERCOM_2_USART_MODE
#define CONF_SERCOM_2_USART_MODE 0x1
#endif
// <o> Sample Rate
// <0x0=>16x arithmetic
// <0x1=>16x fractional
// <0x2=>8x arithmetic
// <0x3=>8x fractional
// <0x4=>3x arithmetic
// <i> How many over-sampling bits used when sampling data state
// <id> usart_arch_sampr
#ifndef CONF_SERCOM_2_USART_SAMPR
#define CONF_SERCOM_2_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
#ifndef CONF_SERCOM_2_USART_SAMPA
#define CONF_SERCOM_2_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
// <0=>MSB is transmitted first
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
#ifndef CONF_SERCOM_2_USART_DORD
#define CONF_SERCOM_2_USART_DORD 1
#endif
// Does not do anything in UART mode
#define CONF_SERCOM_2_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
#ifndef CONF_SERCOM_2_USART_ENC
#define CONF_SERCOM_2_USART_ENC 0
#endif
// <o> LIN Slave Enable
// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
// <0=>Disable
// <1=>Enable
// <id> usart_arch_lin_slave_enable
#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_2_USART_INACK
#define CONF_SERCOM_2_USART_INACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_DSNACK
#define CONF_SERCOM_2_USART_DSNACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_MAXITER
#define CONF_SERCOM_2_USART_MAXITER 0x7
#endif
#ifndef CONF_SERCOM_2_USART_GTIME
#define CONF_SERCOM_2_USART_GTIME 0x2
#endif
#define CONF_SERCOM_2_USART_RXINV 0x0
#define CONF_SERCOM_2_USART_TXINV 0x0
#ifndef CONF_SERCOM_2_USART_CMODE
#define CONF_SERCOM_2_USART_CMODE 0
#endif
#ifndef CONF_SERCOM_2_USART_RXPO
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
#endif
#ifndef CONF_SERCOM_2_USART_TXPO
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 4
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 5
#endif
#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 0
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 1
#endif
#endif
// Calculate BAUD register value in UART mode
#if CONF_SERCOM_2_USART_SAMPR == 0
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 1
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 2
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 3
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 4
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_3_I2CM_ENABLE
#define CONF_SERCOM_3_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_3_I2CM_BAUD
#define CONF_SERCOM_3_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN
#define CONF_SERCOM_3_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN
#define CONF_SERCOM_3_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_3_I2CM_LOWTOUT
#define CONF_SERCOM_3_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_3_I2CM_INACTOUT
#define CONF_SERCOM_3_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_3_I2CM_SDAHOLD
#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY
#define CONF_SERCOM_3_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_3_I2CM_SPEED
#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215U
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \
- (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \
/ 1000U)) \
* 10U \
+ 5U) \
/ (CONF_SERCOM_3_I2CM_BAUD * 10U))
#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE
#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_3_I2CM_BAUD_RATE \
((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h
Unescape Escape View File

@ -1,180 +1,180 @@
/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 1
#endif
#include "peripheral_clk_config.h"
// <h> Basic configuration
// <o> Prescaler
// <0x0=> No division
// <0x1=> Divide by 2
// <0x2=> Divide by 4
// <0x3=> Divide by 8
// <0x4=> Divide by 16
// <0x5=> Divide by 64
// <0x6=> Divide by 256
// <0x7=> Divide by 1024
// <i> This defines the prescaler value
// <id> timer_prescaler
#ifndef CONF_TC0_PRESCALER
#define CONF_TC0_PRESCALER 0x3
#endif
// <o> Length of one timer tick in uS <0-4294967295>
// <id> timer_tick
#ifndef CONF_TC0_TIMER_TICK
#define CONF_TC0_TIMER_TICK 1000
#endif
// </h>
// <e> Advanced configuration
// <id> timer_advanced_configuration
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC0_PRESCSYNC
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <q> Run in standby
// <i> Indicates whether the module will continue to run in standby sleep mode
// <id> tc_arch_runstdby
#ifndef CONF_TC0_RUNSTDBY
#define CONF_TC0_RUNSTDBY 0
#endif
// <q> Run in debug mode
// <i> Indicates whether the module will run in debug mode
// <id> tc_arch_dbgrun
#ifndef CONF_TC0_DBGRUN
#define CONF_TC0_DBGRUN 0
#endif
// <q> Run on demand
// <i> Run if requested by some other peripheral in the device
// <id> tc_arch_ondemand
#ifndef CONF_TC0_ONDEMAND
#define CONF_TC0_ONDEMAND 0
#endif
// </e>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
#endif
// <q> Output Event On Match or Capture on Channel 0
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo0
#ifndef CONF_TC0_MCEO0
#define CONF_TC0_MCEO0 0
#endif
// <q> Output Event On Match or Capture on Channel 1
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo1
#ifndef CONF_TC0_MCEO1
#define CONF_TC0_MCEO1 0
#endif
// <q> Output Event On Timer Tick
// <i> Enable output of event on timer tick
// <id> tc_arch_ovfeo
#ifndef CONF_TC0_OVFEO
#define CONF_TC0_OVFEO 0
#endif
// <q> Event Input
// <i> Enable asynchronous input events
// <id> tc_arch_tcei
#ifndef CONF_TC0_TCEI
#define CONF_TC0_TCEI 0
#endif
// <q> Inverted Event Input
// <i> Invert the asynchronous input events
// <id> tc_arch_tcinv
#ifndef CONF_TC0_TCINV
#define CONF_TC0_TCINV 0
#endif
// <o> Event action
// <0=> Event action disabled
// <1=> Start, restart or re-trigger TC on event
// <2=> Count on event
// <3=> Start on event
// <4=> Time stamp capture
// <5=> Period captured in CC0, pulse width in CC1
// <6=> Period captured in CC1, pulse width in CC0
// <7=> Pulse width capture
// <i> Event which will be performed on an event
//<id> tc_arch_evact
#ifndef CONF_TC0_EVACT
#define CONF_TC0_EVACT 0
#endif
// </e>
// Default values which the driver needs in order to work correctly
// Mode set to 32-bit
#ifndef CONF_TC0_MODE
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
#endif
// CC 1 register set to 0
#ifndef CONF_TC0_CC1
#define CONF_TC0_CC1 0
#endif
#ifndef CONF_TC0_ALOCK
#define CONF_TC0_ALOCK 0
#endif
// Not used in 32-bit mode
#define CONF_TC0_PER 0
// Calculating correct top value based on requested tick interval.
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
// Prescaler set to 64
#if CONF_TC0_PRESCALER > 0x4
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 64
#endif
// Prescaler set to 256
#if CONF_TC0_PRESCALER > 0x5
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 256
#endif
// Prescaler set to 1024
#if CONF_TC0_PRESCALER > 0x6
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 1024
#endif
#ifndef CONF_TC0_CC0
#define CONF_TC0_CC0 \
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
#endif
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H
/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 1
#endif
#include "peripheral_clk_config.h"
// <h> Basic configuration
// <o> Prescaler
// <0x0=> No division
// <0x1=> Divide by 2
// <0x2=> Divide by 4
// <0x3=> Divide by 8
// <0x4=> Divide by 16
// <0x5=> Divide by 64
// <0x6=> Divide by 256
// <0x7=> Divide by 1024
// <i> This defines the prescaler value
// <id> timer_prescaler
#ifndef CONF_TC0_PRESCALER
#define CONF_TC0_PRESCALER 0x3
#endif
// <o> Length of one timer tick in uS <0-4294967295>
// <id> timer_tick
#ifndef CONF_TC0_TIMER_TICK
#define CONF_TC0_TIMER_TICK 1000
#endif
// </h>
// <e> Advanced configuration
// <id> timer_advanced_configuration
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC0_PRESCSYNC
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <q> Run in standby
// <i> Indicates whether the module will continue to run in standby sleep mode
// <id> tc_arch_runstdby
#ifndef CONF_TC0_RUNSTDBY
#define CONF_TC0_RUNSTDBY 0
#endif
// <q> Run in debug mode
// <i> Indicates whether the module will run in debug mode
// <id> tc_arch_dbgrun
#ifndef CONF_TC0_DBGRUN
#define CONF_TC0_DBGRUN 0
#endif
// <q> Run on demand
// <i> Run if requested by some other peripheral in the device
// <id> tc_arch_ondemand
#ifndef CONF_TC0_ONDEMAND
#define CONF_TC0_ONDEMAND 0
#endif
// </e>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
#endif
// <q> Output Event On Match or Capture on Channel 0
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo0
#ifndef CONF_TC0_MCEO0
#define CONF_TC0_MCEO0 0
#endif
// <q> Output Event On Match or Capture on Channel 1
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo1
#ifndef CONF_TC0_MCEO1
#define CONF_TC0_MCEO1 0
#endif
// <q> Output Event On Timer Tick
// <i> Enable output of event on timer tick
// <id> tc_arch_ovfeo
#ifndef CONF_TC0_OVFEO
#define CONF_TC0_OVFEO 0
#endif
// <q> Event Input
// <i> Enable asynchronous input events
// <id> tc_arch_tcei
#ifndef CONF_TC0_TCEI
#define CONF_TC0_TCEI 0
#endif
// <q> Inverted Event Input
// <i> Invert the asynchronous input events
// <id> tc_arch_tcinv
#ifndef CONF_TC0_TCINV
#define CONF_TC0_TCINV 0
#endif
// <o> Event action
// <0=> Event action disabled
// <1=> Start, restart or re-trigger TC on event
// <2=> Count on event
// <3=> Start on event
// <4=> Time stamp capture
// <5=> Period captured in CC0, pulse width in CC1
// <6=> Period captured in CC1, pulse width in CC0
// <7=> Pulse width capture
// <i> Event which will be performed on an event
//<id> tc_arch_evact
#ifndef CONF_TC0_EVACT
#define CONF_TC0_EVACT 0
#endif
// </e>
// Default values which the driver needs in order to work correctly
// Mode set to 32-bit
#ifndef CONF_TC0_MODE
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
#endif
// CC 1 register set to 0
#ifndef CONF_TC0_CC1
#define CONF_TC0_CC1 0
#endif
#ifndef CONF_TC0_ALOCK
#define CONF_TC0_ALOCK 0
#endif
// Not used in 32-bit mode
#define CONF_TC0_PER 0
// Calculating correct top value based on requested tick interval.
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
// Prescaler set to 64
#if CONF_TC0_PRESCALER > 0x4
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 64
#endif
// Prescaler set to 256
#if CONF_TC0_PRESCALER > 0x5
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 256
#endif
// Prescaler set to 1024
#if CONF_TC0_PRESCALER > 0x6
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 1024
#endif
#ifndef CONF_TC0_CC0
#define CONF_TC0_CC0 \
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
#endif
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H

514
software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h
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/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> EIC Clock Source
// <id> eic_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for EIC.
#ifndef CONF_GCLK_EIC_SRC
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_EIC_FREQUENCY
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 119997440
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 119997440
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
* \brief SERCOM2's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM3_CORE_SRC
#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
* \brief SERCOM3's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
* \brief SERCOM3's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC0_SRC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC0_FREQUENCY
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 119997440
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H
/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> EIC Clock Source
// <id> eic_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for EIC.
#ifndef CONF_GCLK_EIC_SRC
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_EIC_FREQUENCY
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 119997440
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 119997440
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
* \brief SERCOM2's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM3_CORE_SRC
#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
* \brief SERCOM3's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
* \brief SERCOM3's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC0_SRC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC0_FREQUENCY
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 119997440
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

18
software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c
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@ -1,9 +1,9 @@
#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
}
#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
}

36
software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h
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#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif
#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif

24
software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h
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@ -1,12 +1,12 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#endif // ATMEL_START_PINS_H_INCLUDED
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#endif // ATMEL_START_PINS_H_INCLUDED

268
software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c
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@ -1,134 +1,134 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
/*! The buffer size for USART */
#define USART_0_BUFFER_SIZE 16
struct usart_async_descriptor USART_0;
struct timer_descriptor TIMER_0;
static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE];
struct i2c_m_sync_desc I2C_0;
void EXTERNAL_IRQ_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
ext_irq_init();
}
/**
* \brief USART Clock initialization function
*
* Enables register interface and peripheral clock
*/
void USART_0_CLOCK_init()
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
/**
* \brief USART pinmux initialization function
*
* Set each required pin to USART functionality
*/
void USART_0_PORT_init()
{
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
/**
* \brief USART initialization function
*
* Enables USART peripheral, clocks and initializes USART driver
*/
void USART_0_init(void)
{
USART_0_CLOCK_init();
usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL);
USART_0_PORT_init();
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_pull_mode(PA22,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0);
gpio_set_pin_pull_mode(PA23,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1);
}
void I2C_0_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, SERCOM3);
I2C_0_PORT_init();
}
/**
* \brief Timer initialization function
*
* Enables Timer peripheral, clocks and initializes Timer driver
*/
static void TIMER_0_init(void)
{
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
timer_init(&TIMER_0, TC0, _tc_get_timer());
}
void system_init(void)
{
init_mcu();
EXTERNAL_IRQ_0_init();
USART_0_init();
I2C_0_init();
TIMER_0_init();
}
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
/*! The buffer size for USART */
#define USART_0_BUFFER_SIZE 16
struct usart_async_descriptor USART_0;
struct timer_descriptor TIMER_0;
static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE];
struct i2c_m_sync_desc I2C_0;
void EXTERNAL_IRQ_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
ext_irq_init();
}
/**
* \brief USART Clock initialization function
*
* Enables register interface and peripheral clock
*/
void USART_0_CLOCK_init()
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
/**
* \brief USART pinmux initialization function
*
* Set each required pin to USART functionality
*/
void USART_0_PORT_init()
{
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
/**
* \brief USART initialization function
*
* Enables USART peripheral, clocks and initializes USART driver
*/
void USART_0_init(void)
{
USART_0_CLOCK_init();
usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL);
USART_0_PORT_init();
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_pull_mode(PA22,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0);
gpio_set_pin_pull_mode(PA23,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1);
}
void I2C_0_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, SERCOM3);
I2C_0_PORT_init();
}
/**
* \brief Timer initialization function
*
* Enables Timer peripheral, clocks and initializes Timer driver
*/
static void TIMER_0_init(void)
{
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
timer_init(&TIMER_0, TC0, _tc_get_timer());
}
void system_init(void)
{
init_mcu();
EXTERNAL_IRQ_0_init();
USART_0_init();
I2C_0_init();
TIMER_0_init();
}

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_ext_irq.h>
#include <hal_usart_async.h>
#include <hal_i2c_m_sync.h>
#include <hal_timer.h>
#include <hpl_tc_base.h>
extern struct usart_async_descriptor USART_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct timer_descriptor TIMER_0;
void USART_0_PORT_init(void);
void USART_0_CLOCK_init(void);
void USART_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_ext_irq.h>
#include <hal_usart_async.h>
#include <hal_i2c_m_sync.h>
#include <hal_timer.h>
#include <hpl_tc_base.h>
extern struct usart_async_descriptor USART_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct timer_descriptor TIMER_0;
void USART_0_PORT_init(void);
void USART_0_CLOCK_init(void);
void USART_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using EXTERNAL_IRQ_0
*/
void EXTERNAL_IRQ_0_example(void)
{
}
/**
* Example of using USART_0 to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_USART_0[12] = "Hello World!";
static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr)
{
/* Transfer completed */
}
void USART_0_example(void)
{
struct io_descriptor *io;
usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0);
/*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb);
usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/
usart_async_get_io_descriptor(&USART_0, &io);
usart_async_enable(&USART_0);
io_write(io, example_USART_0, 12);
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
static struct timer_task TIMER_0_task1, TIMER_0_task2;
/**
* Example of using TIMER_0.
*/
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
{
}
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
{
}
void TIMER_0_example(void)
{
TIMER_0_task1.interval = 100;
TIMER_0_task1.cb = TIMER_0_task1_cb;
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
TIMER_0_task2.interval = 200;
TIMER_0_task2.cb = TIMER_0_task2_cb;
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
timer_add_task(&TIMER_0, &TIMER_0_task1);
timer_add_task(&TIMER_0, &TIMER_0_task2);
timer_start(&TIMER_0);
}
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using EXTERNAL_IRQ_0
*/
void EXTERNAL_IRQ_0_example(void)
{
}
/**
* Example of using USART_0 to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_USART_0[12] = "Hello World!";
static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr)
{
/* Transfer completed */
}
void USART_0_example(void)
{
struct io_descriptor *io;
usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0);
/*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb);
usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/
usart_async_get_io_descriptor(&USART_0, &io);
usart_async_enable(&USART_0);
io_write(io, example_USART_0, 12);
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
static struct timer_task TIMER_0_task1, TIMER_0_task2;
/**
* Example of using TIMER_0.
*/
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
{
}
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
{
}
void TIMER_0_example(void)
{
TIMER_0_task1.interval = 100;
TIMER_0_task1.cb = TIMER_0_task1_cb;
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
TIMER_0_task2.interval = 200;
TIMER_0_task2.cb = TIMER_0_task2_cb;
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
timer_add_task(&TIMER_0, &TIMER_0_task1);
timer_add_task(&TIMER_0, &TIMER_0_task2);
timer_start(&TIMER_0);
}

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void EXTERNAL_IRQ_0_example(void);
void USART_0_example(void);
void I2C_0_example(void);
void TIMER_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void EXTERNAL_IRQ_0_example(void);
void USART_0_example(void);
void I2C_0_example(void);
void TIMER_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED

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==============
EXT IRQ driver
==============
The External Interrupt driver allows external pins to be
configured as interrupt lines. Each interrupt line can be
individually masked and can generate an interrupt on rising,
falling or both edges, or on high or low levels. Some of
external pin can also be configured to wake up the device
from sleep modes where all clocks have been disabled.
External pins can also generate an event.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Detect external pins interrupt
Applications
------------
* Generate an interrupt on rising, falling or both edges,
or on high or low levels.
Dependencies
------------
* GPIO hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A
==============
EXT IRQ driver
==============
The External Interrupt driver allows external pins to be
configured as interrupt lines. Each interrupt line can be
individually masked and can generate an interrupt on rising,
falling or both edges, or on high or low levels. Some of
external pin can also be configured to wake up the device
from sleep modes where all clocks have been disabled.
External pins can also generate an event.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Detect external pins interrupt
Applications
------------
* Generate an interrupt on rising, falling or both edges,
or on high or low levels.
Dependencies
------------
* GPIO hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

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=============================
I2C Master synchronous driver
=============================
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
for on-board low-speed bi-directional communication between controllers and
peripherals. The master device is responsible for initiating and controlling
all transfers on the I2C bus. Only one master device can be active on the I2C
bus at the time, but the master role can be transferred between devices on the
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
resistors.
The stop condition is automatically controlled by the driver if the I/O write and
read functions are used, but can be manually controlled by using the
i2c_m_sync_transfer function.
Often a master accesses different information in the slave by accessing
different registers in the slave. This is done by first sending a message to
the target slave containing the register address, followed by a repeated start
condition (no stop condition between) ending with transferring register data.
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
function, but limited to 8-bit register addresses.
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
stick within the SCL clock frequency range supported by the selected mode.
The requested SCL clock frequency is not validated by the
i2c_m_sync_set_baudrate function against the selected I2C mode.
Features
--------
* I2C Master support
* Initialization and de-initialization
* Enabling and disabling
* Run-time bus speed configuration
* Write and read I2C messages
* Slave register access functions (limited to 8-bit address)
* Manual or automatic stop condition generation
* 10- and 7- bit addressing
* I2C Modes supported
+----------------------+-------------------+
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
+----------------------+-------------------+
|* Fastmode+ | (SCL: 1 - 1000kHz)|
+----------------------+-------------------+
|* Highspeed mode | (SCL: 1 - 3400kHz)|
+----------------------+-------------------+
Applications
------------
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
* Data communication between micro controllers
* Controlling displays
Dependencies
------------
* I2C Master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
General
^^^^^^^
* System Managmenet Bus (SMBus) not supported.
* Power Management Bus (PMBus) not supported.
Clock considerations
^^^^^^^^^^^^^^^^^^^^
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
Known issues and workarounds
----------------------------
N/A
=============================
I2C Master synchronous driver
=============================
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
for on-board low-speed bi-directional communication between controllers and
peripherals. The master device is responsible for initiating and controlling
all transfers on the I2C bus. Only one master device can be active on the I2C
bus at the time, but the master role can be transferred between devices on the
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
resistors.
The stop condition is automatically controlled by the driver if the I/O write and
read functions are used, but can be manually controlled by using the
i2c_m_sync_transfer function.
Often a master accesses different information in the slave by accessing
different registers in the slave. This is done by first sending a message to
the target slave containing the register address, followed by a repeated start
condition (no stop condition between) ending with transferring register data.
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
function, but limited to 8-bit register addresses.
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
stick within the SCL clock frequency range supported by the selected mode.
The requested SCL clock frequency is not validated by the
i2c_m_sync_set_baudrate function against the selected I2C mode.
Features
--------
* I2C Master support
* Initialization and de-initialization
* Enabling and disabling
* Run-time bus speed configuration
* Write and read I2C messages
* Slave register access functions (limited to 8-bit address)
* Manual or automatic stop condition generation
* 10- and 7- bit addressing
* I2C Modes supported
+----------------------+-------------------+
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
+----------------------+-------------------+
|* Fastmode+ | (SCL: 1 - 1000kHz)|
+----------------------+-------------------+
|* Highspeed mode | (SCL: 1 - 3400kHz)|
+----------------------+-------------------+
Applications
------------
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
* Data communication between micro controllers
* Controlling displays
Dependencies
------------
* I2C Master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
General
^^^^^^^
* System Managmenet Bus (SMBus) not supported.
* Power Management Bus (PMBus) not supported.
Clock considerations
^^^^^^^^^^^^^^^^^^^^
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
Known issues and workarounds
----------------------------
N/A

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============================
The Timer driver (bare-bone)
============================
The Timer driver provides means for delayed and periodical function invocation.
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
changes execution delays and periods for all tasks in the timers task queue.
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
the period set in the task configuration.
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
reuse the memory of expired task in the callback.
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Starting and stopping
* Timer tasks - periodical invocation of functions
* Changing and obtaining of the period of a timer
Applications
------------
* Delayed and periodical function execution for middle-ware stacks and applications.
Dependencies
------------
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
Concurrency
-----------
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
until the task adding or removing is complete.
The task queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
Limitations
-----------
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
Knows issues and workarounds
----------------------------
Not applicable
============================
The Timer driver (bare-bone)
============================
The Timer driver provides means for delayed and periodical function invocation.
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
changes execution delays and periods for all tasks in the timers task queue.
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
the period set in the task configuration.
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
reuse the memory of expired task in the callback.
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Starting and stopping
* Timer tasks - periodical invocation of functions
* Changing and obtaining of the period of a timer
Applications
------------
* Delayed and periodical function execution for middle-ware stacks and applications.
Dependencies
------------
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
Concurrency
-----------
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
until the task adding or removing is complete.
The task queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
Limitations
-----------
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
Knows issues and workarounds
----------------------------
Not applicable

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The USART Asynchronous Driver
=============================
The universal synchronous and asynchronous receiver and transmitter
(USART) is usually used to transfer data from one device to the other.
The USART driver use a ring buffer to store received data. When the USART
raise the data received interrupt, this data will be stored in the ring buffer
at the next free location. When the ring buffer is full, the next reception
will overwrite the oldest data stored in the ring buffer. There is one
USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
is called SERCOM0_USART_BUFFER_SIZE.
On the other hand, when sending data over USART, the data is not copied to an
internal buffer, but the data buffer supplied by the user is used. The callback
will only be generated at the end of the buffer and not for each byte.
User can set action for flow control pins by function usart_set_flow_control,
if the flow control is enabled. All the available states are defined in union
usart_flow_control_state.
Note that user can set state of flow control pins only if automatic support of
the flow control is not supported by the hardware.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* UART or USRT communication mode
* Character size
* Data order
* Flow control
* Data transfer: transmission, reception
* Notifications about transfer done or error case via callbacks
* Status information with busy state and transfer count
Applications
------------
They are commonly used in a terminal application or low-speed communication
between devices.
Dependencies
------------
USART capable hardware, with interrupt on each character is sent or
received.
Concurrency
-----------
Write buffer should not be changed while data is being sent.
Limitations
-----------
* The driver does not support 9-bit character size.
* The "USART with ISO7816" mode can be only used in ISO7816 capable devices.
And the SCK pin can't be set directly. Application can use a GCLK output PIN
to generate SCK. For example to communicate with a SMARTCARD with ISO7816
(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be
config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification.
Known issues and workarounds
----------------------------
N/A
The USART Asynchronous Driver
=============================
The universal synchronous and asynchronous receiver and transmitter
(USART) is usually used to transfer data from one device to the other.
The USART driver use a ring buffer to store received data. When the USART
raise the data received interrupt, this data will be stored in the ring buffer
at the next free location. When the ring buffer is full, the next reception
will overwrite the oldest data stored in the ring buffer. There is one
USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
is called SERCOM0_USART_BUFFER_SIZE.
On the other hand, when sending data over USART, the data is not copied to an
internal buffer, but the data buffer supplied by the user is used. The callback
will only be generated at the end of the buffer and not for each byte.
User can set action for flow control pins by function usart_set_flow_control,
if the flow control is enabled. All the available states are defined in union
usart_flow_control_state.
Note that user can set state of flow control pins only if automatic support of
the flow control is not supported by the hardware.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* UART or USRT communication mode
* Character size
* Data order
* Flow control
* Data transfer: transmission, reception
* Notifications about transfer done or error case via callbacks
* Status information with busy state and transfer count
Applications
------------
They are commonly used in a terminal application or low-speed communication
between devices.
Dependencies
------------
USART capable hardware, with interrupt on each character is sent or
received.
Concurrency
-----------
Write buffer should not be changed while data is being sent.
Limitations
-----------
* The driver does not support 9-bit character size.
* The "USART with ISO7816" mode can be only used in ISO7816 capable devices.
And the SCK pin can't be set directly. Application can use a GCLK output PIN
to generate SCK. For example to communicate with a SMARTCARD with ISO7816
(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be
config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification.
Known issues and workarounds
----------------------------
N/A

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/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */
/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h
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/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HAL_CACHE_H_
#define HAL_CACHE_H_
#include <hpl_cmcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Enable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_enable(const void *hw);
/**
* \brief Disable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_disable(const void *hw);
/**
* \brief Initialize cache module
*
* This function initialize cache module configuration.
*
* \return status of operation
*/
int32_t cache_init(void);
/**
* \brief Configure cache module
*
* \param[in] pointer pointing to the starting address of cache module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/**
* \brief Invalidate entire cache entries
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_invalidate_all(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HAL_CACHE_H_ */
/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HAL_CACHE_H_
#define HAL_CACHE_H_
#include <hpl_cmcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Enable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_enable(const void *hw);
/**
* \brief Disable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_disable(const void *hw);
/**
* \brief Initialize cache module
*
* This function initialize cache module configuration.
*
* \return status of operation
*/
int32_t cache_init(void);
/**
* \brief Configure cache module
*
* \param[in] pointer pointing to the starting address of cache module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/**
* \brief Invalidate entire cache entries
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_invalidate_all(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HAL_CACHE_H_ */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h
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/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#ifndef _HAL_DELAY_H_INCLUDED
#define _HAL_DELAY_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_delay Delay Driver
*
*@{
*/
/**
* \brief Initialize Delay driver
*
* \param[in] hw The pointer to hardware instance
*/
void delay_init(void *const hw);
/**
* \brief Perform delay in us
*
* This function performs delay for the given amount of microseconds.
*
* \param[in] us The amount delay in us
*/
void delay_us(const uint16_t us);
/**
* \brief Perform delay in ms
*
* This function performs delay for the given amount of milliseconds.
*
* \param[in] ms The amount delay in ms
*/
void delay_ms(const uint16_t ms);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t delay_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_DELAY_H_INCLUDED */
/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#ifndef _HAL_DELAY_H_INCLUDED
#define _HAL_DELAY_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_delay Delay Driver
*
*@{
*/
/**
* \brief Initialize Delay driver
*
* \param[in] hw The pointer to hardware instance
*/
void delay_init(void *const hw);
/**
* \brief Perform delay in us
*
* This function performs delay for the given amount of microseconds.
*
* \param[in] us The amount delay in us
*/
void delay_us(const uint16_t us);
/**
* \brief Perform delay in ms
*
* This function performs delay for the given amount of milliseconds.
*
* \param[in] ms The amount delay in ms
*/
void delay_ms(const uint16_t ms);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t delay_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_DELAY_H_INCLUDED */

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/**
* \file
*
* \brief External interrupt functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_EXT_IRQ_H_INCLUDED
#define _HAL_EXT_IRQ_H_INCLUDED
#include <hpl_ext_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_ext_irq
*
* @{
*/
/**
* \brief External IRQ callback type
*/
typedef void (*ext_irq_cb_t)(void);
/**
* \brief Initialize external IRQ component, if any
*
* \return Initialization status.
* \retval -1 External IRQ module is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t ext_irq_init(void);
/**
* \brief Deinitialize external IRQ, if any
*
* \return De-initialization status.
* \retval -1 External IRQ module is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t ext_irq_deinit(void);
/**
* \brief Register callback for the given external interrupt
*
* \param[in] pin Pin to enable external IRQ on
* \param[in] cb Callback function
*
* \return Registration status.
* \retval -1 Passed parameters were invalid
* \retval 0 The callback registration is completed successfully
*/
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
/**
* \brief Enable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Enabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The enabling is completed successfully
*/
int32_t ext_irq_enable(const uint32_t pin);
/**
* \brief Disable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Disabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The disabling is completed successfully
*/
int32_t ext_irq_disable(const uint32_t pin);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t ext_irq_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_EXT_IRQ_H_INCLUDED */
/**
* \file
*
* \brief External interrupt functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_EXT_IRQ_H_INCLUDED
#define _HAL_EXT_IRQ_H_INCLUDED
#include <hpl_ext_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_ext_irq
*
* @{
*/
/**
* \brief External IRQ callback type
*/
typedef void (*ext_irq_cb_t)(void);
/**
* \brief Initialize external IRQ component, if any
*
* \return Initialization status.
* \retval -1 External IRQ module is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t ext_irq_init(void);
/**
* \brief Deinitialize external IRQ, if any
*
* \return De-initialization status.
* \retval -1 External IRQ module is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t ext_irq_deinit(void);
/**
* \brief Register callback for the given external interrupt
*
* \param[in] pin Pin to enable external IRQ on
* \param[in] cb Callback function
*
* \return Registration status.
* \retval -1 Passed parameters were invalid
* \retval 0 The callback registration is completed successfully
*/
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
/**
* \brief Enable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Enabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The enabling is completed successfully
*/
int32_t ext_irq_enable(const uint32_t pin);
/**
* \brief Disable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Disabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The disabling is completed successfully
*/
int32_t ext_irq_disable(const uint32_t pin);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t ext_irq_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_EXT_IRQ_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_gpio.h
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/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HAL_GPIO_INCLUDED_
#define _HAL_GPIO_INCLUDED_
#include <hpl_gpio.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Set gpio pull mode
*
* Set pin pull mode, non existing pull modes throws an fatal assert
*
* \param[in] pin The pin number for device
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
* GPIO_PULL_UP = Pull pin high with internal resistor
* GPIO_PULL_OFF = Disable pin pull mode
*/
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
{
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
}
/**
* \brief Set pin function
*
* Select which function a pin will be used for
*
* \param[in] pin The pin number for device
* \param[in] function The pin function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
{
_gpio_set_pin_function(pin, function);
}
/**
* \brief Set port data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
_gpio_set_direction(port, mask, direction);
}
/**
* \brief Set gpio data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] pin The pin number for device
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
{
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
}
/**
* \brief Set port level
*
* Sets output level on the pins defined by the bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
* pin
* \param[in] level true = Pin levels set to "high" state
* false = Pin levels set to "low" state
*/
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
{
_gpio_set_level(port, mask, level);
}
/**
* \brief Set gpio level
*
* Sets output level on a pin
*
* \param[in] pin The pin number for device
* \param[in] level true = Pin level set to "high" state
* false = Pin level set to "low" state
*/
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
{
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
}
/**
* \brief Toggle out level on pins
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
* pin
*/
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
{
_gpio_toggle_level(port, mask);
}
/**
* \brief Toggle output level on pin
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] pin The pin number for device
*/
static inline void gpio_toggle_pin_level(const uint8_t pin)
{
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
}
/**
* \brief Get input level on pins
*
* Read the input level on pins connected to a port
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
{
return _gpio_get_level(port);
}
/**
* \brief Get level on pin
*
* Reads the level on pins connected to a port
*
* \param[in] pin The pin number for device
*/
static inline bool gpio_get_pin_level(const uint8_t pin)
{
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
}
/**
* \brief Get current driver version
*/
uint32_t gpio_get_version(void);
#ifdef __cplusplus
}
#endif
#endif
/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HAL_GPIO_INCLUDED_
#define _HAL_GPIO_INCLUDED_
#include <hpl_gpio.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Set gpio pull mode
*
* Set pin pull mode, non existing pull modes throws an fatal assert
*
* \param[in] pin The pin number for device
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
* GPIO_PULL_UP = Pull pin high with internal resistor
* GPIO_PULL_OFF = Disable pin pull mode
*/
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
{
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
}
/**
* \brief Set pin function
*
* Select which function a pin will be used for
*
* \param[in] pin The pin number for device
* \param[in] function The pin function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
{
_gpio_set_pin_function(pin, function);
}
/**
* \brief Set port data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
_gpio_set_direction(port, mask, direction);
}
/**
* \brief Set gpio data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] pin The pin number for device
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
{
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
}
/**
* \brief Set port level
*
* Sets output level on the pins defined by the bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
* pin
* \param[in] level true = Pin levels set to "high" state
* false = Pin levels set to "low" state
*/
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
{
_gpio_set_level(port, mask, level);
}
/**
* \brief Set gpio level
*
* Sets output level on a pin
*
* \param[in] pin The pin number for device
* \param[in] level true = Pin level set to "high" state
* false = Pin level set to "low" state
*/
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
{
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
}
/**
* \brief Toggle out level on pins
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
* pin
*/
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
{
_gpio_toggle_level(port, mask);
}
/**
* \brief Toggle output level on pin
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] pin The pin number for device
*/
static inline void gpio_toggle_pin_level(const uint8_t pin)
{
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
}
/**
* \brief Get input level on pins
*
* Read the input level on pins connected to a port
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
{
return _gpio_get_level(port);
}
/**
* \brief Get level on pin
*
* Reads the level on pins connected to a port
*
* \param[in] pin The pin number for device
*/
static inline bool gpio_get_pin_level(const uint8_t pin)
{
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
}
/**
* \brief Get current driver version
*/
uint32_t gpio_get_version(void);
#ifdef __cplusplus
}
#endif
#endif

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_i2c_m_sync.h
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/**
* \file
*
* \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
#define _HAL_I2C_M_SYNC_H_INCLUDED
#include <hpl_i2c_m_sync.h>
#include <hal_io.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_i2c_master_sync
*
* @{
*/
#define I2C_M_MAX_RETRY 1
/**
* \brief I2C descriptor structure, embed i2c_device & i2c_interface
*/
struct i2c_m_sync_desc {
struct _i2c_m_sync_device device;
struct io_descriptor io;
uint16_t slave_addr;
};
/**
* \brief Initialize synchronous I2C interface
*
* This function initializes the given I/O descriptor to be used as a
* synchronous I2C interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
* \retval -1 The passed parameters were invalid or the interface is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
/**
* \brief Deinitialize I2C interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Uninitialization status.
* \retval -1 The passed parameters were invalid or the interface is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
/**
* \brief Set the slave device address
*
* This function sets the next transfer target slave I2C device address.
* It takes no effect to any already started access.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] addr The slave address to access
* \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
*
* \return Masked slave address. The mask is a maximum 10-bit address, and 10th
* bit is set if a 10-bit address is used
*/
int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
/**
* \brief Set baudrate
*
* This function sets the I2C device to the specified baudrate.
* It only takes effect when the hardware is disabled.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] clkrate Unused parameter. Should always be 0
* \param[in] baudrate The baudrate value set to master
*
* \return Whether successfully set the baudrate
* \retval -1 The passed parameters were invalid or the device is already enabled
* \retval 0 The baudrate set is completed successfully
*/
int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Sync version of enable hardware
*
* This function enables the I2C device, and then waits for this enabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully enable the device
* \retval -1 The passed parameters were invalid or the device enable failed
* \retval 0 The hardware enabling is completed successfully
*/
int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of disable hardware
*
* This function disables the I2C device and then waits for this disabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully disable the device
* \retval -1 The passed parameters were invalid or the device disable failed
* \retval 0 The hardware disabling is completed successfully
*/
int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of write command to I2C slave
*
* This function will write the value to a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer holding data to write to the I2C slave device
* \param[in] length The length (in bytes) to write to the I2C slave device
*
* \return Whether successfully write to the device
* \retval <0 The passed parameters were invalid or write fail
* \retval 0 Writing to register is completed successfully
*/
int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of read register value from I2C slave
*
* This function will read a byte value from a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer to hold the read data from the I2C slave device
* \param[in] length The length (in bytes) to read from the I2C slave device
*
* \return Whether successfully read from the device
* \retval <0 The passed parameters were invalid or read fail
* \retval 0 Reading from register is completed successfully
*/
int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of transfer message to/from the I2C slave
*
* This function will transfer a message between the I2C slave and the master. This function will wait for the operation
* to be done.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] msg An i2c_m_msg struct
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
/**
* \brief Sync version of send stop condition on the i2c bus
*
* This function will create a stop condition on the i2c bus to release the bus
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
/**
* \brief Return I/O descriptor for this I2C instance
*
* This function will return a I/O instance for this I2C driver instance
*
* \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
* \param[in] io_descriptor A pointer to an I/O descriptor pointer type
*
* \return Error code
* \retval 0 No error detected
* \retval <0 Error code
*/
int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t i2c_m_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
/**
* \file
*
* \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
#define _HAL_I2C_M_SYNC_H_INCLUDED
#include <hpl_i2c_m_sync.h>
#include <hal_io.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_i2c_master_sync
*
* @{
*/
#define I2C_M_MAX_RETRY 1
/**
* \brief I2C descriptor structure, embed i2c_device & i2c_interface
*/
struct i2c_m_sync_desc {
struct _i2c_m_sync_device device;
struct io_descriptor io;
uint16_t slave_addr;
};
/**
* \brief Initialize synchronous I2C interface
*
* This function initializes the given I/O descriptor to be used as a
* synchronous I2C interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
* \retval -1 The passed parameters were invalid or the interface is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
/**
* \brief Deinitialize I2C interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Uninitialization status.
* \retval -1 The passed parameters were invalid or the interface is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
/**
* \brief Set the slave device address
*
* This function sets the next transfer target slave I2C device address.
* It takes no effect to any already started access.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] addr The slave address to access
* \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
*
* \return Masked slave address. The mask is a maximum 10-bit address, and 10th
* bit is set if a 10-bit address is used
*/
int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
/**
* \brief Set baudrate
*
* This function sets the I2C device to the specified baudrate.
* It only takes effect when the hardware is disabled.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] clkrate Unused parameter. Should always be 0
* \param[in] baudrate The baudrate value set to master
*
* \return Whether successfully set the baudrate
* \retval -1 The passed parameters were invalid or the device is already enabled
* \retval 0 The baudrate set is completed successfully
*/
int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Sync version of enable hardware
*
* This function enables the I2C device, and then waits for this enabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully enable the device
* \retval -1 The passed parameters were invalid or the device enable failed
* \retval 0 The hardware enabling is completed successfully
*/
int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of disable hardware
*
* This function disables the I2C device and then waits for this disabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully disable the device
* \retval -1 The passed parameters were invalid or the device disable failed
* \retval 0 The hardware disabling is completed successfully
*/
int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of write command to I2C slave
*
* This function will write the value to a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer holding data to write to the I2C slave device
* \param[in] length The length (in bytes) to write to the I2C slave device
*
* \return Whether successfully write to the device
* \retval <0 The passed parameters were invalid or write fail
* \retval 0 Writing to register is completed successfully
*/
int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of read register value from I2C slave
*
* This function will read a byte value from a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer to hold the read data from the I2C slave device
* \param[in] length The length (in bytes) to read from the I2C slave device
*
* \return Whether successfully read from the device
* \retval <0 The passed parameters were invalid or read fail
* \retval 0 Reading from register is completed successfully
*/
int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of transfer message to/from the I2C slave
*
* This function will transfer a message between the I2C slave and the master. This function will wait for the operation
* to be done.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] msg An i2c_m_msg struct
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
/**
* \brief Sync version of send stop condition on the i2c bus
*
* This function will create a stop condition on the i2c bus to release the bus
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
/**
* \brief Return I/O descriptor for this I2C instance
*
* This function will return a I/O instance for this I2C driver instance
*
* \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
* \param[in] io_descriptor A pointer to an I/O descriptor pointer type
*
* \return Error code
* \retval 0 No error detected
* \retval <0 Error code
*/
int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t i2c_m_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file
*
* \brief HAL initialization related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_INIT_H_INCLUDED
#define _HAL_INIT_H_INCLUDED
#include <hpl_init.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_init Init Driver
*
*@{
*/
/**
* \brief Initialize the hardware abstraction layer
*
* This function calls the various initialization functions.
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
}
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t init_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_INIT_H_INCLUDED */
/**
* \file
*
* \brief HAL initialization related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_INIT_H_INCLUDED
#define _HAL_INIT_H_INCLUDED
#include <hpl_init.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_init Init Driver
*
*@{
*/
/**
* \brief Initialize the hardware abstraction layer
*
* This function calls the various initialization functions.
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
}
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t init_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_INIT_H_INCLUDED */

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/**
* \file
*
* \brief I/O related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_IO_INCLUDED
#define _HAL_IO_INCLUDED
/**
* \addtogroup doc_driver_hal_helper_io I/O Driver
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I/O descriptor
*
* The I/O descriptor forward declaration.
*/
struct io_descriptor;
/**
* \brief I/O write function pointer type
*/
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read function pointer type
*/
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
/**
* \brief I/O descriptor
*/
struct io_descriptor {
io_write_t write; /*! The write function pointer. */
io_read_t read; /*! The read function pointer. */
};
/**
* \brief I/O write interface
*
* This function writes up to \p length of bytes to a given I/O descriptor.
* It returns the number of bytes actually write.
*
* \param[in] descr An I/O descriptor to write
* \param[in] buf The buffer pointer to story the write data
* \param[in] length The number of bytes to write
*
* \return The number of bytes written
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read interface
*
* This function reads up to \p length bytes from a given I/O descriptor, and
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
* actually read.
*
* \param[in] descr An I/O descriptor to read
* \param[in] buf The buffer pointer to story the read data
* \param[in] length The number of bytes to read
*
* \return The number of bytes actually read. This number can be less than the
* requested length. E.g., in a driver that uses ring buffer for
* reception, it may depend on the availability of data in the
* ring buffer.
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_IO_INCLUDED */
/**
* \file
*
* \brief I/O related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_IO_INCLUDED
#define _HAL_IO_INCLUDED
/**
* \addtogroup doc_driver_hal_helper_io I/O Driver
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I/O descriptor
*
* The I/O descriptor forward declaration.
*/
struct io_descriptor;
/**
* \brief I/O write function pointer type
*/
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read function pointer type
*/
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
/**
* \brief I/O descriptor
*/
struct io_descriptor {
io_write_t write; /*! The write function pointer. */
io_read_t read; /*! The read function pointer. */
};
/**
* \brief I/O write interface
*
* This function writes up to \p length of bytes to a given I/O descriptor.
* It returns the number of bytes actually write.
*
* \param[in] descr An I/O descriptor to write
* \param[in] buf The buffer pointer to story the write data
* \param[in] length The number of bytes to write
*
* \return The number of bytes written
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read interface
*
* This function reads up to \p length bytes from a given I/O descriptor, and
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
* actually read.
*
* \param[in] descr An I/O descriptor to read
* \param[in] buf The buffer pointer to story the read data
* \param[in] length The number of bytes to read
*
* \return The number of bytes actually read. This number can be less than the
* requested length. E.g., in a driver that uses ring buffer for
* reception, it may depend on the availability of data in the
* ring buffer.
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_IO_INCLUDED */

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/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SLEEP_H_INCLUDED
#define _HAL_SLEEP_H_INCLUDED
#include <hpl_sleep.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_sleep
*
*@{
*/
/**
* \brief Set the sleep mode of the device and put the MCU to sleep
*
* For an overview of which systems are disabled in sleep for the different
* sleep modes, see the data sheet.
*
* \param[in] mode Sleep mode to use
*
* \return The status of a sleep request
* \retval -1 The requested sleep mode was invalid or not available
* \retval 0 The operation completed successfully, returned after leaving the
* sleep
*/
int sleep(const uint8_t mode);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t sleep_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SLEEP_H_INCLUDED */
/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SLEEP_H_INCLUDED
#define _HAL_SLEEP_H_INCLUDED
#include <hpl_sleep.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_sleep
*
*@{
*/
/**
* \brief Set the sleep mode of the device and put the MCU to sleep
*
* For an overview of which systems are disabled in sleep for the different
* sleep modes, see the data sheet.
*
* \param[in] mode Sleep mode to use
*
* \return The status of a sleep request
* \retval -1 The requested sleep mode was invalid or not available
* \retval 0 The operation completed successfully, returned after leaving the
* sleep
*/
int sleep(const uint8_t mode);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t sleep_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SLEEP_H_INCLUDED */

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/**
* \file
*
* \brief Timer task functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_TIMER_H_INCLUDED
#define _HAL_TIMER_H_INCLUDED
#include <utils_list.h>
#include <hpl_timer.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_timer
*
* @{
*/
/**
* \brief Timer mode type
*/
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
/**
* \brief Timer task descriptor
*
* The timer task descriptor forward declaration.
*/
struct timer_task;
/**
* \brief Timer task callback function type
*/
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
/**
* \brief Timer task structure
*/
struct timer_task {
struct list_element elem; /*! List element. */
uint32_t time_label; /*! Absolute timer start time. */
uint32_t interval; /*! Number of timer ticks before calling the task. */
timer_cb_t cb; /*! Function pointer to the task. */
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
};
/**
* \brief Timer structure
*/
struct timer_descriptor {
struct _timer_device device;
uint32_t time;
struct list_descriptor tasks; /*! Timer tasks list. */
volatile uint8_t flags;
};
/**
* \brief Initialize timer
*
* This function initializes the given timer.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A timer descriptor to initialize
* \param[in] hw The pointer to the hardware instance
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
*/
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
/**
* \brief Deinitialize timer
*
* This function deinitializes the given timer.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr A timer descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t timer_deinit(struct timer_descriptor *const descr);
/**
* \brief Start timer
*
* This function starts the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to start
*
* \return Timer starting status.
*/
int32_t timer_start(struct timer_descriptor *const descr);
/**
* \brief Stop timer
*
* This function stops the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
*
* \return Timer stopping status.
*/
int32_t timer_stop(struct timer_descriptor *const descr);
/**
* \brief Set amount of clock cycles per timer tick
*
* This function sets the amount of clock cycles per timer tick for the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
* \param[in] clock_cycles The amount of clock cycles per tick to set
*
* \return Setting clock cycles amount status.
*/
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
/**
* \brief Retrieve the amount of clock cycles in a tick
*
* This function retrieves how many clock cycles there are in a single timer tick.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to convert ticks to
* clock cycles
* \param[out] cycles The amount of clock cycles
*
* \return The status of clock cycles retrieving.
*/
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
/**
* \brief Add timer task
*
* This function adds the given timer task to the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to add task to
* \param[in] task A task to add
*
* \return Timer's task adding status.
*/
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
/**
* \brief Remove timer task
*
* This function removes the given timer task from the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to remove task from
* \param[in] task A task to remove
*
* \return Timer's task removing status.
*/
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t timer_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_TIMER_H_INCLUDED */
/**
* \file
*
* \brief Timer task functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_TIMER_H_INCLUDED
#define _HAL_TIMER_H_INCLUDED
#include <utils_list.h>
#include <hpl_timer.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_timer
*
* @{
*/
/**
* \brief Timer mode type
*/
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
/**
* \brief Timer task descriptor
*
* The timer task descriptor forward declaration.
*/
struct timer_task;
/**
* \brief Timer task callback function type
*/
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
/**
* \brief Timer task structure
*/
struct timer_task {
struct list_element elem; /*! List element. */
uint32_t time_label; /*! Absolute timer start time. */
uint32_t interval; /*! Number of timer ticks before calling the task. */
timer_cb_t cb; /*! Function pointer to the task. */
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
};
/**
* \brief Timer structure
*/
struct timer_descriptor {
struct _timer_device device;
uint32_t time;
struct list_descriptor tasks; /*! Timer tasks list. */
volatile uint8_t flags;
};
/**
* \brief Initialize timer
*
* This function initializes the given timer.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A timer descriptor to initialize
* \param[in] hw The pointer to the hardware instance
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
*/
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
/**
* \brief Deinitialize timer
*
* This function deinitializes the given timer.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr A timer descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t timer_deinit(struct timer_descriptor *const descr);
/**
* \brief Start timer
*
* This function starts the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to start
*
* \return Timer starting status.
*/
int32_t timer_start(struct timer_descriptor *const descr);
/**
* \brief Stop timer
*
* This function stops the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
*
* \return Timer stopping status.
*/
int32_t timer_stop(struct timer_descriptor *const descr);
/**
* \brief Set amount of clock cycles per timer tick
*
* This function sets the amount of clock cycles per timer tick for the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
* \param[in] clock_cycles The amount of clock cycles per tick to set
*
* \return Setting clock cycles amount status.
*/
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
/**
* \brief Retrieve the amount of clock cycles in a tick
*
* This function retrieves how many clock cycles there are in a single timer tick.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to convert ticks to
* clock cycles
* \param[out] cycles The amount of clock cycles
*
* \return The status of clock cycles retrieving.
*/
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
/**
* \brief Add timer task
*
* This function adds the given timer task to the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to add task to
* \param[in] task A task to add
*
* \return Timer's task adding status.
*/
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
/**
* \brief Remove timer task
*
* This function removes the given timer task from the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to remove task from
* \param[in] task A task to remove
*
* \return Timer's task removing status.
*/
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t timer_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_TIMER_H_INCLUDED */

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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_USART_ASYNC_H_INCLUDED
#define _HAL_USART_ASYNC_H_INCLUDED
#include "hal_io.h"
#include <hpl_usart_async.h>
#include <utils_ringbuffer.h>
/**
* \addtogroup doc_driver_hal_usart_async
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART descriptor
*
* The USART descriptor forward declaration.
*/
struct usart_async_descriptor;
/**
* \brief USART callback type
*/
typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr);
/**
* \brief USART callback types
*/
enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB };
/**
* \brief USART callbacks
*/
struct usart_async_callbacks {
usart_cb_t tx_done;
usart_cb_t rx_done;
usart_cb_t error;
};
/** \brief USART status
* Status descriptor holds the current status of transfer.
*/
struct usart_async_status {
/** Status flags */
uint32_t flags;
/** Number of characters transmitted */
uint16_t txcnt;
/** Number of characters receviced */
uint16_t rxcnt;
};
/**
* \brief Asynchronous USART descriptor structure
*/
struct usart_async_descriptor {
struct io_descriptor io;
struct _usart_async_device device;
struct usart_async_callbacks usart_cb;
uint32_t stat;
struct ringbuffer rx;
uint16_t tx_por;
uint8_t * tx_buffer;
uint16_t tx_buffer_length;
};
/** USART write busy */
#define USART_ASYNC_STATUS_BUSY 0x0001
/**
* \brief Initialize USART interface
*
* This function initializes the given I/O descriptor to be used as USART
* interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A USART descriptor which is used to communicate via the USART
* \param[in] hw The pointer to the hardware instance
* \param[in] rx_buffer An RX buffer
* \param[in] rx_buffer_length The length of the buffer above
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
* \retval -1 Passed parameters were invalid or the interface is already
* initialized
* \retval 0 The initialization is completed successfully
*/
int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer,
const uint16_t rx_buffer_length, void *const func);
/**
* \brief Deinitialize USART interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware
* is permitted to be deinitialized.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return De-initialization status.
*/
int32_t usart_async_deinit(struct usart_async_descriptor *const descr);
/**
* \brief Enable USART interface
*
* Enables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Enabling status.
*/
int32_t usart_async_enable(struct usart_async_descriptor *const descr);
/**
* \brief Disable USART interface
*
* Disables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Disabling status.
*/
int32_t usart_async_disable(struct usart_async_descriptor *const descr);
/**
* \brief Retrieve I/O descriptor
*
* This function retrieves the I/O descriptor of the given USART descriptor.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] io An I/O descriptor to retrieve
*
* \return The status of I/O descriptor retrieving.
*/
int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io);
/**
* \brief Register USART callback
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] type Callback type
* \param[in] cb A callback function
*
* \return The status of callback assignment.
* \retval -1 Passed parameters were invalid or the interface is not initialized
* \retval 0 A callback is registered successfully
*/
int32_t usart_async_register_callback(struct usart_async_descriptor *const descr,
const enum usart_async_callback_type type, usart_cb_t cb);
/**
* \brief Specify action for flow control pins
*
* This function sets action (or state) for flow control pins if
* the flow control is enabled.
* It sets state of flow control pins only if automatic support of
* the flow control is not supported by the hardware.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] state A state to set the flow control pins
*
* \return The status of flow control action setup.
*/
int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr,
const union usart_flow_control_state state);
/**
* \brief Set USART baud rate
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] baud_rate A baud rate to set
*
* \return The status of baud rate setting.
*/
int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate);
/**
* \brief Set USART data order
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] data_order A data order to set
*
* \return The status of data order setting.
*/
int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order);
/**
* \brief Set USART mode
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] mode A mode to set
*
* \return The status of mode setting.
*/
int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode);
/**
* \brief Set USART parity
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] parity A parity to set
*
* \return The status of parity setting.
*/
int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity);
/**
* \brief Set USART stop bits
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] stop_bits Stop bits to set
*
* \return The status of stop bits setting.
*/
int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits);
/**
* \brief Set USART character size
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] size A character size to set
*
* \return The status of character size setting.
*/
int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr,
const enum usart_character_size size);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the flow control pins
* if the flow control is enabled.
*
* The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
* if the flow control is done by the hardware
* and the pins state cannot be read out.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] state The state of flow control pins
*
* \return The status of flow control state reading.
*/
int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr,
union usart_flow_control_state *const state);
/**
* \brief Check if the USART transmitter is empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART TX empty checking.
* \retval 0 The USART transmitter is not empty
* \retval 1 The USART transmitter is empty
*/
int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr);
/**
* \brief Check if the USART receiver is not empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of the USART RX empty checking.
* \retval 1 The USART receiver is not empty
* \retval 0 The USART receiver is empty
*/
int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr);
/**
* \brief Retrieve the current interface status
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] status The state of USART
*
* \return The status of USART status retrieving.
*/
int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status);
/**
* \brief flush USART ringbuf
*
* This function flush USART RX ringbuf.
*
* \param[in] descr The pointer to USART descriptor
*
* \return ERR_NONE
*/
int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t usart_async_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_USART_ASYNC_H_INCLUDED */
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_USART_ASYNC_H_INCLUDED
#define _HAL_USART_ASYNC_H_INCLUDED
#include "hal_io.h"
#include <hpl_usart_async.h>
#include <utils_ringbuffer.h>
/**
* \addtogroup doc_driver_hal_usart_async
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART descriptor
*
* The USART descriptor forward declaration.
*/
struct usart_async_descriptor;
/**
* \brief USART callback type
*/
typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr);
/**
* \brief USART callback types
*/
enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB };
/**
* \brief USART callbacks
*/
struct usart_async_callbacks {
usart_cb_t tx_done;
usart_cb_t rx_done;
usart_cb_t error;
};
/** \brief USART status
* Status descriptor holds the current status of transfer.
*/
struct usart_async_status {
/** Status flags */
uint32_t flags;
/** Number of characters transmitted */
uint16_t txcnt;
/** Number of characters receviced */
uint16_t rxcnt;
};
/**
* \brief Asynchronous USART descriptor structure
*/
struct usart_async_descriptor {
struct io_descriptor io;
struct _usart_async_device device;
struct usart_async_callbacks usart_cb;
uint32_t stat;
struct ringbuffer rx;
uint16_t tx_por;
uint8_t * tx_buffer;
uint16_t tx_buffer_length;
};
/** USART write busy */
#define USART_ASYNC_STATUS_BUSY 0x0001
/**
* \brief Initialize USART interface
*
* This function initializes the given I/O descriptor to be used as USART
* interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A USART descriptor which is used to communicate via the USART
* \param[in] hw The pointer to the hardware instance
* \param[in] rx_buffer An RX buffer
* \param[in] rx_buffer_length The length of the buffer above
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
* \retval -1 Passed parameters were invalid or the interface is already
* initialized
* \retval 0 The initialization is completed successfully
*/
int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer,
const uint16_t rx_buffer_length, void *const func);
/**
* \brief Deinitialize USART interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware
* is permitted to be deinitialized.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return De-initialization status.
*/
int32_t usart_async_deinit(struct usart_async_descriptor *const descr);
/**
* \brief Enable USART interface
*
* Enables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Enabling status.
*/
int32_t usart_async_enable(struct usart_async_descriptor *const descr);
/**
* \brief Disable USART interface
*
* Disables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Disabling status.
*/
int32_t usart_async_disable(struct usart_async_descriptor *const descr);
/**
* \brief Retrieve I/O descriptor
*
* This function retrieves the I/O descriptor of the given USART descriptor.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] io An I/O descriptor to retrieve
*
* \return The status of I/O descriptor retrieving.
*/
int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io);
/**
* \brief Register USART callback
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] type Callback type
* \param[in] cb A callback function
*
* \return The status of callback assignment.
* \retval -1 Passed parameters were invalid or the interface is not initialized
* \retval 0 A callback is registered successfully
*/
int32_t usart_async_register_callback(struct usart_async_descriptor *const descr,
const enum usart_async_callback_type type, usart_cb_t cb);
/**
* \brief Specify action for flow control pins
*
* This function sets action (or state) for flow control pins if
* the flow control is enabled.
* It sets state of flow control pins only if automatic support of
* the flow control is not supported by the hardware.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] state A state to set the flow control pins
*
* \return The status of flow control action setup.
*/
int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr,
const union usart_flow_control_state state);
/**
* \brief Set USART baud rate
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] baud_rate A baud rate to set
*
* \return The status of baud rate setting.
*/
int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate);
/**
* \brief Set USART data order
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] data_order A data order to set
*
* \return The status of data order setting.
*/
int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order);
/**
* \brief Set USART mode
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] mode A mode to set
*
* \return The status of mode setting.
*/
int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode);
/**
* \brief Set USART parity
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] parity A parity to set
*
* \return The status of parity setting.
*/
int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity);
/**
* \brief Set USART stop bits
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] stop_bits Stop bits to set
*
* \return The status of stop bits setting.
*/
int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits);
/**
* \brief Set USART character size
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] size A character size to set
*
* \return The status of character size setting.
*/
int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr,
const enum usart_character_size size);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the flow control pins
* if the flow control is enabled.
*
* The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
* if the flow control is done by the hardware
* and the pins state cannot be read out.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] state The state of flow control pins
*
* \return The status of flow control state reading.
*/
int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr,
union usart_flow_control_state *const state);
/**
* \brief Check if the USART transmitter is empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART TX empty checking.
* \retval 0 The USART transmitter is not empty
* \retval 1 The USART transmitter is empty
*/
int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr);
/**
* \brief Check if the USART receiver is not empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of the USART RX empty checking.
* \retval 1 The USART receiver is not empty
* \retval 0 The USART receiver is empty
*/
int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr);
/**
* \brief Retrieve the current interface status
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] status The state of USART
*
* \return The status of USART status retrieving.
*/
int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status);
/**
* \brief flush USART ringbuf
*
* This function flush USART RX ringbuf.
*
* \param[in] descr The pointer to USART descriptor
*
* \return ERR_NONE
*/
int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t usart_async_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_USART_ASYNC_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_cmcc.h
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/**
* \file
*
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HPL_CMCC_H_
#define HPL_CMCC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/**
* \Cache driver MACROS
*/
#define CMCC_DISABLE 0U
#define CMCC_ENABLE 1U
#define IS_CMCC_DISABLED 0U
#define IS_CMCC_ENABLED 1U
#define CMCC_WAY_NOS 4U
#define CMCC_LINE_NOS 64U
#define CMCC_MONITOR_DISABLE 0U
/**
* \brief Cache size configurations
*/
enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
/**
* \brief Way Numbers
*/
enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
/**
* \brief Cache monitor configurations
*/
enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
/**
* \brief Cache configuration structure
*/
struct _cache_cfg {
enum conf_cache_size cache_size;
bool data_cache_disable;
bool inst_cache_disable;
bool gclk_gate_disable;
};
/**
* \brief Cache enable status
*/
static inline bool _is_cache_enabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
}
/**
* \brief Cache disable status
*/
static inline bool _is_cache_disabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
}
/**
* \brief Cache enable
*/
static inline int32_t _cmcc_enable(const void *hw)
{
int32_t return_value;
if (_is_cache_disabled(hw)) {
hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
} else {
return_value = ERR_NO_CHANGE;
}
return return_value;
}
/**
* \brief Cache disable
*/
static inline int32_t _cmcc_disable(const void *hw)
{
hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
while (!(_is_cache_disabled(hw)))
;
return ERR_NONE;
}
/**
* \brief Initialize Cache Module
*
* This function initialize low level cmcc module configuration.
*
* \return initialize status
*/
int32_t _cmcc_init(void);
/**
* \brief Configure CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
/**
* \brief Enable data cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
*
* \return status of operation
*/
int32_t _cmcc_enable_data_cache(const void *hw, bool value);
/**
* \brief Enable instruction cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
*
* \return status of operation
*/
int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
/**
* \brief Enable clock gating in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
*
* \return status of operation
*/
int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
/**
* \brief Configure the cache size in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache size configuration enumerator
* 0->1K, 1->2K, 2->4K(default)
*
* \return status of operation
*/
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
/**
* \brief Lock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
/**
* \brief Unlock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
/**
* \brief Invalidate the mentioned cache line in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
*
* \return status of operation
*/
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
/**
* \brief Invalidate entire cache entries in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_invalidate_all(const void *hw);
/**
* \brief Configure cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache monitor configurations enumerator
*
* \return status of operation
*/
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
/**
* \brief Enable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_enable_monitor(const void *hw);
/**
* \brief Disable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_disable_monitor(const void *hw);
/**
* \brief Reset cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_reset_monitor(const void *hw);
/**
* \brief Get cache monitor event counter value from CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return event counter value
*/
uint32_t _cmcc_get_monitor_event_count(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HPL_CMCC_H_ */
/**
* \file
*
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HPL_CMCC_H_
#define HPL_CMCC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/**
* \Cache driver MACROS
*/
#define CMCC_DISABLE 0U
#define CMCC_ENABLE 1U
#define IS_CMCC_DISABLED 0U
#define IS_CMCC_ENABLED 1U
#define CMCC_WAY_NOS 4U
#define CMCC_LINE_NOS 64U
#define CMCC_MONITOR_DISABLE 0U
/**
* \brief Cache size configurations
*/
enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
/**
* \brief Way Numbers
*/
enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
/**
* \brief Cache monitor configurations
*/
enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
/**
* \brief Cache configuration structure
*/
struct _cache_cfg {
enum conf_cache_size cache_size;
bool data_cache_disable;
bool inst_cache_disable;
bool gclk_gate_disable;
};
/**
* \brief Cache enable status
*/
static inline bool _is_cache_enabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
}
/**
* \brief Cache disable status
*/
static inline bool _is_cache_disabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
}
/**
* \brief Cache enable
*/
static inline int32_t _cmcc_enable(const void *hw)
{
int32_t return_value;
if (_is_cache_disabled(hw)) {
hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
} else {
return_value = ERR_NO_CHANGE;
}
return return_value;
}
/**
* \brief Cache disable
*/
static inline int32_t _cmcc_disable(const void *hw)
{
hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
while (!(_is_cache_disabled(hw)))
;
return ERR_NONE;
}
/**
* \brief Initialize Cache Module
*
* This function initialize low level cmcc module configuration.
*
* \return initialize status
*/
int32_t _cmcc_init(void);
/**
* \brief Configure CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
/**
* \brief Enable data cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
*
* \return status of operation
*/
int32_t _cmcc_enable_data_cache(const void *hw, bool value);
/**
* \brief Enable instruction cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
*
* \return status of operation
*/
int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
/**
* \brief Enable clock gating in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
*
* \return status of operation
*/
int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
/**
* \brief Configure the cache size in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache size configuration enumerator
* 0->1K, 1->2K, 2->4K(default)
*
* \return status of operation
*/
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
/**
* \brief Lock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
/**
* \brief Unlock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
/**
* \brief Invalidate the mentioned cache line in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
*
* \return status of operation
*/
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
/**
* \brief Invalidate entire cache entries in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_invalidate_all(const void *hw);
/**
* \brief Configure cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache monitor configurations enumerator
*
* \return status of operation
*/
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
/**
* \brief Enable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_enable_monitor(const void *hw);
/**
* \brief Disable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_disable_monitor(const void *hw);
/**
* \brief Reset cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_reset_monitor(const void *hw);
/**
* \brief Get cache monitor event counter value from CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return event counter value
*/
uint32_t _cmcc_get_monitor_event_count(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HPL_CMCC_H_ */

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/**
* \file
*
* \brief CPU core related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CORE_H_INCLUDED
#define _HPL_CORE_H_INCLUDED
/**
* \addtogroup HPL Core
*
* \section hpl_core_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_core_port.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_CORE_H_INCLUDED */
/**
* \file
*
* \brief CPU core related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CORE_H_INCLUDED
#define _HPL_CORE_H_INCLUDED
/**
* \addtogroup HPL Core
*
* \section hpl_core_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_core_port.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_CORE_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_delay.h
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/**
* \file
*
* \brief Delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DELAY_H_INCLUDED
#define _HPL_DELAY_H_INCLUDED
/**
* \addtogroup HPL Delay
*
* \section hpl_delay_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize delay functionality
*
* \param[in] hw The pointer to hardware instance
*/
void _delay_init(void *const hw);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of us
*
* \param[in] us The amount of us to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_us(const uint16_t us);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of ms
*
* \param[in] ms The amount of ms to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_ms(const uint16_t ms);
/**
* \brief Delay loop to delay n number of cycles
*
* \param[in] hw The pointer to hardware instance
* \param[in] cycles The amount of cycles to delay for
*/
void _delay_cycles(void *const hw, uint32_t cycles);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_DELAY_H_INCLUDED */
/**
* \file
*
* \brief Delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DELAY_H_INCLUDED
#define _HPL_DELAY_H_INCLUDED
/**
* \addtogroup HPL Delay
*
* \section hpl_delay_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize delay functionality
*
* \param[in] hw The pointer to hardware instance
*/
void _delay_init(void *const hw);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of us
*
* \param[in] us The amount of us to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_us(const uint16_t us);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of ms
*
* \param[in] ms The amount of ms to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_ms(const uint16_t ms);
/**
* \brief Delay loop to delay n number of cycles
*
* \param[in] hw The pointer to hardware instance
* \param[in] cycles The amount of cycles to delay for
*/
void _delay_cycles(void *const hw, uint32_t cycles);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_DELAY_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_dma.h
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@ -1,176 +1,176 @@
/**
* \file
*
* \brief DMA related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DMA_H_INCLUDED
#define _HPL_DMA_H_INCLUDED
/**
* \addtogroup HPL DMA
*
* \section hpl_dma_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
struct _dma_resource;
/**
* \brief DMA callback types
*/
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
/**
* \brief DMA interrupt callbacks
*/
struct _dma_callbacks {
void (*transfer_done)(struct _dma_resource *resource);
void (*error)(struct _dma_resource *resource);
};
/**
* \brief DMA resource structure
*/
struct _dma_resource {
struct _dma_callbacks dma_cb;
void * back;
};
/**
* \brief Initialize DMA
*
* This function does low level DMA configuration.
*
* \return initialize status
*/
int32_t _dma_init(void);
/**
* \brief Set destination address
*
* \param[in] channel DMA channel to set destination address for
* \param[in] dst Destination address
*
* \return setting status
*/
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
/**
* \brief Set source address
*
* \param[in] channel DMA channel to set source address for
* \param[in] src Source address
*
* \return setting status
*/
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
/**
* \brief Set next descriptor address
*
* \param[in] current_channel Current DMA channel to set next descriptor address
* \param[in] next_channel Next DMA channel used as next descriptor
*
* \return setting status
*/
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
/**
* \brief Enable/disable source address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set source address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Enable/disable Destination address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set destination address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Set the amount of data to be transfered per transaction
*
* \param[in] channel DMA channel to set data amount for
* \param[in] amount Data amount
*
* \return status of operation
*/
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
/**
* \brief Trigger DMA transaction on the given channel
*
* \param[in] channel DMA channel to trigger transaction on
*
* \return status of operation
*/
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
/**
* \brief Retrieves DMA resource structure
*
* \param[out] resource The resource to be retrieved
* \param[in] channel DMA channel to retrieve structure for
*
* \return status of operation
*/
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
/**
* \brief Enable/disable DMA interrupt
*
* \param[in] channel DMA channel to enable/disable interrupt for
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
#ifdef __cplusplus
}
#endif
#endif /* HPL_DMA_H_INCLUDED */
/**
* \file
*
* \brief DMA related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DMA_H_INCLUDED
#define _HPL_DMA_H_INCLUDED
/**
* \addtogroup HPL DMA
*
* \section hpl_dma_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
struct _dma_resource;
/**
* \brief DMA callback types
*/
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
/**
* \brief DMA interrupt callbacks
*/
struct _dma_callbacks {
void (*transfer_done)(struct _dma_resource *resource);
void (*error)(struct _dma_resource *resource);
};
/**
* \brief DMA resource structure
*/
struct _dma_resource {
struct _dma_callbacks dma_cb;
void * back;
};
/**
* \brief Initialize DMA
*
* This function does low level DMA configuration.
*
* \return initialize status
*/
int32_t _dma_init(void);
/**
* \brief Set destination address
*
* \param[in] channel DMA channel to set destination address for
* \param[in] dst Destination address
*
* \return setting status
*/
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
/**
* \brief Set source address
*
* \param[in] channel DMA channel to set source address for
* \param[in] src Source address
*
* \return setting status
*/
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
/**
* \brief Set next descriptor address
*
* \param[in] current_channel Current DMA channel to set next descriptor address
* \param[in] next_channel Next DMA channel used as next descriptor
*
* \return setting status
*/
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
/**
* \brief Enable/disable source address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set source address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Enable/disable Destination address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set destination address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Set the amount of data to be transfered per transaction
*
* \param[in] channel DMA channel to set data amount for
* \param[in] amount Data amount
*
* \return status of operation
*/
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
/**
* \brief Trigger DMA transaction on the given channel
*
* \param[in] channel DMA channel to trigger transaction on
*
* \return status of operation
*/
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
/**
* \brief Retrieves DMA resource structure
*
* \param[out] resource The resource to be retrieved
* \param[in] channel DMA channel to retrieve structure for
*
* \return status of operation
*/
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
/**
* \brief Enable/disable DMA interrupt
*
* \param[in] channel DMA channel to enable/disable interrupt for
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
#ifdef __cplusplus
}
#endif
#endif /* HPL_DMA_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ext_irq.h
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/**
* \file
*
* \brief External IRQ related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_EXT_IRQ_H_INCLUDED
#define _HPL_EXT_IRQ_H_INCLUDED
/**
* \addtogroup HPL EXT IRQ
*
* \section hpl_ext_irq_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize external interrupt module
*
* This function does low level external interrupt configuration.
*
* \param[in] cb The pointer to callback function from external interrupt
*
* \return Initialization status.
* \retval -1 External irq module is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t _ext_irq_init(void (*cb)(const uint32_t pin));
/**
* \brief Deinitialize external interrupt module
*
* \return Initialization status.
* \retval -1 External irq module is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t _ext_irq_deinit(void);
/**
* \brief Enable / disable external irq
*
* \param[in] pin Pin to enable external irq on
* \param[in] enable True to enable, false to disable
*
* \return Status of external irq enabling / disabling
* \retval -1 External irq module can't be enabled / disabled
* \retval 0 External irq module is enabled / disabled successfully
*/
int32_t _ext_irq_enable(const uint32_t pin, const bool enable);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_EXT_IRQ_H_INCLUDED */
/**
* \file
*
* \brief External IRQ related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_EXT_IRQ_H_INCLUDED
#define _HPL_EXT_IRQ_H_INCLUDED
/**
* \addtogroup HPL EXT IRQ
*
* \section hpl_ext_irq_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize external interrupt module
*
* This function does low level external interrupt configuration.
*
* \param[in] cb The pointer to callback function from external interrupt
*
* \return Initialization status.
* \retval -1 External irq module is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t _ext_irq_init(void (*cb)(const uint32_t pin));
/**
* \brief Deinitialize external interrupt module
*
* \return Initialization status.
* \retval -1 External irq module is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t _ext_irq_deinit(void);
/**
* \brief Enable / disable external irq
*
* \param[in] pin Pin to enable external irq on
* \param[in] enable True to enable, false to disable
*
* \return Status of external irq enabling / disabling
* \retval -1 External irq module can't be enabled / disabled
* \retval 0 External irq module is enabled / disabled successfully
*/
int32_t _ext_irq_enable(const uint32_t pin, const bool enable);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_EXT_IRQ_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_gpio.h
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/**
* \file
*
* \brief Port related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_GPIO_H_INCLUDED
#define _HPL_GPIO_H_INCLUDED
/**
* \addtogroup HPL Port
*
* \section hpl_port_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Macros for the pin and port group, lower 5
* bits stands for pin number in the group, higher 3
* bits stands for port group
*/
#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
#define GPIO_PORT(n) ((n) >> 5)
#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
#define GPIO_PIN_FUNCTION_OFF 0xffffffff
/**
* \brief PORT pull mode settings
*/
enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
/**
* \brief PORT direction settins
*/
enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
/**
* \brief PORT group abstraction
*/
enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
/**
* \name HPL functions
*/
//@{
/**
* \brief Port initialization function
*
* Port initialization function should setup the port module based
* on a static configuration file, this function should normally
* not be called directly, but is a part of hal_init()
*/
void _gpio_init(void);
/**
* \brief Set direction on port with mask
*
* Set data direction for each pin, or disable the pin
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input
* and disable input buffer to disable the pin
* GPIO_DIRECTION_IN = set pin direction to input
* and enable input buffer to enable the pin
* GPIO_DIRECTION_OUT = set pin direction to output
* and disable input buffer
*/
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction);
/**
* \brief Set output level on port with mask
*
* Sets output state on pin to high or low with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
* \param[in] level true = pin level is set to 1
* false = pin level is set to 0
*/
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
/**
* \brief Change output level to the opposite with mask
*
* Change pin output level to the opposite with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
*/
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
/**
* \brief Get input levels on all port pins
*
* Get input level on all port pins, will read IN register if configured to
* input and OUT register if configured as output
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t _gpio_get_level(const enum gpio_port port);
/**
* \brief Set pin pull mode
*
* Set pull mode on a single pin
*
* \notice This function will automatically change pin direction to input
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] pin The pin in the group that pull mode should be selected
* for
* \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled
* GPIO_PULL_DOWN = pull resistor on pin will pull pin
* level to ground level
* GPIO_PULL_UP = pull resistor on pin will pull pin
* level to VCC
*/
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
const enum gpio_pull_mode pull_mode);
/**
* \brief Set gpio function
*
* Select which function a gpio is used for
*
* \param[in] gpio The gpio to set function for
* \param[in] function The gpio function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
#include <hpl_gpio_base.h>
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_GPIO_H_INCLUDED */
/**
* \file
*
* \brief Port related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_GPIO_H_INCLUDED
#define _HPL_GPIO_H_INCLUDED
/**
* \addtogroup HPL Port
*
* \section hpl_port_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Macros for the pin and port group, lower 5
* bits stands for pin number in the group, higher 3
* bits stands for port group
*/
#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
#define GPIO_PORT(n) ((n) >> 5)
#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
#define GPIO_PIN_FUNCTION_OFF 0xffffffff
/**
* \brief PORT pull mode settings
*/
enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
/**
* \brief PORT direction settins
*/
enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
/**
* \brief PORT group abstraction
*/
enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
/**
* \name HPL functions
*/
//@{
/**
* \brief Port initialization function
*
* Port initialization function should setup the port module based
* on a static configuration file, this function should normally
* not be called directly, but is a part of hal_init()
*/
void _gpio_init(void);
/**
* \brief Set direction on port with mask
*
* Set data direction for each pin, or disable the pin
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input
* and disable input buffer to disable the pin
* GPIO_DIRECTION_IN = set pin direction to input
* and enable input buffer to enable the pin
* GPIO_DIRECTION_OUT = set pin direction to output
* and disable input buffer
*/
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction);
/**
* \brief Set output level on port with mask
*
* Sets output state on pin to high or low with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
* \param[in] level true = pin level is set to 1
* false = pin level is set to 0
*/
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
/**
* \brief Change output level to the opposite with mask
*
* Change pin output level to the opposite with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
*/
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
/**
* \brief Get input levels on all port pins
*
* Get input level on all port pins, will read IN register if configured to
* input and OUT register if configured as output
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t _gpio_get_level(const enum gpio_port port);
/**
* \brief Set pin pull mode
*
* Set pull mode on a single pin
*
* \notice This function will automatically change pin direction to input
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] pin The pin in the group that pull mode should be selected
* for
* \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled
* GPIO_PULL_DOWN = pull resistor on pin will pull pin
* level to ground level
* GPIO_PULL_UP = pull resistor on pin will pull pin
* level to VCC
*/
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
const enum gpio_pull_mode pull_mode);
/**
* \brief Set gpio function
*
* Select which function a gpio is used for
*
* \param[in] gpio The gpio to set function for
* \param[in] function The gpio function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
#include <hpl_gpio_base.h>
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_GPIO_H_INCLUDED */

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/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
#define _HPL_I2C_M_ASYNC_H_INCLUDED
#include "hpl_i2c_m_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c master callback names
*/
enum _i2c_m_async_callback_type {
I2C_M_ASYNC_DEVICE_ERROR,
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
I2C_M_ASYNC_DEVICE_RX_COMPLETE
};
struct _i2c_m_async_device;
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
/**
* \brief i2c callback pointers structure
*/
struct _i2c_m_async_callback {
_i2c_error_cb_t error;
_i2c_complete_cb_t tx_complete;
_i2c_complete_cb_t rx_complete;
};
/**
* \brief i2c device structure
*/
struct _i2c_m_async_device {
struct _i2c_m_service service;
void * hw;
struct _i2c_m_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C in interrupt mode
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c interrupt device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C in interrupt mode
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Register callback to I2C
*
* This function does low level I2C callback register.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] cb_type The callback type request
* \param[in] func The callback function pointer
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
FUNC_PTR func);
/**
* \brief Generate stop condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Operation status
* \retval 0 Operation executed successfully
* \retval <0 Operation failed
*/
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Returns the number of bytes left or not used in the I2C message buffer
*
* This function will return the number of bytes left (not written to the bus) or still free
* (not received from the bus) in the message buffer, depending on direction of transmission.
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Number of bytes or error code
* \retval >0 Positive number indicating bytes left
* \retval 0 Buffer is full/empty depending on direction
* \retval <0 Error code
*/
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable/disable I2C master interrupt
*
* param[in] device The pointer to I2C master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
const bool state);
#ifdef __cplusplus
}
#endif
#endif
/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
#define _HPL_I2C_M_ASYNC_H_INCLUDED
#include "hpl_i2c_m_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c master callback names
*/
enum _i2c_m_async_callback_type {
I2C_M_ASYNC_DEVICE_ERROR,
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
I2C_M_ASYNC_DEVICE_RX_COMPLETE
};
struct _i2c_m_async_device;
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
/**
* \brief i2c callback pointers structure
*/
struct _i2c_m_async_callback {
_i2c_error_cb_t error;
_i2c_complete_cb_t tx_complete;
_i2c_complete_cb_t rx_complete;
};
/**
* \brief i2c device structure
*/
struct _i2c_m_async_device {
struct _i2c_m_service service;
void * hw;
struct _i2c_m_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C in interrupt mode
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c interrupt device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C in interrupt mode
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Register callback to I2C
*
* This function does low level I2C callback register.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] cb_type The callback type request
* \param[in] func The callback function pointer
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
FUNC_PTR func);
/**
* \brief Generate stop condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Operation status
* \retval 0 Operation executed successfully
* \retval <0 Operation failed
*/
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Returns the number of bytes left or not used in the I2C message buffer
*
* This function will return the number of bytes left (not written to the bus) or still free
* (not received from the bus) in the message buffer, depending on direction of transmission.
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Number of bytes or error code
* \retval >0 Positive number indicating bytes left
* \retval 0 Buffer is full/empty depending on direction
* \retval <0 Error code
*/
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable/disable I2C master interrupt
*
* param[in] device The pointer to I2C master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
const bool state);
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
#define _HPL_I2C_M_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c flags
*/
#define I2C_M_RD 0x0001 /* read data, from slave to master */
#define I2C_M_BUSY 0x0100
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
#define I2C_M_FAIL 0x1000
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
/**
* \brief i2c Return codes
*/
#define I2C_OK 0 /* Operation successful */
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
#define I2C_ERR_BUS -5 /* Bus error */
#define I2C_ERR_BUSY -6 /* Device busy */
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
/**
* \brief i2c I2C Modes
*/
#define I2C_STANDARD_MODE 0x00
#define I2C_FASTMODE 0x01
#define I2C_HIGHSPEED_MODE 0x02
/**
* \brief i2c master message structure
*/
struct _i2c_m_msg {
uint16_t addr;
volatile uint16_t flags;
int32_t len;
uint8_t * buffer;
};
/**
* \brief i2c master service
*/
struct _i2c_m_service {
struct _i2c_m_msg msg;
uint16_t mode;
uint16_t trise;
};
/**
* \brief i2c sync master device structure
*/
struct _i2c_m_sync_device {
struct _i2c_m_service service;
void * hw;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Send send condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_dev The pointer to i2c device struct
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
#ifdef __cplusplus
}
#endif
#endif
/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
#define _HPL_I2C_M_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c flags
*/
#define I2C_M_RD 0x0001 /* read data, from slave to master */
#define I2C_M_BUSY 0x0100
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
#define I2C_M_FAIL 0x1000
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
/**
* \brief i2c Return codes
*/
#define I2C_OK 0 /* Operation successful */
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
#define I2C_ERR_BUS -5 /* Bus error */
#define I2C_ERR_BUSY -6 /* Device busy */
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
/**
* \brief i2c I2C Modes
*/
#define I2C_STANDARD_MODE 0x00
#define I2C_FASTMODE 0x01
#define I2C_HIGHSPEED_MODE 0x02
/**
* \brief i2c master message structure
*/
struct _i2c_m_msg {
uint16_t addr;
volatile uint16_t flags;
int32_t len;
uint8_t * buffer;
};
/**
* \brief i2c master service
*/
struct _i2c_m_service {
struct _i2c_m_msg msg;
uint16_t mode;
uint16_t trise;
};
/**
* \brief i2c sync master device structure
*/
struct _i2c_m_sync_device {
struct _i2c_m_service service;
void * hw;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Send send condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_dev The pointer to i2c device struct
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
#ifdef __cplusplus
}
#endif
#endif

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@ -1,184 +1,184 @@
/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
#define _HPL_I2C_S_ASYNC_H_INCLUDED
#include "hpl_i2c_s_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c callback types
*/
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
/**
* \brief Forward declaration of I2C Slave device
*/
struct _i2c_s_async_device;
/**
* \brief i2c slave callback function type
*/
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
/**
* \brief i2c slave callback pointers structure
*/
struct _i2c_s_async_callback {
void (*error)(struct _i2c_s_async_device *const device);
void (*tx)(struct _i2c_s_async_device *const device);
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
};
/**
* \brief i2c slave device structure
*/
struct _i2c_s_async_device {
void * hw;
struct _i2c_s_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize asynchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c interrupt device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
/**
* \brief Deinitialize asynchronous I2C in interrupt mode
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
/**
* \brief Abort data transmission
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
/**
* \brief Enable/disable I2C slave interrupt
*
* param[in] device The pointer to I2C slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
const bool disable);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */
/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
#define _HPL_I2C_S_ASYNC_H_INCLUDED
#include "hpl_i2c_s_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c callback types
*/
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
/**
* \brief Forward declaration of I2C Slave device
*/
struct _i2c_s_async_device;
/**
* \brief i2c slave callback function type
*/
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
/**
* \brief i2c slave callback pointers structure
*/
struct _i2c_s_async_callback {
void (*error)(struct _i2c_s_async_device *const device);
void (*tx)(struct _i2c_s_async_device *const device);
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
};
/**
* \brief i2c slave device structure
*/
struct _i2c_s_async_device {
void * hw;
struct _i2c_s_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize asynchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c interrupt device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
/**
* \brief Deinitialize asynchronous I2C in interrupt mode
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
/**
* \brief Abort data transmission
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
/**
* \brief Enable/disable I2C slave interrupt
*
* param[in] device The pointer to I2C slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
const bool disable);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */

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@ -1,184 +1,184 @@
/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
#define _HPL_I2C_S_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I2C Slave status type
*/
typedef uint32_t i2c_s_status_t;
/**
* \brief i2c slave device structure
*/
struct _i2c_s_sync_device {
void *hw;
};
#include <compiler.h>
/**
* \name HPL functions
*/
/**
* \brief Initialize synchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
/**
* \brief Deinitialize synchronous I2C slave
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
/**
* \brief Clear the Data Ready interrupt flag
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
/**
* \brief Read a byte from the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Data received via I2C interface.
*/
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if I2C is ready to send next byte
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the ready check.
* \retval true if the I2C is ready to send next byte
* \retval false if the I2C is not ready to send next byte
*/
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if there is data received by I2C
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the data received check.
* \retval true if the I2C has received a byte
* \retval false if the I2C has not received a byte
*/
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */
/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
#define _HPL_I2C_S_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I2C Slave status type
*/
typedef uint32_t i2c_s_status_t;
/**
* \brief i2c slave device structure
*/
struct _i2c_s_sync_device {
void *hw;
};
#include <compiler.h>
/**
* \name HPL functions
*/
/**
* \brief Initialize synchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
/**
* \brief Deinitialize synchronous I2C slave
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
/**
* \brief Clear the Data Ready interrupt flag
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
/**
* \brief Read a byte from the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Data received via I2C interface.
*/
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if I2C is ready to send next byte
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the ready check.
* \retval true if the I2C is ready to send next byte
* \retval false if the I2C is not ready to send next byte
*/
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if there is data received by I2C
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the data received check.
* \retval true if the I2C has received a byte
* \retval false if the I2C has not received a byte
*/
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief Init related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_INIT_H_INCLUDED
#define _HPL_INIT_H_INCLUDED
/**
* \addtogroup HPL Init
*
* \section hpl_init_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initializes clock sources
*/
void _sysctrl_init_sources(void);
/**
* \brief Initializes Power Manager
*/
void _pm_init(void);
/**
* \brief Initialize generators
*/
void _gclk_init_generators(void);
/**
* \brief Initialize 32 kHz clock sources
*/
void _osc32kctrl_init_sources(void);
/**
* \brief Initialize clock sources
*/
void _oscctrl_init_sources(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _sysctrl_init_referenced_generators(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _oscctrl_init_referenced_generators(void);
/**
* \brief Initialize master clock generator
*/
void _mclk_init(void);
/**
* \brief Initialize clock generator
*/
void _lpmcu_misc_regs_init(void);
/**
* \brief Initialize clock generator
*/
void _pmc_init(void);
/**
* \brief Set performance level
*
* \param[in] level The performance level to set
*/
void _set_performance_level(const uint8_t level);
/**
* \brief Initialize the chip
*/
void _init_chip(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_INIT_H_INCLUDED */
/**
* \file
*
* \brief Init related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_INIT_H_INCLUDED
#define _HPL_INIT_H_INCLUDED
/**
* \addtogroup HPL Init
*
* \section hpl_init_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initializes clock sources
*/
void _sysctrl_init_sources(void);
/**
* \brief Initializes Power Manager
*/
void _pm_init(void);
/**
* \brief Initialize generators
*/
void _gclk_init_generators(void);
/**
* \brief Initialize 32 kHz clock sources
*/
void _osc32kctrl_init_sources(void);
/**
* \brief Initialize clock sources
*/
void _oscctrl_init_sources(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _sysctrl_init_referenced_generators(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _oscctrl_init_referenced_generators(void);
/**
* \brief Initialize master clock generator
*/
void _mclk_init(void);
/**
* \brief Initialize clock generator
*/
void _lpmcu_misc_regs_init(void);
/**
* \brief Initialize clock generator
*/
void _pmc_init(void);
/**
* \brief Set performance level
*
* \param[in] level The performance level to set
*/
void _set_performance_level(const uint8_t level);
/**
* \brief Initialize the chip
*/
void _init_chip(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_INIT_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_irq.h
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/**
* \file
*
* \brief IRQ related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_IRQ_H_INCLUDED
#define _HPL_IRQ_H_INCLUDED
/**
* \addtogroup HPL IRQ
*
* \section hpl_irq_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief IRQ descriptor
*/
struct _irq_descriptor {
void (*handler)(void *parameter);
void *parameter;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve current IRQ number
*
* \return The current IRQ number
*/
uint8_t _irq_get_current(void);
/**
* \brief Disable the given IRQ
*
* \param[in] n The number of IRQ to disable
*/
void _irq_disable(uint8_t n);
/**
* \brief Set the given IRQ
*
* \param[in] n The number of IRQ to set
*/
void _irq_set(uint8_t n);
/**
* \brief Clear the given IRQ
*
* \param[in] n The number of IRQ to clear
*/
void _irq_clear(uint8_t n);
/**
* \brief Enable the given IRQ
*
* \param[in] n The number of IRQ to enable
*/
void _irq_enable(uint8_t n);
/**
* \brief Register IRQ handler
*
* \param[in] number The number registered IRQ
* \param[in] irq The pointer to irq handler to register
*
* \return The status of IRQ handler registering
* \retval -1 Passed parameters were invalid
* \retval 0 The registering is completed successfully
*/
void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_IRQ_H_INCLUDED */
/**
* \file
*
* \brief IRQ related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_IRQ_H_INCLUDED
#define _HPL_IRQ_H_INCLUDED
/**
* \addtogroup HPL IRQ
*
* \section hpl_irq_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief IRQ descriptor
*/
struct _irq_descriptor {
void (*handler)(void *parameter);
void *parameter;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve current IRQ number
*
* \return The current IRQ number
*/
uint8_t _irq_get_current(void);
/**
* \brief Disable the given IRQ
*
* \param[in] n The number of IRQ to disable
*/
void _irq_disable(uint8_t n);
/**
* \brief Set the given IRQ
*
* \param[in] n The number of IRQ to set
*/
void _irq_set(uint8_t n);
/**
* \brief Clear the given IRQ
*
* \param[in] n The number of IRQ to clear
*/
void _irq_clear(uint8_t n);
/**
* \brief Enable the given IRQ
*
* \param[in] n The number of IRQ to enable
*/
void _irq_enable(uint8_t n);
/**
* \brief Register IRQ handler
*
* \param[in] number The number registered IRQ
* \param[in] irq The pointer to irq handler to register
*
* \return The status of IRQ handler registering
* \retval -1 Passed parameters were invalid
* \retval 0 The registering is completed successfully
*/
void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_IRQ_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_missing_features.h
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/**
* \file
*
* \brief Family-dependent missing features expected by HAL
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_MISSING_FEATURES
#define _HPL_MISSING_FEATURES
#endif /* _HPL_MISSING_FEATURES */
/**
* \file
*
* \brief Family-dependent missing features expected by HAL
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_MISSING_FEATURES
#define _HPL_MISSING_FEATURES
#endif /* _HPL_MISSING_FEATURES */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_pwm.h
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/**
* \file
*
* \brief PWM related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_PWM_H_INCLUDED
#define _HPL_PWM_H_INCLUDED
/**
* \addtogroup HPL PWM
*
* \section hpl_pwm_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief PWM callback types
*/
enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
/**
* \brief PWM pulse-width period
*/
typedef uint32_t pwm_period_t;
/**
* \brief PWM device structure
*
* The PWM device structure forward declaration.
*/
struct _pwm_device;
/**
* \brief PWM interrupt callbacks
*/
struct _pwm_callback {
void (*pwm_period_cb)(struct _pwm_device *device);
void (*pwm_error_cb)(struct _pwm_device *device);
};
/**
* \brief PWM descriptor device structure
*/
struct _pwm_device {
struct _pwm_callback callback;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief PWM functions, pointers to low-level functions
*/
struct _pwm_hpl_interface {
int32_t (*init)(struct _pwm_device *const device, void *const hw);
void (*deinit)(struct _pwm_device *const device);
void (*start_pwm)(struct _pwm_device *const device);
void (*stop_pwm)(struct _pwm_device *const device);
void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
bool (*is_pwm_enabled)(const struct _pwm_device *const device);
pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
};
/**
* \brief Initialize TC
*
* This function does low level TC configuration.
*
* \param[in] device The pointer to PWM device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _pwm_init(struct _pwm_device *const device, void *const hw);
/**
* \brief Deinitialize TC
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_deinit(struct _pwm_device *const device);
/**
* \brief Retrieve offset of the given tc hardware instance
*
* \param[in] device The pointer to PWM device instance
*
* \return The offset of the given tc hardware instance
*/
uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device);
/**
* \brief Start hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_enable(struct _pwm_device *const device);
/**
* \brief Stop hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_disable(struct _pwm_device *const device);
/**
* \brief Set pwm parameter
*
* \param[in] device The pointer to PWM device instance
* \param[in] period Total period of one PWM cycle.
* \param[in] duty_cycle Period of PWM first half during one cycle.
*/
void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
/**
* \brief Check if pwm is working
*
* \param[in] device The pointer to PWM device instance
*
* \return Check status.
* \retval true The given pwm is working
* \retval false The given pwm is not working
*/
bool _pwm_is_enabled(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform period value
*
* \param[in] device The pointer to PWM device instance
*
* \return Period value.
*/
pwm_period_t _pwm_get_period(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform duty cycle value
*
* \param[in] device The pointer to PWM device instance
*
* \return Duty cycle value
*/
uint32_t _pwm_get_duty(const struct _pwm_device *const device);
/**
* \brief Enable/disable PWM interrupt
*
* param[in] device The pointer to PWM device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_PWM_H_INCLUDED */
/**
* \file
*
* \brief PWM related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_PWM_H_INCLUDED
#define _HPL_PWM_H_INCLUDED
/**
* \addtogroup HPL PWM
*
* \section hpl_pwm_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief PWM callback types
*/
enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
/**
* \brief PWM pulse-width period
*/
typedef uint32_t pwm_period_t;
/**
* \brief PWM device structure
*
* The PWM device structure forward declaration.
*/
struct _pwm_device;
/**
* \brief PWM interrupt callbacks
*/
struct _pwm_callback {
void (*pwm_period_cb)(struct _pwm_device *device);
void (*pwm_error_cb)(struct _pwm_device *device);
};
/**
* \brief PWM descriptor device structure
*/
struct _pwm_device {
struct _pwm_callback callback;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief PWM functions, pointers to low-level functions
*/
struct _pwm_hpl_interface {
int32_t (*init)(struct _pwm_device *const device, void *const hw);
void (*deinit)(struct _pwm_device *const device);
void (*start_pwm)(struct _pwm_device *const device);
void (*stop_pwm)(struct _pwm_device *const device);
void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
bool (*is_pwm_enabled)(const struct _pwm_device *const device);
pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
};
/**
* \brief Initialize TC
*
* This function does low level TC configuration.
*
* \param[in] device The pointer to PWM device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _pwm_init(struct _pwm_device *const device, void *const hw);
/**
* \brief Deinitialize TC
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_deinit(struct _pwm_device *const device);
/**
* \brief Retrieve offset of the given tc hardware instance
*
* \param[in] device The pointer to PWM device instance
*
* \return The offset of the given tc hardware instance
*/
uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device);
/**
* \brief Start hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_enable(struct _pwm_device *const device);
/**
* \brief Stop hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_disable(struct _pwm_device *const device);
/**
* \brief Set pwm parameter
*
* \param[in] device The pointer to PWM device instance
* \param[in] period Total period of one PWM cycle.
* \param[in] duty_cycle Period of PWM first half during one cycle.
*/
void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
/**
* \brief Check if pwm is working
*
* \param[in] device The pointer to PWM device instance
*
* \return Check status.
* \retval true The given pwm is working
* \retval false The given pwm is not working
*/
bool _pwm_is_enabled(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform period value
*
* \param[in] device The pointer to PWM device instance
*
* \return Period value.
*/
pwm_period_t _pwm_get_period(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform duty cycle value
*
* \param[in] device The pointer to PWM device instance
*
* \return Duty cycle value
*/
uint32_t _pwm_get_duty(const struct _pwm_device *const device);
/**
* \brief Enable/disable PWM interrupt
*
* param[in] device The pointer to PWM device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_PWM_H_INCLUDED */

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/**
* \file
*
* \brief RAMECC related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_RAMECC_H_INCLUDED
#define _HPL_RAMECC_H_INCLUDED
/**
* \addtogroup HPL RAMECC
*
* \section hpl_ramecc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief RAMECC callback type
*/
typedef void (*ramecc_cb_t)(const uint32_t data);
/**
* \brief RAMECC callback types
*/
enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB };
/**
* \brief RAMECC interrupt callbacks
*/
struct _ramecc_callbacks {
ramecc_cb_t dual_bit_err;
ramecc_cb_t single_bit_err;
};
/**
* \brief RAMECC device structure
*/
struct _ramecc_device {
struct _ramecc_callbacks ramecc_cb;
struct _irq_descriptor irq;
};
/**
* \brief Initialize RAMECC
*
* This function does low level RAMECC configuration.
*
* \return initialize status
*/
int32_t _ramecc_init(void);
/**
* \brief Register RAMECC callback
*
* \param[in] type The type of callback
* \param[in] cb A callback function
*/
void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_RAMECC_H_INCLUDED */
/**
* \file
*
* \brief RAMECC related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_RAMECC_H_INCLUDED
#define _HPL_RAMECC_H_INCLUDED
/**
* \addtogroup HPL RAMECC
*
* \section hpl_ramecc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief RAMECC callback type
*/
typedef void (*ramecc_cb_t)(const uint32_t data);
/**
* \brief RAMECC callback types
*/
enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB };
/**
* \brief RAMECC interrupt callbacks
*/
struct _ramecc_callbacks {
ramecc_cb_t dual_bit_err;
ramecc_cb_t single_bit_err;
};
/**
* \brief RAMECC device structure
*/
struct _ramecc_device {
struct _ramecc_callbacks ramecc_cb;
struct _irq_descriptor irq;
};
/**
* \brief Initialize RAMECC
*
* This function does low level RAMECC configuration.
*
* \return initialize status
*/
int32_t _ramecc_init(void);
/**
* \brief Register RAMECC callback
*
* \param[in] type The type of callback
* \param[in] cb A callback function
*/
void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_RAMECC_H_INCLUDED */

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@ -1,93 +1,93 @@
/**
* \file
*
* \brief Reset related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_RESET_H_INCLUDED
#define _HPL_RESET_H_INCLUDED
/**
* \addtogroup HPL Reset
*
* \section hpl_reset_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Reset reason enumeration
*
* The list of possible reset reasons.
*/
enum reset_reason {
RESET_REASON_POR = 1,
RESET_REASON_BOD12 = 2,
RESET_REASON_BOD33 = 4,
RESET_REASON_NVM = 8,
RESET_REASON_EXT = 16,
RESET_REASON_WDT = 32,
RESET_REASON_SYST = 64,
RESET_REASON_BACKUP = 128
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve the reset reason
*
* Retrieves the reset reason of the last MCU reset.
*
*\return An enum value indicating the reason of the last reset.
*/
enum reset_reason _get_reset_reason(void);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_RESET_H_INCLUDED */
/**
* \file
*
* \brief Reset related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_RESET_H_INCLUDED
#define _HPL_RESET_H_INCLUDED
/**
* \addtogroup HPL Reset
*
* \section hpl_reset_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Reset reason enumeration
*
* The list of possible reset reasons.
*/
enum reset_reason {
RESET_REASON_POR = 1,
RESET_REASON_BOD12 = 2,
RESET_REASON_BOD33 = 4,
RESET_REASON_NVM = 8,
RESET_REASON_EXT = 16,
RESET_REASON_WDT = 32,
RESET_REASON_SYST = 64,
RESET_REASON_BACKUP = 128
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve the reset reason
*
* Retrieves the reset reason of the last MCU reset.
*
*\return An enum value indicating the reason of the last reset.
*/
enum reset_reason _get_reset_reason(void);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_RESET_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_sleep.h
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/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SLEEP_H_INCLUDED
#define _HPL_SLEEP_H_INCLUDED
/**
* \addtogroup HPL Sleep
*
* \section hpl_sleep_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Set the sleep mode for the device
*
* This function sets the sleep mode for the device.
* For an overview of which systems are disabled in sleep for the different
* sleep modes see datasheet.
*
* \param[in] mode Sleep mode to use
*
* \return the status of a sleep request
* \retval -1 The requested sleep mode was invalid
* \retval 0 The operation completed successfully, sleep mode is set
*/
int32_t _set_sleep_mode(const uint8_t mode);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
/**
* \brief Put MCU to sleep
*/
void _go_to_sleep(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SLEEP_H_INCLUDED */
/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SLEEP_H_INCLUDED
#define _HPL_SLEEP_H_INCLUDED
/**
* \addtogroup HPL Sleep
*
* \section hpl_sleep_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Set the sleep mode for the device
*
* This function sets the sleep mode for the device.
* For an overview of which systems are disabled in sleep for the different
* sleep modes see datasheet.
*
* \param[in] mode Sleep mode to use
*
* \return the status of a sleep request
* \retval -1 The requested sleep mode was invalid
* \retval 0 The operation completed successfully, sleep mode is set
*/
int32_t _set_sleep_mode(const uint8_t mode);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
/**
* \brief Put MCU to sleep
*/
void _go_to_sleep(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SLEEP_H_INCLUDED */

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/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_H_INCLUDED
#define _HPL_SPI_H_INCLUDED
#include <compiler.h>
#include <utils.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief SPI Dummy char is used when reading data from the SPI slave
*/
#define SPI_DUMMY_CHAR 0x1ff
/**
* \brief SPI message to let driver to process
*/
//@{
struct spi_msg {
/** Pointer to the output data buffer */
uint8_t *txbuf;
/** Pointer to the input data buffer */
uint8_t *rxbuf;
/** Size of the message data in SPI characters */
uint32_t size;
};
//@}
/**
* \brief SPI transfer modes
* SPI transfer mode controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
*/
enum spi_transfer_mode {
/** Leading edge is rising edge, data sample on leading edge. */
SPI_MODE_0,
/** Leading edge is rising edge, data sample on trailing edge. */
SPI_MODE_1,
/** Leading edge is falling edge, data sample on leading edge. */
SPI_MODE_2,
/** Leading edge is falling edge, data sample on trailing edge. */
SPI_MODE_3
};
/**
* \brief SPI character sizes
* The character size influence the way the data is sent/received.
* For char size <= 8 data is stored byte by byte.
* For char size between 9 ~ 16 data is stored in 2-byte length.
* Note that the default and recommended char size is 8 bit since it's
* supported by all system.
*/
enum spi_char_size {
/** Character size is 8 bit. */
SPI_CHAR_SIZE_8 = 0,
/** Character size is 9 bit. */
SPI_CHAR_SIZE_9 = 1,
/** Character size is 10 bit. */
SPI_CHAR_SIZE_10 = 2,
/** Character size is 11 bit. */
SPI_CHAR_SIZE_11 = 3,
/** Character size is 12 bit. */
SPI_CHAR_SIZE_12 = 4,
/** Character size is 13 bit. */
SPI_CHAR_SIZE_13 = 5,
/** Character size is 14 bit. */
SPI_CHAR_SIZE_14 = 6,
/** Character size is 15 bit. */
SPI_CHAR_SIZE_15 = 7,
/** Character size is 16 bit. */
SPI_CHAR_SIZE_16 = 8
};
/**
* \brief SPI data order
*/
enum spi_data_order {
/** MSB goes first. */
SPI_DATA_ORDER_MSB_1ST = 0,
/** LSB goes first. */
SPI_DATA_ORDER_LSB_1ST = 1
};
/** \brief Transfer descriptor for SPI
* Transfer descriptor holds TX and RX buffers
*/
struct spi_xfer {
/** Pointer to data buffer to TX */
uint8_t *txbuf;
/** Pointer to data buffer to RX */
uint8_t *rxbuf;
/** Size of data characters to TX & RX */
uint32_t size;
};
/** SPI generic driver. */
struct spi_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Reference start of sync/async variables */
uint32_t sync_async_misc[1];
};
/**
* \brief Calculate the baudrate value for hardware to use to set baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] clk Clock frequency (Hz) for baudrate generation.
* \param[in] baud Target baudrate (bps).
* \return Error or baudrate value.
* \retval >0 Baudrate value.
* \retval ERR_INVALID_ARG Calculation fail.
*/
int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_H_INCLUDED */
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_H_INCLUDED
#define _HPL_SPI_H_INCLUDED
#include <compiler.h>
#include <utils.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief SPI Dummy char is used when reading data from the SPI slave
*/
#define SPI_DUMMY_CHAR 0x1ff
/**
* \brief SPI message to let driver to process
*/
//@{
struct spi_msg {
/** Pointer to the output data buffer */
uint8_t *txbuf;
/** Pointer to the input data buffer */
uint8_t *rxbuf;
/** Size of the message data in SPI characters */
uint32_t size;
};
//@}
/**
* \brief SPI transfer modes
* SPI transfer mode controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
*/
enum spi_transfer_mode {
/** Leading edge is rising edge, data sample on leading edge. */
SPI_MODE_0,
/** Leading edge is rising edge, data sample on trailing edge. */
SPI_MODE_1,
/** Leading edge is falling edge, data sample on leading edge. */
SPI_MODE_2,
/** Leading edge is falling edge, data sample on trailing edge. */
SPI_MODE_3
};
/**
* \brief SPI character sizes
* The character size influence the way the data is sent/received.
* For char size <= 8 data is stored byte by byte.
* For char size between 9 ~ 16 data is stored in 2-byte length.
* Note that the default and recommended char size is 8 bit since it's
* supported by all system.
*/
enum spi_char_size {
/** Character size is 8 bit. */
SPI_CHAR_SIZE_8 = 0,
/** Character size is 9 bit. */
SPI_CHAR_SIZE_9 = 1,
/** Character size is 10 bit. */
SPI_CHAR_SIZE_10 = 2,
/** Character size is 11 bit. */
SPI_CHAR_SIZE_11 = 3,
/** Character size is 12 bit. */
SPI_CHAR_SIZE_12 = 4,
/** Character size is 13 bit. */
SPI_CHAR_SIZE_13 = 5,
/** Character size is 14 bit. */
SPI_CHAR_SIZE_14 = 6,
/** Character size is 15 bit. */
SPI_CHAR_SIZE_15 = 7,
/** Character size is 16 bit. */
SPI_CHAR_SIZE_16 = 8
};
/**
* \brief SPI data order
*/
enum spi_data_order {
/** MSB goes first. */
SPI_DATA_ORDER_MSB_1ST = 0,
/** LSB goes first. */
SPI_DATA_ORDER_LSB_1ST = 1
};
/** \brief Transfer descriptor for SPI
* Transfer descriptor holds TX and RX buffers
*/
struct spi_xfer {
/** Pointer to data buffer to TX */
uint8_t *txbuf;
/** Pointer to data buffer to RX */
uint8_t *rxbuf;
/** Size of data characters to TX & RX */
uint32_t size;
};
/** SPI generic driver. */
struct spi_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Reference start of sync/async variables */
uint32_t sync_async_misc[1];
};
/**
* \brief Calculate the baudrate value for hardware to use to set baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] clk Clock frequency (Hz) for baudrate generation.
* \param[in] baud Target baudrate (bps).
* \return Error or baudrate value.
* \retval >0 Baudrate value.
* \retval ERR_INVALID_ARG Calculation fail.
*/
int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_async.h
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@ -1,131 +1,131 @@
/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_ASYNC_H_INCLUDED
#define _HPL_SPI_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_irq.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Callbacks the SPI driver must offer in async mode
*/
//@{
/** The callback types */
enum _spi_async_dev_cb_type {
/** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_TX,
/** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_RX,
/** Callback type for \ref _spi_async_dev_cb_complete_t. */
SPI_DEV_CB_COMPLETE,
/** Callback type for error */
SPI_DEV_CB_ERROR,
/** Number of callbacks. */
SPI_DEV_CB_N
};
struct _spi_async_dev;
/** \brief The prototype for callback on SPI transfer error.
* If status code is zero, it indicates the normal completion, that is,
* SS deactivation.
* If status code belows zero, it indicates complete.
*/
typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status);
/** \brief The prototype for callback on SPI transmit/receive event
* For TX, the callback is invoked when transmit is done or ready to start
* transmit.
* For RX, the callback is invoked when receive is done or ready to read data,
* see \ref _spi_async_dev_read_one_t on data reading.
* Without DMA enabled, the callback is invoked on each character event.
* With DMA enabled, the callback is invoked on DMA buffer done.
*/
typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev);
/**
* \brief The callbacks offered by SPI driver
*/
struct _spi_async_dev_callbacks {
/** TX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t tx;
/** RX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t rx;
/** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */
_spi_async_dev_cb_xfer_t complete;
/** Error callback, see \ref */
_spi_async_dev_cb_error_t err;
};
//@}
/**
* \brief SPI async driver
*/
//@{
/** SPI driver to support async HAL */
struct _spi_async_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
/** \brief Pointer to callback functions, ignored for polling mode
* Pointer to the callback functions so that initialize the driver to
* handle interrupts.
*/
struct _spi_async_dev_callbacks callbacks;
/** IRQ instance for SPI device. */
struct _irq_descriptor irq;
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */
/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_ASYNC_H_INCLUDED
#define _HPL_SPI_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_irq.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Callbacks the SPI driver must offer in async mode
*/
//@{
/** The callback types */
enum _spi_async_dev_cb_type {
/** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_TX,
/** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_RX,
/** Callback type for \ref _spi_async_dev_cb_complete_t. */
SPI_DEV_CB_COMPLETE,
/** Callback type for error */
SPI_DEV_CB_ERROR,
/** Number of callbacks. */
SPI_DEV_CB_N
};
struct _spi_async_dev;
/** \brief The prototype for callback on SPI transfer error.
* If status code is zero, it indicates the normal completion, that is,
* SS deactivation.
* If status code belows zero, it indicates complete.
*/
typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status);
/** \brief The prototype for callback on SPI transmit/receive event
* For TX, the callback is invoked when transmit is done or ready to start
* transmit.
* For RX, the callback is invoked when receive is done or ready to read data,
* see \ref _spi_async_dev_read_one_t on data reading.
* Without DMA enabled, the callback is invoked on each character event.
* With DMA enabled, the callback is invoked on DMA buffer done.
*/
typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev);
/**
* \brief The callbacks offered by SPI driver
*/
struct _spi_async_dev_callbacks {
/** TX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t tx;
/** RX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t rx;
/** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */
_spi_async_dev_cb_xfer_t complete;
/** Error callback, see \ref */
_spi_async_dev_cb_error_t err;
};
//@}
/**
* \brief SPI async driver
*/
//@{
/** SPI driver to support async HAL */
struct _spi_async_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
/** \brief Pointer to callback functions, ignored for polling mode
* Pointer to the callback functions so that initialize the driver to
* handle interrupts.
*/
struct _spi_async_dev_callbacks callbacks;
/** IRQ instance for SPI device. */
struct _irq_descriptor irq;
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
#define _HPL_SPI_M_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_m_async_dev _spi_async_dev
#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on after data transmission complate
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI master interrupt
*
* param[in] device The pointer to SPI master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */
/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
#define _HPL_SPI_M_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_m_async_dev _spi_async_dev
#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on after data transmission complate
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI master interrupt
*
* param[in] device The pointer to SPI master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_dma.h
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/**
* \file
*
* \brief SPI Master DMA related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_DMA_H_INCLUDED
#define _HPL_SPI_M_DMA_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_dma.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI dma device driver. */
#define _spi_m_dma_dev _spi_dma_dev
#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord);
/**
* \brief Register the SPI device callback
* \param[in] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func);
/** \brief Do SPI data transfer (TX & RX) with DMA
* Log the TX & RX buffers and transfer them in background. It never blocks.
*
* \param[in] dev Pointer to the SPI device instance.
* \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
* \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
* \param[in] length spi transfer data length.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */
/**
* \file
*
* \brief SPI Master DMA related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_DMA_H_INCLUDED
#define _HPL_SPI_M_DMA_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_dma.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI dma device driver. */
#define _spi_m_dma_dev _spi_dma_dev
#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord);
/**
* \brief Register the SPI device callback
* \param[in] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func);
/** \brief Do SPI data transfer (TX & RX) with DMA
* Log the TX & RX buffers and transfer them in background. It never blocks.
*
* \param[in] dev Pointer to the SPI device instance.
* \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
* \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
* \param[in] length spi transfer data length.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_sync.h
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@ -1,166 +1,166 @@
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
#define _HPL_SPI_M_SYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_m_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
/**
* \brief Deinitialize SPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI char size
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Transfer the whole message without interrupt
* Transfer the message, it will keep waiting until the message finish or
* error.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] msg Pointer to the message instance to process.
* \return Error or number of characters transferred.
* \retval ERR_BUSY SPI hardware is not ready to start transfer (not
* enabled, busy applying settings, ...).
* \retval SPI_ERR_OVERFLOW Overflow error.
* \retval >=0 Number of characters transferred.
*/
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
#define _HPL_SPI_M_SYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_m_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
/**
* \brief Deinitialize SPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI char size
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Transfer the whole message without interrupt
* Transfer the message, it will keep waiting until the message finish or
* error.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] msg Pointer to the message instance to process.
* \return Error or number of characters transferred.
* \retval ERR_BUSY SPI hardware is not ready to start transfer (not
* enabled, busy applying settings, ...).
* \retval SPI_ERR_OVERFLOW Overflow error.
* \retval >=0 Number of characters transferred.
*/
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED
#define _HPL_SPI_S_ASYNC_H_INCLUDED
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_s_async_dev _spi_async_dev
#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on Slave Select (SS) rising
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI slave interrupt
*
* param[in] device The pointer to SPI slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */
/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED
#define _HPL_SPI_S_ASYNC_H_INCLUDED
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_s_async_dev _spi_async_dev
#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on Slave Select (SS) rising
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI slave interrupt
*
* param[in] device The pointer to SPI slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_SYNC_H_INCLUDED
#define _HPL_SPI_S_SYNC_H_INCLUDED
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_s_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retval 0 OK Status
*/
int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data);
/**
* \brief Check if TX ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return TX ready state
* \retval true TX ready
* \retval false TX not ready
*/
bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if RX character ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return RX character ready state
* \retval true RX character ready
* \retval false RX character not ready
*/
bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if SS deactiviation detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return SS deactiviation state
* \retval true SS deactiviation detected
* \retval false SS deactiviation not detected
*/
bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev);
/**
* \brief Check if error is detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return Error detection state
* \retval true Error detected
* \retval false Error not detected
*/
bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_SYNC_H_INCLUDED
#define _HPL_SPI_S_SYNC_H_INCLUDED
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_s_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retval 0 OK Status
*/
int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data);
/**
* \brief Check if TX ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return TX ready state
* \retval true TX ready
* \retval false TX not ready
*/
bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if RX character ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return RX character ready state
* \retval true RX character ready
* \retval false RX character not ready
*/
bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if SS deactiviation detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return SS deactiviation state
* \retval true SS deactiviation detected
* \retval false SS deactiviation not detected
*/
bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev);
/**
* \brief Check if error is detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return Error detection state
* \retval true Error detected
* \retval false Error not detected
*/
bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_sync.h
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/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_SYNC_H_INCLUDED
#define _HPL_SPI_SYNC_H_INCLUDED
#include <compiler.h>
#include <utils.h>
#include <hpl_spi.h>
/**
* \addtogroup hpl_spi HPL SPI
*
* \section hpl_spi_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** SPI driver to support sync HAL */
struct _spi_sync_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
};
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */
/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_SYNC_H_INCLUDED
#define _HPL_SPI_SYNC_H_INCLUDED
#include <compiler.h>
#include <utils.h>
#include <hpl_spi.h>
/**
* \addtogroup hpl_spi HPL SPI
*
* \section hpl_spi_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** SPI driver to support sync HAL */
struct _spi_sync_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
};
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_timer.h
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/**
* \file
*
* \brief Timer related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_TIMER_H_INCLUDED
#define _HPL_TIMER_H_INCLUDED
/**
* \addtogroup HPL Timer
*
* \section hpl_timer_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Timer device structure
*
* The Timer device structure forward declaration.
*/
struct _timer_device;
/**
* \brief Timer interrupt callbacks
*/
struct _timer_callbacks {
void (*period_expired)(struct _timer_device *device);
};
/**
* \brief Timer device structure
*/
struct _timer_device {
struct _timer_callbacks timer_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief Timer functions, pointers to low-level functions
*/
struct _timer_hpl_interface {
int32_t (*init)(struct _timer_device *const device, void *const hw);
void (*deinit)(struct _timer_device *const device);
void (*start_timer)(struct _timer_device *const device);
void (*stop_timer)(struct _timer_device *const device);
void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
uint32_t (*get_period)(const struct _timer_device *const device);
bool (*is_timer_started)(const struct _timer_device *const device);
void (*set_timer_irq)(struct _timer_device *const device);
};
/**
* \brief Initialize TCC
*
* This function does low level TCC configuration.
*
* \param[in] device The pointer to timer device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _timer_init(struct _timer_device *const device, void *const hw);
/**
* \brief Deinitialize TCC
*
* \param[in] device The pointer to timer device instance
*/
void _timer_deinit(struct _timer_device *const device);
/**
* \brief Start hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_start(struct _timer_device *const device);
/**
* \brief Stop hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_stop(struct _timer_device *const device);
/**
* \brief Set timer period
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
/**
* \brief Retrieve timer period
*
* \param[in] device The pointer to timer device instance
*
* \return Timer period
*/
uint32_t _timer_get_period(const struct _timer_device *const device);
/**
* \brief Check if timer is running
*
* \param[in] device The pointer to timer device instance
*
* \return Check status.
* \retval true The given timer is running
* \retval false The given timer is not running
*/
bool _timer_is_started(const struct _timer_device *const device);
/**
* \brief Set timer IRQ
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_irq(struct _timer_device *const device);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_TIMER_H_INCLUDED */
/**
* \file
*
* \brief Timer related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_TIMER_H_INCLUDED
#define _HPL_TIMER_H_INCLUDED
/**
* \addtogroup HPL Timer
*
* \section hpl_timer_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Timer device structure
*
* The Timer device structure forward declaration.
*/
struct _timer_device;
/**
* \brief Timer interrupt callbacks
*/
struct _timer_callbacks {
void (*period_expired)(struct _timer_device *device);
};
/**
* \brief Timer device structure
*/
struct _timer_device {
struct _timer_callbacks timer_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief Timer functions, pointers to low-level functions
*/
struct _timer_hpl_interface {
int32_t (*init)(struct _timer_device *const device, void *const hw);
void (*deinit)(struct _timer_device *const device);
void (*start_timer)(struct _timer_device *const device);
void (*stop_timer)(struct _timer_device *const device);
void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
uint32_t (*get_period)(const struct _timer_device *const device);
bool (*is_timer_started)(const struct _timer_device *const device);
void (*set_timer_irq)(struct _timer_device *const device);
};
/**
* \brief Initialize TCC
*
* This function does low level TCC configuration.
*
* \param[in] device The pointer to timer device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _timer_init(struct _timer_device *const device, void *const hw);
/**
* \brief Deinitialize TCC
*
* \param[in] device The pointer to timer device instance
*/
void _timer_deinit(struct _timer_device *const device);
/**
* \brief Start hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_start(struct _timer_device *const device);
/**
* \brief Stop hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_stop(struct _timer_device *const device);
/**
* \brief Set timer period
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
/**
* \brief Retrieve timer period
*
* \param[in] device The pointer to timer device instance
*
* \return Timer period
*/
uint32_t _timer_get_period(const struct _timer_device *const device);
/**
* \brief Check if timer is running
*
* \param[in] device The pointer to timer device instance
*
* \return Check status.
* \retval true The given timer is running
* \retval false The given timer is not running
*/
bool _timer_is_started(const struct _timer_device *const device);
/**
* \brief Set timer IRQ
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_irq(struct _timer_device *const device);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_TIMER_H_INCLUDED */

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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_H_INCLUDED
#define _HPL_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART flow control state
*/
union usart_flow_control_state {
struct {
uint8_t cts : 1;
uint8_t rts : 1;
uint8_t unavailable : 1;
uint8_t reserved : 5;
} bit;
uint8_t value;
};
/**
* \brief USART baud rate mode
*/
enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH };
/**
* \brief USART data order
*/
enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 };
/**
* \brief USART mode
*/
enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 };
/**
* \brief USART parity
*/
enum usart_parity {
USART_PARITY_EVEN = 0,
USART_PARITY_ODD = 1,
USART_PARITY_NONE = 2,
USART_PARITY_SPACE = 3,
USART_PARITY_MARK = 4
};
/**
* \brief USART stop bits mode
*/
enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 };
/**
* \brief USART character size
*/
enum usart_character_size {
USART_CHARACTER_SIZE_8BITS = 0,
USART_CHARACTER_SIZE_9BITS = 1,
USART_CHARACTER_SIZE_5BITS = 5,
USART_CHARACTER_SIZE_6BITS = 6,
USART_CHARACTER_SIZE_7BITS = 7
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_H_INCLUDED */
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_H_INCLUDED
#define _HPL_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART flow control state
*/
union usart_flow_control_state {
struct {
uint8_t cts : 1;
uint8_t rts : 1;
uint8_t unavailable : 1;
uint8_t reserved : 5;
} bit;
uint8_t value;
};
/**
* \brief USART baud rate mode
*/
enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH };
/**
* \brief USART data order
*/
enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 };
/**
* \brief USART mode
*/
enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 };
/**
* \brief USART parity
*/
enum usart_parity {
USART_PARITY_EVEN = 0,
USART_PARITY_ODD = 1,
USART_PARITY_NONE = 2,
USART_PARITY_SPACE = 3,
USART_PARITY_MARK = 4
};
/**
* \brief USART stop bits mode
*/
enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 };
/**
* \brief USART character size
*/
enum usart_character_size {
USART_CHARACTER_SIZE_8BITS = 0,
USART_CHARACTER_SIZE_9BITS = 1,
USART_CHARACTER_SIZE_5BITS = 5,
USART_CHARACTER_SIZE_6BITS = 6,
USART_CHARACTER_SIZE_7BITS = 7
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_H_INCLUDED */

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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_ASYNC_H_INCLUDED
#define _HPL_USART_ASYNC_H_INCLUDED
/**
* \addtogroup HPL USART
*
* \section hpl_usart_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_usart.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART callback types
*/
enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR };
/**
* \brief USART device structure
*
* The USART device structure forward declaration.
*/
struct _usart_async_device;
/**
* \brief USART interrupt callbacks
*/
struct _usart_async_callbacks {
void (*tx_byte_sent)(struct _usart_async_device *device);
void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data);
void (*tx_done_cb)(struct _usart_async_device *device);
void (*error_cb)(struct _usart_async_device *device);
};
/**
* \brief USART descriptor device structure
*/
struct _usart_async_device {
struct _usart_async_callbacks usart_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize asynchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_deinit(struct _usart_async_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable(struct _usart_async_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_disable(struct _usart_async_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_async_get_status(const struct _usart_async_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_async_is_byte_sent(const struct _usart_async_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_async_set_flow_control_state(struct _usart_async_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device);
/**
* \brief Enable data register empty interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device);
/**
* \brief Enable transmission complete interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device);
/**
* \brief Enable/disable USART interrupt
*
* param[in] device The pointer to USART device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_ASYNC_H_INCLUDED */
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_ASYNC_H_INCLUDED
#define _HPL_USART_ASYNC_H_INCLUDED
/**
* \addtogroup HPL USART
*
* \section hpl_usart_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_usart.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART callback types
*/
enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR };
/**
* \brief USART device structure
*
* The USART device structure forward declaration.
*/
struct _usart_async_device;
/**
* \brief USART interrupt callbacks
*/
struct _usart_async_callbacks {
void (*tx_byte_sent)(struct _usart_async_device *device);
void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data);
void (*tx_done_cb)(struct _usart_async_device *device);
void (*error_cb)(struct _usart_async_device *device);
};
/**
* \brief USART descriptor device structure
*/
struct _usart_async_device {
struct _usart_async_callbacks usart_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize asynchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_deinit(struct _usart_async_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable(struct _usart_async_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_disable(struct _usart_async_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_async_get_status(const struct _usart_async_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_async_is_byte_sent(const struct _usart_async_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_async_set_flow_control_state(struct _usart_async_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device);
/**
* \brief Enable data register empty interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device);
/**
* \brief Enable transmission complete interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device);
/**
* \brief Enable/disable USART interrupt
*
* param[in] device The pointer to USART device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_ASYNC_H_INCLUDED */

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_sync.h
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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SYNC_USART_H_INCLUDED
#define _HPL_SYNC_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <hpl_usart.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART descriptor device structure
*/
struct _usart_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_deinit(struct _usart_sync_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_enable(struct _usart_sync_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_disable(struct _usart_sync_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data);
/**
* \brief Read a byte from the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*
* \return Data received via USART interface.
*/
uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device);
/**
* \brief Check if USART transmitter has sent the byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART transmitter has sent the byte
* \retval false if the USART transmitter has not send the byte
*/
bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device);
/**
* \brief Check if there is data received by USART
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the data received check.
* \retval true if the USART has received a byte
* \retval false if the USART has not received a byte
*/
bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SYNC_USART_H_INCLUDED */
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SYNC_USART_H_INCLUDED
#define _HPL_SYNC_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <hpl_usart.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART descriptor device structure
*/
struct _usart_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_deinit(struct _usart_sync_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_enable(struct _usart_sync_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_disable(struct _usart_sync_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data);
/**
* \brief Read a byte from the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*
* \return Data received via USART interface.
*/
uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device);
/**
* \brief Check if USART transmitter has sent the byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART transmitter has sent the byte
* \retval false if the USART transmitter has not send the byte
*/
bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device);
/**
* \brief Check if there is data received by USART
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the data received check.
* \retval true if the USART has received a byte
* \retval false if the USART has not received a byte
*/
bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SYNC_USART_H_INCLUDED */

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/**
* \file
*
* \brief Critical sections related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_atomic.h"
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Disable interrupts, enter critical section
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic)
{
*atomic = __get_PRIMASK();
__disable_irq();
__DMB();
}
/**
* \brief Exit atomic section
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic)
{
__DMB();
__set_PRIMASK(*atomic);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t atomic_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \file
*
* \brief Critical sections related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_atomic.h"
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Disable interrupts, enter critical section
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic)
{
*atomic = __get_PRIMASK();
__disable_irq();
__DMB();
}
/**
* \brief Exit atomic section
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic)
{
__DMB();
__set_PRIMASK(*atomic);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t atomic_get_version(void)
{
return DRIVER_VERSION;
}

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software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_cache.c
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/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <compiler.h>
#include <hpl_cmcc.h>
/**
* \brief Initialize cache module
*/
int32_t cache_init(void)
{
return _cmcc_init();
}
/**
* \brief Enable cache module
*/
int32_t cache_enable(const void *hw)
{
return _cmcc_enable(hw);
}
/**
* \brief Disable cache module
*/
int32_t cache_disable(const void *hw)
{
return _cmcc_disable(hw);
}
/**
* \brief Configure cache module
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache)
{
return _cmcc_configure(hw, cache);
}
/**
* \brief Invalidate entire cache entries
*/
int32_t cache_invalidate_all(const void *hw)
{
return _cmcc_invalidate_all(hw);
}
/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <compiler.h>
#include <hpl_cmcc.h>
/**
* \brief Initialize cache module
*/
int32_t cache_init(void)
{
return _cmcc_init();
}
/**
* \brief Enable cache module
*/
int32_t cache_enable(const void *hw)
{
return _cmcc_enable(hw);
}
/**
* \brief Disable cache module
*/
int32_t cache_disable(const void *hw)
{
return _cmcc_disable(hw);
}
/**
* \brief Configure cache module
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache)
{
return _cmcc_configure(hw, cache);
}
/**
* \brief Invalidate entire cache entries
*/
int32_t cache_invalidate_all(const void *hw)
{
return _cmcc_invalidate_all(hw);
}

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/**
* \file
*
* \brief HAL delay related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#include "hal_delay.h"
#include <hpl_delay.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief The pointer to a hardware instance used by the driver.
*/
static void *hardware;
/**
* \brief Initialize Delay driver
*/
void delay_init(void *const hw)
{
_delay_init(hardware = hw);
}
/**
* \brief Perform delay in us
*/
void delay_us(const uint16_t us)
{
_delay_cycles(hardware, _get_cycles_for_us(us));
}
/**
* \brief Perform delay in ms
*/
void delay_ms(const uint16_t ms)
{
_delay_cycles(hardware, _get_cycles_for_ms(ms));
}
/**
* \brief Retrieve the current driver version
*/
uint32_t delay_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \file
*
* \brief HAL delay related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#include "hal_delay.h"
#include <hpl_delay.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief The pointer to a hardware instance used by the driver.
*/
static void *hardware;
/**
* \brief Initialize Delay driver
*/
void delay_init(void *const hw)
{
_delay_init(hardware = hw);
}
/**
* \brief Perform delay in us
*/
void delay_us(const uint16_t us)
{
_delay_cycles(hardware, _get_cycles_for_us(us));
}
/**
* \brief Perform delay in ms
*/
void delay_ms(const uint16_t ms)
{
_delay_cycles(hardware, _get_cycles_for_ms(ms));
}
/**
* \brief Retrieve the current driver version
*/
uint32_t delay_get_version(void)
{
return DRIVER_VERSION;
}

376
software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_ext_irq.c
Unescape Escape View File

@ -1,188 +1,188 @@
/**
* \file
*
* \brief External interrupt functionality imkplementation.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_ext_irq.h"
#define EXT_IRQ_AMOUNT 0
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief External IRQ struct
*/
struct ext_irq {
ext_irq_cb_t cb;
uint32_t pin;
};
/* Remove KEIL compiling error in case no IRQ line selected */
#if EXT_IRQ_AMOUNT == 0
#undef EXT_IRQ_AMOUNT
#define EXT_IRQ_AMOUNT 1
#endif
/**
* \brief Array of external IRQs callbacks
*/
static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT];
static void process_ext_irq(const uint32_t pin);
/**
* \brief Initialize external irq component if any
*/
int32_t ext_irq_init(void)
{
uint16_t i;
for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
ext_irqs[i].pin = 0xFFFFFFFF;
ext_irqs[i].cb = NULL;
}
return _ext_irq_init(process_ext_irq);
}
/**
* \brief Deinitialize external irq if any
*/
int32_t ext_irq_deinit(void)
{
return _ext_irq_deinit();
}
/**
* \brief Register callback for the given external interrupt
*/
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb)
{
uint8_t i = 0, j = 0;
bool found = false;
for (; i < EXT_IRQ_AMOUNT; i++) {
if (ext_irqs[i].pin == pin) {
ext_irqs[i].cb = cb;
found = true;
break;
}
}
if (NULL == cb) {
if (!found) {
return ERR_INVALID_ARG;
}
return _ext_irq_enable(pin, false);
}
if (!found) {
for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
if (NULL == ext_irqs[i].cb) {
ext_irqs[i].cb = cb;
ext_irqs[i].pin = pin;
found = true;
break;
}
}
for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) {
if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) {
struct ext_irq tmp = ext_irqs[j];
ext_irqs[j] = ext_irqs[i];
ext_irqs[i] = tmp;
}
}
}
if (!found) {
return ERR_INVALID_ARG;
}
return _ext_irq_enable(pin, true);
}
/**
* \brief Enable external irq
*/
int32_t ext_irq_enable(const uint32_t pin)
{
return _ext_irq_enable(pin, true);
}
/**
* \brief Disable external irq
*/
int32_t ext_irq_disable(const uint32_t pin)
{
return _ext_irq_enable(pin, false);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t ext_irq_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \brief Interrupt processing routine
*
* \param[in] pin The pin which triggered the interrupt
*/
static void process_ext_irq(const uint32_t pin)
{
uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
while (upper >= lower) {
middle = (upper + lower) >> 1;
if (middle >= EXT_IRQ_AMOUNT) {
return;
}
if (ext_irqs[middle].pin == pin) {
if (ext_irqs[middle].cb) {
ext_irqs[middle].cb();
}
return;
}
if (ext_irqs[middle].pin < pin) {
lower = middle + 1;
} else {
upper = middle - 1;
}
}
}
/**
* \file
*
* \brief External interrupt functionality imkplementation.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_ext_irq.h"
#define EXT_IRQ_AMOUNT 0
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief External IRQ struct
*/
struct ext_irq {
ext_irq_cb_t cb;
uint32_t pin;
};
/* Remove KEIL compiling error in case no IRQ line selected */
#if EXT_IRQ_AMOUNT == 0
#undef EXT_IRQ_AMOUNT
#define EXT_IRQ_AMOUNT 1
#endif
/**
* \brief Array of external IRQs callbacks
*/
static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT];
static void process_ext_irq(const uint32_t pin);
/**
* \brief Initialize external irq component if any
*/
int32_t ext_irq_init(void)
{
uint16_t i;
for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
ext_irqs[i].pin = 0xFFFFFFFF;
ext_irqs[i].cb = NULL;
}
return _ext_irq_init(process_ext_irq);
}
/**
* \brief Deinitialize external irq if any
*/
int32_t ext_irq_deinit(void)
{
return _ext_irq_deinit();
}
/**
* \brief Register callback for the given external interrupt
*/
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb)
{
uint8_t i = 0, j = 0;
bool found = false;
for (; i < EXT_IRQ_AMOUNT; i++) {
if (ext_irqs[i].pin == pin) {
ext_irqs[i].cb = cb;
found = true;
break;
}
}
if (NULL == cb) {
if (!found) {
return ERR_INVALID_ARG;
}
return _ext_irq_enable(pin, false);
}
if (!found) {
for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
if (NULL == ext_irqs[i].cb) {
ext_irqs[i].cb = cb;
ext_irqs[i].pin = pin;
found = true;
break;
}
}
for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) {
if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) {
struct ext_irq tmp = ext_irqs[j];
ext_irqs[j] = ext_irqs[i];
ext_irqs[i] = tmp;
}
}
}
if (!found) {
return ERR_INVALID_ARG;
}
return _ext_irq_enable(pin, true);
}
/**
* \brief Enable external irq
*/
int32_t ext_irq_enable(const uint32_t pin)
{
return _ext_irq_enable(pin, true);
}
/**
* \brief Disable external irq
*/
int32_t ext_irq_disable(const uint32_t pin)
{
return _ext_irq_enable(pin, false);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t ext_irq_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \brief Interrupt processing routine
*
* \param[in] pin The pin which triggered the interrupt
*/
static void process_ext_irq(const uint32_t pin)
{
uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
while (upper >= lower) {
middle = (upper + lower) >> 1;
if (middle >= EXT_IRQ_AMOUNT) {
return;
}
if (ext_irqs[middle].pin == pin) {
if (ext_irqs[middle].cb) {
ext_irqs[middle].cb();
}
return;
}
if (ext_irqs[middle].pin < pin) {
lower = middle + 1;
} else {
upper = middle - 1;
}
}
}

88
software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_gpio.c
Unescape Escape View File

@ -1,44 +1,44 @@
/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_gpio.h"
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
uint32_t gpio_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_gpio.h"
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
uint32_t gpio_get_version(void)
{
return DRIVER_VERSION;
}

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