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prepping d21 test project

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stable
Penguin 5 years ago
parent 2852975f89
commit 70286bfc2c
1222 changed files with 621762 additions and 66366 deletions
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3
.gitmodules vendored
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[submodule "software/firmware/project_oracle_test_prj/project_oracle_test_prj/thirdparty/lvgl"]
path = software/firmware/project_oracle_test_prj/project_oracle_test_prj/thirdparty/lvgl
url = https://github.com/lvgl/lvgl.git
[submodule "software/thirdparty/lvgl"]
path = software/thirdparty/lvgl
url = https://github.com/lvgl/lvgl.git

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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/.vs/oracle_test_d21/v14/.atsuo
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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21.atsln
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Microsoft Visual Studio Solution File, Format Version 12.00
# Atmel Studio Solution File, Format Version 11.00
VisualStudioVersion = 14.0.23107.0
MinimumVisualStudioVersion = 10.0.40219.1
Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "oracle_test_d21", "oracle_test_d21\oracle_test_d21.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|ARM = Debug|ARM
Release|ARM = Release|ARM
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
EndGlobal

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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21/oracle_test_d21.componentinfo.xml
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<?xml version="1.0" encoding="utf-8"?>
<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
<ProjectComponents />
</Store>

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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21/oracle_test_d21.cproj
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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21/src/ASF/common/boards/board.h
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/**
* \file
*
* \brief Standard board header file.
*
* This file includes the appropriate board header file according to the
* defined board (parameter BOARD).
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/**
* \defgroup group_common_boards Generic board support
*
* The generic board support module includes board-specific definitions
* and function prototypes, such as the board initialization function.
*
* \{
*/
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/*! \name Base Boards
*/
//! @{
#define EVK1100 1 //!< AT32UC3A EVK1100 board.
#define EVK1101 2 //!< AT32UC3B EVK1101 board.
#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
#define EVK1105 5 //!< AT32UC3A EVK1105 board.
#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
#define UC3L_EK 7 //!< AT32UC3L-EK board.
#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board.
#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board.
#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board.
#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards.
#define RZ600 31 //!< AT32UC3A RZ600 MCU board.
#define SAM3S_EK 32 //!< SAM3S-EK board.
#define SAM3U_EK 33 //!< SAM3U-EK board.
#define SAM3X_EK 34 //!< SAM3X-EK board.
#define SAM3N_EK 35 //!< SAM3N-EK board.
#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
#define SAM4S_EK 37 //!< SAM4S-EK board.
#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
#define STK600_MEGA 39 //!< STK600 MEGA board.
#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board.
#define SAM4L_EK 45 //!< SAM4L-EK board.
#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
#define SAM4E_EK 51 //!< SAM4E-EK board.
#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit.
#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit.
#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit.
#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board.
#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB.
#define SAM4C_EK 64 //!< SAM4C-EK board.
#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
#define ATPL230AMB 73 //!< ATPL230AMB board.
#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board.
#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board.
#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board.
#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board.
#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board.
#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board.
#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board.
#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board.
#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board.
#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board.
#define SAME70_XPLAINED 85 //!< SAME70 Xplained board.
#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board.
#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board.
#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board.
#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board.
#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board.
#define SAMB11ZR_XPLAINED_PRO 92 //!< SAM B11 ZR Xplained Pro board.
#define SAMR30_XPLAINED_PRO 93 //!< SAM R30 Xplained Pro board.
#define SAMHA1G16A_XPLAINED_PRO 94 //!< SAM HA1G16A Xplained Pro board.
#define SAMR34_XPLAINED_PRO 95 //!< SAM R34 Xplained Pro board.
#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices.
#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
#define USER_BOARD 99 //!< User-reserved board (if any).
#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader).
#define SAMB11ZR_SENSOR_TAG 101 //!< SAMB11ZR sensor tag board
#define SAMR30_MODULE_XPLAINED_PRO 102 //!< SAM R30 Module Xplained Pro board.
#define SAMR21G18_MODULE 103 //!< SAMR21G18-MR210UA Module.
#define SAMR21B18_MODULE 104 //!< SAMR21B18-MZ210PA Module.
//! @}
/*! \name Extension Boards
*/
//! @{
#define EXT1102 1 //!< AT32UC3B EXT1102 board
#define MC300 2 //!< AT32UC3 MC300 board
#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
//! @}
#if BOARD == EVK1100
# include "evk1100/evk1100.h"
#elif BOARD == EVK1101
# include "evk1101/evk1101.h"
#elif BOARD == UC3C_EK
# include "uc3c_ek/uc3c_ek.h"
#elif BOARD == EVK1104
# include "evk1104/evk1104.h"
#elif BOARD == EVK1105
# include "evk1105/evk1105.h"
#elif BOARD == STK600_RCUC3L0
# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
#elif BOARD == UC3L_EK
# include "uc3l_ek/uc3l_ek.h"
#elif BOARD == STK600_RCUC3L4
# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
#elif BOARD == XPLAIN
# include "xplain/xplain.h"
#elif BOARD == STK600_MEGA
/*No header-file to include*/
#elif BOARD == STK600_MEGA_RF
# include "stk600.h"
#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
#elif BOARD == ATMEGA256RFR2_ZIGBIT
# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
#elif BOARD == STK600_RC032X
# include "stk600/rc032x/stk600_rc032x.h"
#elif BOARD == STK600_RC044X
# include "stk600/rc044x/stk600_rc044x.h"
#elif BOARD == STK600_RC064X
# include "stk600/rc064x/stk600_rc064x.h"
#elif BOARD == STK600_RC100X
# include "stk600/rc100x/stk600_rc100x.h"
#elif BOARD == UC3_A3_XPLAINED
# include "uc3_a3_xplained/uc3_a3_xplained.h"
#elif BOARD == UC3_L0_XPLAINED
# include "uc3_l0_xplained/uc3_l0_xplained.h"
#elif BOARD == STK600_RCUC3B0
# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
#elif BOARD == STK600_RCUC3D
# include "stk600/rcuc3d/stk600_rcuc3d.h"
#elif BOARD == STK600_RCUC3C0
# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
#elif BOARD == SAMG53_XPLAINED_PRO
# include "samg53_xplained_pro/samg53_xplained_pro.h"
#elif BOARD == SAMG55_XPLAINED_PRO
# include "samg55_xplained_pro/samg55_xplained_pro.h"
#elif BOARD == XMEGA_B1_XPLAINED
# include "xmega_b1_xplained/xmega_b1_xplained.h"
#elif BOARD == STK600_RC064X_LCDX
# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
#elif BOARD == STK600_RC100X_LCDX
# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
#elif BOARD == XMEGA_A1_XPLAINED
# include "xmega_a1_xplained/xmega_a1_xplained.h"
#elif BOARD == XMEGA_A1U_XPLAINED_PRO
# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
#elif BOARD == UC3_L0_XPLAINED_BC
# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
#elif BOARD == SAM3S_EK
# include "sam3s_ek/sam3s_ek.h"
# include "system_sam3s.h"
#elif BOARD == SAM3S_EK2
# include "sam3s_ek2/sam3s_ek2.h"
# include "system_sam3sd8.h"
#elif BOARD == SAM3U_EK
# include "sam3u_ek/sam3u_ek.h"
# include "system_sam3u.h"
#elif BOARD == SAM3X_EK
# include "sam3x_ek/sam3x_ek.h"
# include "system_sam3x.h"
#elif BOARD == SAM3N_EK
# include "sam3n_ek/sam3n_ek.h"
# include "system_sam3n.h"
#elif BOARD == SAM4S_EK
# include "sam4s_ek/sam4s_ek.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_WPIR_RD
# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_XPLAINED
# include "sam4s_xplained/sam4s_xplained.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_EK2
# include "sam4s_ek2/sam4s_ek2.h"
# include "system_sam4s.h"
#elif BOARD == MEGA_1284P_XPLAINED
/*No header-file to include*/
#elif BOARD == ARDUINO_DUE_X
# include "arduino_due_x/arduino_due_x.h"
# include "system_sam3x.h"
#elif BOARD == SAM4L_EK
# include "sam4l_ek/sam4l_ek.h"
#elif BOARD == SAM4E_EK
# include "sam4e_ek/sam4e_ek.h"
#elif BOARD == SAMD20_XPLAINED_PRO
# include "samd20_xplained_pro/samd20_xplained_pro.h"
#elif BOARD == SAMD21_XPLAINED_PRO
# include "samd21_xplained_pro/samd21_xplained_pro.h"
#elif BOARD == SAMR21_XPLAINED_PRO
# include "samr21_xplained_pro/samr21_xplained_pro.h"
#elif BOARD == SAMR30_XPLAINED_PRO && defined(__SAMR30G18A__)
# include "samr30_xplained_pro/samr30_xplained_pro.h"
#elif BOARD == SAMR30_MODULE_XPLAINED_PRO && defined(__SAMR30E18A__)
# include "samr30_module_xplained_pro/samr30_module_xplained_pro.h"
#elif BOARD == SAMR21ZLL_EK
# include "samr21zll_ek/samr21zll_ek.h"
#elif BOARD == SAMD11_XPLAINED_PRO
# include "samd11_xplained_pro/samd11_xplained_pro.h"
#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
# include "saml21_xplained_pro/saml21_xplained_pro.h"
#elif BOARD == SAML22_XPLAINED_PRO
# include "saml22_xplained_pro/saml22_xplained_pro.h"
#elif BOARD == SAML22_XPLAINED_PRO_B
# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
# include "saml21_xplained_pro_b/saml21_xplained_pro.h"
#elif BOARD == SAMD10_XPLAINED_MINI
# include "samd10_xplained_mini/samd10_xplained_mini.h"
#elif BOARD == SAMDA1_XPLAINED_PRO
# include "samda1_xplained_pro/samda1_xplained_pro.h"
#elif BOARD == SAMHA1G16A_XPLAINED_PRO
# include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
#elif BOARD == SAMC21_XPLAINED_PRO
# include "samc21_xplained_pro/samc21_xplained_pro.h"
#elif BOARD == SAM4N_XPLAINED_PRO
# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
#elif BOARD == SAMW25_XPLAINED_PRO
# include "samw25_xplained_pro/samw25_xplained_pro.h"
#elif BOARD == SAMV71_XPLAINED_ULTRA
# include "samv71_xplained_ultra/samv71_xplained_ultra.h"
#elif BOARD == MEGA1284P_XPLAINED_BC
# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
#elif BOARD == UC3_L0_QT600
# include "uc3_l0_qt600/uc3_l0_qt600.h"
#elif BOARD == XMEGA_A3BU_XPLAINED
# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
#elif BOARD == XMEGA_E5_XPLAINED
# include "xmega_e5_xplained/xmega_e5_xplained.h"
#elif BOARD == UC3B_BOARD_CONTROLLER
# include "uc3b_board_controller/uc3b_board_controller.h"
#elif BOARD == RZ600
# include "rz600/rz600.h"
#elif BOARD == STK600_RCUC3A0
# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
#elif BOARD == ATXMEGA128A1_QT600
# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
#elif BOARD == STK600_RCUC3L3
# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
#elif BOARD == SAM4S_XPLAINED_PRO
# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
#elif BOARD == SAM4L_XPLAINED_PRO
# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
#elif BOARD == SAM4L8_XPLAINED_PRO
# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
#elif BOARD == SAM4C_EK
# include "sam4c_ek/sam4c_ek.h"
#elif BOARD == SAM4CMP_DB
# include "sam4cmp_db/sam4cmp_db.h"
#elif BOARD == SAM4CMS_DB
# include "sam4cms_db/sam4cms_db.h"
#elif BOARD == SAM4CP16BMB
# include "sam4cp16bmb/sam4cp16bmb.h"
#elif BOARD == ATPL230AMB
# include "atpl230amb/atpl230amb.h"
#elif BOARD == XMEGA_C3_XPLAINED
# include "xmega_c3_xplained/xmega_c3_xplained.h"
#elif BOARD == XMEGA_RF233_ZIGBIT
# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
#elif BOARD == XMEGA_A3_REB_CBB
# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
#elif BOARD == ATMEGARFX_RCB
# include "atmegarfx_rcb/atmegarfx_rcb.h"
#elif BOARD == RCB256RFR2_XPRO
# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
#elif BOARD == XMEGA_RF212B_ZIGBIT
# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
#elif BOARD == SAM4E_XPLAINED_PRO
# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
#elif BOARD == ATMEGA328P_XPLAINED_MINI
# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
#elif BOARD == ATMEGA328PB_XPLAINED_MINI
# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
#elif BOARD == SAMB11_XPLAINED_PRO
# include "samb11_xplained_pro/samb11_xplained_pro.h"
#elif BOARD == SAME70_XPLAINED
# include "same70_xplained/same70_xplained.h"
#elif BOARD == ATMEGA168PB_XPLAINED_MINI
# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
#elif BOARD == ATMEGA324PB_XPLAINED_PRO
# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
#elif BOARD == SAMB11ZR_XPLAINED_PRO
# include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
#elif BOARD == SIMULATOR_XMEGA_A1
# include "simulator/xmega_a1/simulator_xmega_a1.h"
#elif BOARD == AVR_SIMULATOR_UC3
# include "avr_simulator_uc3/avr_simulator_uc3.h"
#elif BOARD == SAMR21G18_MODULE
# include "samr21g18_module/samr21g18_module.h"
#elif BOARD == SAMR21B18_MODULE
# include "samr21b18_module/samr21b18_module.h"
#elif BOARD == SAMR34_XPLAINED_PRO && defined(__SAMR34J18B__)
# include "samr34_xplained_pro/samr34_xplained_pro.h"
#elif BOARD == USER_BOARD
// User-reserved area: #include the header file of your board here (if any).
# include "user_board.h"
#elif BOARD == DUMMY_BOARD
# include "dummy/dummy_board.h"
#elif BOARD == SAMB11ZR_SENSOR_TAG
# include "samb11zr_sensor_tag/samb11zr_sensor_tag.h"
#else
# error No known Atmel board defined
#endif
#if (defined EXT_BOARD)
# if EXT_BOARD == MC300
# include "mc300/mc300.h"
# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
(EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
(EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
(EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
# include "sensors_xplained/sensors_xplained.h"
# elif EXT_BOARD == RZ600_AT86RF231
# include "at86rf231/at86rf231.h"
# elif EXT_BOARD == RZ600_AT86RF230B
# include "at86rf230b/at86rf230b.h"
# elif EXT_BOARD == RZ600_AT86RF212
# include "at86rf212/at86rf212.h"
# elif EXT_BOARD == SECURITY_XPLAINED
# include "security_xplained.h"
# elif EXT_BOARD == USER_EXT_BOARD
// User-reserved area: #include the header file of your extension board here
// (if any).
# endif
#endif
#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
/*! \brief This function initializes the board target resources
*
* This function should be called to ensure proper initialization of the target
* board hardware connected to the part.
*/
extern void board_init(void);
#endif // #ifdef __AVR32_ABI_COMPILER__
#else
/*! \brief This function initializes the board target resources
*
* This function should be called to ensure proper initialization of the target
* board hardware connected to the part.
*/
extern void board_init(void);
#endif
#ifdef __cplusplus
}
#endif
/**
* \}
*/
#endif // _BOARD_H_

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/**
* \file
*
* \brief Global interrupt management for 8- and 32-bit AVR
*
* Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef UTILS_INTERRUPT_H
#define UTILS_INTERRUPT_H
#include <parts.h>
#if XMEGA || MEGA
# include "interrupt/interrupt_avr8.h"
#elif UC3
# include "interrupt/interrupt_avr32.h"
#elif SAM || SAMB
# include "interrupt/interrupt_sam_nvic.h"
#else
# error Unsupported device.
#endif
/**
* \defgroup interrupt_group Global interrupt management
*
* This is a driver for global enabling and disabling of interrupts.
*
* @{
*/
#if defined(__DOXYGEN__)
/**
* \def CONFIG_INTERRUPT_FORCE_INTC
* \brief Force usage of the ASF INTC driver
*
* Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
* This is useful to ensure compatibility across compilers and shall be used only when required
* by the application needs.
*/
# define CONFIG_INTERRUPT_FORCE_INTC
#endif
//! \name Global interrupt flags
//@{
/**
* \typedef irqflags_t
* \brief Type used for holding state of interrupt flag
*/
/**
* \def cpu_irq_enable
* \brief Enable interrupts globally
*/
/**
* \def cpu_irq_disable
* \brief Disable interrupts globally
*/
/**
* \fn irqflags_t cpu_irq_save(void)
* \brief Get and clear the global interrupt flags
*
* Use in conjunction with \ref cpu_irq_restore.
*
* \return Current state of interrupt flags.
*
* \note This function leaves interrupts disabled.
*/
/**
* \fn void cpu_irq_restore(irqflags_t flags)
* \brief Restore global interrupt flags
*
* Use in conjunction with \ref cpu_irq_save.
*
* \param flags State to set interrupt flag to.
*/
/**
* \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
* \brief Check if interrupts are globally enabled in supplied flags
*
* \param flags Currents state of interrupt flags.
*
* \return True if interrupts are enabled.
*/
/**
* \def cpu_irq_is_enabled
* \brief Check if interrupts are globally enabled
*
* \return True if interrupts are enabled.
*/
//@}
//! @}
/**
* \ingroup interrupt_group
* \defgroup interrupt_deprecated_group Deprecated interrupt definitions
*/
#endif /* UTILS_INTERRUPT_H */

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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
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/**
* \file
*
* \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "interrupt_sam_nvic.h"
#if !defined(__DOXYGEN__)
/* Deprecated - global flag to determine the global interrupt state. Required by
* QTouch library, however new applications should use cpu_irq_is_enabled()
* which probes the true global interrupt state from the CPU special registers.
*/
volatile bool g_interrupt_enabled = true;
#endif
void cpu_irq_enter_critical(void)
{
if (cpu_irq_critical_section_counter == 0) {
if (cpu_irq_is_enabled()) {
cpu_irq_disable();
cpu_irq_prev_interrupt_state = true;
} else {
/* Make sure the to save the prev state as false */
cpu_irq_prev_interrupt_state = false;
}
}
cpu_irq_critical_section_counter++;
}
void cpu_irq_leave_critical(void)
{
/* Check if the user is trying to leave a critical section when not in a critical section */
Assert(cpu_irq_critical_section_counter > 0);
cpu_irq_critical_section_counter--;
/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
was enabled when entering critical state */
if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
cpu_irq_enable();
}
}

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/**
* \file
*
* \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef UTILS_INTERRUPT_INTERRUPT_H
#define UTILS_INTERRUPT_INTERRUPT_H
#include <compiler.h>
#include <parts.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \weakgroup interrupt_group
*
* @{
*/
/**
* \name Interrupt Service Routine definition
*
* @{
*/
/**
* \brief Define service routine
*
* \note For NVIC devices the interrupt service routines are predefined to
* add to vector table in binary generation, so there is no service
* register at run time. The routine collections are in exceptions.h.
*
* Usage:
* \code
ISR(foo_irq_handler)
{
// Function definition
...
}
\endcode
*
* \param func Name for the function.
*/
# define ISR(func) \
void func (void)
/**
* \brief Initialize interrupt vectors
*
* For NVIC the interrupt vectors are put in vector table. So nothing
* to do to initialize them, except defined the vector function with
* right name.
*
* This must be called prior to \ref irq_register_handler.
*/
# define irq_initialize_vectors() \
do { \
} while(0)
/**
* \brief Register handler for interrupt
*
* For NVIC the interrupt vectors are put in vector table. So nothing
* to do to register them, except defined the vector function with
* right name.
*
* Usage:
* \code
irq_initialize_vectors();
irq_register_handler(foo_irq_handler);
\endcode
*
* \note The function \a func must be defined with the \ref ISR macro.
* \note The functions prototypes can be found in the device exception header
* files (exceptions.h).
*/
# define irq_register_handler(int_num, int_prio) \
NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
NVIC_EnableIRQ( (IRQn_Type)int_num); \
//@}
# define cpu_irq_enable() \
do { \
g_interrupt_enabled = true; \
__DMB(); \
__enable_irq(); \
} while (0)
# define cpu_irq_disable() \
do { \
__disable_irq(); \
__DMB(); \
g_interrupt_enabled = false; \
} while (0)
typedef uint32_t irqflags_t;
#if !defined(__DOXYGEN__)
extern volatile bool g_interrupt_enabled;
#endif
#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
static volatile uint32_t cpu_irq_critical_section_counter;
static volatile bool cpu_irq_prev_interrupt_state;
static inline irqflags_t cpu_irq_save(void)
{
volatile irqflags_t flags = cpu_irq_is_enabled();
cpu_irq_disable();
return flags;
}
static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
{
return (flags);
}
static inline void cpu_irq_restore(irqflags_t flags)
{
if (cpu_irq_is_enabled_flags(flags))
cpu_irq_enable();
}
void cpu_irq_enter_critical(void);
void cpu_irq_leave_critical(void);
/**
* \weakgroup interrupt_deprecated_group
* @{
*/
#define Enable_global_interrupt() cpu_irq_enable()
#define Disable_global_interrupt() cpu_irq_disable()
#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
//@}
//@}
#ifdef __cplusplus
}
#endif
#endif /* UTILS_INTERRUPT_INTERRUPT_H */

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/**
* \file
*
* \brief SAM D21 Xplained Pro board initialization
*
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <compiler.h>
#include <board.h>
#include <conf_board.h>
#include <port.h>
#if defined(__GNUC__)
void board_init(void) WEAK __attribute__((alias("system_board_init")));
#elif defined(__ICCARM__)
void board_init(void);
# pragma weak board_init=system_board_init
#endif
void system_board_init(void)
{
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
/* Configure LEDs as outputs, turn them off */
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(LED_0_PIN, &pin_conf);
port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
/* Set buttons as inputs */
pin_conf.direction = PORT_PIN_DIR_INPUT;
pin_conf.input_pull = PORT_PIN_PULL_UP;
port_pin_set_config(BUTTON_0_PIN, &pin_conf);
#ifdef CONF_BOARD_AT86RFX
port_get_config_defaults(&pin_conf);
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
port_pin_set_output_level(AT86RFX_SPI_SCK, true);
port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
port_pin_set_output_level(AT86RFX_SPI_CS, true);
port_pin_set_output_level(AT86RFX_RST_PIN, true);
port_pin_set_output_level(AT86RFX_SLP_PIN, true);
pin_conf.direction = PORT_PIN_DIR_INPUT;
port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
#endif
}

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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
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/**
* \file
*
* \brief SAM D21 Xplained Pro board definition
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
#define SAMD21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samd21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMD21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PB30
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA15
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15
#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15
#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15
#define SW0_EIC_LINE 15
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 0
#define LED_0_PWM4CTRL_OUTPUT 0
#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Serialflash definitions
*
* On board Serialflash definitions.
*
* @{ */
#define SERIALFLASH_SPI_MODULE SERCOM5
#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define SERIALFLASH_SPI_CS PIN_PA13
/** @} */
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PB00
#define EXT1_PIN_4 PIN_PB01
#define EXT1_PIN_5 PIN_PB06
#define EXT1_PIN_6 PIN_PB07
#define EXT1_PIN_7 PIN_PB02
#define EXT1_PIN_8 PIN_PB03
#define EXT1_PIN_9 PIN_PB04
#define EXT1_PIN_10 PIN_PB05
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB09
#define EXT1_PIN_14 PIN_PB08
#define EXT1_PIN_15 PIN_PA05
#define EXT1_PIN_16 PIN_PA06
#define EXT1_PIN_17 PIN_PA04
#define EXT1_PIN_18 PIN_PA07
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 8
#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8
#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8
#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
#define EXT1_ADC_1_CHANNEL 9
#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9
#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9
#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC6
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0
#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1
#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM2
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM0
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #2 pin definitions
* @{
*/
#define EXT2_PIN_3 PIN_PA10
#define EXT2_PIN_4 PIN_PA11
#define EXT2_PIN_5 PIN_PA20
#define EXT2_PIN_6 PIN_PA21
#define EXT2_PIN_7 PIN_PB12
#define EXT2_PIN_8 PIN_PB13
#define EXT2_PIN_9 PIN_PB14
#define EXT2_PIN_10 PIN_PB15
#define EXT2_PIN_11 PIN_PA08
#define EXT2_PIN_12 PIN_PA09
#define EXT2_PIN_13 PIN_PB11
#define EXT2_PIN_14 PIN_PB10
#define EXT2_PIN_15 PIN_PA17
#define EXT2_PIN_16 PIN_PA18
#define EXT2_PIN_17 PIN_PA16
#define EXT2_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #2 pin definitions by function
* @{
*/
#define EXT2_PIN_ADC_0 EXT2_PIN_3
#define EXT2_PIN_ADC_1 EXT2_PIN_4
#define EXT2_PIN_GPIO_0 EXT2_PIN_5
#define EXT2_PIN_GPIO_1 EXT2_PIN_6
#define EXT2_PIN_PWM_0 EXT2_PIN_7
#define EXT2_PIN_PWM_1 EXT2_PIN_8
#define EXT2_PIN_IRQ EXT2_PIN_9
#define EXT2_PIN_I2C_SDA EXT2_PIN_11
#define EXT2_PIN_I2C_SCL EXT2_PIN_12
#define EXT2_PIN_UART_RX EXT2_PIN_13
#define EXT2_PIN_UART_TX EXT2_PIN_14
#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
#define EXT2_PIN_SPI_MISO EXT2_PIN_17
#define EXT2_PIN_SPI_SCK EXT2_PIN_18
/** @} */
/** \name Extension header #2 ADC definitions
* @{
*/
#define EXT2_ADC_MODULE ADC
#define EXT2_ADC_0_CHANNEL 18
#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
#define EXT2_ADC_1_CHANNEL 19
#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
/** @} */
/** \name Extension header #2 PWM definitions
* @{
*/
#define EXT2_PWM_MODULE TC4
#define EXT2_PWM_0_CHANNEL 0
#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0
#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0
#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0
#define EXT2_PWM_1_CHANNEL 1
#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1
#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1
#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1
/** @} */
/** \name Extension header #2 PWM for Control definitions
* @{
*/
#define EXT2_PWM4CTRL_MODULE TCC0
#define EXT2_PWM4CTRL_0_CHANNEL 2
#define EXT2_PWM4CTRL_0_OUTPUT 6
#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_1_CHANNEL 3
#define EXT2_PWM4CTRL_1_OUTPUT 7
#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7
/** @} */
/** \name Extension header #2 IRQ/External interrupt definitions
* @{
*/
#define EXT2_IRQ_MODULE EIC
#define EXT2_IRQ_INPUT 14
#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
/** @} */
/** \name Extension header #2 I2C definitions
* @{
*/
#define EXT2_I2C_MODULE SERCOM2
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #2 UART definitions
* @{
*/
#define EXT2_UART_MODULE SERCOM4
#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0
#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1
#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #2 SPI definitions
* @{
*/
#define EXT2_SPI_MODULE SERCOM1
#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PA02
#define EXT3_PIN_4 PIN_PA03
#define EXT3_PIN_5 PIN_PB30
#define EXT3_PIN_6 PIN_PA15
#define EXT3_PIN_7 PIN_PA12
#define EXT3_PIN_8 PIN_PA13
#define EXT3_PIN_9 PIN_PA28
#define EXT3_PIN_10 PIN_PA27
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PB11
#define EXT3_PIN_14 PIN_PB10
#define EXT3_PIN_15 PIN_PB17
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB16
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 0
#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0
#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0
#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
#define EXT3_ADC_1_CHANNEL 1
#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #3 PWM for Control definitions
* @{
*/
#define EXT3_PWM4CTRL_MODULE TCC2
#define EXT3_PWM4CTRL_0_CHANNEL 0
#define EXT3_PWM4CTRL_0_OUTPUT 0
#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_1_CHANNEL 1
#define EXT3_PWM4CTRL_1_OUTPUT 1
#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 8
#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8
#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8
#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM2
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM4
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA14
#define USB_VBUS_EIC_LINE 14
#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
#define USB_ID_PIN PIN_PA03
#define USB_ID_EIC_LINE 3
#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3
#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PA27
#define EDBG_GPIO1_PIN PIN_PA28
#define EDBG_GPIO2_PIN PIN_PA20
#define EDBG_GPIO3_PIN PIN_PA21
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM2
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM3
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
/** @} */
/** @} */
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#ifndef EXT2_CONFIG
#define AT86RFX_SPI EXT1_SPI_MODULE
#define AT86RFX_RST_PIN EXT1_PIN_7
#define AT86RFX_MISC_PIN EXT1_PIN_12
#define AT86RFX_IRQ_PIN EXT1_PIN_9
#define AT86RFX_SLP_PIN EXT1_PIN_10
#define AT86RFX_SPI_CS EXT1_PIN_15
#define AT86RFX_SPI_MOSI EXT1_PIN_16
#define AT86RFX_SPI_MISO EXT1_PIN_17
#define AT86RFX_SPI_SCK EXT1_PIN_18
#define AT86RFX_CSD EXT1_PIN_5
#define AT86RFX_CPS EXT1_PIN_8
#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3
#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX
#endif
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ() \
extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ() \
extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION() \
{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */

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/**
* \file
*
* \brief SAM GPIO Port Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <port.h>
/**
* \brief Writes a Port pin configuration to the hardware module.
*
* Writes out a given configuration of a Port pin configuration to the hardware
* module.
*
* \note If the pin direction is set as an output, the pull-up/pull-down input
* configuration setting is ignored.
*
* \param[in] gpio_pin Index of the GPIO pin to configure
* \param[in] config Configuration settings for the pin
*/
void port_pin_set_config(
const uint8_t gpio_pin,
const struct port_config *const config)
{
/* Sanity check arguments */
Assert(config);
struct system_pinmux_config pinmux_config;
system_pinmux_get_config_defaults(&pinmux_config);
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
pinmux_config.powersave = config->powersave;
system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
}
/**
* \brief Writes a Port group configuration group to the hardware module.
*
* Writes out a given configuration of a Port group configuration to the
* hardware module.
*
* \note If the pin direction is set as an output, the pull-up/pull-down input
* configuration setting is ignored.
*
* \param[out] port Base of the PORT module to write to
* \param[in] mask Mask of the port pin(s) to configure
* \param[in] config Configuration settings for the pin group
*/
void port_group_set_config(
PortGroup *const port,
const uint32_t mask,
const struct port_config *const config)
{
/* Sanity check arguments */
Assert(port);
Assert(config);
struct system_pinmux_config pinmux_config;
system_pinmux_get_config_defaults(&pinmux_config);
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
pinmux_config.powersave = config->powersave;
system_pinmux_group_set_config(port, mask, &pinmux_config);
}

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/**
* \file
*
* \brief SAM GPIO Port Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef PORT_H_INCLUDED
#define PORT_H_INCLUDED
/**
* \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver
*
* This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
* an interface for the configuration and management of the device's General
* Purpose Input/Output (GPIO) pin functionality, for manual pin state reading
* and writing.
*
* The following peripheral is used by this module:
* - PORT (GPIO Management)
*
* The following devices can use this module:
* - Atmel | SMART SAM D20/D21
* - Atmel | SMART SAM R21
* - Atmel | SMART SAM D09/D10/D11
* - Atmel | SMART SAM L21/L22
* - Atmel | SMART SAM DA1
* - Atmel | SMART SAM C20/C21
* - Atmel | SMART SAM HA1
* - Atmel | SMART SAM R30
* - Atmel | SMART SAM R34
* - Atmel | SMART SAM R35
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_port_prerequisites
* - \ref asfdoc_sam0_port_module_overview
* - \ref asfdoc_sam0_port_special_considerations
* - \ref asfdoc_sam0_port_extra_info
* - \ref asfdoc_sam0_port_examples
* - \ref asfdoc_sam0_port_api_overview
*
*
* \section asfdoc_sam0_port_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_port_module_overview Module Overview
*
* The device GPIO (PORT) module provides an interface between the user
* application logic and external hardware peripherals, when general pin state
* manipulation is required. This driver provides an easy-to-use interface to
* the physical pin input samplers and output drivers, so that pins can be read
* from or written to for general purpose external hardware control.
*
* \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
* <table>
* <tr>
* <th>Driver Feature Macro</th>
* <th>Supported devices</th>
* </tr>
* <tr>
* <td>FEATURE_PORT_INPUT_EVENT</td>
* <td>SAM L21/L22/C20/C21/R30/R34/R35</td>
* </tr>
* </table>
* \note The specific features are only available in the driver when the
* selected device supports those features.
*
* \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
* SAM devices use two naming conventions for the I/O pins in the device; one
* physical and one logical. Each physical pin on a device package is assigned
* both a physical port and pin identifier (e.g. "PORTA.0") as well as a
* monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
* former is used to map physical pins to their physical internal device module
* counterparts, for simplicity the design of this driver uses the logical GPIO
* numbers instead.
*
* \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
*
* \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
* this module is interconnected within the device.
*
* \anchor asfdoc_sam0_port_module_int_connections
* \dot
* digraph overview {
* node [label="Port Pad" shape=square] pad;
*
* subgraph driver {
* node [label="Peripheral MUX" shape=trapezium] pinmux;
* node [label="GPIO Module" shape=ellipse] gpio;
* node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
* }
*
* pinmux -> gpio;
* pad -> pinmux;
* pinmux -> peripherals;
* }
* \enddot
*
*
* \section asfdoc_sam0_port_special_considerations Special Considerations
*
* The SAM port pin input sampler can be disabled when the pin is configured
* in pure output mode to save power; reading the pin state of a pin configured
* in output-only mode will read the logical output state that was last set.
*
* \section asfdoc_sam0_port_extra_info Extra Information
*
* For extra information, see \ref asfdoc_sam0_port_extra. This includes:
* - \ref asfdoc_sam0_port_extra_acronyms
* - \ref asfdoc_sam0_port_extra_dependencies
* - \ref asfdoc_sam0_port_extra_errata
* - \ref asfdoc_sam0_port_extra_history
*
*
* \section asfdoc_sam0_port_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_port_exqsg.
*
*
* \section asfdoc_sam0_port_api_overview API Overview
* @{
*/
#include <compiler.h>
#include <pinmux.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name Driver Feature Definition
* Define port features set according to different device family.
* @{
*/
#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
/** Event input control feature support for PORT group. */
# define FEATURE_PORT_INPUT_EVENT
#endif
/*@}*/
/** \name PORT Alias Macros
* @{
*/
/** Convenience definition for GPIO module group A on the device (if
* available). */
#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
# define PORTA PORT->Group[0]
#endif
#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
/** Convenience definition for GPIO module group B on the device (if
* available). */
# define PORTB PORT->Group[1]
#endif
#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
/** Convenience definition for GPIO module group C on the device (if
* available). */
# define PORTC PORT->Group[2]
#endif
#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
/** Convenience definition for GPIO module group D on the device (if
* available). */
# define PORTD PORT->Group[3]
#endif
/** @} */
/**
* \brief Port pin direction configuration enum.
*
* Enum for the possible pin direction settings of the port pin configuration
* structure, to indicate the direction the pin should use.
*/
enum port_pin_dir {
/** The pin's input buffer should be enabled, so that the pin state can
* be read */
PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT,
/** The pin's output buffer should be enabled, so that the pin state can
* be set */
PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
/** The pin's output and input buffers should be enabled, so that the pin
* state can be set and read back */
PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
};
/**
* \brief Port pin input pull configuration enum.
*
* Enum for the possible pin pull settings of the port pin configuration
* structure, to indicate the type of logic level pull the pin should use.
*/
enum port_pin_pull {
/** No logical pull should be applied to the pin */
PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
/** Pin should be pulled up when idle */
PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
/** Pin should be pulled down when idle */
PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
};
#ifdef FEATURE_PORT_INPUT_EVENT
/**
* \brief Port input event action.
*
* List of port input events action on pin.
*/
enum port_input_event_action {
/** Event out to pin */
PORT_INPUT_EVENT_ACTION_OUT = 0,
/** Set output register of pin on event */
PORT_INPUT_EVENT_ACTION_SET,
/** Clear output register pin on event */
PORT_INPUT_EVENT_ACTION_CLR,
/** Toggle output register pin on event */
PORT_INPUT_EVENT_ACTION_TGL,
};
/**
* \brief Port input event.
*
* List of port input events.
*/
enum port_input_event{
/** Port input event 0 */
PORT_INPUT_EVENT_0 = 0,
/** Port input event 1 */
PORT_INPUT_EVENT_1 = 1,
/** Port input event 2 */
PORT_INPUT_EVENT_2 = 2,
/** Port input event 3 */
PORT_INPUT_EVENT_3 = 3,
};
/**
* \brief Port input event configuration structure.
*
* Configuration structure for a port input event.
*/
struct port_input_event_config{
/** Port input event action */
enum port_input_event_action action;
/** GPIO pin */
uint8_t gpio_pin;
};
#endif
/**
* \brief Port pin configuration structure.
*
* Configuration structure for a port pin instance. This structure should be
* initialized by the \ref port_get_config_defaults() function before being
* modified by the user application.
*/
struct port_config {
/** Port buffer input/output direction */
enum port_pin_dir direction;
/** Port pull-up/pull-down for input pins */
enum port_pin_pull input_pull;
/** Enable lowest possible powerstate on the pin
*
* \note All other configurations will be ignored, the pin will be disabled.
*/
bool powersave;
};
/** \name State Reading/Writing (Physical Group Orientated)
* @{
*/
/**
* \brief Retrieves the PORT module group instance from a given GPIO pin number.
*
* Retrieves the PORT module group instance associated with a given logical
* GPIO pin number.
*
* \param[in] gpio_pin Index of the GPIO pin to convert
*
* \return Base address of the associated PORT module.
*/
static inline PortGroup* port_get_group_from_gpio_pin(
const uint8_t gpio_pin)
{
return system_pinmux_get_group_from_gpio_pin(gpio_pin);
}
/**
* \brief Retrieves the state of a group of port pins that are configured as inputs.
*
* Reads the current logic level of a port module's pins and returns the
* current levels as a bitmask.
*
* \param[in] port Base of the PORT module to read from
* \param[in] mask Mask of the port pin(s) to read
*
* \return Status of the port pin(s) input buffers.
*/
static inline uint32_t port_group_get_input_level(
const PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
Assert(port);
return (port->IN.reg & mask);
}
/**
* \brief Retrieves the state of a group of port pins that are configured as outputs.
*
* Reads the current logical output level of a port module's pins and returns
* the current levels as a bitmask.
*
* \param[in] port Base of the PORT module to read from
* \param[in] mask Mask of the port pin(s) to read
*
* \return Status of the port pin(s) output buffers.
*/
static inline uint32_t port_group_get_output_level(
const PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
Assert(port);
return (port->OUT.reg & mask);
}
/**
* \brief Sets the state of a group of port pins that are configured as outputs.
*
* Sets the current output level of a port module's pins to a given logic
* level.
*
* \param[out] port Base of the PORT module to write to
* \param[in] mask Mask of the port pin(s) to change
* \param[in] level_mask Mask of the port level(s) to set
*/
static inline void port_group_set_output_level(
PortGroup *const port,
const uint32_t mask,
const uint32_t level_mask)
{
/* Sanity check arguments */
Assert(port);
port->OUTSET.reg = (mask & level_mask);
port->OUTCLR.reg = (mask & ~level_mask);
}
/**
* \brief Toggles the state of a group of port pins that are configured as an outputs.
*
* Toggles the current output levels of a port module's pins.
*
* \param[out] port Base of the PORT module to write to
* \param[in] mask Mask of the port pin(s) to toggle
*/
static inline void port_group_toggle_output_level(
PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
Assert(port);
port->OUTTGL.reg = mask;
}
/** @} */
/** \name Configuration and Initialization
* @{
*/
/**
* \brief Initializes a Port pin/group configuration structure to defaults.
*
* Initializes a given Port pin/group configuration structure to a set of
* known default values. This function should be called on all new
* instances of these configuration structures before being modified by the
* user application.
*
* The default configuration is as follows:
* \li Input mode with internal pull-up enabled
*
* \param[out] config Configuration structure to initialize to default values
*/
static inline void port_get_config_defaults(
struct port_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->direction = PORT_PIN_DIR_INPUT;
config->input_pull = PORT_PIN_PULL_UP;
config->powersave = false;
}
void port_pin_set_config(
const uint8_t gpio_pin,
const struct port_config *const config);
void port_group_set_config(
PortGroup *const port,
const uint32_t mask,
const struct port_config *const config);
/** @} */
/** \name State Reading/Writing (Logical Pin Orientated)
* @{
*/
/**
* \brief Retrieves the state of a port pin that is configured as an input.
*
* Reads the current logic level of a port pin and returns the current
* level as a Boolean value.
*
* \param[in] gpio_pin Index of the GPIO pin to read
*
* \return Status of the port pin's input buffer.
*/
static inline bool port_pin_get_input_level(
const uint8_t gpio_pin)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
return (port_base->IN.reg & pin_mask);
}
/**
* \brief Retrieves the state of a port pin that is configured as an output.
*
* Reads the current logical output level of a port pin and returns the current
* level as a Boolean value.
*
* \param[in] gpio_pin Index of the GPIO pin to read
*
* \return Status of the port pin's output buffer.
*/
static inline bool port_pin_get_output_level(
const uint8_t gpio_pin)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
return (port_base->OUT.reg & pin_mask);
}
/**
* \brief Sets the state of a port pin that is configured as an output.
*
* Sets the current output level of a port pin to a given logic level.
*
* \param[in] gpio_pin Index of the GPIO pin to write to
* \param[in] level Logical level to set the given pin to
*/
static inline void port_pin_set_output_level(
const uint8_t gpio_pin,
const bool level)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
/* Set the pin to high or low atomically based on the requested level */
if (level) {
port_base->OUTSET.reg = pin_mask;
} else {
port_base->OUTCLR.reg = pin_mask;
}
}
/**
* \brief Toggles the state of a port pin that is configured as an output.
*
* Toggles the current output level of a port pin.
*
* \param[in] gpio_pin Index of the GPIO pin to toggle
*/
static inline void port_pin_toggle_output_level(
const uint8_t gpio_pin)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
/* Toggle pin output level */
port_base->OUTTGL.reg = pin_mask;
}
/** @} */
#ifdef FEATURE_PORT_INPUT_EVENT
/** \name Port Input Event
* @{
*/
/**
* \brief Enable the port event input.
*
* Enable the port event input with the given pin and event.
*
* \param[in] gpio_pin Index of the GPIO pin
* \param[in] n Port input event
*
* \retval STATUS_ERR_INVALID_ARG Invalid parameter
* \retval STATUS_OK Successfully
*/
static inline enum status_code port_enable_input_event(
const uint8_t gpio_pin,
const enum port_input_event n)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
switch (n) {
case PORT_INPUT_EVENT_0:
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
break;
case PORT_INPUT_EVENT_1:
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
break;
case PORT_INPUT_EVENT_2:
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
break;
case PORT_INPUT_EVENT_3:
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
break;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
}
/**
* \brief Disable the port event input.
*
* Disable the port event input with the given pin and event.
*
* \param[in] gpio_pin Index of the GPIO pin
* \param[in] gpio_pin Port input event
*
* \retval STATUS_ERR_INVALID_ARG Invalid parameter
* \retval STATUS_OK Successfully
*/
static inline enum status_code port_disable_input_event(
const uint8_t gpio_pin,
const enum port_input_event n)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
switch (n) {
case PORT_INPUT_EVENT_0:
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
break;
case PORT_INPUT_EVENT_1:
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
break;
case PORT_INPUT_EVENT_2:
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
break;
case PORT_INPUT_EVENT_3:
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
break;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
}
/**
* \brief Retrieve the default configuration for port input event.
*
* Fills a configuration structure with the default configuration for port input event:
* - Event output to pin
* - Event action to be executed on PIN 0
*
* \param[out] config Configuration structure to fill with default values
*/
static inline void port_input_event_get_config_defaults(
struct port_input_event_config *const config)
{
Assert(config);
config->action = PORT_INPUT_EVENT_ACTION_OUT;
config->gpio_pin = 0;
}
/**
* \brief Configure port input event.
*
* Configures port input event with the given configuration settings.
*
* \param[in] config Port input even configuration structure containing the new config
*
* \retval STATUS_ERR_INVALID_ARG Invalid parameter
* \retval STATUS_OK Successfully
*/
static inline enum status_code port_input_event_set_config(
const enum port_input_event n,
struct port_input_event_config *const config)
{
Assert(config);
PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
uint8_t pin_index = config->gpio_pin % 32;
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
/* Configure the GPIO pin as outputs*/
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(config->gpio_pin, &pin_conf);
switch (n) {
case PORT_INPUT_EVENT_0:
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
| PORT_EVCTRL_PID0(pin_index);
break;
case PORT_INPUT_EVENT_1:
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
| PORT_EVCTRL_PID1(pin_index);
break;
case PORT_INPUT_EVENT_2:
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
| PORT_EVCTRL_PID2(pin_index);
break;
case PORT_INPUT_EVENT_3:
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
| PORT_EVCTRL_PID3(pin_index);
break;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
}
/** @} */
#endif
#ifdef __cplusplus
}
#endif
/** @} */
/**
* \page asfdoc_sam0_port_extra Extra Information for PORT Driver
*
* \section asfdoc_sam0_port_extra_acronyms Acronyms
* Below is a table listing the acronyms used in this module, along with their
* intended meanings.
*
* <table>
* <tr>
* <th>Acronym</th>
* <th>Description</th>
* </tr>
* <tr>
* <td>GPIO</td>
* <td>General Purpose Input/Output</td>
* </tr>
* <tr>
* <td>MUX</td>
* <td>Multiplexer</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_port_extra_dependencies Dependencies
* This driver has the following dependencies:
*
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
*
*
* \section asfdoc_sam0_port_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_port_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>Added input event feature</td>
* </tr>
* <tr>
* <td>Initial release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_port_exqsg Examples for PORT Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that a QSG can be compiled as a standalone application or be
* added to the user application.
*
* - \subpage asfdoc_sam0_port_basic_use_case
*
* \page asfdoc_sam0_port_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>42113E</td>
* <td>12/2015</td>
* <td>Added input event feature.
* Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30/R34 and SAM DA1.</td>
* </tr>
* <tr>
* <td>42113D</td>
* <td>12/2014</td>
* <td>Added support for SAM R21 and SAM D10/D11</td>
* </tr>
* <tr>
* <td>42113C</td>
* <td>01/2014</td>
* <td>Added support for SAM D21</td>
* </tr>
* <tr>
* <td>42113B</td>
* <td>06/2013</td>
* <td>Corrected documentation typos</td>
* </tr>
* <tr>
* <td>42113A</td>
* <td>06/2013</td>
* <td>Initial document release</td>
* </tr>
* </table>
*/
#endif

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/**
* \file
*
* \brief SAM GPIO Port Driver Quick Start
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
*
* In this use case, the PORT module is configured for:
* \li One pin in input mode, with pull-up enabled
* \li One pin in output mode
*
* This use case sets up the PORT to read the current state of a GPIO pin set as
* an input, and mirrors the opposite logical state on a pin configured as an
* output.
*
* \section asfdoc_sam0_port_basic_use_case_setup Setup
*
* \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
* Copy-paste the following setup code to your user application:
* \snippet qs_port_basic.c setup
*
* Add to user application initialization (typically the start of \c main()):
* \snippet qs_port_basic.c setup_init
*
* \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
* -# Create a PORT module pin configuration struct, which can be filled out to
* adjust the configuration of a single port pin.
* \snippet qs_port_basic.c setup_1
* -# Initialize the pin configuration struct with the module's default values.
* \snippet qs_port_basic.c setup_2
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Adjust the configuration struct to request an input pin.
* \snippet qs_port_basic.c setup_3
* -# Configure push button pin with the initialized pin configuration struct, to enable
* the input sampler on the pin.
* \snippet qs_port_basic.c setup_4
* -# Adjust the configuration struct to request an output pin.
* \snippet qs_port_basic.c setup_5
* \note The existing configuration struct may be re-used, as long as any
* values that have been altered from the default settings are taken
* into account by the user application.
*
* -# Configure LED pin with the initialized pin configuration struct, to enable
* the output driver on the pin.
* \snippet qs_port_basic.c setup_6
*
* \section asfdoc_sam0_port_basic_use_case_use_main Use Case
*
* \subsection asfdoc_sam0_port_basic_use_case_code Code
* Copy-paste the following code to your user application:
* \snippet qs_port_basic.c main
*
* \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
* -# Read in the current input sampler state of push button pin, which has been
* configured as an input in the use-case setup code.
* \snippet qs_port_basic.c main_1
* -# Write the inverted pin level state to LED pin, which has been configured as
* an output in the use-case setup code.
* \snippet qs_port_basic.c main_2
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/

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/**
* \file
*
* \brief SAM SERCOM I2C Common Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef I2C_COMMON_H_INCLUDED
#define I2C_COMMON_H_INCLUDED
#include <compiler.h>
#include <sercom.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \if (I2C_MASTER_MODE && I2C_SLAVE_MODE)
* \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C (SERCOM I2C) Driver
* \elseif I2C_MASTER_MODE
* \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Master Mode (SERCOM I2C) Driver
* \elseif I2C_SLAVE_MODE
* \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Slave Mode (SERCOM I2C) Driver
* \endif
*
* This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
* an interface for the configuration and management of the device's SERCOM
* I<SUP>2</SUP>C module, for the transfer of data via an I<SUP>2</SUP>C bus.
* The following driver API modes are covered by this manual:
*
* \if I2C_MASTER_MODE
* - Master Mode Polled APIs
* \endif
* \if I2C_MASTER_CALLBACK_MODE
* - Master Mode Callback APIs
* \endif
* \if I2C_SLAVE_MODE
* - Slave Mode Polled APIs
* \endif
* \if I2C_SLAVE_CALLBACK_MODE
* - Slave Mode Callback APIs
* \endif
*
* The following peripheral is used by this module:
* - SERCOM (Serial Communication Interface)
*
* The following devices can use this module:
* - Atmel | SMART SAM D20/D21
* - Atmel | SMART SAM R21
* - Atmel | SMART SAM D09/D10/D11
* - Atmel | SMART SAM L21/L22
* - Atmel | SMART SAM DA1
* - Atmel | SMART SAM C20/C21
* - Atmel | SMART SAM HA1
* - Atmel | SMART SAM R30
* - Atmel | SMART SAM R34
* - Atmel | SMART SAM R35
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_sercom_i2c_prerequisites
* - \ref asfdoc_sam0_sercom_i2c_overview
* - \ref asfdoc_sam0_sercom_i2c_special_considerations
* - \ref asfdoc_sam0_sercom_i2c_extra
* - \ref asfdoc_sam0_sercom_i2c_examples
* - \ref asfdoc_sam0_sercom_i2c_api_overview
*
* \section asfdoc_sam0_sercom_i2c_prerequisites Prerequisites
* There are no prerequisites.
*
* \section asfdoc_sam0_sercom_i2c_overview Module Overview
* The outline of this section is as follows:
* - \ref asfdoc_sam0_sercom_i2c_module_features
* - \ref asfdoc_sam0_sercom_i2c_functional_desc
* - \ref asfdoc_sam0_sercom_i2c_bus_topology
* - \ref asfdoc_sam0_sercom_i2c_transactions
* - \ref asfdoc_sam0_sercom_i2c_multi_master
* - \ref asfdoc_sam0_sercom_i2c_bus_states
* - \ref asfdoc_sam0_sercom_i2c_timeout
* - \ref asfdoc_sam0_sercom_i2c_sleep_modes
*
* \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition
* <table>
* <tr>
* <th>Driver Feature Macro</th>
* <th>Supported devices</th>
* </tr>
* <tr>
* <td>FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED</td>
* <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
* </tr>
* <tr>
* <td>FEATURE_I2C_10_BIT_ADDRESS</td>
* <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
* </tr>
* <tr>
* <td>FEATURE_I2C_SCL_STRETCH_MODE</td>
* <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
* </tr>
* <tr>
* <td>FEATURE_I2C_SCL_EXTEND_TIMEOUT</td>
* <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
* </tr>
* </table>
* \note The specific features are only available in the driver when the selected
* device supports those features.
* \note When using the I2C high-speed mode for off-board communication,
* there are various high frequency interference, which can lead to distortion of the signals
* and communication failure. When using Xplained Pro boards in order to test I2C high-speed
* communication, the following recommendation should be followed:
* - Use the SDA-line on PA08 and SCL-line on PA09 for both boards. This will provide stronger
* pull-ups on both SDA and SCL.
* - The SCL should not be higher than 1.5MHz.
*
* \subsection asfdoc_sam0_sercom_i2c_functional_desc Functional Description
* The I<SUP>2</SUP>C provides a simple two-wire bidirectional bus consisting of a
* wired-AND type serial clock line (SCL) and a wired-AND type serial data line
* (SDA).
*
* The I<SUP>2</SUP>C bus provides a simple, but efficient method of interconnecting
* multiple master and slave devices. An arbitration mechanism is provided for
* resolving bus ownership between masters, as only one master device may own
* the bus at any given time. The arbitration mechanism relies on the wired-AND
* connections to avoid bus drivers short-circuiting.
*
* A unique address is assigned to all slave devices connected to the bus. A
* device can contain both master and slave logic, and can emulate multiple
* slave devices by responding to more than one address.
*
* \subsection asfdoc_sam0_sercom_i2c_bus_topology Bus Topology
* The I<SUP>2</SUP>C bus topology is illustrated in
* \ref asfdoc_sam0_sercom_i2c_bus_topology_figure "the figure below". The pull-up
* resistors (Rs) will provide a high level on the bus lines when none of the
* I<SUP>2</SUP>C devices are driving the bus. These are optional, and can be
* replaced with a constant current source.
*
* \anchor asfdoc_sam0_sercom_i2c_bus_topology_figure
* \image html bus_topology.svg "I2C Bus Topology" Width=100%
*
* \subsection asfdoc_sam0_sercom_i2c_transactions Transactions
* The I<SUP>2</SUP>C standard defines three fundamental transaction formats:
* - Master Write
* - The master transmits data packets to the slave after addressing it
* - Master Read
* - The slave transmits data packets to the master after being addressed
* - Combined Read/Write
* - A combined transaction consists of several write and read transactions
*
* A data transfer starts with the master issuing a \b Start condition on the
* bus, followed by the address of the slave together with a bit to indicate
* whether the master wants to read from or write to the slave.
* The addressed slave must respond to this by sending an \b ACK back to the
* master.
*
* After this, data packets are sent from the master or slave, according to the
* read/write bit. Each packet must be acknowledged (ACK) or not
* acknowledged (NACK) by the receiver.
*
* If a slave responds with a NACK, the master must assume that the slave
* cannot receive any more data and cancel the write operation.
*
* The master completes a transaction by issuing a \b Stop condition.
*
* A master can issue multiple \b Start conditions during a transaction; this
* is then called a \b Repeated \b Start condition.
*
* \subsubsection asfdoc_sam0_sercom_i2c_address_packets Address Packets
* The slave address consists of seven bits. The 8<SUP>th</SUP> bit in the transfer
* determines the data direction (read or write). An address packet always
* succeeds a \b Start or \b Repeated \b Start condition. The 8<SUP>th</SUP> bit is handled
* in the driver, and the user will only have to provide the 7-bit address.
*
* \subsubsection asfdoc_sam0_sercom_i2c_data_packets Data Packets
* Data packets are nine bits long, consisting of one 8-bit data byte, and an
* acknowledgement bit. Data packets follow either an address packet or another
* data packet on the bus.
*
* \subsubsection asfdoc_sam0_sercom_i2c_trans_examples Transaction Examples
* The gray bits in the following examples are sent from master to slave, and
* the white bits are sent from slave to master.
* Example of a read transaction is shown in
* \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_read "the figure below". Here, the
* master first issues a \b Start condition and gets ownership of the bus. An
* address packet with the direction flag set to read is then sent and
* acknowledged by the slave. Then the slave sends one data packet which is
* acknowledged by the master. The slave sends another packet, which is not
* acknowledged by the master and indicates that the master will terminate the
* transaction. In the end, the transaction is terminated by the master issuing
* a \b Stop condition.
*
* \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_read
* \image html i2c_read.svg "I2C Packet Read" Width=100%
*
* Example of a write transaction is shown in
* \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_write "the figure below". Here, the
* master first issues a \b Start condition and gets ownership of the bus. An
* address packet with the dir flag set to write is then sent and acknowledged
* by the slave. Then the master sends two data packets, each acknowledged by
* the slave. In the end, the transaction is terminated by the master issuing
* a \b Stop condition.
*
* \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_write
* \image html i2c_write.svg "I2C Packet Write" Width=100%
*
* \subsubsection asfdoc_sam0_sercom_i2c_packet_timeout Packet Timeout
* When a master sends an I<SUP>2</SUP>C packet, there is no way of
* being sure that a slave will acknowledge the packet. To avoid stalling the
* device forever while waiting for an acknowledge, a user selectable timeout
* is provided in the \ref i2c_master_config struct which
* lets the driver exit a read or write operation after the specified time.
* The function will then return the STATUS_ERR_TIMEOUT flag.
*
* This is also the case for the slave when using the functions postfixed
* \c _wait.
*
* The time before the timeout occurs, will be the same as
* for \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "unknown bus state" timeout.
*
* \subsubsection asfdoc_sam0_sercom_i2c_repeated_start Repeated Start
* To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be
* used.
* These functions will not send a \b Stop condition when the transfer is done,
* thus the next transfer will start with a \b Repeated \b Start. To end the
* transaction, the functions without the \c _no_stop postfix must be used
* for the last read/write.
*
* \subsection asfdoc_sam0_sercom_i2c_multi_master Multi Master
* In a multi master environment, arbitration of the bus is important, as only
* one master can own the bus at any point.
*
* \subsubsection asfdoc_sam0_sercom_i2c_arbitration Arbitration
*
* \par Clock stretching
* The serial clock line is always driven by a master device. However, all
* devices connected to the bus are allowed stretch the low period of the clock
* to slow down the overall clock frequency or to insert wait states while
* processing data.
* Both master and slave can randomly stretch the clock, which will force the
* other device into a wait-state until the clock line goes high again.
*
* \par Arbitration on the data line
* If two masters start transmitting at the same time, they will both transmit
* until one master detects that the other master is pulling the data line low.
* When this is detected, the master not pulling the line low, will stop the
* transmission and wait until the bus is idle.
* As it is the master trying to contact the slave with the lowest address that
* will get the bus ownership, this will create an arbitration scheme always
* prioritizing the slaves with the lowest address in case of a bus collision.
*
* \subsubsection asfdoc_sam0_sercom_i2c_clock_sync Clock Synchronization
* In situations where more than one master is trying to control the bus clock
* line at the same time, a clock synchronization algorithm based on the same
* principles used for clock stretching is necessary.
*
*
* \subsection asfdoc_sam0_sercom_i2c_bus_states Bus States
* As the I<SUP>2</SUP>C bus is limited to one transaction at the time,
* a master that wants to perform a bus transaction must wait until the bus is
* free.
* Because of this, it is necessary for all masters in a multi-master system to
* know the current status of the bus to be able to avoid conflicts and to
* ensure data integrity.
* \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start
* condition)
* \li \b OWNER If the master initiates a transaction successfully
* \li \b BUSY If another master is driving the bus
* \li \b UNKNOWN If the master has recently been enabled or connected to
* the bus. Is forced to \b IDLE after given
* \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" when
* the master module is enabled
*
* The bus state diagram can be seen in
* \ref asfdoc_sam0_sercom_i2c_bus_states_figure "the figure below".
* \li S: Start condition
* \li P: Stop condition
* \li Sr: Repeated start condition
* \anchor asfdoc_sam0_sercom_i2c_bus_states_figure
* \image html bus_state_diagram.svg "I2C Bus State Diagram" Width=100%
*
* \subsection asfdoc_sam0_sercom_i2c_timeout Bus Timing
* Inactive bus timeout for the master and SDA hold time is configurable in the
* drivers.
*
* \subsubsection asfdoc_sam0_sercom_i2c_unknown_bus_timeout Unknown Bus State Timeout
* When a master is enabled or connected to the bus, the bus state will be
* unknown until either a given timeout or a stop command has occurred. The
* timeout is configurable in the \ref i2c_master_config struct.
* The timeout time will depend on toolchain and optimization level used, as
* the timeout is a loop incrementing a value until it reaches the specified
* timeout value.
*
* \subsubsection sda_hold SDA Hold Timeout
* When using the I<SUP>2</SUP>C in slave mode, it will be important to
* set a SDA hold time which assures that the master will be able to pick up
* the bit sent from the slave. The SDA hold time makes sure that this is the
* case by holding the data line low for a given period after the negative edge
* on the clock.
*
* The SDA hold time is also available for the master driver, but is not a
* necessity.
*
* \subsection asfdoc_sam0_sercom_i2c_sleep_modes Operation in Sleep Modes
* The I<SUP>2</SUP>C module can operate in all sleep modes by setting
* the run_in_standby Boolean in the \ref i2c_master_config or
* \ref i2c_slave_config struct.
* The operation in slave and master mode is shown in
* \ref asfdoc_sam0_sercom_i2c_sleep_modes_table "the table below".
*
* \anchor asfdoc_sam0_sercom_i2c_sleep_modes_table
* <table>
* <caption>I2C Standby Operations</caption>
* <tr>
* <th>Run in standby</th>
* <th>Slave</th>
* <th>Master</th>
* </tr>
* <tr>
* <td>false</td>
* <td>Disabled, all reception is dropped</td>
* <td>Generic Clock (GCLK) disabled when master is idle</td>
* </tr>
* <tr>
* <td>true</td>
* <td>Wake on address match when enabled</td>
* <td>GCLK enabled while in sleep modes</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_sercom_i2c_special_considerations Special Considerations
*
* \if (I2C_MASTER_CALLBACK_MODE || I2C_SLAVE_CALLBACK_MODE)
* \subsection asfdoc_sam0_sercom_i2c_common_interrupt Interrupt-driven Operation
* While an interrupt-driven operation is in progress, subsequent calls to a
* write or read operation will return the STATUS_BUSY flag, indicating that
* only one operation is allowed at any given time.
*
* To check if another transmission can be initiated, the user can either call
* another transfer operation, or use the
* \ref i2c_master_get_job_status/\ref i2c_slave_get_job_status functions
* depending on mode.
*
* If the user would like to get callback from operations while using the
* interrupt-driven driver, the callback must be registered and then enabled
* using the "register_callback" and "enable_callback" functions.
* \else
* There are no special considerations for this driver for the APIs listed in
* this document.
* \endif
*
* \section asfdoc_sam0_sercom_i2c_extra Extra Information
* For extra information, see \ref asfdoc_sam0_sercom_i2c_extra_info_page.
* This includes:
* - \ref asfdoc_sam0_sercom_i2c_acronyms
* - \ref asfdoc_sam0_sercom_i2c_extra_dependencies
* - \ref asfdoc_sam0_sercom_i2c_extra_errata
* - \ref asfdoc_sam0_sercom_i2c_extra_history
*
* \section asfdoc_sam0_sercom_i2c_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_sercom_i2c_exqsg.
*
* \section asfdoc_sam0_sercom_i2c_api_overview API Overview
* @{
*/
/**
* \name Driver Feature Definition
* Define SERCOM I<SUP>2</SUP>C driver features set according to different device family.
*
* @{
*/
#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || (SAMDA1) || \
(SAMHA1) || (SAMHA0) || (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
/** Fast mode plus and high speed support. */
# define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
/** 10-bit address support */
# define FEATURE_I2C_10_BIT_ADDRESS
/** SCL stretch mode support */
# define FEATURE_I2C_SCL_STRETCH_MODE
/** SCL extend timeout support */
# define FEATURE_I2C_SCL_EXTEND_TIMEOUT
# define FEATURE_I2C_DMA_SUPPORT
#endif
/*@}*/
/** \brief Transfer direction
*
* For master: transfer direction or setting direction bit in address.
* For slave: direction of request from master.
*/
enum i2c_transfer_direction {
/** Master write operation is in progress */
I2C_TRANSFER_WRITE = 0,
/** Master read operation is in progress */
I2C_TRANSFER_READ = 1,
};
/** @} */
#ifdef __cplusplus
}
#endif
/**
* \page asfdoc_sam0_sercom_i2c_extra_info_page Extra Information for SERCOM I2C Driver
*
* \section asfdoc_sam0_sercom_i2c_acronyms Acronyms
* \ref asfdoc_sam0_sercom_i2c_acronyms_table "Below" is a table listing the acronyms
* used in this module, along with their intended meanings.
*
* \anchor asfdoc_sam0_sercom_i2c_acronyms_table
* <table>
* <caption>Acronyms</caption>
* <tr>
* <th>Acronym</th>
* <th>Description</th>
* </tr>
* <tr>
* <td>SDA</td>
* <td>Serial Data Line</td>
* </tr>
* <tr>
* <td>SCL</td>
* <td>Serial Clock Line</td>
* </tr>
* <tr>
* <td>SERCOM</td>
* <td>Serial Communication Interface</td>
* </tr>
* <tr>
* <td>DMA</td>
* <td>Direct Memory Access</td>
* </tr>
* </table>
*
* \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies
* The I<SUP>2</SUP>C driver has the following dependencies:
* \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
*
*
* \section asfdoc_sam0_sercom_i2c_extra_errata Errata
* There are no errata related to this driver.
*
* \section asfdoc_sam0_sercom_i2c_extra_history Module History
* \ref asfdoc_sam0_sercom_i2c_extra_history_table "Below" is an overview of the
* module history, detailing enhancements and fixes made to the module since
* its first release. The current version of this corresponds to the newest
* version listed in
* \ref asfdoc_sam0_sercom_i2c_extra_history_table "the table below".
*
* \anchor asfdoc_sam0_sercom_i2c_extra_history_table
* <table>
* <caption>Module History</caption>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>
* \li Added 10-bit addressing and high speed support in SAM D21
* \li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet
* </td>
* </tr>
* <tr>
* <td>
* \li Added support for SCL stretch and extended timeout hardware features in SAM D21
* \li Added fast mode plus support in SAM D21
* </td>
* </tr>
* <tr>
* <td>Fixed incorrect logical mask for determining if a bus error has
* occurred in I<SUP>2</SUP>C Slave mode
* </td>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_sercom_i2c_exqsg Examples for SERCOM I2C Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that a QSG can be compiled as a standalone application or be
* added to the user application.
*
* \if I2C_MASTER_MODE
* - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case"
* \endif
* \if I2C_MASTER_CALLBACK_MODE
* - \subpage asfdoc_sam0_sercom_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case"
* - \subpage asfdoc_sam0_sercom_i2c_master_dma_use_case "Quick Start Guide for the I2C Master module - DMA Use Case"
* \endif
* \if I2C_SLAVE_MODE
* - \subpage asfdoc_sam0_sercom_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case"
* \endif
* \if I2C_SLAVE_CALLBACK_MODE
* - \subpage asfdoc_sam0_sercom_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case"
* - \subpage asfdoc_sam0_sercom_i2c_slave_dma_use_case "Quick Start Guide for the I2C Slave module - DMA Use Case"
* \endif
*
* \page asfdoc_sam0_sercom_i2c_document_revision_history Document Revision History
*
* \if (I2C_MASTER_MODE || I2C_MASTER_CALLBACK_MODE)
* <table>
* <tr>
* <th>Doc. Rev.</th>
* <th>Date</th>
* <th>Comments</th>
* </tr>
* <tr>
* <td>42117E</td>
* <td>12/2015</td>
* <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
* </tr>
* <tr>
* <td>42117D</td>
* <td>12/2014</td>
* <td>Added support for 10-bit addressing and high speed in SAM D21.
* Added support for SAM R21 and SAM D10/D11.</td>
* </tr>
* <tr>
* <td>42117C</td>
* <td>01/2014</td>
* <td>Added support for SAM D21</td>
* </tr>
* <tr>
* <td>42117B</td>
* <td>06/2013</td>
* <td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
* </tr>
* <tr>
* <td>42117A</td>
* <td>06/2013</td>
* <td>Initial release</td>
* </tr>
* </table>
* \else
* <table>
* <tr>
* <th>Doc. Rev.</th>
* <th>Date</th>
* <th>Comments</th>
* </tr>
* <tr>
* <td>42116E</td>
* <td>12/2015</td>
* <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
* </tr>
* <tr>
* <td>42116D</td>
* <td>12/2014</td>
* <td>Added support for 10-bit addressing and high speed in SAM D21.
* Added support for SAM R21 and SAM D10/D11.</td>
* </tr>
* <tr>
* <td>42116C</td>
* <td>01/2014</td>
* <td>Added support for SAM D21</td>
* </tr>
* <tr>
* <td>42116B</td>
* <td>06/2013</td>
* <td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
* </tr>
* <tr>
* <td>42116A</td>
* <td>06/2013</td>
* <td>Initial release</td>
* </tr>
* </table>
*\endif
*/
#endif /* I2C_COMMON_H_INCLUDED */

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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21/src/ASF/sam0/drivers/sercom/i2c/i2c_master.h
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/**
* \file
*
* \brief SAM SERCOM I2C Master Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef I2C_MASTER_H_INCLUDED
#define I2C_MASTER_H_INCLUDED
#include "i2c_common.h"
#include <sercom.h>
#include <pinmux.h>
#if I2C_MASTER_CALLBACK_MODE == true
# include <sercom_interrupt.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef PINMUX_DEFAULT
# define PINMUX_DEFAULT 0
#endif
/**
* \addtogroup asfdoc_sam0_sercom_i2c_group
*
* @{
*/
/**
* \brief I<SUP>2</SUP>C master packet for read/write
*
* Structure to be used when transferring I<SUP>2</SUP>C master packets.
*/
struct i2c_master_packet {
/** Address to slave device */
uint16_t address;
/** Length of data array */
uint16_t data_length;
/** Data array containing all data to be transferred */
uint8_t *data;
/** Use 10-bit addressing. Set to false if the feature is not supported by the device */
bool ten_bit_address;
/** Use high speed transfer. Set to false if the feature is not supported by the device */
bool high_speed;
/** High speed mode master code (0000 1XXX), valid when high_speed is true */
uint8_t hs_master_code;
};
/** \brief Interrupt flags
*
* Flags used when reading or setting interrupt flags.
*/
enum i2c_master_interrupt_flag {
/** Interrupt flag used for write */
I2C_MASTER_INTERRUPT_WRITE = 0,
/** Interrupt flag used for read */
I2C_MASTER_INTERRUPT_READ = 1,
};
/**
* \brief Values for hold time after start bit.
*
* Values for the possible I<SUP>2</SUP>C master mode SDA internal hold times after start
* bit has been sent.
*/
enum i2c_master_start_hold_time {
/** Internal SDA hold time disabled */
I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0),
/** Internal SDA hold time 50ns - 100ns */
I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1),
/** Internal SDA hold time 300ns - 600ns */
I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2),
/** Internal SDA hold time 400ns - 800ns */
I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3),
};
/**
* \brief Values for inactive bus time-out.
*
* If the inactive bus time-out is enabled and the bus is inactive for
* longer than the time-out setting, the bus state logic will be set to idle.
*/
enum i2c_master_inactive_timeout {
/** Inactive bus time-out disabled */
I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0),
/** Inactive bus time-out 5-6 SCL cycle time-out */
I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1),
/** Inactive bus time-out 10-11 SCL cycle time-out */
I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2),
/** Inactive bus time-out 20-21 SCL cycle time-out */
I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3),
};
/**
* \brief I<SUP>2</SUP>C frequencies
*
* Values for I<SUP>2</SUP>C speeds supported by the module. The driver
* will also support setting any other value, in which case set
* the value in the \ref i2c_master_config at desired value divided by 1000.
*
* Example: If 10KHz operation is required, give baud_rate in the configuration
* structure the value 10.
*/
enum i2c_master_baud_rate {
/** Baud rate at 100KHz (Standard-mode) */
I2C_MASTER_BAUD_RATE_100KHZ = 100,
/** Baud rate at 400KHz (Fast-mode) */
I2C_MASTER_BAUD_RATE_400KHZ = 400,
#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
/** Baud rate at 1MHz (Fast-mode Plus) */
I2C_MASTER_BAUD_RATE_1000KHZ = 1000,
/** Baud rate at 3.4MHz (High-speed mode) */
I2C_MASTER_BAUD_RATE_3400KHZ = 3400,
#endif
};
#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
/**
* \brief Enum for the transfer speed
*
* Enum for the transfer speed.
*/
enum i2c_master_transfer_speed {
/** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0),
/** Fast-mode Plus (Fm+) up to 1MHz */
I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1),
/** High-speed mode (Hs-mode) up to 3.4MHz */
I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2),
};
#endif
#if I2C_MASTER_CALLBACK_MODE == true
/**
* \brief Callback types
*
* The available callback types for the I<SUP>2</SUP>C master module.
*/
enum i2c_master_callback {
/** Callback for packet write complete */
I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
/** Callback for packet read complete */
I2C_MASTER_CALLBACK_READ_COMPLETE = 1,
/** Callback for error */
I2C_MASTER_CALLBACK_ERROR = 2,
# if !defined(__DOXYGEN__)
/** Total number of callbacks */
_I2C_MASTER_CALLBACK_N = 3,
# endif
};
# if !defined(__DOXYGEN__)
/* Prototype for software module */
struct i2c_master_module;
typedef void (*i2c_master_callback_t)(
struct i2c_master_module *const module);
# endif
#endif
/**
* \brief SERCOM I<SUP>2</SUP>C Master driver software device instance structure.
*
* SERCOM I<SUP>2</SUP>C Master driver software instance structure, used to
* retain software state information of an associated hardware module instance.
*
* \note The fields of this structure should not be altered by the user
* application; they are reserved for module-internal use only.
*/
struct i2c_master_module {
#if !defined(__DOXYGEN__)
/** Hardware instance initialized for the struct */
Sercom *hw;
/** Module lock */
volatile bool locked;
/** Unknown bus state timeout */
uint16_t unknown_bus_state_timeout;
/** Buffer write timeout value */
uint16_t buffer_timeout;
/** If true, stop condition will be sent after a read/write */
bool send_stop;
/** If true, nack signal will be sent after a read/write */
bool send_nack;
# if I2C_MASTER_CALLBACK_MODE == true
/** Pointers to callback functions */
volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
/** Mask for registered callbacks */
volatile uint8_t registered_callback;
/** Mask for enabled callbacks */
volatile uint8_t enabled_callback;
/** The total number of bytes to transfer */
volatile uint16_t buffer_length;
/**
* Counter used for bytes left to send in write and to count number of
* obtained bytes in read
*/
volatile uint16_t buffer_remaining;
/** Data buffer for packet write and read */
volatile uint8_t *buffer;
/** Save direction of async request. 1 = read, 0 = write */
volatile enum i2c_transfer_direction transfer_direction;
/** Status for status read back in error callback */
volatile enum status_code status;
# endif
#endif
};
/**
* \brief Configuration structure for the I<SUP>2</SUP>C Master device
*
* This is the configuration structure for the I<SUP>2</SUP>C Master device. It
* is used as an argument for \ref i2c_master_init to provide the desired
* configurations for the module. The structure should be initialized using the
* \ref i2c_master_get_config_defaults.
*/
struct i2c_master_config {
/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
* standard-mode, Fast-mode, and Fast-mode Plus Transfers,
* \ref i2c_master_baud_rate */
uint32_t baud_rate;
#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
* High-speed mode, \ref i2c_master_baud_rate */
uint32_t baud_rate_high_speed;
/** Transfer speed mode */
enum i2c_master_transfer_speed transfer_speed;
#endif
/** GCLK generator to use as clock source */
enum gclk_generator generator_source;
/** Bus hold time after start signal on data line */
enum i2c_master_start_hold_time start_hold_time;
/** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" */
uint16_t unknown_bus_state_timeout;
/** Timeout for packet write to wait for slave */
uint16_t buffer_timeout;
/** Set to keep module active in sleep modes */
bool run_in_standby;
/** PAD0 (SDA) pinmux */
uint32_t pinmux_pad0;
/** PAD1 (SCL) pinmux */
uint32_t pinmux_pad1;
/** Set to enable SCL low time-out */
bool scl_low_timeout;
/** Inactive bus time out */
enum i2c_master_inactive_timeout inactive_timeout;
#ifdef FEATURE_I2C_SCL_STRETCH_MODE
/** Set to enable SCL stretch only after ACK bit (required for high speed) */
bool scl_stretch_only_after_ack_bit;
#endif
#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
/** Set to enable slave SCL low extend time-out */
bool slave_scl_low_extend_timeout;
/** Set to enable maser SCL low extend time-out */
bool master_scl_low_extend_timeout;
#endif
/** Get more accurate BAUD, considering rise time(required for standard-mode and Fast-mode) */
uint16_t sda_scl_rise_time_ns;
};
/**
* \name Lock/Unlock
* @{
*/
/**
* \brief Attempt to get lock on driver instance
*
* This function checks the instance's lock, which indicates whether or not it
* is currently in use, and sets the lock if it was not already set.
*
* The purpose of this is to enable exclusive access to driver instances, so
* that, e.g., transactions by different services will not interfere with each
* other.
*
* \param[in,out] module Pointer to the driver instance to lock
*
* \retval STATUS_OK If the module was locked
* \retval STATUS_BUSY If the module was already locked
*/
static inline enum status_code i2c_master_lock(
struct i2c_master_module *const module)
{
enum status_code status;
system_interrupt_enter_critical_section();
if (module->locked) {
status = STATUS_BUSY;
} else {
module->locked = true;
status = STATUS_OK;
}
system_interrupt_leave_critical_section();
return status;
}
/**
* \brief Unlock driver instance
*
* This function clears the instance lock, indicating that it is available for
* use.
*
* \param[in,out] module Pointer to the driver instance to lock
*
* \retval STATUS_OK If the module was locked
* \retval STATUS_BUSY If the module was already locked
*/
static inline void i2c_master_unlock(struct i2c_master_module *const module)
{
module->locked = false;
}
/** @} */
/**
* \name Configuration and Initialization
* @{
*/
/**
* \brief Returns the synchronization status of the module
*
* Returns the synchronization status of the module.
*
* \param[in] module Pointer to software module structure
*
* \return Status of the synchronization.
* \retval true Module is busy synchronizing
* \retval false Module is not synchronizing
*/
static inline bool i2c_master_is_syncing (
const struct i2c_master_module *const module)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_hw = &(module->hw->I2CM);
#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY);
#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
#else
# error Unknown SERCOM SYNCBUSY scheme!
#endif
}
#if !defined(__DOXYGEN__)
/**
* \internal
* Wait for hardware module to sync
*
* \param[in] module Pointer to software module structure
*/
static void _i2c_master_wait_for_sync(
const struct i2c_master_module *const module)
{
/* Sanity check */
Assert(module);
while (i2c_master_is_syncing(module)) {
/* Wait for I2C module to sync. */
}
}
#endif
/**
* \brief Gets the I<SUP>2</SUP>C master default configurations
*
* Use to initialize the configuration structure to known default values.
*
* The default configuration is as follows:
* - Baudrate 100KHz
* - GCLK generator 0
* - Do not run in standby
* - Start bit hold time 300ns - 600ns
* - Buffer timeout = 65535
* - Unknown bus status timeout = 65535
* - Do not run in standby
* - PINMUX_DEFAULT for SERCOM pads
*
* Those default configuration only available if the device supports it:
* - High speed baudrate 3.4MHz
* - Standard-mode and Fast-mode transfer speed
* - SCL stretch disabled
* - Slave SCL low extend time-out disabled
* - Master SCL low extend time-out disabled
*
* \param[out] config Pointer to configuration structure to be initiated
*/
static inline void i2c_master_get_config_defaults(
struct i2c_master_config *const config)
{
/*Sanity check argument */
Assert(config);
config->baud_rate = I2C_MASTER_BAUD_RATE_100KHZ;
#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
config->transfer_speed = I2C_MASTER_SPEED_STANDARD_AND_FAST;
#endif
config->generator_source = GCLK_GENERATOR_0;
config->run_in_standby = false;
config->start_hold_time = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
config->buffer_timeout = 65535;
config->unknown_bus_state_timeout = 65535;
config->pinmux_pad0 = PINMUX_DEFAULT;
config->pinmux_pad1 = PINMUX_DEFAULT;
config->scl_low_timeout = false;
config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
#ifdef FEATURE_I2C_SCL_STRETCH_MODE
config->scl_stretch_only_after_ack_bit = false;
#endif
#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
config->slave_scl_low_extend_timeout = false;
config->master_scl_low_extend_timeout = false;
#endif
/* The typical value is 215ns */
config->sda_scl_rise_time_ns = 215;
}
enum status_code i2c_master_init(
struct i2c_master_module *const module,
Sercom *const hw,
const struct i2c_master_config *const config);
/**
* \brief Enables the I<SUP>2</SUP>C module
*
* Enables the requested I<SUP>2</SUP>C module and set the bus state to IDLE
* after the specified \ref asfdoc_sam0_sercom_i2c_timeout "timeout" period if no
* stop bit is detected.
*
* \param[in] module Pointer to the software module struct
*/
static inline void i2c_master_enable(
const struct i2c_master_module *const module)
{
/* Sanity check of arguments */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
/* Timeout counter used to force bus state */
uint32_t timeout_counter = 0;
/* Wait for module to sync */
_i2c_master_wait_for_sync(module);
/* Enable module */
i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
#if I2C_MASTER_CALLBACK_MODE == true
/* Enable module interrupts */
system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
#endif
/* Start timeout if bus state is unknown */
while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
timeout_counter++;
if(timeout_counter >= (module->unknown_bus_state_timeout)) {
/* Timeout, force bus state to idle */
i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1);
/* Workaround #1 */
return;
}
}
}
/**
* \brief Disable the I<SUP>2</SUP>C module
*
* Disables the requested I<SUP>2</SUP>C module.
*
* \param[in] module Pointer to the software module struct
*/
static inline void i2c_master_disable(
const struct i2c_master_module *const module)
{
/* Sanity check of arguments */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
#if I2C_MASTER_CALLBACK_MODE == true
/* Disable module interrupts */
system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
#endif
/* Wait for module to sync */
_i2c_master_wait_for_sync(module);
/* Disbale interrupt */
i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
/* Clear interrupt flag */
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MASK;
/* Disable module */
i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
}
void i2c_master_reset(struct i2c_master_module *const module);
/** @} */
/**
* \name Read and Write
* @{
*/
enum status_code i2c_master_read_packet_wait(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_read_packet_wait_no_stop(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_write_packet_wait(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_write_packet_wait_no_stop(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
void i2c_master_send_stop(struct i2c_master_module *const module);
void i2c_master_send_nack(struct i2c_master_module *const module);
enum status_code i2c_master_read_byte(
struct i2c_master_module *const module,
uint8_t *byte);
enum status_code i2c_master_write_byte(
struct i2c_master_module *const module,
uint8_t byte);
enum status_code i2c_master_read_packet_wait_no_nack(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
/** @} */
#ifdef FEATURE_I2C_DMA_SUPPORT
/**
* \name SERCOM I2C Master with DMA Interfaces
* @{
*/
/**
* \brief Set I<SUP>2</SUP>C for DMA transfer with slave address and transfer size.
*
* This function will set the slave address, transfer size and enable the auto transfer
* mode for DMA.
*
* \param[in,out] module Pointer to the driver instance to lock
* \param[in] addr I<SUP>2</SUP>C slave address
* \param[in] length I<SUP>2</SUP>C transfer length with DMA
* \param[in] direction I<SUP>2</SUP>C transfer direction
*
*/
static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module,
uint16_t addr, uint8_t length, enum i2c_transfer_direction direction)
{
module->hw->I2CM.ADDR.reg =
SERCOM_I2CM_ADDR_ADDR(addr<<1) |
SERCOM_I2CM_ADDR_LENEN |
SERCOM_I2CM_ADDR_LEN(length) |
direction;
}
/** @} */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* I2C_MASTER_H_INCLUDED */

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/**
* \file
*
* \brief SAM SERCOM I2C Master Interrupt Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef I2C_MASTER_INTERRUPT_H_INCLUDED
#define I2C_MASTER_INTERRUPT_H_INCLUDED
#include "i2c_master.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup asfdoc_sam0_sercom_i2c_group
* @{
*
*/
/**
* \name Callbacks
* @{
*/
#if !defined(__DOXYGEN__)
void _i2c_master_interrupt_handler(
uint8_t instance);
#endif
void i2c_master_register_callback(
struct i2c_master_module *const module,
i2c_master_callback_t callback,
enum i2c_master_callback callback_type);
void i2c_master_unregister_callback(
struct i2c_master_module *const module,
enum i2c_master_callback callback_type);
/**
* \brief Enables callback
*
* Enables the callback specified by the callback_type.
*
* \param[in,out] module Pointer to the software module struct
* \param[in] callback_type Callback type to enable
*/
static inline void i2c_master_enable_callback(
struct i2c_master_module *const module,
enum i2c_master_callback callback_type)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
/* Mark callback as enabled */
module->enabled_callback |= (1 << callback_type);
}
/**
* \brief Disables callback
*
* Disables the callback specified by the callback_type.
*
* \param[in,out] module Pointer to the software module struct
* \param[in] callback_type Callback type to disable
*/
static inline void i2c_master_disable_callback(
struct i2c_master_module *const module,
enum i2c_master_callback callback_type)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
/* Mark callback as disabled */
module->enabled_callback &= ~(1 << callback_type);
}
/** @} */
/**
* \name Read and Write, Interrupt-driven
* @{
*/
enum status_code i2c_master_read_bytes(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_read_packet_job(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_read_packet_job_no_stop(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_read_packet_job_no_nack(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_write_bytes(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_write_packet_job(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
enum status_code i2c_master_write_packet_job_no_stop(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet);
/**
* \brief Cancel any currently ongoing operation
*
* Terminates the running transfer operation.
*
* \param[in,out] module Pointer to software module structure
*/
static inline void i2c_master_cancel_job(
struct i2c_master_module *const module)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
/* Set buffer to 0 */
module->buffer_remaining = 0;
/* Update status */
module->status = STATUS_ABORTED;
}
/**
* \brief Get status from ongoing job
*
* Will return the status of a transfer operation.
*
* \param[in] module Pointer to software module structure
*
* \return Last status code from transfer operation.
* \retval STATUS_OK No error has occurred
* \retval STATUS_BUSY If transfer is in progress
* \retval STATUS_BUSY If master module is busy
* \retval STATUS_ERR_DENIED If error on bus
* \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
* \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
* acknowledged the address
* \retval STATUS_ERR_TIMEOUT If timeout occurred
* \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent
* data, indicating that slave does not
* want more data and was not able to read
*/
static inline enum status_code i2c_master_get_job_status(
struct i2c_master_module *const module)
{
/* Check sanity */
Assert(module);
Assert(module->hw);
/* Return current status code */
return module->status;
}
/** @} */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* I2C_MASTER_INTERRUPT_H_INCLUDED */

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/**
* \file
*
* \brief SAM I2C Master Interrupt Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "i2c_master_interrupt.h"
extern enum status_code _i2c_master_wait_for_bus(
struct i2c_master_module *const module);
extern enum status_code _i2c_master_address_response(
struct i2c_master_module *const module);
extern enum status_code _i2c_master_send_hs_master_code(
struct i2c_master_module *const module,
uint8_t hs_master_code);;
/**
* \internal
* Read next data. Used by interrupt handler to get next data byte from slave.
*
* \param[in,out] module Pointer to software module structure
*/
static void _i2c_master_read(
struct i2c_master_module *const module)
{
/* Sanity check arguments. */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
/* Find index to save next value in buffer */
uint16_t buffer_index = module->buffer_length;
buffer_index -= module->buffer_remaining;
module->buffer_remaining--;
if (sclsm_flag) {
if (module->send_nack && module->buffer_remaining == 1) {
/* Set action to NACK. */
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
}
} else {
if (module->send_nack && module->buffer_remaining == 0) {
/* Set action to NACK. */
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
}
}
if (module->buffer_remaining == 0) {
if (module->send_stop) {
/* Send stop condition */
_i2c_master_wait_for_sync(module);
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
}
}
/* Read byte from slave and put in buffer */
_i2c_master_wait_for_sync(module);
module->buffer[buffer_index] = i2c_module->DATA.reg;
}
/**
* \internal
*
* Write next data. Used by interrupt handler to send next data byte to slave.
*
* \param[in,out] module Pointer to software module structure
*/
static void _i2c_master_write(struct i2c_master_module *const module)
{
/* Sanity check arguments. */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
/* Check for ack from slave */
if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
{
/* Set status */
module->status = STATUS_ERR_OVERFLOW;
/* Do not write more data */
return;
}
/* Find index to get next byte in buffer */
uint16_t buffer_index = module->buffer_length;
buffer_index -= module->buffer_remaining;
module->buffer_remaining--;
/* Write byte from buffer to slave */
_i2c_master_wait_for_sync(module);
i2c_module->DATA.reg = module->buffer[buffer_index];
}
/**
* \internal
* Acts on slave address response. Checks for errors concerning master->slave
* handshake.
*
* \param[in,out] module Pointer to software module structure
*/
static void _i2c_master_async_address_response(
struct i2c_master_module *const module)
{
/* Sanity check arguments. */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
/* Check for error. Ignore bus-error; workaround for bus state stuck in
* BUSY.
*/
if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
{
/* Clear write interrupt flag */
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
/* Check arbitration */
if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
/* Return busy */
module->status = STATUS_ERR_PACKET_COLLISION;
}
/* No slave responds */
else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
module->status = STATUS_ERR_BAD_ADDRESS;
module->buffer_remaining = 0;
if (module->send_stop) {
/* Send stop condition */
_i2c_master_wait_for_sync(module);
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
}
}
}
module->buffer_length = module->buffer_remaining;
/* Check for status OK. */
if (module->status == STATUS_BUSY) {
/* Call function based on transfer direction. */
if (module->transfer_direction == I2C_TRANSFER_WRITE) {
_i2c_master_write(module);
} else {
_i2c_master_read(module);
}
}
}
/**
* \brief Registers callback for the specified callback type
*
* Associates the given callback function with the
* specified callback type.
*
* To enable the callback, the \ref i2c_master_enable_callback function
* must be used.
*
* \param[in,out] module Pointer to the software module struct
* \param[in] callback Pointer to the function desired for the
* specified callback
* \param[in] callback_type Callback type to register
*/
void i2c_master_register_callback(
struct i2c_master_module *const module,
const i2c_master_callback_t callback,
enum i2c_master_callback callback_type)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
Assert(callback);
/* Register callback */
module->callbacks[callback_type] = callback;
/* Set corresponding bit to set callback as registered */
module->registered_callback |= (1 << callback_type);
}
/**
* \brief Unregisters callback for the specified callback type
*
* When called, the currently registered callback for the given callback type
* will be removed.
*
* \param[in,out] module Pointer to the software module struct
* \param[in] callback_type Specifies the callback type to unregister
*/
void i2c_master_unregister_callback(
struct i2c_master_module *const module,
enum i2c_master_callback callback_type)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
/* Register callback */
module->callbacks[callback_type] = NULL;
/* Clear corresponding bit to set callback as unregistered */
module->registered_callback &= ~(1 << callback_type);
}
/**
* \internal
* Starts a read bytes operation.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting reading I<SUP>2</SUP>C packet.
* \retval STATUS_OK If reading was started successfully
* \retval STATUS_BUSY If module is currently busy with another transfer
*/
enum status_code i2c_master_read_bytes(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
/* Save packet to software module */
module->buffer = packet->data;
module->buffer_remaining = packet->data_length;
module->transfer_direction = I2C_TRANSFER_READ;
module->status = STATUS_BUSY;
module->send_stop = false;
module->send_nack = false;
/* Enable interrupts */
i2c_module->INTENSET.reg =
SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
return STATUS_OK;
}
/**
* \internal
* Starts a read packet operation.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting reading I<SUP>2</SUP>C packet.
* \retval STATUS_OK If reading was started successfully
* \retval STATUS_BUSY If module is currently busy with another transfer
*/
static enum status_code _i2c_master_read_packet(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
enum status_code tmp_status;
/* Save packet to software module */
module->buffer = packet->data;
module->buffer_remaining = packet->data_length;
module->transfer_direction = I2C_TRANSFER_READ;
module->status = STATUS_BUSY;
bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
/* Switch to high speed mode */
if (packet->high_speed) {
_i2c_master_send_hs_master_code(module, packet->hs_master_code);
}
/* Set action to ACK or NACK. */
if ((sclsm_flag) && (packet->data_length == 1)) {
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
} else {
i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
}
if (packet->ten_bit_address) {
/*
* Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
* be set and read/write bit (ADDR.ADDR[0]) equal to 0.
*/
i2c_module->ADDR.reg = (packet->address << 1) |
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
SERCOM_I2CM_ADDR_TENBITEN;
/* Wait for response on bus. */
tmp_status = _i2c_master_wait_for_bus(module);
/* Set action to ack. */
i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
/* Check for address response error unless previous error is
* detected. */
if (tmp_status == STATUS_OK) {
tmp_status = _i2c_master_address_response(module);
}
if (tmp_status == STATUS_OK) {
/* Enable interrupts */
i2c_module->INTENSET.reg =
SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
/*
* Write ADDR[7:0] register to "11110 address[9:8] 1"
* ADDR.TENBITEN must be cleared
*/
i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
I2C_TRANSFER_READ;
} else {
return tmp_status;
}
} else {
/* Enable interrupts */
i2c_module->INTENSET.reg =
SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
/* Set address and direction bit. Will send start command on bus */
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
}
return STATUS_OK;
}
/**
* \brief Initiates a read packet operation
*
* Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
* bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting reading I<SUP>2</SUP>C packet.
* \retval STATUS_OK If reading was started successfully
* \retval STATUS_BUSY If module is currently busy with another transfer
*/
enum status_code i2c_master_read_packet_job(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
Assert(packet);
/* Check if the I2C module is busy with a job */
if (module->buffer_remaining > 0) {
return STATUS_BUSY;
}
/* Make sure we send STOP */
module->send_stop = true;
module->send_nack = true;
/* Start reading */
return _i2c_master_read_packet(module, packet);
}
/**
* \brief Initiates a read packet operation without sending a STOP condition when done
*
* Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
* sending a stop condition, thus retaining ownership of the bus when done.
* To end the transaction, a \ref i2c_master_read_packet_wait "read" or
* \ref i2c_master_write_packet_wait "write" with stop condition must be
* performed.
*
* This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting reading I<SUP>2</SUP>C packet.
* \retval STATUS_OK If reading was started successfully
* \retval STATUS_BUSY If module is currently busy with another operation
*/
enum status_code i2c_master_read_packet_job_no_stop(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
Assert(packet);
/* Check if the I2C module is busy with a job */
if (module->buffer_remaining > 0) {
return STATUS_BUSY;
}
/* Make sure we don't send STOP */
module->send_stop = false;
module->send_nack = true;
/* Start reading */
return _i2c_master_read_packet(module, packet);
}
/**
* \brief Initiates a read packet operation without sending a NACK signal and a
* STOP condition when done
*
* Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
* sending a nack and a stop condition, thus retaining ownership of the bus when done.
* To end the transaction, a \ref i2c_master_read_packet_wait "read" or
* \ref i2c_master_write_packet_wait "write" with stop condition must be
* performed.
*
* This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting reading I<SUP>2</SUP>C packet.
* \retval STATUS_OK If reading was started successfully
* \retval STATUS_BUSY If module is currently busy with another operation
*/
enum status_code i2c_master_read_packet_job_no_nack(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
Assert(packet);
/* Check if the I2C module is busy with a job */
if (module->buffer_remaining > 0) {
return STATUS_BUSY;
}
/* Make sure we don't send STOP */
module->send_stop = false;
module->send_nack = false;
/* Start reading */
return _i2c_master_read_packet(module, packet);
}
/**
* \internal
* Starts a write bytes operation.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting write I<SUP>2</SUP>C bytes.
* \retval STATUS_OK If writing was started successfully
* \retval STATUS_BUSY If module is currently busy with another transfer
*/
enum status_code i2c_master_write_bytes(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
/* Save packet to software module */
module->buffer = packet->data;
module->buffer_remaining = packet->data_length;
module->transfer_direction = I2C_TRANSFER_WRITE;
module->status = STATUS_BUSY;
module->send_stop = false;
module->send_nack = false;
/* Enable interrupts */
i2c_module->INTENSET.reg =
SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
return STATUS_OK;
}
/**
* \internal Initiates a write packet operation
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting writing I<SUP>2</SUP>C packet job.
* \retval STATUS_OK If writing was started successfully
* \retval STATUS_BUSY If module is currently busy with another transfer
*/
static enum status_code _i2c_master_write_packet(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
/* Switch to high speed mode */
if (packet->high_speed) {
_i2c_master_send_hs_master_code(module, packet->hs_master_code);
}
/* Set action to ACK. */
i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
/* Save packet to software module */
module->buffer = packet->data;
module->buffer_remaining = packet->data_length;
module->transfer_direction = I2C_TRANSFER_WRITE;
module->status = STATUS_BUSY;
/* Enable interrupts */
i2c_module->INTENSET.reg =
SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
/* Set address and direction bit, will send start command on bus */
if (packet->ten_bit_address) {
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
SERCOM_I2CM_ADDR_TENBITEN;
} else {
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
}
return STATUS_OK;
}
/**
* \brief Initiates a write packet operation
*
* Writes a data packet to the specified slave address on the I<SUP>2</SUP>C
* bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting writing I<SUP>2</SUP>C packet job.
* \retval STATUS_OK If writing was started successfully
* \retval STATUS_BUSY If module is currently busy with another transfer
*/
enum status_code i2c_master_write_packet_job(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
Assert(packet);
/* Check if the I2C module is busy with another job. */
if (module->buffer_remaining > 0) {
return STATUS_BUSY;
}
/* Make sure we send STOP at end*/
module->send_stop = true;
module->send_nack = true;
/* Start write operation */
return _i2c_master_write_packet(module, packet);
}
/**
* \brief Initiates a write packet operation without sending a STOP condition when done
*
* Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
* without sending a stop condition, thus retaining ownership of the bus when
* done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
* \ref i2c_master_write_packet_wait "write" with stop condition or sending
* a stop with the \ref i2c_master_send_stop function must be performed.
*
* This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop.
*
* \param[in,out] module Pointer to software module struct
* \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
*
* \return Status of starting writing I<SUP>2</SUP>C packet job.
* \retval STATUS_OK If writing was started successfully
* \retval STATUS_BUSY If module is currently busy with another
*/
enum status_code i2c_master_write_packet_job_no_stop(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
/* Sanity check */
Assert(module);
Assert(module->hw);
Assert(packet);
/* Check if the I2C module is busy with another job. */
if (module->buffer_remaining > 0) {
return STATUS_BUSY;
}
/* Do not send stop condition when done */
module->send_stop = false;
module->send_nack = true;
/* Start write operation */
return _i2c_master_write_packet(module, packet);
}
/**
* \internal
* Interrupt handler for I<SUP>2</SUP>C master.
*
* \param[in] instance SERCOM instance that triggered the interrupt
*/
void _i2c_master_interrupt_handler(
uint8_t instance)
{
/* Get software module for callback handling */
struct i2c_master_module *module =
(struct i2c_master_module*)_sercom_instances[instance];
Assert(module);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
/* Combine callback registered and enabled masks */
uint8_t callback_mask = module->enabled_callback;
callback_mask &= module->registered_callback;
/* Check if the module should respond to address ack */
if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
/* Call function for address response */
_i2c_master_async_address_response(module);
/* Check if buffer write is done */
} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
(module->status == STATUS_BUSY) &&
(module->transfer_direction == I2C_TRANSFER_WRITE)) {
/* Stop packet operation */
i2c_module->INTENCLR.reg =
SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
module->buffer_length = 0;
module->status = STATUS_OK;
if (module->send_stop) {
/* Send stop condition */
_i2c_master_wait_for_sync(module);
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
} else {
/* Clear write interrupt flag */
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
}
if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
}
/* Continue buffer write/read */
} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
/* Check that bus ownership is not lost */
if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) &&
(!(sclsm_flag && (module->buffer_remaining == 1)))) {
module->status = STATUS_ERR_PACKET_COLLISION;
} else if (module->transfer_direction == I2C_TRANSFER_WRITE) {
_i2c_master_write(module);
} else {
_i2c_master_read(module);
}
}
/* Check if read buffer transfer is complete */
if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
(module->status == STATUS_BUSY) &&
(module->transfer_direction == I2C_TRANSFER_READ)) {
/* Clear read interrupt flag */
if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
}
/* Stop packet operation */
i2c_module->INTENCLR.reg =
SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
module->buffer_length = 0;
module->status = STATUS_OK;
/* Call appropriate callback if enabled and registered */
if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
&& (module->transfer_direction == I2C_TRANSFER_READ)) {
module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
} else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
}
}
/* Check for error */
if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) {
/* Stop packet operation */
i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
SERCOM_I2CM_INTENCLR_SB;
module->buffer_length = 0;
module->buffer_remaining = 0;
/* Send nack and stop command unless arbitration is lost */
if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
module->send_stop) {
_i2c_master_wait_for_sync(module);
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
SERCOM_I2CM_CTRLB_CMD(3);
}
/* Call error callback if enabled and registered */
if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) {
module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
}
}
}

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/**
* \file
*
* \brief SAM SERCOM I2C Master Quick Start Guide
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_sercom_i2c_master_basic_use_case Quick Start Guide for SERCOM I2C Master - Basic
*
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
* - Master mode
* - 100KHz operation speed
* - Not operational in standby
* - 10000 packet timeout value
* - 65535 unknown bus state timeout value
*
*
* \section asfdoc_sam0_sercom_i2c_master_basic_use_case_prereq Prerequisites
* The device must be connected to an I<SUP>2</SUP>C slave.
*
* \section asfdoc_sam0_sercom_i2c_master_basic_use_setup Setup
*
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_code Code
* The following must be added to the user application:
*
* - A sample buffer to send, a sample buffer to read:
* \snippet qs_i2c_master_basic_use.c packet_data
*
* - Slave address to access:
* \snippet qs_i2c_master_basic_use.c address
*
* - Number of times to try to send packet if it fails:
* \snippet qs_i2c_master_basic_use.c timeout
*
* - Globally accessible module structure:
* \snippet qs_i2c_master_basic_use.c dev_inst
*
* - Function for setting up the module:
* \snippet qs_i2c_master_basic_use.c initialize_i2c
*
* - Add to user application \c main():
* \snippet qs_i2c_master_basic_use.c init
*
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_workflow Workflow
* -# Configure and enable module.
* \snippet qs_i2c_master_basic_use.c initialize_i2c
* -# Create and initialize configuration structure.
* \snippet qs_i2c_master_basic_use.c init_conf
* -# Change settings in the configuration.
* \snippet qs_i2c_master_basic_use.c conf_change
* -# Initialize the module with the set configurations.
* \snippet qs_i2c_master_basic_use.c init_module
* -# Enable the module.
* \snippet qs_i2c_master_basic_use.c enable_module
* -# Create a variable to see when we should stop trying to send packet.
* \snippet qs_i2c_master_basic_use.c timeout_counter
* -# Create a packet to send.
* \snippet qs_i2c_master_basic_use.c packet
*
* \section asfdoc_sam0_sercom_i2c_master_basic_use_implemenation Implementation
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_code Code
* Add to user application \c main():
* \snippet qs_i2c_master_basic_use.c main
*
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_workflow Workflow
* -# Write packet to slave.
* \snippet qs_i2c_master_basic_use.c write_packet
* The module will try to send the packet TIMEOUT number of times or until it is
* successfully sent.
* -# Read packet from slave.
* \snippet qs_i2c_master_basic_use.c read_packet
* The module will try to read the packet TIMEOUT number of times or until it is
* successfully read.
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <asf.h>
#include <conf_clocks.h>

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/**
* \file
*
* \brief SAM SERCOM I2C Master Interface Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_sercom_i2c_master_callback_use_case Quick Start Guide for SERCOM I2C Master - Callback
*
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
* - Master mode
* - 100KHz operation speed
* - Not operational in standby
* - 65535 unknown bus state timeout value
*
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_prereq Prerequisites
* The device must be connected to an I<SUP>2</SUP>C slave.
*
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_setup Setup
*
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_setup_code Code
* The following must be added to the user application:
*
* A sample buffer to write from, a reversed buffer to write from and length of
* buffers.
* \snippet qs_i2c_master_callback.c packet_data
*
* Address of slave:
* \snippet qs_i2c_master_callback.c address
*
* Globally accessible module structure:
* \snippet qs_i2c_master_callback.c dev_inst
*
* Globally accessible packet:
* \snippet qs_i2c_master_callback.c packet_glob
*
* Function for setting up module:
* \snippet qs_i2c_master_callback.c initialize_i2c
*
* Callback function for write complete:
* \snippet qs_i2c_master_callback.c callback_func
*
* Function for setting up the callback functionality of the driver:
* \snippet qs_i2c_master_callback.c setup_callback
*
* Add to user application \c main():
* \snippet qs_i2c_master_callback.c run_initialize_i2c
*
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_setup_workflow Workflow
* -# Configure and enable module.
* \snippet qs_i2c_master_callback.c config
* -# Create and initialize configuration structure.
* \snippet qs_i2c_master_callback.c init_conf
* -# Change settings in the configuration.
* \snippet qs_i2c_master_callback.c conf_change
* -# Initialize the module with the set configurations.
* \snippet qs_i2c_master_callback.c init_module
* -# Enable the module.
* \snippet qs_i2c_master_callback.c enable_module
* -# Configure callback functionality.
* \snippet qs_i2c_master_callback.c config_callback
* -# Register write complete callback.
* \snippet qs_i2c_master_callback.c callback_reg
* -# Enable write complete callback.
* \snippet qs_i2c_master_callback.c callback_en
* -# Create a packet to send to slave.
* \snippet qs_i2c_master_callback.c write_packet
*
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_implementation Implementation
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_code Code
* Add to user application \c main():
* \snippet qs_i2c_master_callback.c while
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_implementation_workflow Workflow
* -# Write packet to slave.
* \snippet qs_i2c_master_callback.c write_packet
* -# Infinite while loop, while waiting for interaction with slave.
* \snippet qs_i2c_master_callback.c while
*
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_callback Callback
* Each time a packet is sent, the callback function will be called.
*
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_callback_workflow Workflow
* - Write complete callback:
* -# Send every other packet in reversed order.
* \snippet qs_i2c_master_callback.c revert_order
* -# Write new packet to slave.
* \snippet qs_i2c_master_callback.c write_packet
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <asf.h>
#include <conf_clocks.h>

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/**
* \file
*
* \brief SAM SERCOM I2C Master Driver with DMA Quick Start Guide
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_sercom_i2c_master_dma_use_case Quick Start Guide for Using DMA with SERCOM I2C Master
*
* The supported board list:
* - SAMD21 Xplained Pro
* - SAMR21 Xplained Pro
* - SAML21 Xplained Pro
* - SAML22 Xplained Pro
* - SAMDA1 Xplained Pro
* - SAMC21 Xplained Pro
* - SAMHA1G16A Xplained Pro
*
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
* - Master mode
* - 100KHz operation speed
* - Not operational in standby
* - 10000 packet timeout value
* - 65535 unknown bus state timeout value
*
*
* \section asfdoc_sam0_sercom_i2c_master_dma_use_case_prereq Prerequisites
* The device must be connected to an I<SUP>2</SUP>C slave.
*
* \section asfdoc_sam0_sercom_i2c_master_dma_use_setup Setup
*
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_code Code
* The following must be added to the user application:
*
* - A sample buffer to send, number of entries to send and address of slave:
* \snippet qs_i2c_master_dma.c packet_data
*
* Number of times to try to send packet if it fails:
* \snippet qs_i2c_master_dma.c timeout
*
* - Globally accessible module structure:
* \snippet qs_i2c_master_dma.c dev_i2c_inst
*
* - Function for setting up the module:
* \snippet qs_i2c_master_dma.c initialize_i2c
*
* - Globally accessible DMA module structure:
* \snippet qs_i2c_master_dma.c dma_resource
*
* - Globally transfer done flag:
* \snippet qs_i2c_master_dma.c transfer_done_flag
*
* - Globally accessible DMA transfer descriptor:
* \snippet qs_i2c_master_dma.c transfer_descriptor
*
* - Function for transfer done callback:
* \snippet qs_i2c_master_dma.c transfer_done
*
* - Function for setting up the DMA resource:
* \snippet qs_i2c_master_dma.c config_dma_resource
*
* - Function for setting up the DMA transfer descriptor:
* \snippet qs_i2c_master_dma.c setup_dma_transfer_descriptor
* - Add to user application \c main():
* \snippet qs_i2c_master_dma.c init
*
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow Workflow
* -# Configure and enable module:
* \snippet qs_i2c_master_dma.c config_i2c
* -# Create and initialize configuration structure.
* \snippet qs_i2c_master_dma.c init_conf
* -# Change settings in the configuration.
* \snippet qs_i2c_master_dma.c conf_change
* -# Initialize the module with the set configurations.
* \snippet qs_i2c_master_dma.c init_module
* -# Enable the module.
* \snippet qs_i2c_master_dma.c enable_module
*
* -# Configure DMA
* -# Create a DMA resource configuration structure, which can be filled out to
* adjust the configuration of a single DMA transfer.
* \snippet qs_i2c_master_dma.c dma_setup_1
*
* -# Initialize the DMA resource configuration struct with the module's
* default values.
* \snippet qs_i2c_master_dma.c dma_setup_2
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Set extra configurations for the DMA resource. It is using peripheral
* trigger. SERCOM TX trigger causes a transaction transfer in
* this example.
* \snippet qs_i2c_master_dma.c dma_setup_3
*
* -# Allocate a DMA resource with the configurations.
* \snippet qs_i2c_master_dma.c dma_setup_4
*
* -# Create a DMA transfer descriptor configuration structure, which can be
* filled out to adjust the configuration of a single DMA transfer.
* \snippet qs_i2c_master_dma.c dma_setup_5
*
* -# Initialize the DMA transfer descriptor configuration struct with the module's
* default values.
* \snippet qs_i2c_master_dma.c dma_setup_6
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Set the specific parameters for a DMA transfer with transfer size, source
* address, and destination address.
* \snippet qs_i2c_master_dma.c dma_setup_7
*
* -# Create the DMA transfer descriptor.
* \snippet qs_i2c_master_dma.c dma_setup_8
*
* \section asfdoc_sam0_sercom_i2c_master_dma_use_implemenation Implementation
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_code Code
* Add to user application \c main():
* \snippet qs_i2c_master_dma.c main
*
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_workflow Workflow
* -# Start the DMA transfer job.
* \snippet qs_i2c_master_dma.c start_transfer_job
*
* -# Set the auto address length and enable flag.
* \snippet qs_i2c_master_dma.c set_i2c_addr
*
* -# Waiting for transfer complete.
* \snippet qs_i2c_master_dma.c waiting_for_complete
*
* -# Enter an infinite loop once transfer complete.
* \snippet qs_i2c_master_dma.c inf_loop
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/

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/**
* \file
*
* \brief SAM Serial Peripheral Interface Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "sercom.h"
#define SHIFT 32
#define BAUD_INT_MAX 8192
#define BAUD_FP_MAX 8
#if !defined(__DOXYGEN__)
/**
* \internal Configuration structure to save current gclk status.
*/
struct _sercom_conf {
/* Status of gclk generator initialization */
bool generator_is_set;
/* Sercom gclk generator used */
enum gclk_generator generator_source;
};
static struct _sercom_conf _sercom_config;
/**
* \internal Calculate 64 bit division, ref can be found in
* http://en.wikipedia.org/wiki/Division_algorithm#Long_division
*/
static uint64_t long_division(uint64_t n, uint64_t d)
{
int32_t i;
uint64_t q = 0, r = 0, bit_shift;
for (i = 63; i >= 0; i--) {
bit_shift = (uint64_t)1 << i;
r = r << 1;
if (n & bit_shift) {
r |= 0x01;
}
if (r >= d) {
r = r - d;
q |= bit_shift;
}
}
return q;
}
/**
* \internal Calculate synchronous baudrate value (SPI/UART)
*/
enum status_code _sercom_get_sync_baud_val(
const uint32_t baudrate,
const uint32_t external_clock,
uint16_t *const baudvalue)
{
/* Baud value variable */
uint16_t baud_calculated = 0;
uint32_t clock_value = external_clock;
/* Check if baudrate is outside of valid range */
if (baudrate > (external_clock / 2)) {
/* Return with error code */
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
}
/* Calculate BAUD value from clock frequency and baudrate */
clock_value = external_clock / 2;
while (clock_value >= baudrate) {
clock_value = clock_value - baudrate;
baud_calculated++;
}
baud_calculated = baud_calculated - 1;
/* Check if BAUD value is more than 255, which is maximum
* for synchronous mode */
if (baud_calculated > 0xFF) {
/* Return with an error code */
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
} else {
*baudvalue = baud_calculated;
return STATUS_OK;
}
}
/**
* \internal Calculate asynchronous baudrate value (UART)
*/
enum status_code _sercom_get_async_baud_val(
const uint32_t baudrate,
const uint32_t peripheral_clock,
uint16_t *const baudval,
enum sercom_asynchronous_operation_mode mode,
enum sercom_asynchronous_sample_num sample_num)
{
/* Temporary variables */
uint64_t ratio = 0;
uint64_t scale = 0;
uint64_t baud_calculated = 0;
uint8_t baud_fp;
uint32_t baud_int = 0;
uint64_t temp1;
/* Check if the baudrate is outside of valid range */
if ((baudrate * sample_num) > peripheral_clock) {
/* Return with error code */
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
}
if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
/* Calculate the BAUD value */
temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
ratio = long_division(temp1, peripheral_clock);
scale = ((uint64_t)1 << SHIFT) - ratio;
baud_calculated = (65536 * scale) >> SHIFT;
} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
temp1 = ((uint64_t)baudrate * sample_num);
baud_int = long_division( peripheral_clock, temp1);
if(baud_int > BAUD_INT_MAX) {
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
}
temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
baud_fp = temp1 - 8 * baud_int;
baud_calculated = baud_int | (baud_fp << 13);
}
*baudval = baud_calculated;
return STATUS_OK;
}
#endif
/**
* \brief Set GCLK channel to generator.
*
* This will set the appropriate GCLK channel to the requested GCLK generator.
* This will set the generator for all SERCOM instances, and the user will thus
* only be able to set the same generator that has previously been set, if any.
*
* After the generator has been set the first time, the generator can be changed
* using the \c force_change flag.
*
* \param[in] generator_source The generator to use for SERCOM.
* \param[in] force_change Force change the generator.
*
* \return Status code indicating the GCLK generator change operation.
* \retval STATUS_OK If the generator update request was
* successful.
* \retval STATUS_ERR_ALREADY_INITIALIZED If a generator was already configured
* and the new configuration was not
* forced.
*/
enum status_code sercom_set_gclk_generator(
const enum gclk_generator generator_source,
const bool force_change)
{
/* Check if valid option */
if (!_sercom_config.generator_is_set || force_change) {
/* Create and fill a GCLK configuration structure for the new config */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = generator_source;
system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
system_gclk_chan_enable(SERCOM_GCLK_ID);
/* Save config */
_sercom_config.generator_source = generator_source;
_sercom_config.generator_is_set = true;
return STATUS_OK;
} else if (generator_source == _sercom_config.generator_source) {
/* Return status OK if same config */
return STATUS_OK;
}
/* Return invalid config to already initialized GCLK */
return STATUS_ERR_ALREADY_INITIALIZED;
}
/** \internal
* Creates a switch statement case entry to convert a SERCOM instance and pad
* index to the default SERCOM pad MUX setting.
*/
#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
case (uintptr_t)SERCOM##n: \
switch (pad) { \
case 0: \
return SERCOM##n##_PAD0_DEFAULT; \
case 1: \
return SERCOM##n##_PAD1_DEFAULT; \
case 2: \
return SERCOM##n##_PAD2_DEFAULT; \
case 3: \
return SERCOM##n##_PAD3_DEFAULT; \
} \
break;
/**
* \internal Gets the default PAD pinout for a given SERCOM.
*
* Returns the pinmux settings for the given SERCOM and pad. This is used
* for default configuration of pins.
*
* \param[in] sercom_module Pointer to the SERCOM module
* \param[in] pad PAD to get default pinout for
*
* \returns The default pinmux for the given SERCOM instance and PAD
*
*/
uint32_t _sercom_get_default_pad(
Sercom *const sercom_module,
const uint8_t pad)
{
switch ((uintptr_t)sercom_module) {
/* Auto-generate a lookup table for the default SERCOM pad defaults */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
}
Assert(false);
return 0;
}
/**
* \internal
* Find index of given instance.
*
* \param[in] sercom_instance Instance pointer.
*
* \return Index of given instance.
*/
uint8_t _sercom_get_sercom_inst_index(
Sercom *const sercom_instance)
{
/* Save all available SERCOM instances for compare */
Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
/* Find index for sercom instance */
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
return i;
}
}
/* Invalid data given */
Assert(false);
return 0;
}

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/**
* \file
*
* \brief SAM Serial Peripheral Interface Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef SERCOM_H_INCLUDED
#define SERCOM_H_INCLUDED
#include <compiler.h>
#include <system.h>
#include <clock.h>
#include <system_interrupt.h>
#include "sercom_pinout.h"
#ifdef __cplusplus
extern "C" {
#endif
/* SERCOM modules should share same slow GCLK channel ID */
#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
#if (0x1ff >= REV_SERCOM)
# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
#elif (0x400 >= REV_SERCOM)
# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
#else
# error "Unknown SYNCBUSY scheme for this SERCOM revision"
#endif
/**
* \brief sercom asynchronous operation mode
*
* Select sercom asynchronous operation mode
*/
enum sercom_asynchronous_operation_mode {
SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
};
/**
* \brief sercom asynchronous samples per bit
*
* Select number of samples per bit
*/
enum sercom_asynchronous_sample_num {
SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
};
enum status_code sercom_set_gclk_generator(
const enum gclk_generator generator_source,
const bool force_change);
enum status_code _sercom_get_sync_baud_val(
const uint32_t baudrate,
const uint32_t external_clock,
uint16_t *const baudval);
enum status_code _sercom_get_async_baud_val(
const uint32_t baudrate,
const uint32_t peripheral_clock,
uint16_t *const baudval,
enum sercom_asynchronous_operation_mode mode,
enum sercom_asynchronous_sample_num sample_num);
uint32_t _sercom_get_default_pad(
Sercom *const sercom_module,
const uint8_t pad);
uint8_t _sercom_get_sercom_inst_index(
Sercom *const sercom_instance);
#ifdef __cplusplus
}
#endif
#endif //__SERCOM_H_INCLUDED

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/**
* \file
*
* \brief SAM Serial Peripheral Interface Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "sercom_interrupt.h"
void *_sercom_instances[SERCOM_INST_NUM];
/** Save status of initialized handlers */
static bool _handler_table_initialized = false;
/** Void pointers for saving device instance structures */
static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
/**
* \internal
* Default interrupt handler.
*
* \param[in] instance SERCOM instance used.
*/
static void _sercom_default_handler(
const uint8_t instance)
{
Assert(false);
}
/**
* \internal
* Saves the given callback handler.
*
* \param[in] instance Instance index.
* \param[in] interrupt_handler Pointer to instance callback handler.
*/
void _sercom_set_handler(
const uint8_t instance,
const sercom_handler_t interrupt_handler)
{
/* Initialize handlers with default handler and device instances with 0 */
if (_handler_table_initialized == false) {
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
_sercom_interrupt_handlers[i] = &_sercom_default_handler;
_sercom_instances[i] = NULL;
}
_handler_table_initialized = true;
}
/* Save interrupt handler */
_sercom_interrupt_handlers[instance] = interrupt_handler;
}
/** \internal
* Converts a given SERCOM index to its interrupt vector index.
*/
#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
SYSTEM_INTERRUPT_MODULE_SERCOM##n,
/** \internal
* Generates a SERCOM interrupt handler function for a given SERCOM index.
*/
#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
void SERCOM##n##_Handler(void) \
{ \
_sercom_interrupt_handlers[n](n); \
}
/**
* \internal
* Returns the system interrupt vector.
*
* \param[in] sercom_instance Instance pointer
*
* \return Enum of system interrupt vector
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
*/
enum system_interrupt_vector _sercom_get_interrupt_vector(
Sercom *const sercom_instance)
{
const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
{
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
};
/* Retrieve the index of the SERCOM being requested */
uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
/* Get the vector number from the lookup table for the requested SERCOM */
return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
}
/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)

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/**
* \file
*
* \brief SAM Serial Peripheral Interface Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef SERCOM_INTERRUPT_H_INCLUDED
#define SERCOM_INTERRUPT_H_INCLUDED
#include "sercom.h"
#include <system_interrupt.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Look-up table for device instances */
extern void *_sercom_instances[SERCOM_INST_NUM];
typedef void (*sercom_handler_t)(uint8_t instance);
enum system_interrupt_vector _sercom_get_interrupt_vector(
Sercom *const sercom_instance);
void _sercom_set_handler(
const uint8_t instance,
const sercom_handler_t interrupt_handler);
#ifdef __cplusplus
}
#endif
#endif /* SERCOM_INTERRUPT_H_INCLUDED */

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/**
* \file
*
* \brief SAM SERCOM Module Pinout Definitions
*
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef SERCOM_PINOUT_H_INCLUDED
#define SERCOM_PINOUT_H_INCLUDED
#include <compiler.h>
#if SAMR21E
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
/* SERCOM3 */
# if SAM_PART_IS_DEFINED(SAMR21E19A)
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
# else
#define SERCOM3_PAD0_DEFAULT PINMUX_PA27F_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA28F_SERCOM3_PAD1
#endif
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
/* SERCOM4 */
# if SAM_PART_IS_DEFINED(SAMR21E19A)
#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
# else
#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3
# endif
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
#elif SAMR21G
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
#elif (SAMD09)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA08D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA09D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA30C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA31C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA24C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA25C_SERCOM1_PAD3
#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3
#elif (SAMD10C) || (SAMD11C)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA08D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA09D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA30C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA31C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA24C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA25C_SERCOM1_PAD3
#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
#elif (SAML22N)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA20D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA21D_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PB02C_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PB21C_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PB00C_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PB01C_SERCOM3_PAD3
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT PINMUX_PA12C_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13C_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14C_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15C_SERCOM4_PAD3
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PB22D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PB23D_SERCOM5_PAD3
#elif (SAML22J) || (SAML22G)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA20D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA21D_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA12D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA13D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA14D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA15D_SERCOM3_PAD3
#elif (SAMC20E) || (SAMC21E)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
#elif (SAMC20G) || (SAMC21G)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
#ifdef ID_SERCOM4
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
#endif
#ifdef ID_SERCOM5
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PB22D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PB23D_SERCOM5_PAD3
#endif
#elif (SAMC20J) || (SAMC21J)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
#ifdef ID_SERCOM4
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
#endif
#ifdef ID_SERCOM5
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PB00D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PB01D_SERCOM5_PAD3
#endif
#elif (SAMDA1)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
#if (SAMDA1E)
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
#else
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
#endif
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
#elif (SAMHA1E) || (SAMHA0E)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM5_PAD1_DEFAULT 0 /* No available pin */
#define SERCOM5_PAD2_DEFAULT PINMUX_PA20C_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT 0 /* No available pin */
#elif (SAMHA1G) || (SAMHA0G)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PB16C_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PB17C_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PA20C_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PA21C_SERCOM5_PAD3
#elif (SAML21E) || (SAMR34) || (SAMR35)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
#if !SAM_PART_IS_DEFINED(SAML21E18A)
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
#endif
#elif (SAMR30E)
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM0_PAD1_DEFAULT 0 /* No available pin */
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#define SERCOM1_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM1_PAD1_DEFAULT 0 /* No available pin */
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT 0 /* No available pin */
#define SERCOM2_PAD3_DEFAULT 0 /* No available pin */
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT 0
#define SERCOM5_PAD1_DEFAULT 0
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
#else
/* SERCOM0 */
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
/* SERCOM1 */
#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
#else
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
#endif
/* SERCOM2 */
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
/* SERCOM3 */
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
#if !(SAMD20E || SAMD21E)
/* SERCOM4 */
#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
/* SERCOM5 */
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
#endif
#endif
#endif /* SERCOM_PINOUT_H_INCLUDED */

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/**
* \file
*
* \brief SAM USART Quick Start
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic
*
* This quick start will echo back characters typed into the terminal. In this
* use case the USART will be configured with the following settings:
* - Asynchronous mode
* - 9600 Baudrate
* - 8-bits, No Parity and one Stop Bit
* - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
*
* \section asfdoc_sam0_sercom_usart_basic_use_case_setup Setup
*
* \subsection asfdoc_sam0_sercom_usart_basic_use_case_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_usart_basic_use_case_setup_code Code
* Add to the main application source file, outside of any functions:
* \snippet qs_usart_basic_use.c module_inst
*
* Copy-paste the following setup code to your user application:
* \snippet qs_usart_basic_use.c setup
*
* Add to user application initialization (typically the start of \c main()):
* \snippet qs_usart_basic_use.c setup_init
*
* \subsection asfdoc_sam0_usart_basic_use_case_setup_flow Workflow
* -# Create a module software instance structure for the USART module to store
* the USART driver state while it is in use.
* \snippet qs_usart_basic_use.c module_inst
* \note This should never go out of scope as long as the module is in use.
* In most cases, this should be global.
*
* -# Configure the USART module.
* -# Create a USART module configuration struct, which can be filled out to
* adjust the configuration of a physical USART peripheral.
* \snippet qs_usart_basic_use.c setup_config
* -# Initialize the USART configuration struct with the module's default values.
* \snippet qs_usart_basic_use.c setup_config_defaults
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Alter the USART settings to configure the physical pinout, baudrate, and
* other relevant parameters.
* \snippet qs_usart_basic_use.c setup_change_config
* -# Configure the USART module with the desired settings, retrying while the
* driver is busy until the configuration is stressfully set.
* \snippet qs_usart_basic_use.c setup_set_config
* -# Enable the USART module.
* \snippet qs_usart_basic_use.c setup_enable
*
*
* \section asfdoc_sam0_usart_basic_use_case_main Use Case
*
* \subsection asfdoc_sam0_usart_basic_use_case_main_code Code
* Copy-paste the following code to your user application:
* \snippet qs_usart_basic_use.c main
*
* \subsection asfdoc_sam0_usart_basic_use_case_main_flow Workflow
* -# Send a string to the USART to show the demo is running, blocking until
* all characters have been sent.
* \snippet qs_usart_basic_use.c main_send_string
* -# Enter an infinite loop to continuously echo received values on the USART.
* \snippet qs_usart_basic_use.c main_loop
* -# Perform a blocking read of the USART, storing the received character into
* the previously declared temporary variable.
* \snippet qs_usart_basic_use.c main_read
* -# Echo the received variable back to the USART via a blocking write.
* \snippet qs_usart_basic_use.c main_write
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/

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/**
* \file
*
* \brief SAM USART Quick Start
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_sercom_usart_callback_use_case Quick Start Guide for SERCOM USART - Callback
*
* This quick start will echo back characters typed into the terminal, using
* asynchronous TX and RX callbacks from the USART peripheral. In this use case
* the USART will be configured with the following settings:
* - Asynchronous mode
* - 9600 Baudrate
* - 8-bits, No Parity and one Stop Bit
* - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
*
* \section asfdoc_sam0_sercom_usart_callback_use_case_setup Setup
*
* \subsection asfdoc_sam0_sercom_usart_callback_use_case_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_usart_callback_use_case_setup_code Code
* Add to the main application source file, outside of any functions:
* \snippet qs_usart_callback.c module_inst
* \snippet qs_usart_callback.c rx_buffer_var
*
* Copy-paste the following callback function code to your user application:
* \snippet qs_usart_callback.c callback_funcs
*
* Copy-paste the following setup code to your user application:
* \snippet qs_usart_callback.c setup
*
* Add to user application initialization (typically the start of \c main()):
* \snippet qs_usart_callback.c setup_init
*
* \subsection asfdoc_sam0_usart_callback_use_case_setup_flow Workflow
* -# Create a module software instance structure for the USART module to store
* the USART driver state while it is in use.
* \snippet qs_usart_callback.c module_inst
* \note This should never go out of scope as long as the module is in use.
* In most cases, this should be global.
*
* -# Configure the USART module.
* -# Create a USART module configuration struct, which can be filled out to
* adjust the configuration of a physical USART peripheral.
* \snippet qs_usart_callback.c setup_config
* -# Initialize the USART configuration struct with the module's default values.
* \snippet qs_usart_callback.c setup_config_defaults
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Alter the USART settings to configure the physical pinout, baudrate, and
* other relevant parameters.
* \snippet qs_usart_callback.c setup_change_config
* -# Configure the USART module with the desired settings, retrying while the
* driver is busy until the configuration is stressfully set.
* \snippet qs_usart_callback.c setup_set_config
* -# Enable the USART module.
* \snippet qs_usart_callback.c setup_enable
* -# Configure the USART callbacks.
* -# Register the TX and RX callback functions with the driver.
* \snippet qs_usart_callback.c setup_register_callbacks
* -# Enable the TX and RX callbacks so that they will be called by the driver
* when appropriate.
* \snippet qs_usart_callback.c setup_enable_callbacks
*
* \section asfdoc_sam0_usart_callback_use_case_main Use Case
*
* \subsection asfdoc_sam0_usart_callback_use_case_main_code Code
* Copy-paste the following code to your user application:
* \snippet qs_usart_callback.c main
*
* \subsection asfdoc_sam0_usart_callback_use_case_main_flow Workflow
* -# Enable global interrupts, so that the callbacks can be fired.
* \snippet qs_usart_callback.c enable_global_interrupts
* -# Send a string to the USART to show the demo is running, blocking until
* all characters have been sent.
* \snippet qs_usart_callback.c main_send_string
* -# Enter an infinite loop to continuously echo received values on the USART.
* \snippet qs_usart_callback.c main_loop
* -# Perform an asynchronous read of the USART, which will fire the registered
* callback when characters are received.
* \snippet qs_usart_callback.c main_read
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <asf.h>
#include <conf_clocks.h>

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/**
* \file
*
* \brief SAM Quick Start Guide for Using Usart driver with DMA
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
/**
* \page asfdoc_sam0_sercom_usart_dma_use_case Quick Start Guide for Using DMA with SERCOM USART
*
* The supported board list:
* - SAM D21 Xplained Pro
* - SAM R21 Xplained Pro
* - SAM D11 Xplained Pro
* - SAM DA1 Xplained Pro
* - SAM HA1G16A Xplained Pro
* - SAM L21 Xplained Pro
* - SAM L22 Xplained Pro
* - SAM C21 Xplained Pro
*
* This quick start will receive eight bytes of data from the PC terminal and transmit back the string
* to the terminal through DMA. In this use case the USART will be configured with the following
* settings:
* - Asynchronous mode
* - 9600 Baudrate
* - 8-bits, No Parity and one Stop Bit
* - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
*
* \section asfdoc_sam0_sercom_usart_dma_use_case_setup Setup
*
* \subsection asfdoc_sam0_sercom_usart_dma_use_case_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_usart_dma_use_case_setup_code Code
* Add to the main application source file, outside of any functions:
* \snippet qs_usart_dma_use.c module_inst
* \snippet qs_usart_dma_use.c dma_resource
* \snippet qs_usart_dma_use.c usart_buffer
* \snippet qs_usart_dma_use.c transfer_descriptor
*
* Copy-paste the following setup code to your user application:
* \snippet qs_usart_dma_use.c setup
*
* Add to user application initialization (typically the start of \c main()):
* \snippet qs_usart_dma_use.c setup_init
*
* \subsection asfdoc_sam0_usart_dma_use_case_setup_flow Workflow
*
* \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_inst Create variables
* -# Create a module software instance structure for the USART module to store
* the USART driver state while it is in use.
* \snippet qs_usart_dma_use.c module_inst
* \note This should never go out of scope as long as the module is in use.
* In most cases, this should be global.
*
* -# Create module software instance structures for DMA resources to store
* the DMA resource state while it is in use.
* \snippet qs_usart_dma_use.c dma_resource
* \note This should never go out of scope as long as the module is in use.
* In most cases, this should be global.
*
* -# Create a buffer to store the data to be transferred /received.
* \snippet qs_usart_dma_use.c usart_buffer
* -# Create DMA transfer descriptors for RX/TX.
* \snippet qs_usart_dma_use.c transfer_descriptor
*
* \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_usart Configure the USART
* -# Create a USART module configuration struct, which can be filled out to
* adjust the configuration of a physical USART peripheral.
* \snippet qs_usart_dma_use.c setup_config
* -# Initialize the USART configuration struct with the module's default values.
* \snippet qs_usart_dma_use.c setup_config_defaults
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Alter the USART settings to configure the physical pinout, baudrate, and
* other relevant parameters.
* \snippet qs_usart_dma_use.c setup_change_config
* -# Configure the USART module with the desired settings, retrying while the
* driver is busy until the configuration is stressfully set.
* \snippet qs_usart_dma_use.c setup_set_config
* -# Enable the USART module.
* \snippet qs_usart_dma_use.c setup_enable
*
* \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_dma Configure DMA
* -# Create a callback function of receiver done.
* \snippet qs_usart_dma_use.c transfer_done_rx
*
* -# Create a callback function of transmission done.
* \snippet qs_usart_dma_use.c transfer_done_tx
*
* -# Create a DMA resource configuration structure, which can be filled out to
* adjust the configuration of a single DMA transfer.
* \snippet qs_usart_dma_use.c setup_rx_1
*
* -# Initialize the DMA resource configuration struct with the module's
* default values.
* \snippet qs_usart_dma_use.c setup_rx_2
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Set extra configurations for the DMA resource. It is using peripheral
* trigger. SERCOM TX empty trigger causes a beat transfer in
* this example.
* \snippet qs_usart_dma_use.c setup_rx_3
*
* -# Allocate a DMA resource with the configurations.
* \snippet qs_usart_dma_use.c setup_rx_4
*
* -# Create a DMA transfer descriptor configuration structure, which can be
* filled out to adjust the configuration of a single DMA transfer.
* \snippet qs_usart_dma_use.c setup_rx_5
*
* -# Initialize the DMA transfer descriptor configuration struct with the module's
* default values.
* \snippet qs_usart_dma_use.c setup_rx_6
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Set the specific parameters for a DMA transfer with transfer size, source
* address, and destination address.
* \snippet qs_usart_dma_use.c setup_rx_7
*
* -# Create the DMA transfer descriptor.
* \snippet qs_usart_dma_use.c setup_rx_8
*
* -# Create a DMA resource configuration structure for TX, which can be filled
* out to adjust the configuration of a single DMA transfer.
* \snippet qs_usart_dma_use.c setup_tx_1
*
* -# Initialize the DMA resource configuration struct with the module's
* default values.
* \snippet qs_usart_dma_use.c setup_tx_2
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Set extra configurations for the DMA resource. It is using peripheral
* trigger. SERCOM RX Ready trigger causes a beat transfer in
* this example.
* \snippet qs_usart_dma_use.c setup_tx_3
*
* -# Allocate a DMA resource with the configurations.
* \snippet qs_usart_dma_use.c setup_tx_4
*
* -# Create a DMA transfer descriptor configuration structure, which can be
* filled out to adjust the configuration of a single DMA transfer.
* \snippet qs_usart_dma_use.c setup_tx_5
*
* -# Initialize the DMA transfer descriptor configuration struct with the module's
* default values.
* \snippet qs_usart_dma_use.c setup_tx_6
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Set the specific parameters for a DMA transfer with transfer size, source
* address, and destination address.
* \snippet qs_usart_dma_use.c setup_tx_7
*
* -# Create the DMA transfer descriptor.
* \snippet qs_usart_dma_use.c setup_tx_8
*
* \section asfdoc_sam0_usart_dma_use_case_main Use Case
*
* \subsection asfdoc_sam0_usart_dma_use_case_main_code Code
* Copy-paste the following code to your user application:
* \snippet qs_usart_dma_use.c main
*
* \subsection asfdoc_sam0_usart_dma_use_case_main_flow Workflow
* -# Wait for receiving data.
* \snippet qs_usart_dma_use.c main_1
*
* -# Enter endless loop.
* \snippet qs_usart_dma_use.c endless_loop
*/

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/**
* \file
*
* \brief SAM USART LIN Quick Start
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_sercom_usart_lin_use_case Quick Start Guide for SERCOM USART LIN
*
* The supported board list:
* - SAMC21 Xplained Pro
*
* This quick start will set up LIN frame format transmission according to your
* configuration \c CONF_LIN_NODE_TYPE.
* For LIN master, it will send LIN command after startup.
* For LIN salve, once received a format from LIN master with ID \c LIN_ID_FIELD_VALUE,
* it will reply four data bytes plus a checksum.
*
* \section asfdoc_sam0_sercom_usart_lin_use_case_setup Setup
*
* \subsection asfdoc_sam0_sercom_usart_lin_use_case_prereq Prerequisites
* When verify data transmission between LIN master and slave, two boards are needed:
* one is for LIN master and the other is for LIN slave.
* connect LIN master LIN PIN with LIN slave LIN PIN.
*
* \subsection asfdoc_sam0_usart_lin_use_case_setup_code Code
* Add to the main application source file, outside of any functions:
* \snippet qs_lin.c module_var
*
* Copy-paste the following setup code to your user application:
* \snippet qs_lin.c setup
*
* Add to user application initialization (typically the start of \c main()):
* \snippet qs_lin.c setup_init
*
* \subsection asfdoc_sam0_usart_lin_use_case_setup_flow Workflow
* -# Create USART CDC and LIN module software instance structure for the USART module to store
* the USART driver state while it is in use.
* \snippet qs_lin.c module_inst
* -# Define LIN ID field for header format.
* \snippet qs_lin.c lin_id
* \note The ID \c LIN_ID_FIELD_VALUE is eight bits as [P1,P0,ID5...ID0], when it's 0x64, the
* data field length is four bytes plus a checksum byte.
*
* -# Define LIN RX/TX buffer.
* \snippet qs_lin.c lin_buffer
* \note For \c tx_buffer and \c rx_buffer, the last byte is for checksum.
*
* -# Configure the USART CDC for output message.
* \snippet qs_lin.c CDC_setup
*
* -# Configure the USART LIN module.
* \snippet qs_lin.c lin_setup
* \note The LIN frame format can be configured as master or slave, refer to \c CONF_LIN_NODE_TYPE .
*
* \section asfdoc_sam0_usart_lin_use_case_main Use Case
*
* \subsection asfdoc_sam0_usart_lin_use_case_main_code Code
* Copy-paste the following code to your user application:
* \snippet qs_lin.c main_setup
*
* \subsection asfdoc_sam0_usart_lin_use_case_main_flow Workflow
* -# Set up USART LIN module.
* \snippet qs_lin.c configure_lin
* -# For LIN master, sending LIN command. For LIN slaver, start reading data .
* \snippet qs_lin.c lin_master_cmd
*/

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software/firmware/project_oracle_test_firmware/d21/oracle_test_d21/oracle_test_d21/src/ASF/sam0/drivers/sercom/usart/usart.c
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@ -0,0 +1,806 @@
/**
* \file
*
* \brief SAM SERCOM USART Driver
*
* Copyright (c) 2012-2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "usart.h"
#include <pinmux.h>
#if USART_CALLBACK_MODE == true
# include "usart_interrupt.h"
#endif
/**
* \internal
* Set Configuration of the USART module
*/
static enum status_code _usart_set_config(
struct usart_module *const module,
const struct usart_config *const config)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Index for generic clock */
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
uint32_t gclk_index;
#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (SAMC21)
if (sercom_index == 5) {
gclk_index = SERCOM5_GCLK_ID_CORE;
} else {
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
}
#else
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
#endif
/* Cache new register values to minimize the number of register writes */
uint32_t ctrla = 0;
uint32_t ctrlb = 0;
#ifdef FEATURE_USART_ISO7816
uint32_t ctrlc = 0;
#endif
uint16_t baud = 0;
uint32_t transfer_mode;
enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
#ifdef FEATURE_USART_OVER_SAMPLE
switch (config->sample_rate) {
case USART_SAMPLE_RATE_16X_ARITHMETIC:
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
break;
case USART_SAMPLE_RATE_8X_ARITHMETIC:
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
break;
case USART_SAMPLE_RATE_3X_ARITHMETIC:
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
break;
case USART_SAMPLE_RATE_16X_FRACTIONAL:
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
break;
case USART_SAMPLE_RATE_8X_FRACTIONAL:
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
break;
}
#endif
/* Set data order, internal muxing, and clock polarity */
ctrla = (uint32_t)config->data_order |
(uint32_t)config->mux_setting |
#ifdef FEATURE_USART_OVER_SAMPLE
config->sample_adjustment |
config->sample_rate |
#endif
#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
#endif
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
enum status_code status_code = STATUS_OK;
transfer_mode = (uint32_t)config->transfer_mode;
#ifdef FEATURE_USART_ISO7816
if(config->iso7816_config.enabled) {
transfer_mode = config->iso7816_config.protocol_t;
}
#endif
/* Get baud value from mode and clock */
#ifdef FEATURE_USART_ISO7816
if(config->iso7816_config.enabled) {
baud = config->baudrate;
} else {
#endif
switch (transfer_mode)
{
case USART_TRANSFER_SYNCHRONOUSLY:
if (!config->use_external_clock) {
status_code = _sercom_get_sync_baud_val(config->baudrate,
system_gclk_chan_get_hz(gclk_index), &baud);
}
break;
case USART_TRANSFER_ASYNCHRONOUSLY:
if (config->use_external_clock) {
status_code =
_sercom_get_async_baud_val(config->baudrate,
config->ext_clock_freq, &baud, mode, sample_num);
} else {
status_code =
_sercom_get_async_baud_val(config->baudrate,
system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
}
break;
}
/* Check if calculating the baudrate failed */
if (status_code != STATUS_OK) {
/* Abort */
return status_code;
}
#ifdef FEATURE_USART_ISO7816
}
#endif
#ifdef FEATURE_USART_IRDA
if(config->encoding_format_enable) {
usart_hw->RXPL.reg = config->receive_pulse_length;
}
#endif
/*Set baud val */
usart_hw->BAUD.reg = baud;
/* Set sample mode */
ctrla |= transfer_mode;
if (config->use_external_clock == false) {
ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
}
else {
ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
}
/* Set stopbits and enable transceivers */
ctrlb =
#ifdef FEATURE_USART_IRDA
(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
#endif
#ifdef FEATURE_USART_START_FRAME_DECTION
(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
#endif
#ifdef FEATURE_USART_COLLISION_DECTION
(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
#endif
(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
#ifdef FEATURE_USART_ISO7816
if(config->iso7816_config.enabled) {
ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
if (config->iso7816_config.enable_inverse) {
ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
}
ctrlb |= USART_CHARACTER_SIZE_8BIT;
switch(config->iso7816_config.protocol_t) {
case ISO7816_PROTOCOL_T_0:
ctrlb |= (uint32_t)config->stopbits;
ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
(config->iso7816_config.inhibit_nack) | \
(config->iso7816_config.successive_recv_nack) | \
SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
break;
case ISO7816_PROTOCOL_T_1:
ctrlb |= USART_STOPBITS_1;
break;
}
} else {
#endif
ctrlb |= (uint32_t)config->stopbits;
ctrlb |= (uint32_t)config->character_size;
/* Check parity mode bits */
if (config->parity != USART_PARITY_NONE) {
ctrla |= SERCOM_USART_CTRLA_FORM(1);
ctrlb |= config->parity;
} else {
#ifdef FEATURE_USART_LIN_SLAVE
if(config->lin_slave_enable) {
ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
} else {
ctrla |= SERCOM_USART_CTRLA_FORM(0);
}
#else
ctrla |= SERCOM_USART_CTRLA_FORM(0);
#endif
}
#ifdef FEATURE_USART_ISO7816
}
#endif
#ifdef FEATURE_USART_LIN_MASTER
usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
| config->lin_header_delay
| config->lin_break_length;
if (config->lin_node != LIN_INVALID_MODE) {
ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
ctrla |= config->lin_node;
}
#endif
/* Set whether module should run in standby. */
if (config->run_in_standby || system_is_debugger_present()) {
ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
}
/* Wait until synchronization is complete */
_usart_wait_for_sync(module);
/* Write configuration to CTRLB */
usart_hw->CTRLB.reg = ctrlb;
/* Wait until synchronization is complete */
_usart_wait_for_sync(module);
/* Write configuration to CTRLA */
usart_hw->CTRLA.reg = ctrla;
#ifdef FEATURE_USART_RS485
if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
SERCOM_USART_CTRLA_FORM(0x07)) {
usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
}
#endif
#ifdef FEATURE_USART_ISO7816
if(config->iso7816_config.enabled) {
_usart_wait_for_sync(module);
usart_hw->CTRLC.reg = ctrlc;
}
#endif
return STATUS_OK;
}
/**
* \brief Initializes the device
*
* Initializes the USART device based on the setting specified in the
* configuration struct.
*
* \param[out] module Pointer to USART device
* \param[in] hw Pointer to USART hardware instance
* \param[in] config Pointer to configuration struct
*
* \return Status of the initialization.
*
* \retval STATUS_OK The initialization was successful
* \retval STATUS_BUSY The USART module is busy
* resetting
* \retval STATUS_ERR_DENIED The USART has not been disabled in
* advance of initialization
* \retval STATUS_ERR_INVALID_ARG The configuration struct contains
* invalid configuration
* \retval STATUS_ERR_ALREADY_INITIALIZED The SERCOM instance has already been
* initialized with different clock
* configuration
* \retval STATUS_ERR_BAUD_UNAVAILABLE The BAUD rate given by the
* configuration
* struct cannot be reached with
* the current clock configuration
*/
enum status_code usart_init(
struct usart_module *const module,
Sercom *const hw,
const struct usart_config *const config)
{
/* Sanity check arguments */
Assert(module);
Assert(hw);
Assert(config);
enum status_code status_code = STATUS_OK;
/* Assign module pointer to software instance struct */
module->hw = hw;
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
uint32_t pm_index, gclk_index;
#if (SAML22) || (SAMC20)
pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
#elif (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
if (sercom_index == 5) {
pm_index = MCLK_APBDMASK_SERCOM5_Pos;
gclk_index = SERCOM5_GCLK_ID_CORE;
} else {
pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
}
#elif (SAMC21)
pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
if (sercom_index == 5){
gclk_index = SERCOM5_GCLK_ID_CORE;
} else {
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
}
#else
pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
#endif
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
/* The module is busy resetting itself */
return STATUS_BUSY;
}
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
/* Check the module is enabled */
return STATUS_ERR_DENIED;
}
/* Turn on module in PM */
#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
if (sercom_index == 5) {
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
} else {
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
}
#else
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
#endif
/* Set up the GCLK for the module */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = config->generator_source;
system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
system_gclk_chan_enable(gclk_index);
sercom_set_gclk_generator(config->generator_source, false);
/* Set character size */
module->character_size = config->character_size;
/* Set transmitter and receiver status */
module->receiver_enabled = config->receiver_enable;
module->transmitter_enabled = config->transmitter_enable;
#ifdef FEATURE_USART_LIN_SLAVE
module->lin_slave_enabled = config->lin_slave_enable;
#endif
#ifdef FEATURE_USART_START_FRAME_DECTION
module->start_frame_detection_enabled = config->start_frame_detection_enable;
#endif
#ifdef FEATURE_USART_ISO7816
module->iso7816_mode_enabled = config->iso7816_config.enabled;
#endif
/* Set configuration according to the config struct */
status_code = _usart_set_config(module, config);
if(status_code != STATUS_OK) {
return status_code;
}
struct system_pinmux_config pin_conf;
system_pinmux_get_config_defaults(&pin_conf);
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
uint32_t pad_pinmuxes[] = {
config->pinmux_pad0, config->pinmux_pad1,
config->pinmux_pad2, config->pinmux_pad3
};
/* Configure the SERCOM pins according to the user configuration */
for (uint8_t pad = 0; pad < 4; pad++) {
uint32_t current_pinmux = pad_pinmuxes[pad];
if (current_pinmux == PINMUX_DEFAULT) {
current_pinmux = _sercom_get_default_pad(hw, pad);
}
if (current_pinmux != PINMUX_UNUSED) {
pin_conf.mux_position = current_pinmux & 0xFFFF;
system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
}
}
#if USART_CALLBACK_MODE == true
/* Initialize parameters */
for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
module->callback[i] = NULL;
}
module->tx_buffer_ptr = NULL;
module->rx_buffer_ptr = NULL;
module->remaining_tx_buffer_length = 0x0000;
module->remaining_rx_buffer_length = 0x0000;
module->callback_reg_mask = 0x00;
module->callback_enable_mask = 0x00;
module->rx_status = STATUS_OK;
module->tx_status = STATUS_OK;
/* Set interrupt handler and register USART software module struct in
* look-up table */
uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
_sercom_set_handler(instance_index, _usart_interrupt_handler);
_sercom_instances[instance_index] = module;
#endif
return status_code;
}
/**
* \brief Transmit a character via the USART
*
* This blocking function will transmit a single character via the
* USART.
*
* \param[in] module Pointer to the software instance struct
* \param[in] tx_data Data to transfer
*
* \return Status of the operation.
* \retval STATUS_OK If the operation was completed
* \retval STATUS_BUSY If the operation was not completed, due to the USART
* module being busy
* \retval STATUS_ERR_DENIED If the transmitter is not enabled
*/
enum status_code usart_write_wait(
struct usart_module *const module,
const uint16_t tx_data)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Check that the transmitter is enabled */
if (!(module->transmitter_enabled)) {
return STATUS_ERR_DENIED;
}
#if USART_CALLBACK_MODE == true
/* Check if the USART is busy doing asynchronous operation. */
if (module->remaining_tx_buffer_length > 0) {
return STATUS_BUSY;
}
#else
/* Check if USART is ready for new data */
if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
/* Return error code */
return STATUS_BUSY;
}
#endif
/* Write data to USART module */
usart_hw->DATA.reg = tx_data;
while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
/* Wait until data is sent */
}
return STATUS_OK;
}
/**
* \brief Receive a character via the USART
*
* This blocking function will receive a character via the USART.
*
* \param[in] module Pointer to the software instance struct
* \param[out] rx_data Pointer to received data
*
* \return Status of the operation.
* \retval STATUS_OK If the operation was completed
* \retval STATUS_BUSY If the operation was not completed,
* due to the USART module being busy
* \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
* due to configuration mismatch between USART
* and the sender
* \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
* due to the baudrate being too low or the
* system frequency being too high
* \retval STATUS_ERR_BAD_DATA If the operation was not completed, due to
* data being corrupted
* \retval STATUS_ERR_DENIED If the receiver is not enabled
*/
enum status_code usart_read_wait(
struct usart_module *const module,
uint16_t *const rx_data)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
/* Error variable */
uint8_t error_code;
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Check that the receiver is enabled */
if (!(module->receiver_enabled)) {
return STATUS_ERR_DENIED;
}
#if USART_CALLBACK_MODE == true
/* Check if the USART is busy doing asynchronous operation. */
if (module->remaining_rx_buffer_length > 0) {
return STATUS_BUSY;
}
#endif
/* Check if USART has new data */
if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
/* Return error code */
return STATUS_BUSY;
}
/* Read out the status code and mask away all but the 3 LSBs*/
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
/* Check if an error has occurred during the receiving */
if (error_code) {
/* Check which error occurred */
if (error_code & SERCOM_USART_STATUS_FERR) {
/* Clear flag by writing a 1 to it and
* return with an error code */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
return STATUS_ERR_BAD_FORMAT;
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
/* Clear flag by writing a 1 to it and
* return with an error code */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
return STATUS_ERR_OVERFLOW;
} else if (error_code & SERCOM_USART_STATUS_PERR) {
/* Clear flag by writing a 1 to it and
* return with an error code */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
return STATUS_ERR_BAD_DATA;
}
#ifdef FEATURE_USART_LIN_SLAVE
else if (error_code & SERCOM_USART_STATUS_ISF) {
/* Clear flag by writing 1 to it and
* return with an error code */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
return STATUS_ERR_PROTOCOL;
}
#endif
#ifdef FEATURE_USART_COLLISION_DECTION
else if (error_code & SERCOM_USART_STATUS_COLL) {
/* Clear flag by writing 1 to it
* return with an error code */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
return STATUS_ERR_PACKET_COLLISION;
}
#endif
}
/* Read data from USART module */
*rx_data = usart_hw->DATA.reg;
return STATUS_OK;
}
/**
* \brief Transmit a buffer of characters via the USART
*
* This blocking function will transmit a block of \c length characters
* via the USART.
*
* \note Using this function in combination with the interrupt (\c _job) functions is
* not recommended as it has no functionality to check if there is an
* ongoing interrupt driven operation running or not.
*
* \param[in] module Pointer to USART software instance struct
* \param[in] tx_data Pointer to data to transmit
* \param[in] length Number of characters to transmit
*
* \note If using 9-bit data, the array that *tx_data point to should be defined
* as uint16_t array and should be casted to uint8_t* pointer. Because it
* is an address pointer, the highest byte is not discarded. For example:
* \code
#define TX_LEN 3
uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
\endcode
*
* \return Status of the operation.
* \retval STATUS_OK If operation was completed
* \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
* arguments
* \retval STATUS_ERR_TIMEOUT If operation was not completed, due to USART
* module timing out
* \retval STATUS_ERR_DENIED If the transmitter is not enabled
*/
enum status_code usart_write_buffer_wait(
struct usart_module *const module,
const uint8_t *tx_data,
uint16_t length)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
/* Check if the buffer length is valid */
if (length == 0) {
return STATUS_ERR_INVALID_ARG;
}
/* Check that the transmitter is enabled */
if (!(module->transmitter_enabled)) {
return STATUS_ERR_DENIED;
}
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
uint16_t tx_pos = 0;
/* Blocks while buffer is being transferred */
while (length--) {
/* Wait for the USART to be ready for new data and abort
* operation if it doesn't get ready within the timeout*/
for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
break;
} else if (i == USART_TIMEOUT) {
return STATUS_ERR_TIMEOUT;
}
}
/* Data to send is at least 8 bits long */
uint16_t data_to_send = tx_data[tx_pos++];
/* Check if the character size exceeds 8 bit */
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
data_to_send |= (tx_data[tx_pos++] << 8);
}
/* Send the data through the USART module */
usart_write_wait(module, data_to_send);
}
/* Wait until Transmit is complete or timeout */
for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
break;
} else if (i == USART_TIMEOUT) {
return STATUS_ERR_TIMEOUT;
}
}
return STATUS_OK;
}
/**
* \brief Receive a buffer of \c length characters via the USART
*
* This blocking function will receive a block of \c length characters
* via the USART.
*
* \note Using this function in combination with the interrupt (\c *_job)
* functions is not recommended as it has no functionality to check if
* there is an ongoing interrupt driven operation running or not.
*
* \param[in] module Pointer to USART software instance struct
* \param[out] rx_data Pointer to receive buffer
* \param[in] length Number of characters to receive
*
* \note If using 9-bit data, the array that *rx_data point to should be defined
* as uint16_t array and should be casted to uint8_t* pointer. Because it
* is an address pointer, the highest byte is not discarded. For example:
* \code
#define RX_LEN 3
uint16_t rx_buf[RX_LEN] = {0x0,};
usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
\endcode
*
* \return Status of the operation.
* \retval STATUS_OK If operation was completed
* \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to an
* invalid argument being supplied
* \retval STATUS_ERR_TIMEOUT If operation was not completed, due
* to USART module timing out
* \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
* due to a configuration mismatch
* between USART and the sender
* \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
* due to the baudrate being too low or the
* system frequency being too high
* \retval STATUS_ERR_BAD_DATA If the operation was not completed, due
* to data being corrupted
* \retval STATUS_ERR_DENIED If the receiver is not enabled
*/
enum status_code usart_read_buffer_wait(
struct usart_module *const module,
uint8_t *rx_data,
uint16_t length)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
/* Check if the buffer length is valid */
if (length == 0) {
return STATUS_ERR_INVALID_ARG;
}
/* Check that the receiver is enabled */
if (!(module->receiver_enabled)) {
return STATUS_ERR_DENIED;
}
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
uint16_t rx_pos = 0;
/* Blocks while buffer is being received */
while (length--) {
/* Wait for the USART to have new data and abort operation if it
* doesn't get ready within the timeout*/
for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
break;
} else if (i == USART_TIMEOUT) {
return STATUS_ERR_TIMEOUT;
}
}
enum status_code retval;
uint16_t received_data = 0;
retval = usart_read_wait(module, &received_data);
if (retval != STATUS_OK) {
/* Overflow, abort */
return retval;
}
/* Read value will be at least 8-bits long */
rx_data[rx_pos++] = received_data;
/* If 9-bit data, write next received byte to the buffer */
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
rx_data[rx_pos++] = (received_data >> 8);
}
}
return STATUS_OK;
}

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/**
* \file
*
* \brief SAM SERCOM USART Asynchronous Driver
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*