added testing sw for xplained
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<environment>
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<configurations/>
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<device-packs>
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<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
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</device-packs>
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</environment>
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<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
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<vendor>Atmel</vendor>
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<name>My Project</name>
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<description>Project generated by Atmel Start</description>
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<url>http://start.atmel.com/</url>
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<releases>
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<release version="1.0.1">Initial version</release>
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</releases>
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<taxonomy>
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<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
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</taxonomy>
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<generators>
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<generator id="AtmelStart">
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<description>Atmel Start</description>
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<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
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<command>http://start.atmel.com/</command>
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<files>
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<file category="generator" name="atmel_start_config.atstart"/>
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<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
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</files>
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</generator>
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</generators>
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<conditions>
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<condition id="CMSIS Device Startup">
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<description>Dependency on CMSIS core and Device Startup components</description>
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<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
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<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
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</condition>
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<condition id="ARMCC, GCC, IAR">
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<require Dname="ATSAME54P20A"/>
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<accept Tcompiler="ARMCC"/>
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<accept Tcompiler="GCC"/>
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<accept Tcompiler="IAR"/>
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</condition>
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<condition id="GCC">
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<require Dname="ATSAME54P20A"/>
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<accept Tcompiler="GCC"/>
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</condition>
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</conditions>
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<components generator="AtmelStart">
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<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
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<description>Atmel Start Framework</description>
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<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
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<files>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/timer.rst"/>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
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<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gmac_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_timer.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_timer.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
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<file category="include" condition="ARMCC, GCC, IAR" name=""/>
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<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
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<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
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<file category="include" condition="ARMCC, GCC, IAR" name=""/>
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</files>
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</component>
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</components>
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</package>
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/**
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* \file
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*
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* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
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*
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* Copyright (c) 2012 Atmel Corporation. All rights reserved.
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*
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* \acme_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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||||
* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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||||
* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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||||
* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \acme_license_stop
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*
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* Project: same54_gfx_4_19_20
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* Target: ATSAME54P20A
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*
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**/
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#ifndef RTE_COMPONENTS_H
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#define RTE_COMPONENTS_H
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#define ATMEL_START
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#endif /* RTE_COMPONENTS_H */
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/* Auto-generated config file hpl_cmcc_config.h */
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#ifndef HPL_CMCC_CONFIG_H
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#define HPL_CMCC_CONFIG_H
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||||
// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Basic Configuration
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||||
|
||||
// <q> Cache enable
|
||||
//<i> Defines the cache should be enabled or not.
|
||||
// <id> cmcc_enable
|
||||
#ifndef CONF_CMCC_ENABLE
|
||||
#define CONF_CMCC_ENABLE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Cache Size
|
||||
//<i> Defines the cache memory size to be configured.
|
||||
// <0x0=>1 KB
|
||||
// <0x1=>2 KB
|
||||
// <0x2=>4 KB
|
||||
// <id> cache_size
|
||||
#ifndef CONF_CMCC_CACHE_SIZE
|
||||
#define CONF_CMCC_CACHE_SIZE 0x2
|
||||
#endif
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> cmcc_advanced_configuration
|
||||
// <q> Data cache disable
|
||||
//<i> Defines the data cache should be disabled or not.
|
||||
// <id> cmcc_data_cache_disable
|
||||
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
|
||||
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// <q> Instruction cache disable
|
||||
//<i> Defines the Instruction cache should be disabled or not.
|
||||
// <id> cmcc_inst_cache_disable
|
||||
#ifndef CONF_CMCC_INST_CACHE_DISABLE
|
||||
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// <q> Clock Gating disable
|
||||
//<i> Defines the clock gating should be disabled or not.
|
||||
// <id> cmcc_clock_gating_disable
|
||||
#ifndef CONF_CMCC_CLK_GATING_DISABLE
|
||||
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_CMCC_CONFIG_H
|
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,920 @@
|
||||
/* Auto-generated config file hpl_gclk_config.h */
|
||||
#ifndef HPL_GCLK_CONFIG_H
|
||||
#define HPL_GCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> Generic clock generator 0 configuration
|
||||
// <i> Indicates whether generic clock 0 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_0
|
||||
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_0_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 0 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 0
|
||||
// <id> gclk_gen_0_oscillator
|
||||
#ifndef CONF_GCLK_GEN_0_SOURCE
|
||||
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_0_runstdby
|
||||
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_0_div_sel
|
||||
#ifndef CONF_GCLK_GEN_0_DIVSEL
|
||||
#define CONF_GCLK_GEN_0_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_oe
|
||||
#ifndef CONF_GCLK_GEN_0_OE
|
||||
#define CONF_GCLK_GEN_0_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_0_oov
|
||||
#ifndef CONF_GCLK_GEN_0_OOV
|
||||
#define CONF_GCLK_GEN_0_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_0_idc
|
||||
#ifndef CONF_GCLK_GEN_0_IDC
|
||||
#define CONF_GCLK_GEN_0_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_enable
|
||||
#ifndef CONF_GCLK_GEN_0_GENEN
|
||||
#define CONF_GCLK_GEN_0_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_0_div
|
||||
#ifndef CONF_GCLK_GEN_0_DIV
|
||||
#define CONF_GCLK_GEN_0_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 1 configuration
|
||||
// <i> Indicates whether generic clock 1 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_1
|
||||
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 1 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 1
|
||||
// <id> gclk_gen_1_oscillator
|
||||
#ifndef CONF_GCLK_GEN_1_SOURCE
|
||||
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_1_runstdby
|
||||
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_1_div_sel
|
||||
#ifndef CONF_GCLK_GEN_1_DIVSEL
|
||||
#define CONF_GCLK_GEN_1_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_oe
|
||||
#ifndef CONF_GCLK_GEN_1_OE
|
||||
#define CONF_GCLK_GEN_1_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_1_oov
|
||||
#ifndef CONF_GCLK_GEN_1_OOV
|
||||
#define CONF_GCLK_GEN_1_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_1_idc
|
||||
#ifndef CONF_GCLK_GEN_1_IDC
|
||||
#define CONF_GCLK_GEN_1_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_enable
|
||||
#ifndef CONF_GCLK_GEN_1_GENEN
|
||||
#define CONF_GCLK_GEN_1_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_1_div
|
||||
#ifndef CONF_GCLK_GEN_1_DIV
|
||||
#define CONF_GCLK_GEN_1_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 2 configuration
|
||||
// <i> Indicates whether generic clock 2 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_2
|
||||
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_2_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 2 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 2
|
||||
// <id> gclk_gen_2_oscillator
|
||||
#ifndef CONF_GCLK_GEN_2_SOURCE
|
||||
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_2_runstdby
|
||||
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_2_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_2_div_sel
|
||||
#ifndef CONF_GCLK_GEN_2_DIVSEL
|
||||
#define CONF_GCLK_GEN_2_DIVSEL 1
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_oe
|
||||
#ifndef CONF_GCLK_GEN_2_OE
|
||||
#define CONF_GCLK_GEN_2_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_2_oov
|
||||
#ifndef CONF_GCLK_GEN_2_OOV
|
||||
#define CONF_GCLK_GEN_2_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_2_idc
|
||||
#ifndef CONF_GCLK_GEN_2_IDC
|
||||
#define CONF_GCLK_GEN_2_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_enable
|
||||
#ifndef CONF_GCLK_GEN_2_GENEN
|
||||
#define CONF_GCLK_GEN_2_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_2_div
|
||||
#ifndef CONF_GCLK_GEN_2_DIV
|
||||
#define CONF_GCLK_GEN_2_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 3 configuration
|
||||
// <i> Indicates whether generic clock 3 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_3
|
||||
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_3_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 3 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 3
|
||||
// <id> gclk_gen_3_oscillator
|
||||
#ifndef CONF_GCLK_GEN_3_SOURCE
|
||||
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_3_runstdby
|
||||
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_3_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_3_div_sel
|
||||
#ifndef CONF_GCLK_GEN_3_DIVSEL
|
||||
#define CONF_GCLK_GEN_3_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_oe
|
||||
#ifndef CONF_GCLK_GEN_3_OE
|
||||
#define CONF_GCLK_GEN_3_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_3_oov
|
||||
#ifndef CONF_GCLK_GEN_3_OOV
|
||||
#define CONF_GCLK_GEN_3_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_3_idc
|
||||
#ifndef CONF_GCLK_GEN_3_IDC
|
||||
#define CONF_GCLK_GEN_3_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_enable
|
||||
#ifndef CONF_GCLK_GEN_3_GENEN
|
||||
#define CONF_GCLK_GEN_3_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_3_div
|
||||
#ifndef CONF_GCLK_GEN_3_DIV
|
||||
#define CONF_GCLK_GEN_3_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 4 configuration
|
||||
// <i> Indicates whether generic clock 4 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_4
|
||||
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_4_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 4 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 4
|
||||
// <id> gclk_gen_4_oscillator
|
||||
#ifndef CONF_GCLK_GEN_4_SOURCE
|
||||
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_4_runstdby
|
||||
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_4_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_4_div_sel
|
||||
#ifndef CONF_GCLK_GEN_4_DIVSEL
|
||||
#define CONF_GCLK_GEN_4_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_oe
|
||||
#ifndef CONF_GCLK_GEN_4_OE
|
||||
#define CONF_GCLK_GEN_4_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_4_oov
|
||||
#ifndef CONF_GCLK_GEN_4_OOV
|
||||
#define CONF_GCLK_GEN_4_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_4_idc
|
||||
#ifndef CONF_GCLK_GEN_4_IDC
|
||||
#define CONF_GCLK_GEN_4_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_enable
|
||||
#ifndef CONF_GCLK_GEN_4_GENEN
|
||||
#define CONF_GCLK_GEN_4_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_4_div
|
||||
#ifndef CONF_GCLK_GEN_4_DIV
|
||||
#define CONF_GCLK_GEN_4_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 5 configuration
|
||||
// <i> Indicates whether generic clock 5 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_5
|
||||
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_5_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 5 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 5
|
||||
// <id> gclk_gen_5_oscillator
|
||||
#ifndef CONF_GCLK_GEN_5_SOURCE
|
||||
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_5_runstdby
|
||||
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_5_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_5_div_sel
|
||||
#ifndef CONF_GCLK_GEN_5_DIVSEL
|
||||
#define CONF_GCLK_GEN_5_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_oe
|
||||
#ifndef CONF_GCLK_GEN_5_OE
|
||||
#define CONF_GCLK_GEN_5_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_5_oov
|
||||
#ifndef CONF_GCLK_GEN_5_OOV
|
||||
#define CONF_GCLK_GEN_5_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_5_idc
|
||||
#ifndef CONF_GCLK_GEN_5_IDC
|
||||
#define CONF_GCLK_GEN_5_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_enable
|
||||
#ifndef CONF_GCLK_GEN_5_GENEN
|
||||
#define CONF_GCLK_GEN_5_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_5_div
|
||||
#ifndef CONF_GCLK_GEN_5_DIV
|
||||
#define CONF_GCLK_GEN_5_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 6 configuration
|
||||
// <i> Indicates whether generic clock 6 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_6
|
||||
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_6_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 6 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 6
|
||||
// <id> gclk_gen_6_oscillator
|
||||
#ifndef CONF_GCLK_GEN_6_SOURCE
|
||||
#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_6_runstdby
|
||||
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_6_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_6_div_sel
|
||||
#ifndef CONF_GCLK_GEN_6_DIVSEL
|
||||
#define CONF_GCLK_GEN_6_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_oe
|
||||
#ifndef CONF_GCLK_GEN_6_OE
|
||||
#define CONF_GCLK_GEN_6_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_6_oov
|
||||
#ifndef CONF_GCLK_GEN_6_OOV
|
||||
#define CONF_GCLK_GEN_6_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_6_idc
|
||||
#ifndef CONF_GCLK_GEN_6_IDC
|
||||
#define CONF_GCLK_GEN_6_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_enable
|
||||
#ifndef CONF_GCLK_GEN_6_GENEN
|
||||
#define CONF_GCLK_GEN_6_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_6_div
|
||||
#ifndef CONF_GCLK_GEN_6_DIV
|
||||
#define CONF_GCLK_GEN_6_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 7 configuration
|
||||
// <i> Indicates whether generic clock 7 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_7
|
||||
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_7_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 7 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 7
|
||||
// <id> gclk_gen_7_oscillator
|
||||
#ifndef CONF_GCLK_GEN_7_SOURCE
|
||||
#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_7_runstdby
|
||||
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_7_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_7_div_sel
|
||||
#ifndef CONF_GCLK_GEN_7_DIVSEL
|
||||
#define CONF_GCLK_GEN_7_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_oe
|
||||
#ifndef CONF_GCLK_GEN_7_OE
|
||||
#define CONF_GCLK_GEN_7_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_7_oov
|
||||
#ifndef CONF_GCLK_GEN_7_OOV
|
||||
#define CONF_GCLK_GEN_7_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_7_idc
|
||||
#ifndef CONF_GCLK_GEN_7_IDC
|
||||
#define CONF_GCLK_GEN_7_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_enable
|
||||
#ifndef CONF_GCLK_GEN_7_GENEN
|
||||
#define CONF_GCLK_GEN_7_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_7_div
|
||||
#ifndef CONF_GCLK_GEN_7_DIV
|
||||
#define CONF_GCLK_GEN_7_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 8 configuration
|
||||
// <i> Indicates whether generic clock 8 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_8
|
||||
#ifndef CONF_GCLK_GENERATOR_8_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_8_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 8 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 8
|
||||
// <id> gclk_gen_8_oscillator
|
||||
#ifndef CONF_GCLK_GEN_8_SOURCE
|
||||
#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_8_runstdby
|
||||
#ifndef CONF_GCLK_GEN_8_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_8_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_8_div_sel
|
||||
#ifndef CONF_GCLK_GEN_8_DIVSEL
|
||||
#define CONF_GCLK_GEN_8_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_oe
|
||||
#ifndef CONF_GCLK_GEN_8_OE
|
||||
#define CONF_GCLK_GEN_8_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_8_oov
|
||||
#ifndef CONF_GCLK_GEN_8_OOV
|
||||
#define CONF_GCLK_GEN_8_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_8_idc
|
||||
#ifndef CONF_GCLK_GEN_8_IDC
|
||||
#define CONF_GCLK_GEN_8_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_enable
|
||||
#ifndef CONF_GCLK_GEN_8_GENEN
|
||||
#define CONF_GCLK_GEN_8_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 8 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_8_div
|
||||
#ifndef CONF_GCLK_GEN_8_DIV
|
||||
#define CONF_GCLK_GEN_8_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 9 configuration
|
||||
// <i> Indicates whether generic clock 9 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_9
|
||||
#ifndef CONF_GCLK_GENERATOR_9_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_9_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 9 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 9
|
||||
// <id> gclk_gen_9_oscillator
|
||||
#ifndef CONF_GCLK_GEN_9_SOURCE
|
||||
#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_9_runstdby
|
||||
#ifndef CONF_GCLK_GEN_9_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_9_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_9_div_sel
|
||||
#ifndef CONF_GCLK_GEN_9_DIVSEL
|
||||
#define CONF_GCLK_GEN_9_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_oe
|
||||
#ifndef CONF_GCLK_GEN_9_OE
|
||||
#define CONF_GCLK_GEN_9_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_9_oov
|
||||
#ifndef CONF_GCLK_GEN_9_OOV
|
||||
#define CONF_GCLK_GEN_9_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_9_idc
|
||||
#ifndef CONF_GCLK_GEN_9_IDC
|
||||
#define CONF_GCLK_GEN_9_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_enable
|
||||
#ifndef CONF_GCLK_GEN_9_GENEN
|
||||
#define CONF_GCLK_GEN_9_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 9 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_9_div
|
||||
#ifndef CONF_GCLK_GEN_9_DIV
|
||||
#define CONF_GCLK_GEN_9_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 10 configuration
|
||||
// <i> Indicates whether generic clock 10 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_10
|
||||
#ifndef CONF_GCLK_GENERATOR_10_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_10_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 10 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 10
|
||||
// <id> gclk_gen_10_oscillator
|
||||
#ifndef CONF_GCLK_GEN_10_SOURCE
|
||||
#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_10_runstdby
|
||||
#ifndef CONF_GCLK_GEN_10_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_10_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_10_div_sel
|
||||
#ifndef CONF_GCLK_GEN_10_DIVSEL
|
||||
#define CONF_GCLK_GEN_10_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_oe
|
||||
#ifndef CONF_GCLK_GEN_10_OE
|
||||
#define CONF_GCLK_GEN_10_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_10_oov
|
||||
#ifndef CONF_GCLK_GEN_10_OOV
|
||||
#define CONF_GCLK_GEN_10_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_10_idc
|
||||
#ifndef CONF_GCLK_GEN_10_IDC
|
||||
#define CONF_GCLK_GEN_10_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_enable
|
||||
#ifndef CONF_GCLK_GEN_10_GENEN
|
||||
#define CONF_GCLK_GEN_10_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 10 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_10_div
|
||||
#ifndef CONF_GCLK_GEN_10_DIV
|
||||
#define CONF_GCLK_GEN_10_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 11 configuration
|
||||
// <i> Indicates whether generic clock 11 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_11
|
||||
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_11_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 11 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 11
|
||||
// <id> gclk_gen_11_oscillator
|
||||
#ifndef CONF_GCLK_GEN_11_SOURCE
|
||||
#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_11_runstdby
|
||||
#ifndef CONF_GCLK_GEN_11_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_11_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_11_div_sel
|
||||
#ifndef CONF_GCLK_GEN_11_DIVSEL
|
||||
#define CONF_GCLK_GEN_11_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_oe
|
||||
#ifndef CONF_GCLK_GEN_11_OE
|
||||
#define CONF_GCLK_GEN_11_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_11_oov
|
||||
#ifndef CONF_GCLK_GEN_11_OOV
|
||||
#define CONF_GCLK_GEN_11_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_11_idc
|
||||
#ifndef CONF_GCLK_GEN_11_IDC
|
||||
#define CONF_GCLK_GEN_11_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_enable
|
||||
#ifndef CONF_GCLK_GEN_11_GENEN
|
||||
#define CONF_GCLK_GEN_11_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_11_div
|
||||
#ifndef CONF_GCLK_GEN_11_DIV
|
||||
#define CONF_GCLK_GEN_11_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_GCLK_CONFIG_H
|
@ -0,0 +1,104 @@
|
||||
/* Auto-generated config file hpl_mclk_config.h */
|
||||
#ifndef HPL_MCLK_CONFIG_H
|
||||
#define HPL_MCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// <e> System Configuration
|
||||
// <i> Indicates whether configuration for system is enabled or not
|
||||
// <id> enable_cpu_clock
|
||||
#ifndef CONF_SYSTEM_CONFIG
|
||||
#define CONF_SYSTEM_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Basic settings
|
||||
// <y> CPU Clock source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <i> This defines the clock source for the CPU
|
||||
// <id> cpu_clock_source
|
||||
#ifndef CONF_CPU_SRC
|
||||
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> CPU Clock Division Factor
|
||||
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
|
||||
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
|
||||
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
|
||||
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
|
||||
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
|
||||
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
|
||||
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
|
||||
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
|
||||
// <i> Prescalar for CPU clock
|
||||
// <id> cpu_div
|
||||
#ifndef CONF_MCLK_CPUDIV
|
||||
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// <y> Low Power Clock Division
|
||||
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_lpdiv
|
||||
#ifndef CONF_MCLK_LPDIV
|
||||
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
|
||||
#endif
|
||||
|
||||
// <y> Backup Clock Division
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_bupdiv
|
||||
#ifndef CONF_MCLK_BUPDIV
|
||||
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
|
||||
#endif
|
||||
// <y> High-Speed Clock Division
|
||||
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
|
||||
// <id> mclk_arch_hsdiv
|
||||
#ifndef CONF_MCLK_HSDIV
|
||||
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> NVM Settings
|
||||
// <o> NVM Wait States
|
||||
// <i> These bits select the number of wait states for a read operation.
|
||||
// <0=> 0
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
// <10=> 10
|
||||
// <11=> 11
|
||||
// <12=> 12
|
||||
// <13=> 13
|
||||
// <14=> 14
|
||||
// <15=> 15
|
||||
// <id> nvm_wait_states
|
||||
#ifndef CONF_NVM_WAIT_STATE
|
||||
#define CONF_NVM_WAIT_STATE 5
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_MCLK_CONFIG_H
|
@ -0,0 +1,165 @@
|
||||
/* Auto-generated config file hpl_osc32kctrl_config.h */
|
||||
#ifndef HPL_OSC32KCTRL_CONFIG_H
|
||||
#define HPL_OSC32KCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> RTC Source configuration
|
||||
// <id> enable_rtc_source
|
||||
#ifndef CONF_RTCCTRL_CONFIG
|
||||
#define CONF_RTCCTRL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> RTC source control
|
||||
// <y> RTC Clock Source Selection
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <i> This defines the clock source for RTC
|
||||
// <id> rtc_source_oscillator
|
||||
#ifndef CONF_RTCCTRL_SRC
|
||||
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#endif
|
||||
|
||||
// <q> Use 1 kHz output
|
||||
// <id> rtc_1khz_selection
|
||||
#ifndef CONF_RTCCTRL_1KHZ
|
||||
|
||||
#define CONF_RTCCTRL_1KHZ 0
|
||||
|
||||
#endif
|
||||
|
||||
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
|
||||
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
|
||||
#else
|
||||
#error unexpected CONF_RTCCTRL_SRC
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz External Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for External 32K Osc is enabled or not
|
||||
// <id> enable_xosc32k
|
||||
#ifndef CONF_XOSC32K_CONFIG
|
||||
#define CONF_XOSC32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz External Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
|
||||
// <id> xosc32k_arch_enable
|
||||
#ifndef CONF_XOSC32K_ENABLE
|
||||
#define CONF_XOSC32K_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>62592us
|
||||
// <0x1=>125092us
|
||||
// <0x2=>500092us
|
||||
// <0x3=>1000092us
|
||||
// <0x4=>2000092us
|
||||
// <0x5=>4000092us
|
||||
// <0x6=>8000092us
|
||||
// <id> xosc32k_arch_startup
|
||||
#ifndef CONF_XOSC32K_STARTUP
|
||||
#define CONF_XOSC32K_STARTUP 0x3
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc32k_arch_ondemand
|
||||
#ifndef CONF_XOSC32K_ONDEMAND
|
||||
#define CONF_XOSC32K_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc32k_arch_runstdby
|
||||
#ifndef CONF_XOSC32K_RUNSTDBY
|
||||
#define CONF_XOSC32K_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> 1kHz Output Enable
|
||||
// <i> Indicates whether 1kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en1k
|
||||
#ifndef CONF_XOSC32K_EN1K
|
||||
#define CONF_XOSC32K_EN1K 0
|
||||
#endif
|
||||
|
||||
// <q> 32kHz Output Enable
|
||||
// <i> Indicates whether 32kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en32k
|
||||
#ifndef CONF_XOSC32K_EN32K
|
||||
#define CONF_XOSC32K_EN32K 1
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc32k_arch_swben
|
||||
#ifndef CONF_XOSC32K_SWBEN
|
||||
#define CONF_XOSC32K_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc32k_arch_cfden
|
||||
#ifndef CONF_XOSC32K_CFDEN
|
||||
#define CONF_XOSC32K_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector Event Out
|
||||
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
|
||||
// <id> xosc32k_arch_cfdeo
|
||||
#ifndef CONF_XOSC32K_CFDEO
|
||||
#define CONF_XOSC32K_CFDEO 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN32/XOUT32 Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc32k_arch_xtalen
|
||||
#ifndef CONF_XOSC32K_XTALEN
|
||||
#define CONF_XOSC32K_XTALEN 1
|
||||
#endif
|
||||
|
||||
// <o> Control Gain Mode
|
||||
// <0x0=>Low Power mode
|
||||
// <0x1=>Standard mode
|
||||
// <0x2=>High Speed mode
|
||||
// <id> xosc32k_arch_cgm
|
||||
#ifndef CONF_XOSC32K_CGM
|
||||
#define CONF_XOSC32K_CGM 0x1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for OSCULP32K is enabled or not
|
||||
// <id> enable_osculp32k
|
||||
#ifndef CONF_OSCULP32K_CONFIG
|
||||
#define CONF_OSCULP32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz Ultra Low Power Internal Oscillator Control
|
||||
|
||||
// <q> Oscillator Calibration Control
|
||||
// <i> Indicates whether Oscillator Calibration is enabled or not
|
||||
// <id> osculp32k_calib_enable
|
||||
#ifndef CONF_OSCULP32K_CALIB_ENABLE
|
||||
#define CONF_OSCULP32K_CALIB_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Oscillator Calibration <0x0-0x3F>
|
||||
// <id> osculp32k_calib
|
||||
#ifndef CONF_OSCULP32K_CALIB
|
||||
#define CONF_OSCULP32K_CALIB 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSC32KCTRL_CONFIG_H
|
@ -0,0 +1,640 @@
|
||||
/* Auto-generated config file hpl_oscctrl_config.h */
|
||||
#ifndef HPL_OSCCTRL_CONFIG_H
|
||||
#define HPL_OSCCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC0 is enabled or not
|
||||
// <id> enable_xosc0
|
||||
#ifndef CONF_XOSC0_CONFIG
|
||||
#define CONF_XOSC0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc0_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC0_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc0_arch_enable
|
||||
#ifndef CONF_XOSC0_ENABLE
|
||||
#define CONF_XOSC0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc0_arch_startup
|
||||
#ifndef CONF_XOSC0_STARTUP
|
||||
#define CONF_XOSC0_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc0_arch_swben
|
||||
#ifndef CONF_XOSC0_SWBEN
|
||||
#define CONF_XOSC0_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc0_arch_cfden
|
||||
#ifndef CONF_XOSC0_CFDEN
|
||||
#define CONF_XOSC0_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc0_arch_enalc
|
||||
#ifndef CONF_XOSC0_ENALC
|
||||
#define CONF_XOSC0_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc0_arch_lowbufgain
|
||||
#ifndef CONF_XOSC0_LOWBUFGAIN
|
||||
#define CONF_XOSC0_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc0_arch_ondemand
|
||||
#ifndef CONF_XOSC0_ONDEMAND
|
||||
#define CONF_XOSC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc0_arch_runstdby
|
||||
#ifndef CONF_XOSC0_RUNSTDBY
|
||||
#define CONF_XOSC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc0_arch_xtalen
|
||||
#ifndef CONF_XOSC0_XTALEN
|
||||
#define CONF_XOSC0_XTALEN 0
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC0_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x0
|
||||
#define CONF_XOSC0_IMULT 0x7
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x1
|
||||
#define CONF_XOSC0_IMULT 0x6
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x2
|
||||
#define CONF_XOSC0_IMULT 0x5
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x3
|
||||
#define CONF_XOSC0_IMULT 0x4
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC1 is enabled or not
|
||||
// <id> enable_xosc1
|
||||
#ifndef CONF_XOSC1_CONFIG
|
||||
#define CONF_XOSC1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc1_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC1_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc1_arch_enable
|
||||
#ifndef CONF_XOSC1_ENABLE
|
||||
#define CONF_XOSC1_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc1_arch_startup
|
||||
#ifndef CONF_XOSC1_STARTUP
|
||||
#define CONF_XOSC1_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc1_arch_swben
|
||||
#ifndef CONF_XOSC1_SWBEN
|
||||
#define CONF_XOSC1_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc1_arch_cfden
|
||||
#ifndef CONF_XOSC1_CFDEN
|
||||
#define CONF_XOSC1_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc1_arch_enalc
|
||||
#ifndef CONF_XOSC1_ENALC
|
||||
#define CONF_XOSC1_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc1_arch_lowbufgain
|
||||
#ifndef CONF_XOSC1_LOWBUFGAIN
|
||||
#define CONF_XOSC1_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc1_arch_ondemand
|
||||
#ifndef CONF_XOSC1_ONDEMAND
|
||||
#define CONF_XOSC1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc1_arch_runstdby
|
||||
#ifndef CONF_XOSC1_RUNSTDBY
|
||||
#define CONF_XOSC1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc1_arch_xtalen
|
||||
#ifndef CONF_XOSC1_XTALEN
|
||||
#define CONF_XOSC1_XTALEN 1
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC1_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x0
|
||||
#define CONF_XOSC1_IMULT 0x7
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x1
|
||||
#define CONF_XOSC1_IMULT 0x6
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x2
|
||||
#define CONF_XOSC1_IMULT 0x5
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x3
|
||||
#define CONF_XOSC1_IMULT 0x4
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> DFLL Configuration
|
||||
// <i> Indicates whether configuration for DFLL is enabled or not
|
||||
// <id> enable_dfll
|
||||
#ifndef CONF_DFLL_CONFIG
|
||||
#define CONF_DFLL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source
|
||||
// <id> dfll_ref_clock
|
||||
#ifndef CONF_DFLL_GCLK
|
||||
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Frequency Locked Loop Control
|
||||
// <q> DFLL Enable
|
||||
// <i> Indicates whether DFLL is enabled or not
|
||||
// <id> dfll_arch_enable
|
||||
#ifndef CONF_DFLL_ENABLE
|
||||
#define CONF_DFLL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> dfll_arch_ondemand
|
||||
#ifndef CONF_DFLL_ONDEMAND
|
||||
#define CONF_DFLL_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> dfll_arch_runstdby
|
||||
#ifndef CONF_DFLL_RUNSTDBY
|
||||
#define CONF_DFLL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> USB Clock Recovery Mode
|
||||
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
|
||||
// <id> dfll_arch_usbcrm
|
||||
#ifndef CONF_DFLL_USBCRM
|
||||
#define CONF_DFLL_USBCRM 0
|
||||
#endif
|
||||
|
||||
// <q> Wait Lock
|
||||
// <i> Indicates whether Wait Lock is enabled or not
|
||||
// <id> dfll_arch_waitlock
|
||||
#ifndef CONF_DFLL_WAITLOCK
|
||||
#define CONF_DFLL_WAITLOCK 1
|
||||
#endif
|
||||
|
||||
// <q> Bypass Coarse Lock
|
||||
// <i> Indicates whether Bypass Coarse Lock is enabled or not
|
||||
// <id> dfll_arch_bplckc
|
||||
#ifndef CONF_DFLL_BPLCKC
|
||||
#define CONF_DFLL_BPLCKC 0
|
||||
#endif
|
||||
|
||||
// <q> Quick Lock Disable
|
||||
// <i> Indicates whether Quick Lock Disable is enabled or not
|
||||
// <id> dfll_arch_qldis
|
||||
#ifndef CONF_DFLL_QLDIS
|
||||
#define CONF_DFLL_QLDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Chill Cycle Disable
|
||||
// <i> Indicates whether Chill Cycle Disable is enabled or not
|
||||
// <id> dfll_arch_ccdis
|
||||
#ifndef CONF_DFLL_CCDIS
|
||||
#define CONF_DFLL_CCDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Lose Lock After Wake
|
||||
// <i> Indicates whether Lose Lock After Wake is enabled or not
|
||||
// <id> dfll_arch_llaw
|
||||
#ifndef CONF_DFLL_LLAW
|
||||
#define CONF_DFLL_LLAW 0
|
||||
#endif
|
||||
|
||||
// <q> Stable DFLL Frequency
|
||||
// <i> Indicates whether Stable DFLL Frequency is enabled or not
|
||||
// <id> dfll_arch_stable
|
||||
#ifndef CONF_DFLL_STABLE
|
||||
#define CONF_DFLL_STABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode Selection
|
||||
// <0=>Open Loop Mode
|
||||
// <1=>Closed Loop Mode
|
||||
// <id> dfll_mode
|
||||
#ifndef CONF_DFLL_MODE
|
||||
#define CONF_DFLL_MODE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Maximum Step <0x0-0x1F>
|
||||
// <id> dfll_arch_cstep
|
||||
#ifndef CONF_DFLL_CSTEP
|
||||
#define CONF_DFLL_CSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> Fine Maximum Step <0x0-0xFF>
|
||||
// <id> dfll_arch_fstep
|
||||
#ifndef CONF_DFLL_FSTEP
|
||||
#define CONF_DFLL_FSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> DFLL Multiply Factor <0x0-0xFFFF>
|
||||
// <id> dfll_mul
|
||||
#ifndef CONF_DFLL_MUL
|
||||
#define CONF_DFLL_MUL 0x0
|
||||
#endif
|
||||
|
||||
// <e> DFLL Calibration Overwrite
|
||||
// <i> Indicates whether Overwrite Calibration value of DFLL
|
||||
// <id> dfll_arch_calibration
|
||||
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
|
||||
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Value <0x0-0x3F>
|
||||
// <id> dfll_arch_coarse
|
||||
#ifndef CONF_DFLL_COARSE
|
||||
#define CONF_DFLL_COARSE (0x1f / 4)
|
||||
#endif
|
||||
|
||||
// <o> Fine Value <0x0-0xFF>
|
||||
// <id> dfll_arch_fine
|
||||
#ifndef CONF_DFLL_FINE
|
||||
#define CONF_DFLL_FINE (0x80)
|
||||
#endif
|
||||
|
||||
//</e>
|
||||
|
||||
//</h>
|
||||
|
||||
//</e>
|
||||
|
||||
// <e> FDPLL0 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL0 is enabled or not
|
||||
// <id> enable_fdpll0
|
||||
#ifndef CONF_FDPLL0_CONFIG
|
||||
#define CONF_FDPLL0_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll0_ref_clock
|
||||
#ifndef CONF_FDPLL0_GCLK
|
||||
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll0_arch_enable
|
||||
#ifndef CONF_FDPLL0_ENABLE
|
||||
#define CONF_FDPLL0_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll0_arch_ondemand
|
||||
#ifndef CONF_FDPLL0_ONDEMAND
|
||||
#define CONF_FDPLL0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll0_arch_runstdby
|
||||
#ifndef CONF_FDPLL0_RUNSTDBY
|
||||
#define CONF_FDPLL0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldrfrac
|
||||
#ifndef CONF_FDPLL0_LDRFRAC
|
||||
#define CONF_FDPLL0_LDRFRAC 0x1
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldr
|
||||
#ifndef CONF_FDPLL0_LDR
|
||||
#define CONF_FDPLL0_LDR 0xe4d
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll0_clock_div
|
||||
#ifndef CONF_FDPLL0_DIV
|
||||
#define CONF_FDPLL0_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll0_arch_dcoen
|
||||
#ifndef CONF_FDPLL0_DCOEN
|
||||
#define CONF_FDPLL0_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll0_clock_dcofilter
|
||||
#ifndef CONF_FDPLL0_DCOFILTER
|
||||
#define CONF_FDPLL0_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll0_arch_lbypass
|
||||
#ifndef CONF_FDPLL0_LBYPASS
|
||||
#define CONF_FDPLL0_LBYPASS 1
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll0_arch_ltime
|
||||
#ifndef CONF_FDPLL0_LTIME
|
||||
#define CONF_FDPLL0_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll0_arch_refclk
|
||||
#ifndef CONF_FDPLL0_REFCLK
|
||||
#define CONF_FDPLL0_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll0_arch_wuf
|
||||
#ifndef CONF_FDPLL0_WUF
|
||||
#define CONF_FDPLL0_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll0_arch_filter
|
||||
#ifndef CONF_FDPLL0_FILTER
|
||||
#define CONF_FDPLL0_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
// <e> FDPLL1 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL1 is enabled or not
|
||||
// <id> enable_fdpll1
|
||||
#ifndef CONF_FDPLL1_CONFIG
|
||||
#define CONF_FDPLL1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll1_ref_clock
|
||||
#ifndef CONF_FDPLL1_GCLK
|
||||
#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll1_arch_enable
|
||||
#ifndef CONF_FDPLL1_ENABLE
|
||||
#define CONF_FDPLL1_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll1_arch_ondemand
|
||||
#ifndef CONF_FDPLL1_ONDEMAND
|
||||
#define CONF_FDPLL1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll1_arch_runstdby
|
||||
#ifndef CONF_FDPLL1_RUNSTDBY
|
||||
#define CONF_FDPLL1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldrfrac
|
||||
#ifndef CONF_FDPLL1_LDRFRAC
|
||||
#define CONF_FDPLL1_LDRFRAC 0xd
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldr
|
||||
#ifndef CONF_FDPLL1_LDR
|
||||
#define CONF_FDPLL1_LDR 0x5b7
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll1_clock_div
|
||||
#ifndef CONF_FDPLL1_DIV
|
||||
#define CONF_FDPLL1_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll1_arch_dcoen
|
||||
#ifndef CONF_FDPLL1_DCOEN
|
||||
#define CONF_FDPLL1_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll1_clock_dcofilter
|
||||
#ifndef CONF_FDPLL1_DCOFILTER
|
||||
#define CONF_FDPLL1_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll1_arch_lbypass
|
||||
#ifndef CONF_FDPLL1_LBYPASS
|
||||
#define CONF_FDPLL1_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll1_arch_ltime
|
||||
#ifndef CONF_FDPLL1_LTIME
|
||||
#define CONF_FDPLL1_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll1_arch_refclk
|
||||
#ifndef CONF_FDPLL1_REFCLK
|
||||
#define CONF_FDPLL1_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll1_arch_wuf
|
||||
#ifndef CONF_FDPLL1_WUF
|
||||
#define CONF_FDPLL1_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll1_arch_filter
|
||||
#ifndef CONF_FDPLL1_FILTER
|
||||
#define CONF_FDPLL1_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSCCTRL_CONFIG_H
|
@ -0,0 +1,522 @@
|
||||
/* Auto-generated config file hpl_port_config.h */
|
||||
#ifndef HPL_PORT_CONFIG_H
|
||||
#define HPL_PORT_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> PORT Input Event 0 configuration
|
||||
// <id> enable_port_input_event_0
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 0 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
|
||||
// <id> porta_input_event_enable_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_0
|
||||
#define CONF_PORTA_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 0
|
||||
// <id> porta_event_action_0
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_0
|
||||
#define CONF_PORTA_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
|
||||
// <id> portb_input_event_enable_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 0
|
||||
// <id> portb_event_action_0
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled
|
||||
// <id> portc_input_event_enable_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_0
|
||||
#define CONF_PORTC_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 0
|
||||
// <id> portc_event_action_0
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_0
|
||||
#define CONF_PORTC_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled
|
||||
// <id> portd_input_event_enable_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_0
|
||||
#define CONF_PORTD_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 0
|
||||
// <id> portd_event_action_0
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_0
|
||||
#define CONF_PORTD_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 1 configuration
|
||||
// <id> enable_port_input_event_1
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_1
|
||||
#define CONF_PORT_EVCTRL_PORT_1 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 1 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
|
||||
// <id> porta_input_event_enable_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_1
|
||||
#define CONF_PORTA_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 1
|
||||
// <id> porta_event_action_1
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_1
|
||||
#define CONF_PORTA_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
|
||||
// <id> portb_input_event_enable_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_1
|
||||
#define CONF_PORTB_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 1
|
||||
// <id> portb_event_action_1
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_1
|
||||
#define CONF_PORTB_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled
|
||||
// <id> portc_input_event_enable_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_1
|
||||
#define CONF_PORTC_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 1
|
||||
// <id> portc_event_action_1
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_1
|
||||
#define CONF_PORTC_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled
|
||||
// <id> portd_input_event_enable_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_1
|
||||
#define CONF_PORTD_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 1
|
||||
// <id> portd_event_action_1
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_1
|
||||
#define CONF_PORTD_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 2 configuration
|
||||
// <id> enable_port_input_event_2
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_2
|
||||
#define CONF_PORT_EVCTRL_PORT_2 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 2 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
|
||||
// <id> porta_input_event_enable_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_2
|
||||
#define CONF_PORTA_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 2
|
||||
// <id> porta_event_action_2
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_2
|
||||
#define CONF_PORTA_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
|
||||
// <id> portb_input_event_enable_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_2
|
||||
#define CONF_PORTB_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 2
|
||||
// <id> portb_event_action_2
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_2
|
||||
#define CONF_PORTB_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled
|
||||
// <id> portc_input_event_enable_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_2
|
||||
#define CONF_PORTC_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 2
|
||||
// <id> portc_event_action_2
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_2
|
||||
#define CONF_PORTC_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled
|
||||
// <id> portd_input_event_enable_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_2
|
||||
#define CONF_PORTD_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 2
|
||||
// <id> portd_event_action_2
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_2
|
||||
#define CONF_PORTD_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 3 configuration
|
||||
// <id> enable_port_input_event_3
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_3
|
||||
#define CONF_PORT_EVCTRL_PORT_3 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 3 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
|
||||
// <id> porta_input_event_enable_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_3
|
||||
#define CONF_PORTA_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 3
|
||||
// <id> porta_event_action_3
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_3
|
||||
#define CONF_PORTA_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
|
||||
// <id> portb_input_event_enable_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_3
|
||||
#define CONF_PORTB_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 3
|
||||
// <id> portb_event_action_3
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_3
|
||||
#define CONF_PORTB_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled
|
||||
// <id> portc_input_event_enable_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_3
|
||||
#define CONF_PORTC_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 3
|
||||
// <id> portc_event_action_3
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_3
|
||||
#define CONF_PORTC_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled
|
||||
// <id> portd_input_event_enable_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_3
|
||||
#define CONF_PORTD_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 3
|
||||
// <id> portd_event_action_3
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_3
|
||||
#define CONF_PORTD_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
#define CONF_PORTA_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
|
||||
#define CONF_PORTB_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
|
||||
#define CONF_PORTC_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3))
|
||||
#define CONF_PORTD_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3))
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_PORT_CONFIG_H
|
@ -0,0 +1,278 @@
|
||||
/* Auto-generated config file hpl_sercom_config.h */
|
||||
#ifndef HPL_SERCOM_CONFIG_H
|
||||
#define HPL_SERCOM_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_ENABLE
|
||||
#define CONF_SERCOM_0_USART_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable input buffer in SERCOM module
|
||||
// <id> usart_rx_enable
|
||||
#ifndef CONF_SERCOM_0_USART_RXEN
|
||||
#define CONF_SERCOM_0_USART_RXEN 1
|
||||
#endif
|
||||
|
||||
// <q> Transmitt buffer enable
|
||||
// <i> Enable output buffer in SERCOM module
|
||||
// <id> usart_tx_enable
|
||||
#ifndef CONF_SERCOM_0_USART_TXEN
|
||||
#define CONF_SERCOM_0_USART_TXEN 1
|
||||
#endif
|
||||
|
||||
// <o> Frame parity
|
||||
// <0x0=>No parity
|
||||
// <0x1=>Even parity
|
||||
// <0x2=>Odd parity
|
||||
// <i> Parity bit mode for USART frame
|
||||
// <id> usart_parity
|
||||
#ifndef CONF_SERCOM_0_USART_PARITY
|
||||
#define CONF_SERCOM_0_USART_PARITY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <0x5=>5 bits
|
||||
// <0x6=>6 bits
|
||||
// <0x7=>7 bits
|
||||
// <i> Data character size in USART frame
|
||||
// <id> usart_character_size
|
||||
#ifndef CONF_SERCOM_0_USART_CHSIZE
|
||||
#define CONF_SERCOM_0_USART_CHSIZE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Stop Bit
|
||||
// <0=>One stop bit
|
||||
// <1=>Two stop bits
|
||||
// <i> Number of stop bits in USART frame
|
||||
// <id> usart_stop_bit
|
||||
#ifndef CONF_SERCOM_0_USART_SBMODE
|
||||
#define CONF_SERCOM_0_USART_SBMODE 0
|
||||
#endif
|
||||
|
||||
// <o> Baud rate <1-6250000>
|
||||
// <i> USART baud rate setting
|
||||
// <id> usart_baud_rate
|
||||
#ifndef CONF_SERCOM_0_USART_BAUD
|
||||
#define CONF_SERCOM_0_USART_BAUD 9600
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced configuration
|
||||
// <id> usart_advanced
|
||||
#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG
|
||||
#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Keep the module running in standby sleep mode
|
||||
// <id> usart_arch_runstdby
|
||||
#ifndef CONF_SERCOM_0_USART_RUNSTDBY
|
||||
#define CONF_SERCOM_0_USART_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when the BUFOVF status bit is asserted
|
||||
// <id> usart_arch_ibon
|
||||
#ifndef CONF_SERCOM_0_USART_IBON
|
||||
#define CONF_SERCOM_0_USART_IBON 0
|
||||
#endif
|
||||
|
||||
// <q> Start of Frame Detection Enable
|
||||
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
|
||||
// <id> usart_arch_sfde
|
||||
#ifndef CONF_SERCOM_0_USART_SFDE
|
||||
#define CONF_SERCOM_0_USART_SFDE 0
|
||||
#endif
|
||||
|
||||
// <q> Collision Detection Enable
|
||||
// <i> Collision detection enable
|
||||
// <id> usart_arch_cloden
|
||||
#ifndef CONF_SERCOM_0_USART_CLODEN
|
||||
#define CONF_SERCOM_0_USART_CLODEN 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode
|
||||
// <0x0=>USART with external clock
|
||||
// <0x1=>USART with internal clock
|
||||
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
|
||||
// <id> usart_arch_clock_mode
|
||||
#ifndef CONF_SERCOM_0_USART_MODE
|
||||
#define CONF_SERCOM_0_USART_MODE 0x1
|
||||
#endif
|
||||
|
||||
// <o> Sample Rate
|
||||
// <0x0=>16x arithmetic
|
||||
// <0x1=>16x fractional
|
||||
// <0x2=>8x arithmetic
|
||||
// <0x3=>8x fractional
|
||||
// <0x4=>3x arithmetic
|
||||
// <i> How many over-sampling bits used when sampling data state
|
||||
// <id> usart_arch_sampr
|
||||
#ifndef CONF_SERCOM_0_USART_SAMPR
|
||||
#define CONF_SERCOM_0_USART_SAMPR 0x0
|
||||
#endif
|
||||
|
||||
// <o> Sample Adjustment
|
||||
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
|
||||
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
|
||||
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
|
||||
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
|
||||
// <i> Adjust which samples to use for data sampling in asynchronous mode
|
||||
// <id> usart_arch_sampa
|
||||
#ifndef CONF_SERCOM_0_USART_SAMPA
|
||||
#define CONF_SERCOM_0_USART_SAMPA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Fractional Part <0-7>
|
||||
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
|
||||
// <id> usart_arch_fractional
|
||||
#ifndef CONF_SERCOM_0_USART_FRACTIONAL
|
||||
#define CONF_SERCOM_0_USART_FRACTIONAL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB is transmitted first
|
||||
// <1=>LSB is transmitted first
|
||||
// <i> Data order of the data bits in the frame
|
||||
// <id> usart_arch_dord
|
||||
#ifndef CONF_SERCOM_0_USART_DORD
|
||||
#define CONF_SERCOM_0_USART_DORD 1
|
||||
#endif
|
||||
|
||||
// Does not do anything in UART mode
|
||||
#define CONF_SERCOM_0_USART_CPOL 0
|
||||
|
||||
// <o> Encoding Format
|
||||
// <0=>No encoding
|
||||
// <1=>IrDA encoded
|
||||
// <id> usart_arch_enc
|
||||
#ifndef CONF_SERCOM_0_USART_ENC
|
||||
#define CONF_SERCOM_0_USART_ENC 0
|
||||
#endif
|
||||
|
||||
// <o> LIN Slave Enable
|
||||
// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
|
||||
// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
|
||||
// <0=>Disable
|
||||
// <1=>Enable
|
||||
// <id> usart_arch_lin_slave_enable
|
||||
#ifndef CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE
|
||||
#define CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> usart_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE
|
||||
#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_INACK
|
||||
#define CONF_SERCOM_0_USART_INACK 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_DSNACK
|
||||
#define CONF_SERCOM_0_USART_DSNACK 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_MAXITER
|
||||
#define CONF_SERCOM_0_USART_MAXITER 0x7
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_GTIME
|
||||
#define CONF_SERCOM_0_USART_GTIME 0x2
|
||||
#endif
|
||||
|
||||
#define CONF_SERCOM_0_USART_RXINV 0x0
|
||||
#define CONF_SERCOM_0_USART_TXINV 0x0
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_CMODE
|
||||
#define CONF_SERCOM_0_USART_CMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_RXPO
|
||||
#define CONF_SERCOM_0_USART_RXPO 1 /* RX is on PIN_PA05 */
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_0_USART_TXPO
|
||||
#define CONF_SERCOM_0_USART_TXPO 0 /* TX is on PIN_PA04 */
|
||||
#endif
|
||||
|
||||
/* Set correct parity settings in register interface based on PARITY setting */
|
||||
#if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 1
|
||||
#if CONF_SERCOM_0_USART_PARITY == 0
|
||||
#define CONF_SERCOM_0_USART_PMODE 0
|
||||
#define CONF_SERCOM_0_USART_FORM 4
|
||||
#else
|
||||
#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1
|
||||
#define CONF_SERCOM_0_USART_FORM 5
|
||||
#endif
|
||||
#else /* #if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 0 */
|
||||
#if CONF_SERCOM_0_USART_PARITY == 0
|
||||
#define CONF_SERCOM_0_USART_PMODE 0
|
||||
#define CONF_SERCOM_0_USART_FORM 0
|
||||
#else
|
||||
#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1
|
||||
#define CONF_SERCOM_0_USART_FORM 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Calculate BAUD register value in UART mode
|
||||
#if CONF_SERCOM_0_USART_SAMPR == 0
|
||||
#ifndef CONF_SERCOM_0_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_0_USART_BAUD_RATE \
|
||||
65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_0_USART_SAMPR == 1
|
||||
#ifndef CONF_SERCOM_0_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_0_USART_BAUD_RATE \
|
||||
((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_0_USART_SAMPR == 2
|
||||
#ifndef CONF_SERCOM_0_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_0_USART_BAUD_RATE \
|
||||
65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_0_USART_SAMPR == 3
|
||||
#ifndef CONF_SERCOM_0_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_0_USART_BAUD_RATE \
|
||||
((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_0_USART_SAMPR == 4
|
||||
#ifndef CONF_SERCOM_0_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_0_USART_BAUD_RATE \
|
||||
65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SERCOM_CONFIG_H
|
@ -0,0 +1,180 @@
|
||||
/* Auto-generated config file hpl_tc_config.h */
|
||||
#ifndef HPL_TC_CONFIG_H
|
||||
#define HPL_TC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#ifndef CONF_TC0_ENABLE
|
||||
#define CONF_TC0_ENABLE 1
|
||||
#endif
|
||||
|
||||
#include "peripheral_clk_config.h"
|
||||
|
||||
// <h> Basic configuration
|
||||
|
||||
// <o> Prescaler
|
||||
// <0x0=> No division
|
||||
// <0x1=> Divide by 2
|
||||
// <0x2=> Divide by 4
|
||||
// <0x3=> Divide by 8
|
||||
// <0x4=> Divide by 16
|
||||
// <0x5=> Divide by 64
|
||||
// <0x6=> Divide by 256
|
||||
// <0x7=> Divide by 1024
|
||||
// <i> This defines the prescaler value
|
||||
// <id> timer_prescaler
|
||||
#ifndef CONF_TC0_PRESCALER
|
||||
#define CONF_TC0_PRESCALER 0x3
|
||||
#endif
|
||||
|
||||
// <o> Length of one timer tick in uS <0-4294967295>
|
||||
// <id> timer_tick
|
||||
#ifndef CONF_TC0_TIMER_TICK
|
||||
#define CONF_TC0_TIMER_TICK 1000
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <e> Advanced configuration
|
||||
// <id> timer_advanced_configuration
|
||||
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
|
||||
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <y> Prescaler and Counter Synchronization Selection
|
||||
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
|
||||
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
|
||||
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
|
||||
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
|
||||
// <id> tc_arch_presync
|
||||
#ifndef CONF_TC0_PRESCSYNC
|
||||
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
|
||||
#endif
|
||||
|
||||
// <q> Run in standby
|
||||
// <i> Indicates whether the module will continue to run in standby sleep mode
|
||||
// <id> tc_arch_runstdby
|
||||
#ifndef CONF_TC0_RUNSTDBY
|
||||
#define CONF_TC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Run in debug mode
|
||||
// <i> Indicates whether the module will run in debug mode
|
||||
// <id> tc_arch_dbgrun
|
||||
#ifndef CONF_TC0_DBGRUN
|
||||
#define CONF_TC0_DBGRUN 0
|
||||
#endif
|
||||
|
||||
// <q> Run on demand
|
||||
// <i> Run if requested by some other peripheral in the device
|
||||
// <id> tc_arch_ondemand
|
||||
#ifndef CONF_TC0_ONDEMAND
|
||||
#define CONF_TC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Event control
|
||||
// <id> timer_event_control
|
||||
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
|
||||
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 0
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo0
|
||||
#ifndef CONF_TC0_MCEO0
|
||||
#define CONF_TC0_MCEO0 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 1
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo1
|
||||
#ifndef CONF_TC0_MCEO1
|
||||
#define CONF_TC0_MCEO1 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Timer Tick
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_ovfeo
|
||||
#ifndef CONF_TC0_OVFEO
|
||||
#define CONF_TC0_OVFEO 0
|
||||
#endif
|
||||
|
||||
// <q> Event Input
|
||||
// <i> Enable asynchronous input events
|
||||
// <id> tc_arch_tcei
|
||||
#ifndef CONF_TC0_TCEI
|
||||
#define CONF_TC0_TCEI 0
|
||||
#endif
|
||||
|
||||
// <q> Inverted Event Input
|
||||
// <i> Invert the asynchronous input events
|
||||
// <id> tc_arch_tcinv
|
||||
#ifndef CONF_TC0_TCINV
|
||||
#define CONF_TC0_TCINV 0
|
||||
#endif
|
||||
|
||||
// <o> Event action
|
||||
// <0=> Event action disabled
|
||||
// <1=> Start, restart or re-trigger TC on event
|
||||
// <2=> Count on event
|
||||
// <3=> Start on event
|
||||
// <4=> Time stamp capture
|
||||
// <5=> Period captured in CC0, pulse width in CC1
|
||||
// <6=> Period captured in CC1, pulse width in CC0
|
||||
// <7=> Pulse width capture
|
||||
// <i> Event which will be performed on an event
|
||||
//<id> tc_arch_evact
|
||||
#ifndef CONF_TC0_EVACT
|
||||
#define CONF_TC0_EVACT 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// Default values which the driver needs in order to work correctly
|
||||
|
||||
// Mode set to 32-bit
|
||||
#ifndef CONF_TC0_MODE
|
||||
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
|
||||
#endif
|
||||
|
||||
// CC 1 register set to 0
|
||||
#ifndef CONF_TC0_CC1
|
||||
#define CONF_TC0_CC1 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_TC0_ALOCK
|
||||
#define CONF_TC0_ALOCK 0
|
||||
#endif
|
||||
|
||||
// Not used in 32-bit mode
|
||||
#define CONF_TC0_PER 0
|
||||
|
||||
// Calculating correct top value based on requested tick interval.
|
||||
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
|
||||
|
||||
// Prescaler set to 64
|
||||
#if CONF_TC0_PRESCALER > 0x4
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 64
|
||||
#endif
|
||||
|
||||
// Prescaler set to 256
|
||||
#if CONF_TC0_PRESCALER > 0x5
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 256
|
||||
#endif
|
||||
|
||||
// Prescaler set to 1024
|
||||
#if CONF_TC0_PRESCALER > 0x6
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 1024
|
||||
#endif
|
||||
|
||||
#ifndef CONF_TC0_CC0
|
||||
#define CONF_TC0_CC0 \
|
||||
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_TC_CONFIG_H
|
@ -0,0 +1,137 @@
|
||||
/* Auto-generated config file peripheral_clk_config.h */
|
||||
#ifndef PERIPHERAL_CLK_CONFIG_H
|
||||
#define PERIPHERAL_CLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_CPU_FREQUENCY
|
||||
#define CONF_CPU_FREQUENCY 119997440
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM0_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
|
||||
* \brief SERCOM0's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 119997440
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
|
||||
* \brief SERCOM0's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> TC Clock Source
|
||||
// <id> tc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for TC.
|
||||
#ifndef CONF_GCLK_TC0_SRC
|
||||
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_TC0_FREQUENCY
|
||||
* \brief TC0's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_TC0_FREQUENCY
|
||||
#define CONF_GCLK_TC0_FREQUENCY 119997440
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // PERIPHERAL_CLK_CONFIG_H
|
@ -0,0 +1,163 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME54P20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
@ -0,0 +1,162 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME54P20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
@ -0,0 +1,546 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief gcc starttup file for SAME54
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
extern uint32_t _efixed;
|
||||
extern uint32_t _etext;
|
||||
extern uint32_t _srelocate;
|
||||
extern uint32_t _erelocate;
|
||||
extern uint32_t _szero;
|
||||
extern uint32_t _ezero;
|
||||
extern uint32_t _sstack;
|
||||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M4 core handlers */
|
||||
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
|
||||
void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
|
||||
void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
|
||||
void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
|
||||
void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
|
||||
void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
|
||||
void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
|
||||
void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
|
||||
void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
|
||||
void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
|
||||
void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
|
||||
void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
|
||||
void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
|
||||
void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
|
||||
void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
|
||||
void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
|
||||
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
|
||||
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
|
||||
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
|
||||
void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
|
||||
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
|
||||
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
|
||||
void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
|
||||
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
|
||||
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
|
||||
void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
|
||||
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
|
||||
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
|
||||
void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
|
||||
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
|
||||
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
|
||||
void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
|
||||
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
|
||||
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
|
||||
void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
|
||||
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
|
||||
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
|
||||
void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
|
||||
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
|
||||
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
|
||||
void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
|
||||
void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
|
||||
void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
|
||||
void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
|
||||
void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
|
||||
void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
|
||||
void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
|
||||
void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
|
||||
void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
|
||||
void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
|
||||
void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
|
||||
void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
|
||||
void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
|
||||
void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
|
||||
void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
|
||||
void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
|
||||
#endif
|
||||
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_TC4
|
||||
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
|
||||
void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
|
||||
void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
|
||||
void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
|
||||
void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
|
||||
void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
|
||||
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
|
||||
void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
|
||||
void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
|
||||
void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_ICM
|
||||
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_SDHC0
|
||||
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__ ((section(".vectors")))
|
||||
const DeviceVectors exception_table = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
.pvStack = (void*) (&_estack),
|
||||
|
||||
.pfnReset_Handler = (void*) Reset_Handler,
|
||||
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
|
||||
.pfnHardFault_Handler = (void*) HardFault_Handler,
|
||||
.pfnMemManagement_Handler = (void*) MemManagement_Handler,
|
||||
.pfnBusFault_Handler = (void*) BusFault_Handler,
|
||||
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
|
||||
.pvReservedM9 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM8 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM7 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM6 = (void*) (0UL), /* Reserved */
|
||||
.pfnSVCall_Handler = (void*) SVCall_Handler,
|
||||
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
|
||||
.pvReservedM3 = (void*) (0UL), /* Reserved */
|
||||
.pfnPendSV_Handler = (void*) PendSV_Handler,
|
||||
.pfnSysTick_Handler = (void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
|
||||
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
|
||||
.pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
.pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
.pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
.pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
.pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
|
||||
.pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
.pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
|
||||
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
|
||||
.pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */
|
||||
.pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */
|
||||
.pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */
|
||||
.pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */
|
||||
.pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */
|
||||
.pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */
|
||||
.pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */
|
||||
.pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */
|
||||
.pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */
|
||||
.pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */
|
||||
.pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */
|
||||
.pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */
|
||||
.pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */
|
||||
.pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */
|
||||
.pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */
|
||||
.pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */
|
||||
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
|
||||
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
.pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
.pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
|
||||
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
|
||||
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
|
||||
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
|
||||
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
|
||||
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */
|
||||
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */
|
||||
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */
|
||||
.pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */
|
||||
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */
|
||||
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */
|
||||
.pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */
|
||||
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */
|
||||
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */
|
||||
.pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */
|
||||
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */
|
||||
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */
|
||||
.pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */
|
||||
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */
|
||||
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */
|
||||
.pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#else
|
||||
.pvReserved62 = (void*) (0UL), /* 62 Reserved */
|
||||
.pvReserved63 = (void*) (0UL), /* 63 Reserved */
|
||||
.pvReserved64 = (void*) (0UL), /* 64 Reserved */
|
||||
.pvReserved65 = (void*) (0UL), /* 65 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */
|
||||
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */
|
||||
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */
|
||||
.pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#else
|
||||
.pvReserved66 = (void*) (0UL), /* 66 Reserved */
|
||||
.pvReserved67 = (void*) (0UL), /* 67 Reserved */
|
||||
.pvReserved68 = (void*) (0UL), /* 68 Reserved */
|
||||
.pvReserved69 = (void*) (0UL), /* 69 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */
|
||||
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */
|
||||
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */
|
||||
.pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#else
|
||||
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
|
||||
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
|
||||
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
|
||||
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */
|
||||
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */
|
||||
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */
|
||||
.pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#else
|
||||
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
|
||||
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
|
||||
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
|
||||
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
.pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */
|
||||
#else
|
||||
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
.pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */
|
||||
#else
|
||||
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
.pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
.pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */
|
||||
.pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
.pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#else
|
||||
.pvReserved80 = (void*) (0UL), /* 80 Reserved */
|
||||
.pvReserved81 = (void*) (0UL), /* 81 Reserved */
|
||||
.pvReserved82 = (void*) (0UL), /* 82 Reserved */
|
||||
.pvReserved83 = (void*) (0UL), /* 83 Reserved */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
.pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */
|
||||
#else
|
||||
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
|
||||
#endif
|
||||
.pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
.pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */
|
||||
.pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */
|
||||
.pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */
|
||||
.pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */
|
||||
.pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */
|
||||
.pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */
|
||||
.pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
.pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */
|
||||
.pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */
|
||||
.pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */
|
||||
.pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */
|
||||
.pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
.pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */
|
||||
.pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */
|
||||
.pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
.pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
.pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */
|
||||
.pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */
|
||||
#else
|
||||
.pvReserved101 = (void*) (0UL), /* 101 Reserved */
|
||||
.pvReserved102 = (void*) (0UL), /* 102 Reserved */
|
||||
.pvReserved103 = (void*) (0UL), /* 103 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
.pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
.pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */
|
||||
.pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */
|
||||
#else
|
||||
.pvReserved104 = (void*) (0UL), /* 104 Reserved */
|
||||
.pvReserved105 = (void*) (0UL), /* 105 Reserved */
|
||||
.pvReserved106 = (void*) (0UL), /* 106 Reserved */
|
||||
#endif
|
||||
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */
|
||||
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */
|
||||
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */
|
||||
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */
|
||||
#ifdef ID_TC4
|
||||
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */
|
||||
#else
|
||||
.pvReserved111 = (void*) (0UL), /* 111 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */
|
||||
#else
|
||||
.pvReserved112 = (void*) (0UL), /* 112 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */
|
||||
#else
|
||||
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */
|
||||
#else
|
||||
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
|
||||
#endif
|
||||
.pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
.pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */
|
||||
.pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */
|
||||
.pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
|
||||
.pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */
|
||||
.pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
|
||||
.pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */
|
||||
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
|
||||
.pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
.pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */
|
||||
.pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */
|
||||
.pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */
|
||||
.pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
|
||||
#else
|
||||
.pvReserved128 = (void*) (0UL), /* 128 Reserved */
|
||||
#endif
|
||||
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
|
||||
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
|
||||
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
|
||||
#ifdef ID_ICM
|
||||
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
|
||||
#else
|
||||
.pvReserved132 = (void*) (0UL), /* 132 Reserved */
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
|
||||
#else
|
||||
.pvReserved133 = (void*) (0UL), /* 133 Reserved */
|
||||
#endif
|
||||
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
|
||||
#ifdef ID_SDHC0
|
||||
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
|
||||
#else
|
||||
.pvReserved135 = (void*) (0UL), /* 135 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
|
||||
#else
|
||||
.pvReserved136 = (void*) (0UL) /* 136 Reserved */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
@ -0,0 +1,64 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
@ -0,0 +1,9 @@
|
||||
#include <atmel_start.h>
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void)
|
||||
{
|
||||
system_init();
|
||||
}
|
@ -0,0 +1,18 @@
|
||||
#ifndef ATMEL_START_H_INCLUDED
|
||||
#define ATMEL_START_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "driver_init.h"
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef ATMEL_START_PINS_H_INCLUDED
|
||||
#define ATMEL_START_PINS_H_INCLUDED
|
||||
|
||||
#include <hal_gpio.h>
|
||||
|
||||
// SAME54 has 14 pin functions
|
||||
|
||||
#define GPIO_PIN_FUNCTION_A 0
|
||||
#define GPIO_PIN_FUNCTION_B 1
|
||||
#define GPIO_PIN_FUNCTION_C 2
|
||||
#define GPIO_PIN_FUNCTION_D 3
|
||||
#define GPIO_PIN_FUNCTION_E 4
|
||||
#define GPIO_PIN_FUNCTION_F 5
|
||||
#define GPIO_PIN_FUNCTION_G 6
|
||||
#define GPIO_PIN_FUNCTION_H 7
|
||||
#define GPIO_PIN_FUNCTION_I 8
|
||||
#define GPIO_PIN_FUNCTION_J 9
|
||||
#define GPIO_PIN_FUNCTION_K 10
|
||||
#define GPIO_PIN_FUNCTION_L 11
|
||||
#define GPIO_PIN_FUNCTION_M 12
|
||||
#define GPIO_PIN_FUNCTION_N 13
|
||||
|
||||
#define PA04 GPIO(GPIO_PORTA, 4)
|
||||
#define PA05 GPIO(GPIO_PORTA, 5)
|
||||
|
||||
#endif // ATMEL_START_PINS_H_INCLUDED
|
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_init.h"
|
||||
#include <peripheral_clk_config.h>
|
||||
#include <utils.h>
|
||||
#include <hal_init.h>
|
||||
|
||||
struct timer_descriptor TIMER_0;
|
||||
|
||||
struct usart_sync_descriptor USART_0;
|
||||
|
||||
void USART_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0);
|
||||
|
||||
gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1);
|
||||
}
|
||||
|
||||
void USART_0_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
|
||||
}
|
||||
|
||||
void USART_0_init(void)
|
||||
{
|
||||
USART_0_CLOCK_init();
|
||||
usart_sync_init(&USART_0, SERCOM0, (void *)NULL);
|
||||
USART_0_PORT_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Timer initialization function
|
||||
*
|
||||
* Enables Timer peripheral, clocks and initializes Timer driver
|
||||
*/
|
||||
static void TIMER_0_init(void)
|
||||
{
|
||||
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
timer_init(&TIMER_0, TC0, _tc_get_timer());
|
||||
}
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
init_mcu();
|
||||
|
||||
USART_0_init();
|
||||
|
||||
TIMER_0_init();
|
||||
}
|
@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_INIT_INCLUDED
|
||||
#define DRIVER_INIT_INCLUDED
|
||||
|
||||
#include "atmel_start_pins.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <hal_atomic.h>
|
||||
#include <hal_delay.h>
|
||||
#include <hal_gpio.h>
|
||||
#include <hal_init.h>
|
||||
#include <hal_io.h>
|
||||
#include <hal_sleep.h>
|
||||
|
||||
#include <hal_usart_sync.h>
|
||||
#include <hal_timer.h>
|
||||
#include <hpl_tc_base.h>
|
||||
|
||||
extern struct usart_sync_descriptor USART_0;
|
||||
extern struct timer_descriptor TIMER_0;
|
||||
|
||||
void USART_0_PORT_init(void);
|
||||
void USART_0_CLOCK_init(void);
|
||||
void USART_0_init(void);
|
||||
|
||||
/**
|
||||
* \brief Perform system initialization, initialize pins and clocks for
|
||||
* peripherals
|
||||
*/
|
||||
void system_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_INIT_INCLUDED
|
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_examples.h"
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Example of using USART_0 to write "Hello World" using the IO abstraction.
|
||||
*/
|
||||
void USART_0_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
usart_sync_get_io_descriptor(&USART_0, &io);
|
||||
usart_sync_enable(&USART_0);
|
||||
|
||||
io_write(io, (uint8_t *)"Hello World!", 12);
|
||||
}
|
||||
|
||||
static struct timer_task TIMER_0_task1, TIMER_0_task2;
|
||||
|
||||
/**
|
||||
* Example of using TIMER_0.
|
||||
*/
|
||||
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
void TIMER_0_example(void)
|
||||
{
|
||||
TIMER_0_task1.interval = 100;
|
||||
TIMER_0_task1.cb = TIMER_0_task1_cb;
|
||||
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
|
||||
TIMER_0_task2.interval = 200;
|
||||
TIMER_0_task2.cb = TIMER_0_task2_cb;
|
||||
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
|
||||
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task1);
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task2);
|
||||
timer_start(&TIMER_0);
|
||||
}
|
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_EXAMPLES_H_INCLUDED
|
||||
#define DRIVER_EXAMPLES_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void USART_0_example(void);
|
||||
|
||||
void TIMER_0_example(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_EXAMPLES_H_INCLUDED
|
@ -0,0 +1,52 @@
|
||||
============================
|
||||
The Timer driver (bare-bone)
|
||||
============================
|
||||
|
||||
The Timer driver provides means for delayed and periodical function invocation.
|
||||
|
||||
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
|
||||
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
|
||||
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
|
||||
changes execution delays and periods for all tasks in the timers task queue.
|
||||
|
||||
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
|
||||
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
|
||||
the period set in the task configuration.
|
||||
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
|
||||
reuse the memory of expired task in the callback.
|
||||
|
||||
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Starting and stopping
|
||||
* Timer tasks - periodical invocation of functions
|
||||
* Changing and obtaining of the period of a timer
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Delayed and periodical function execution for middle-ware stacks and applications.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
|
||||
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
|
||||
until the task adding or removing is complete.
|
||||
|
||||
The task queue is not protected from the access by interrupts not used by the driver. Due to this
|
||||
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
|
||||
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
|
||||
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
Not applicable
|
@ -0,0 +1,58 @@
|
||||
The USART Synchronous Driver
|
||||
============================
|
||||
|
||||
The universal synchronous and asynchronous receiver and transmitter
|
||||
(USART) is usually used to transfer data from one device to the other.
|
||||
|
||||
User can set action for flow control pins by function usart_set_flow_control,
|
||||
if the flow control is enabled. All the available states are defined in union
|
||||
usart_flow_control_state.
|
||||
|
||||
Note that user can set state of flow control pins only if automatic support of
|
||||
the flow control is not supported by the hardware.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Control of the following settings:
|
||||
|
||||
* Baudrate
|
||||
* UART or USRT communication mode
|
||||
* Character size
|
||||
* Data order
|
||||
* Flow control
|
||||
* Data transfer: transmission, reception
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
They are commonly used in a terminal application or low-speed communication
|
||||
between devices.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
USART capable hardware.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
Write buffer should not be changed while data is being sent.
|
||||
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
* The driver does not support 9-bit character size.
|
||||
* The "USART with ISO7816" mode can be only used in ISO7816 capable devices.
|
||||
And the SCK pin can't be set directly. Application can use a GCLK output PIN
|
||||
to generate SCK. For example to communicate with a SMARTCARD with ISO7816
|
||||
(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be
|
||||
config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
@ -0,0 +1,120 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Critical sections related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_ATOMIC_H_INCLUDED
|
||||
#define _HAL_ATOMIC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_atomic
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Type for the register holding global interrupt enable flag
|
||||
*/
|
||||
typedef uint32_t hal_atomic_t;
|
||||
|
||||
/**
|
||||
* \brief Helper macro for entering critical sections
|
||||
*
|
||||
* This macro is recommended to be used instead of a direct call
|
||||
* hal_enterCritical() function to enter critical
|
||||
* sections. No semicolon is required after the macro.
|
||||
*
|
||||
* \section atomic_usage Usage Example
|
||||
* \code
|
||||
* CRITICAL_SECTION_ENTER()
|
||||
* Critical code
|
||||
* CRITICAL_SECTION_LEAVE()
|
||||
* \endcode
|
||||
*/
|
||||
#define CRITICAL_SECTION_ENTER() \
|
||||
{ \
|
||||
volatile hal_atomic_t __atomic; \
|
||||
atomic_enter_critical(&__atomic);
|
||||
|
||||
/**
|
||||
* \brief Helper macro for leaving critical sections
|
||||
*
|
||||
* This macro is recommended to be used instead of a direct call
|
||||
* hal_leaveCritical() function to leave critical
|
||||
* sections. No semicolon is required after the macro.
|
||||
*/
|
||||
#define CRITICAL_SECTION_LEAVE() \
|
||||
atomic_leave_critical(&__atomic); \
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable interrupts, enter critical section
|
||||
*
|
||||
* Disables global interrupts. Supports nested critical sections,
|
||||
* so that global interrupts are only re-enabled
|
||||
* upon leaving the outermost nested critical section.
|
||||
*
|
||||
* \param[out] atomic The pointer to a variable to store the value of global
|
||||
* interrupt enable flag
|
||||
*/
|
||||
void atomic_enter_critical(hal_atomic_t volatile *atomic);
|
||||
|
||||
/**
|
||||
* \brief Exit atomic section
|
||||
*
|
||||
* Enables global interrupts. Supports nested critical sections,
|
||||
* so that global interrupts are only re-enabled
|
||||
* upon leaving the outermost nested critical section.
|
||||
*
|
||||
* \param[in] atomic The pointer to a variable, which stores the latest stored
|
||||
* value of the global interrupt enable flag
|
||||
*/
|
||||
void atomic_leave_critical(hal_atomic_t volatile *atomic);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t atomic_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_ATOMIC_H_INCLUDED */
|
@ -0,0 +1,96 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL cache functionality implementation.
|
||||
*
|
||||
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef HAL_CACHE_H_
|
||||
#define HAL_CACHE_H_
|
||||
|
||||
#include <hpl_cmcc.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Enable cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_enable(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Disable cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_disable(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Initialize cache module
|
||||
*
|
||||
* This function initialize cache module configuration.
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_init(void);
|
||||
|
||||
/**
|
||||
* \brief Configure cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
* \param[in] cache configuration structure pointer
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
|
||||
|
||||
/**
|
||||
* \brief Invalidate entire cache entries
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_invalidate_all(const void *hw);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_CACHE_H_ */
|
@ -0,0 +1,89 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL delay related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <hpl_irq.h>
|
||||
#include <hpl_reset.h>
|
||||
#include <hpl_sleep.h>
|
||||
|
||||
#ifndef _HAL_DELAY_H_INCLUDED
|
||||
#define _HAL_DELAY_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_delay Delay Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize Delay driver
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
void delay_init(void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Perform delay in us
|
||||
*
|
||||
* This function performs delay for the given amount of microseconds.
|
||||
*
|
||||
* \param[in] us The amount delay in us
|
||||
*/
|
||||
void delay_us(const uint16_t us);
|
||||
|
||||
/**
|
||||
* \brief Perform delay in ms
|
||||
*
|
||||
* This function performs delay for the given amount of milliseconds.
|
||||
*
|
||||
* \param[in] ms The amount delay in ms
|
||||
*/
|
||||
void delay_ms(const uint16_t ms);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t delay_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_DELAY_H_INCLUDED */
|
@ -0,0 +1,201 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Port
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*/
|
||||
#ifndef _HAL_GPIO_INCLUDED_
|
||||
#define _HAL_GPIO_INCLUDED_
|
||||
|
||||
#include <hpl_gpio.h>
|
||||
#include <utils_assert.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Set gpio pull mode
|
||||
*
|
||||
* Set pin pull mode, non existing pull modes throws an fatal assert
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
|
||||
* GPIO_PULL_UP = Pull pin high with internal resistor
|
||||
* GPIO_PULL_OFF = Disable pin pull mode
|
||||
*/
|
||||
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
|
||||
{
|
||||
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set pin function
|
||||
*
|
||||
* Select which function a pin will be used for
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] function The pin function is given by a 32-bit wide bitfield
|
||||
* found in the header files for the device
|
||||
*
|
||||
*/
|
||||
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
|
||||
{
|
||||
_gpio_set_pin_function(pin, function);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set port data direction
|
||||
*
|
||||
* Select if the pin data direction is input, output or disabled.
|
||||
* If disabled state is not possible, this function throws an assert.
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to the
|
||||
* corresponding pin
|
||||
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
|
||||
* GPIO_DIRECTION_OUT = Data direction out
|
||||
* GPIO_DIRECTION_OFF = Disables the pin
|
||||
* (low power state)
|
||||
*/
|
||||
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
|
||||
const enum gpio_direction direction)
|
||||
{
|
||||
_gpio_set_direction(port, mask, direction);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set gpio data direction
|
||||
*
|
||||
* Select if the pin data direction is input, output or disabled.
|
||||
* If disabled state is not possible, this function throws an assert.
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
|
||||
* GPIO_DIRECTION_OUT = Data direction out
|
||||
* GPIO_DIRECTION_OFF = Disables the pin
|
||||
* (low power state)
|
||||
*/
|
||||
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
|
||||
{
|
||||
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set port level
|
||||
*
|
||||
* Sets output level on the pins defined by the bit mask
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
|
||||
* pin
|
||||
* \param[in] level true = Pin levels set to "high" state
|
||||
* false = Pin levels set to "low" state
|
||||
*/
|
||||
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
|
||||
{
|
||||
_gpio_set_level(port, mask, level);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set gpio level
|
||||
*
|
||||
* Sets output level on a pin
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] level true = Pin level set to "high" state
|
||||
* false = Pin level set to "low" state
|
||||
*/
|
||||
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
|
||||
{
|
||||
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggle out level on pins
|
||||
*
|
||||
* Toggle the pin levels on pins defined by bit mask
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
|
||||
* pin
|
||||
*/
|
||||
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
|
||||
{
|
||||
_gpio_toggle_level(port, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggle output level on pin
|
||||
*
|
||||
* Toggle the pin levels on pins defined by bit mask
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
*/
|
||||
static inline void gpio_toggle_pin_level(const uint8_t pin)
|
||||
{
|
||||
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get input level on pins
|
||||
*
|
||||
* Read the input level on pins connected to a port
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
*/
|
||||
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
|
||||
{
|
||||
return _gpio_get_level(port);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get level on pin
|
||||
*
|
||||
* Reads the level on pins connected to a port
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
*/
|
||||
static inline bool gpio_get_pin_level(const uint8_t pin)
|
||||
{
|
||||
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
|
||||
}
|
||||
/**
|
||||
* \brief Get current driver version
|
||||
*/
|
||||
uint32_t gpio_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
@ -0,0 +1,72 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL initialization related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_INIT_H_INCLUDED
|
||||
#define _HAL_INIT_H_INCLUDED
|
||||
|
||||
#include <hpl_init.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_init Init Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize the hardware abstraction layer
|
||||
*
|
||||
* This function calls the various initialization functions.
|
||||
* Currently the following initialization functions are supported:
|
||||
* - System clock initialization
|
||||
*/
|
||||
static inline void init_mcu(void)
|
||||
{
|
||||
_init_chip();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t init_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_INIT_H_INCLUDED */
|
@ -0,0 +1,110 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_IO_INCLUDED
|
||||
#define _HAL_IO_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_io I/O Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief I/O descriptor
|
||||
*
|
||||
* The I/O descriptor forward declaration.
|
||||
*/
|
||||
struct io_descriptor;
|
||||
|
||||
/**
|
||||
* \brief I/O write function pointer type
|
||||
*/
|
||||
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O read function pointer type
|
||||
*/
|
||||
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O descriptor
|
||||
*/
|
||||
struct io_descriptor {
|
||||
io_write_t write; /*! The write function pointer. */
|
||||
io_read_t read; /*! The read function pointer. */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief I/O write interface
|
||||
*
|
||||
* This function writes up to \p length of bytes to a given I/O descriptor.
|
||||
* It returns the number of bytes actually write.
|
||||
*
|
||||
* \param[in] descr An I/O descriptor to write
|
||||
* \param[in] buf The buffer pointer to story the write data
|
||||
* \param[in] length The number of bytes to write
|
||||
*
|
||||
* \return The number of bytes written
|
||||
*/
|
||||
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O read interface
|
||||
*
|
||||
* This function reads up to \p length bytes from a given I/O descriptor, and
|
||||
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
|
||||
* actually read.
|
||||
*
|
||||
* \param[in] descr An I/O descriptor to read
|
||||
* \param[in] buf The buffer pointer to story the read data
|
||||
* \param[in] length The number of bytes to read
|
||||
*
|
||||
* \return The number of bytes actually read. This number can be less than the
|
||||
* requested length. E.g., in a driver that uses ring buffer for
|
||||
* reception, it may depend on the availability of data in the
|
||||
* ring buffer.
|
||||
*/
|
||||
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HAL_IO_INCLUDED */
|
@ -0,0 +1,74 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Sleep related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SLEEP_H_INCLUDED
|
||||
#define _HAL_SLEEP_H_INCLUDED
|
||||
|
||||
#include <hpl_sleep.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_sleep
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Set the sleep mode of the device and put the MCU to sleep
|
||||
*
|
||||
* For an overview of which systems are disabled in sleep for the different
|
||||
* sleep modes, see the data sheet.
|
||||
*
|
||||
* \param[in] mode Sleep mode to use
|
||||
*
|
||||
* \return The status of a sleep request
|
||||
* \retval -1 The requested sleep mode was invalid or not available
|
||||
* \retval 0 The operation completed successfully, returned after leaving the
|
||||
* sleep
|
||||
*/
|
||||
int sleep(const uint8_t mode);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t sleep_get_version(void);
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_SLEEP_H_INCLUDED */
|
@ -0,0 +1,206 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Timer task functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_TIMER_H_INCLUDED
|
||||
#define _HAL_TIMER_H_INCLUDED
|
||||
|
||||
#include <utils_list.h>
|
||||
#include <hpl_timer.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_timer
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Timer mode type
|
||||
*/
|
||||
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
|
||||
|
||||
/**
|
||||
* \brief Timer task descriptor
|
||||
*
|
||||
* The timer task descriptor forward declaration.
|
||||
*/
|
||||
struct timer_task;
|
||||
|
||||
/**
|
||||
* \brief Timer task callback function type
|
||||
*/
|
||||
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
|
||||
|
||||
/**
|
||||
* \brief Timer task structure
|
||||
*/
|
||||
struct timer_task {
|
||||
struct list_element elem; /*! List element. */
|
||||
uint32_t time_label; /*! Absolute timer start time. */
|
||||
|
||||
uint32_t interval; /*! Number of timer ticks before calling the task. */
|
||||
timer_cb_t cb; /*! Function pointer to the task. */
|
||||
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Timer structure
|
||||
*/
|
||||
struct timer_descriptor {
|
||||
struct _timer_device device;
|
||||
uint32_t time;
|
||||
struct list_descriptor tasks; /*! Timer tasks list. */
|
||||
volatile uint8_t flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize timer
|
||||
*
|
||||
* This function initializes the given timer.
|
||||
* It checks if the given hardware is not initialized and if the given hardware
|
||||
* is permitted to be initialized.
|
||||
*
|
||||
* \param[out] descr A timer descriptor to initialize
|
||||
* \param[in] hw The pointer to the hardware instance
|
||||
* \param[in] func The pointer to a set of function pointers
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize timer
|
||||
*
|
||||
* This function deinitializes the given timer.
|
||||
* It checks if the given hardware is initialized and if the given hardware is
|
||||
* permitted to be deinitialized.
|
||||
*
|
||||
* \param[in] descr A timer descriptor to deinitialize
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t timer_deinit(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Start timer
|
||||
*
|
||||
* This function starts the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to start
|
||||
*
|
||||
* \return Timer starting status.
|
||||
*/
|
||||
int32_t timer_start(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Stop timer
|
||||
*
|
||||
* This function stops the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to stop
|
||||
*
|
||||
* \return Timer stopping status.
|
||||
*/
|
||||
int32_t timer_stop(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Set amount of clock cycles per timer tick
|
||||
*
|
||||
* This function sets the amount of clock cycles per timer tick for the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to stop
|
||||
* \param[in] clock_cycles The amount of clock cycles per tick to set
|
||||
*
|
||||
* \return Setting clock cycles amount status.
|
||||
*/
|
||||
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of clock cycles in a tick
|
||||
*
|
||||
* This function retrieves how many clock cycles there are in a single timer tick.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to convert ticks to
|
||||
* clock cycles
|
||||
* \param[out] cycles The amount of clock cycles
|
||||
*
|
||||
* \return The status of clock cycles retrieving.
|
||||
*/
|
||||
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
|
||||
|
||||
/**
|
||||
* \brief Add timer task
|
||||
*
|
||||
* This function adds the given timer task to the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to add task to
|
||||
* \param[in] task A task to add
|
||||
*
|
||||
* \return Timer's task adding status.
|
||||
*/
|
||||
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
|
||||
|
||||
/**
|
||||
* \brief Remove timer task
|
||||
*
|
||||
* This function removes the given timer task from the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to remove task from
|
||||
* \param[in] task A task to remove
|
||||
*
|
||||
* \return Timer's task removing status.
|
||||
*/
|
||||
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t timer_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_TIMER_H_INCLUDED */
|
@ -0,0 +1,247 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief USART related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SYNC_USART_H_INCLUDED
|
||||
#define _HAL_SYNC_USART_H_INCLUDED
|
||||
|
||||
#include "hal_io.h"
|
||||
#include <hpl_usart_sync.h>
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_usart_sync
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Synchronous USART descriptor
|
||||
*/
|
||||
struct usart_sync_descriptor {
|
||||
struct io_descriptor io;
|
||||
struct _usart_sync_device device;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize USART interface
|
||||
*
|
||||
* This function initializes the given I/O descriptor to be used
|
||||
* as USART interface descriptor.
|
||||
* It checks if the given hardware is not initialized and
|
||||
* if the given hardware is permitted to be initialized.
|
||||
*
|
||||
* \param[out] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] func The pointer to as set of functions pointers
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize USART interface
|
||||
*
|
||||
* This function deinitializes the given I/O descriptor.
|
||||
* It checks if the given hardware is initialized and
|
||||
* if the given hardware is permitted to be deinitialized.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Enable USART interface
|
||||
*
|
||||
* Enables the USART interface
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return Enabling status.
|
||||
*/
|
||||
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Disable USART interface
|
||||
*
|
||||
* Disables the USART interface
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return Disabling status.
|
||||
*/
|
||||
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I/O descriptor
|
||||
*
|
||||
* This function retrieves the I/O descriptor of the given USART descriptor.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[out] io An I/O descriptor to retrieve
|
||||
*
|
||||
* \return The status of the I/O descriptor retrieving.
|
||||
*/
|
||||
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
|
||||
|
||||
/**
|
||||
* \brief Specify action for flow control pins
|
||||
*
|
||||
* This function sets the action (or state) for the flow control pins
|
||||
* if the flow control is enabled.
|
||||
* It sets the state of flow control pins only if the automatic support of
|
||||
* the flow control is not supported by the hardware.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] state A state to set the flow control pins
|
||||
*
|
||||
* \return The status of flow control action setup.
|
||||
*/
|
||||
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
|
||||
const union usart_flow_control_state state);
|
||||
|
||||
/**
|
||||
* \brief Set USART baud rate
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] baud_rate A baud rate to set
|
||||
*
|
||||
* \return The status of baud rate setting.
|
||||
*/
|
||||
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
|
||||
|
||||
/**
|
||||
* \brief Set USART data order
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] data_order A data order to set
|
||||
*
|
||||
* \return The status of data order setting.
|
||||
*/
|
||||
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
|
||||
|
||||
/**
|
||||
* \brief Set USART mode
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] mode A mode to set
|
||||
*
|
||||
* \return The status of mode setting.
|
||||
*/
|
||||
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set USART parity
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] parity A parity to set
|
||||
*
|
||||
* \return The status of parity setting.
|
||||
*/
|
||||
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
|
||||
|
||||
/**
|
||||
* \brief Set USART stop bits
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] stop_bits Stop bits to set
|
||||
*
|
||||
* \return The status of stop bits setting.
|
||||
*/
|
||||
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
|
||||
|
||||
/**
|
||||
* \brief Set USART character size
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] size A character size to set
|
||||
*
|
||||
* \return The status of character size setting.
|
||||
*/
|
||||
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the state of flow control pins
|
||||
*
|
||||
* This function retrieves the of flow control pins
|
||||
* if the flow control is enabled.
|
||||
* Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
|
||||
* if the flow control is done by the hardware
|
||||
* and the pins state cannot be read out.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[out] state The state of flow control pins
|
||||
*
|
||||
* \return The status of flow control state reading.
|
||||
*/
|
||||
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
|
||||
union usart_flow_control_state *const state);
|
||||
|
||||
/**
|
||||
* \brief Check if the USART transmitter is empty
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return The status of USART TX empty checking.
|
||||
* \retval 0 The USART transmitter is not empty
|
||||
* \retval 1 The USART transmitter is empty
|
||||
*/
|
||||
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Check if the USART receiver is not empty
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return The status of USART RX empty checking.
|
||||
* \retval 1 The USART receiver is not empty
|
||||
* \retval 0 The USART receiver is empty
|
||||
*/
|
||||
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t usart_sync_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HAL_SYNC_USART_H_INCLUDED */
|
@ -0,0 +1,277 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
|
||||
*
|
||||
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef HPL_CMCC_H_
|
||||
#define HPL_CMCC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/**
|
||||
* \Cache driver MACROS
|
||||
*/
|
||||
#define CMCC_DISABLE 0U
|
||||
#define CMCC_ENABLE 1U
|
||||
#define IS_CMCC_DISABLED 0U
|
||||
#define IS_CMCC_ENABLED 1U
|
||||
#define CMCC_WAY_NOS 4U
|
||||
#define CMCC_LINE_NOS 64U
|
||||
#define CMCC_MONITOR_DISABLE 0U
|
||||
|
||||
/**
|
||||
* \brief Cache size configurations
|
||||
*/
|
||||
enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
|
||||
|
||||
/**
|
||||
* \brief Way Numbers
|
||||
*/
|
||||
enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
|
||||
|
||||
/**
|
||||
* \brief Cache monitor configurations
|
||||
*/
|
||||
enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
|
||||
|
||||
/**
|
||||
* \brief Cache configuration structure
|
||||
*/
|
||||
struct _cache_cfg {
|
||||
enum conf_cache_size cache_size;
|
||||
bool data_cache_disable;
|
||||
bool inst_cache_disable;
|
||||
bool gclk_gate_disable;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Cache enable status
|
||||
*/
|
||||
static inline bool _is_cache_enabled(const void *hw)
|
||||
{
|
||||
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache disable status
|
||||
*/
|
||||
static inline bool _is_cache_disabled(const void *hw)
|
||||
{
|
||||
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache enable
|
||||
*/
|
||||
static inline int32_t _cmcc_enable(const void *hw)
|
||||
{
|
||||
int32_t return_value;
|
||||
|
||||
if (_is_cache_disabled(hw)) {
|
||||
hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
|
||||
return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
|
||||
} else {
|
||||
return_value = ERR_NO_CHANGE;
|
||||
}
|
||||
|
||||
return return_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache disable
|
||||
*/
|
||||
static inline int32_t _cmcc_disable(const void *hw)
|
||||
{
|
||||
hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
|
||||
while (!(_is_cache_disabled(hw)))
|
||||
;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initialize Cache Module
|
||||
*
|
||||
* This function initialize low level cmcc module configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _cmcc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Configure CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] cache configuration structure pointer
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
|
||||
|
||||
/**
|
||||
* \brief Enable data cache in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_data_cache(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Enable instruction cache in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Enable clock gating in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Configure the cache size in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from cache size configuration enumerator
|
||||
* 0->1K, 1->2K, 2->4K(default)
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
|
||||
|
||||
/**
|
||||
* \brief Lock the mentioned WAY in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num_index" enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
|
||||
|
||||
/**
|
||||
* \brief Unlock the mentioned WAY in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num_index" enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
|
||||
|
||||
/**
|
||||
* \brief Invalidate the mentioned cache line in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
|
||||
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
|
||||
|
||||
/**
|
||||
* \brief Invalidate entire cache entries in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_invalidate_all(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Configure cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from cache monitor configurations enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
|
||||
|
||||
/**
|
||||
* \brief Enable cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Disable cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_disable_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Reset cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_reset_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Get cache monitor event counter value from CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return event counter value
|
||||
*/
|
||||
uint32_t _cmcc_get_monitor_event_count(const void *hw);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPL_CMCC_H_ */
|
@ -0,0 +1,56 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief CPU core related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_CORE_H_INCLUDED
|
||||
#define _HPL_CORE_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Core
|
||||
*
|
||||
* \section hpl_core_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include "hpl_core_port.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_CORE_H_INCLUDED */
|
@ -0,0 +1,97 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Delay related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_DELAY_H_INCLUDED
|
||||
#define _HPL_DELAY_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Delay
|
||||
*
|
||||
* \section hpl_delay_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifndef _UNIT_TEST_
|
||||
#include <compiler.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
|
||||
/**
|
||||
* \brief Initialize delay functionality
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
void _delay_init(void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of cycles to delay for the given amount of us
|
||||
*
|
||||
* \param[in] us The amount of us to delay for
|
||||
*
|
||||
* \return The amount of cycles
|
||||
*/
|
||||
uint32_t _get_cycles_for_us(const uint16_t us);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of cycles to delay for the given amount of ms
|
||||
*
|
||||
* \param[in] ms The amount of ms to delay for
|
||||
*
|
||||
* \return The amount of cycles
|
||||
*/
|
||||
uint32_t _get_cycles_for_ms(const uint16_t ms);
|
||||
|
||||
/**
|
||||
* \brief Delay loop to delay n number of cycles
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] cycles The amount of cycles to delay for
|
||||
*/
|
||||
void _delay_cycles(void *const hw, uint32_t cycles);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_DELAY_H_INCLUDED */
|
@ -0,0 +1,176 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_DMA_H_INCLUDED
|
||||
#define _HPL_DMA_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL DMA
|
||||
*
|
||||
* \section hpl_dma_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct _dma_resource;
|
||||
|
||||
/**
|
||||
* \brief DMA callback types
|
||||
*/
|
||||
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief DMA interrupt callbacks
|
||||
*/
|
||||
struct _dma_callbacks {
|
||||
void (*transfer_done)(struct _dma_resource *resource);
|
||||
void (*error)(struct _dma_resource *resource);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief DMA resource structure
|
||||
*/
|
||||
struct _dma_resource {
|
||||
struct _dma_callbacks dma_cb;
|
||||
void * back;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize DMA
|
||||
*
|
||||
* This function does low level DMA configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _dma_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set destination address
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] dst Destination address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
|
||||
|
||||
/**
|
||||
* \brief Set source address
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] src Source address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
|
||||
|
||||
/**
|
||||
* \brief Set next descriptor address
|
||||
*
|
||||
* \param[in] current_channel Current DMA channel to set next descriptor address
|
||||
* \param[in] next_channel Next DMA channel used as next descriptor
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable source address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable Destination address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
|
||||
/**
|
||||
* \brief Set the amount of data to be transfered per transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set data amount for
|
||||
* \param[in] amount Data amount
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
|
||||
|
||||
/**
|
||||
* \brief Trigger DMA transaction on the given channel
|
||||
*
|
||||
* \param[in] channel DMA channel to trigger transaction on
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
|
||||
|
||||
/**
|
||||
* \brief Retrieves DMA resource structure
|
||||
*
|
||||
* \param[out] resource The resource to be retrieved
|
||||
* \param[in] channel DMA channel to retrieve structure for
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable DMA interrupt
|
||||
*
|
||||
* \param[in] channel DMA channel to enable/disable interrupt for
|
||||
* \param[in] type The type of interrupt to disable/enable if applicable
|
||||
* \param[in] state Enable or disable
|
||||
*/
|
||||
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HPL_DMA_H_INCLUDED */
|
@ -0,0 +1,185 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Port related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_GPIO_H_INCLUDED
|
||||
#define _HPL_GPIO_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Port
|
||||
*
|
||||
* \section hpl_port_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**
|
||||
* \brief Macros for the pin and port group, lower 5
|
||||
* bits stands for pin number in the group, higher 3
|
||||
* bits stands for port group
|
||||
*/
|
||||
#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
|
||||
#define GPIO_PORT(n) ((n) >> 5)
|
||||
#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
|
||||
#define GPIO_PIN_FUNCTION_OFF 0xffffffff
|
||||
|
||||
/**
|
||||
* \brief PORT pull mode settings
|
||||
*/
|
||||
enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
|
||||
/**
|
||||
* \brief PORT direction settins
|
||||
*/
|
||||
enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
|
||||
|
||||
/**
|
||||
* \brief PORT group abstraction
|
||||
*/
|
||||
|
||||
enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Port initialization function
|
||||
*
|
||||
* Port initialization function should setup the port module based
|
||||
* on a static configuration file, this function should normally
|
||||
* not be called directly, but is a part of hal_init()
|
||||
*/
|
||||
void _gpio_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set direction on port with mask
|
||||
*
|
||||
* Set data direction for each pin, or disable the pin
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to the
|
||||
* corresponding pin
|
||||
* \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input
|
||||
* and disable input buffer to disable the pin
|
||||
* GPIO_DIRECTION_IN = set pin direction to input
|
||||
* and enable input buffer to enable the pin
|
||||
* GPIO_DIRECTION_OUT = set pin direction to output
|
||||
* and disable input buffer
|
||||
*/
|
||||
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
|
||||
const enum gpio_direction direction);
|
||||
|
||||
/**
|
||||
* \brief Set output level on port with mask
|
||||
*
|
||||
* Sets output state on pin to high or low with pin masking
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to
|
||||
* the corresponding pin
|
||||
* \param[in] level true = pin level is set to 1
|
||||
* false = pin level is set to 0
|
||||
*/
|
||||
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
|
||||
|
||||
/**
|
||||
* \brief Change output level to the opposite with mask
|
||||
*
|
||||
* Change pin output level to the opposite with pin masking
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to
|
||||
* the corresponding pin
|
||||
*/
|
||||
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
|
||||
|
||||
/**
|
||||
* \brief Get input levels on all port pins
|
||||
*
|
||||
* Get input level on all port pins, will read IN register if configured to
|
||||
* input and OUT register if configured as output
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
*/
|
||||
static inline uint32_t _gpio_get_level(const enum gpio_port port);
|
||||
|
||||
/**
|
||||
* \brief Set pin pull mode
|
||||
*
|
||||
* Set pull mode on a single pin
|
||||
*
|
||||
* \notice This function will automatically change pin direction to input
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] pin The pin in the group that pull mode should be selected
|
||||
* for
|
||||
* \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled
|
||||
* GPIO_PULL_DOWN = pull resistor on pin will pull pin
|
||||
* level to ground level
|
||||
* GPIO_PULL_UP = pull resistor on pin will pull pin
|
||||
* level to VCC
|
||||
*/
|
||||
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
|
||||
const enum gpio_pull_mode pull_mode);
|
||||
|
||||
/**
|
||||
* \brief Set gpio function
|
||||
*
|
||||
* Select which function a gpio is used for
|
||||
*
|
||||
* \param[in] gpio The gpio to set function for
|
||||
* \param[in] function The gpio function is given by a 32-bit wide bitfield
|
||||
* found in the header files for the device
|
||||
*
|
||||
*/
|
||||
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
|
||||
|
||||
#include <hpl_gpio_base.h>
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_GPIO_H_INCLUDED */
|
@ -0,0 +1,205 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
|
||||
#define _HPL_I2C_M_ASYNC_H_INCLUDED
|
||||
|
||||
#include "hpl_i2c_m_sync.h"
|
||||
#include "hpl_irq.h"
|
||||
#include "utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c master callback names
|
||||
*/
|
||||
enum _i2c_m_async_callback_type {
|
||||
I2C_M_ASYNC_DEVICE_ERROR,
|
||||
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
|
||||
I2C_M_ASYNC_DEVICE_RX_COMPLETE
|
||||
};
|
||||
|
||||
struct _i2c_m_async_device;
|
||||
|
||||
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
|
||||
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
|
||||
|
||||
/**
|
||||
* \brief i2c callback pointers structure
|
||||
*/
|
||||
struct _i2c_m_async_callback {
|
||||
_i2c_error_cb_t error;
|
||||
_i2c_complete_cb_t tx_complete;
|
||||
_i2c_complete_cb_t rx_complete;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c device structure
|
||||
*/
|
||||
struct _i2c_m_async_device {
|
||||
struct _i2c_m_service service;
|
||||
void * hw;
|
||||
struct _i2c_m_async_callback cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize I2C in interrupt mode
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c interrupt device structure
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize I2C in interrupt mode
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Transfer data by I2C
|
||||
*
|
||||
* This function does low level I2C data transfer.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] msg The pointer to i2c msg structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate of I2C
|
||||
*
|
||||
* This function does low level I2C set baud rate.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] clkrate The clock rate(KHz) input to i2c module
|
||||
* \param[in] baudrate The demand baud rate(KHz) of i2c module
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* \brief Register callback to I2C
|
||||
*
|
||||
* This function does low level I2C callback register.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] cb_type The callback type request
|
||||
* \param[in] func The callback function pointer
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
|
||||
FUNC_PTR func);
|
||||
|
||||
/**
|
||||
* \brief Generate stop condition on the I2C bus
|
||||
*
|
||||
* This function will generate a stop condition on the I2C bus
|
||||
*
|
||||
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
|
||||
*
|
||||
* \return Operation status
|
||||
* \retval 0 Operation executed successfully
|
||||
* \retval <0 Operation failed
|
||||
*/
|
||||
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Returns the number of bytes left or not used in the I2C message buffer
|
||||
*
|
||||
* This function will return the number of bytes left (not written to the bus) or still free
|
||||
* (not received from the bus) in the message buffer, depending on direction of transmission.
|
||||
*
|
||||
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
|
||||
*
|
||||
* \return Number of bytes or error code
|
||||
* \retval >0 Positive number indicating bytes left
|
||||
* \retval 0 Buffer is full/empty depending on direction
|
||||
* \retval <0 Error code
|
||||
*/
|
||||
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable I2C master interrupt
|
||||
*
|
||||
* param[in] device The pointer to I2C master device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] state Enable or disable
|
||||
*/
|
||||
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
|
||||
const bool state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
@ -0,0 +1,185 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
|
||||
#define _HPL_I2C_M_SYNC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c flags
|
||||
*/
|
||||
#define I2C_M_RD 0x0001 /* read data, from slave to master */
|
||||
#define I2C_M_BUSY 0x0100
|
||||
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
|
||||
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
|
||||
#define I2C_M_FAIL 0x1000
|
||||
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
|
||||
|
||||
/**
|
||||
* \brief i2c Return codes
|
||||
*/
|
||||
#define I2C_OK 0 /* Operation successful */
|
||||
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
|
||||
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
|
||||
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
|
||||
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
|
||||
#define I2C_ERR_BUS -5 /* Bus error */
|
||||
#define I2C_ERR_BUSY -6 /* Device busy */
|
||||
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
|
||||
|
||||
/**
|
||||
* \brief i2c I2C Modes
|
||||
*/
|
||||
#define I2C_STANDARD_MODE 0x00
|
||||
#define I2C_FASTMODE 0x01
|
||||
#define I2C_HIGHSPEED_MODE 0x02
|
||||
|
||||
/**
|
||||
* \brief i2c master message structure
|
||||
*/
|
||||
struct _i2c_m_msg {
|
||||
uint16_t addr;
|
||||
volatile uint16_t flags;
|
||||
int32_t len;
|
||||
uint8_t * buffer;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c master service
|
||||
*/
|
||||
struct _i2c_m_service {
|
||||
struct _i2c_m_msg msg;
|
||||
uint16_t mode;
|
||||
uint16_t trise;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c sync master device structure
|
||||
*/
|
||||
struct _i2c_m_sync_device {
|
||||
struct _i2c_m_service service;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize I2C
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize I2C
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Transfer data by I2C
|
||||
*
|
||||
* This function does low level I2C data transfer.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] msg The pointer to i2c msg structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate of I2C
|
||||
*
|
||||
* This function does low level I2C set baud rate.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] clkrate The clock rate(KHz) input to i2c module
|
||||
* \param[in] baudrate The demand baud rate(KHz) of i2c module
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* \brief Send send condition on the I2C bus
|
||||
*
|
||||
* This function will generate a stop condition on the I2C bus
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device struct
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
@ -0,0 +1,184 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
|
||||
#define _HPL_I2C_S_ASYNC_H_INCLUDED
|
||||
|
||||
#include "hpl_i2c_s_sync.h"
|
||||
#include "hpl_irq.h"
|
||||
#include "utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c callback types
|
||||
*/
|
||||
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
|
||||
|
||||
/**
|
||||
* \brief Forward declaration of I2C Slave device
|
||||
*/
|
||||
struct _i2c_s_async_device;
|
||||
|
||||
/**
|
||||
* \brief i2c slave callback function type
|
||||
*/
|
||||
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
|
||||
|
||||
/**
|
||||
* \brief i2c slave callback pointers structure
|
||||
*/
|
||||
struct _i2c_s_async_callback {
|
||||
void (*error)(struct _i2c_s_async_device *const device);
|
||||
void (*tx)(struct _i2c_s_async_device *const device);
|
||||
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c slave device structure
|
||||
*/
|
||||
struct _i2c_s_async_device {
|
||||
void * hw;
|
||||
struct _i2c_s_async_callback cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize asynchronous I2C slave
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] device The pointer to i2c interrupt device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize asynchronous I2C in interrupt mode
|
||||
*
|
||||
* \param[in] device The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if 10-bit addressing mode is on
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Cheking status
|
||||
* \retval 1 10-bit addressing mode is on
|
||||
* \retval 0 10-bit addressing mode is off
|
||||
*/
|
||||
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set I2C slave address
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] address Address to set
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I2C slave status
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
*\return I2C slave status
|
||||
*/
|
||||
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Abort data transmission
|
||||
*
|
||||
* \param[in] device The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable I2C slave interrupt
|
||||
*
|
||||
* param[in] device The pointer to I2C slave device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] disable Enable or disable
|
||||
*/
|
||||
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
|
||||
const bool disable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */
|
@ -0,0 +1,184 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
|
||||
#define _HPL_I2C_S_SYNC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief I2C Slave status type
|
||||
*/
|
||||
typedef uint32_t i2c_s_status_t;
|
||||
|
||||
/**
|
||||
* \brief i2c slave device structure
|
||||
*/
|
||||
struct _i2c_s_sync_device {
|
||||
void *hw;
|
||||
};
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize synchronous I2C slave
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize synchronous I2C slave
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if 10-bit addressing mode is on
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Cheking status
|
||||
* \retval 1 10-bit addressing mode is on
|
||||
* \retval 0 10-bit addressing mode is off
|
||||
*/
|
||||
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set I2C slave address
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] address Address to set
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I2C slave status
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
*\return I2C slave status
|
||||
*/
|
||||
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Clear the Data Ready interrupt flag
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Read a byte from the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Data received via I2C interface.
|
||||
*/
|
||||
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if I2C is ready to send next byte
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Status of the ready check.
|
||||
* \retval true if the I2C is ready to send next byte
|
||||
* \retval false if the I2C is not ready to send next byte
|
||||
*/
|
||||
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if there is data received by I2C
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Status of the data received check.
|
||||
* \retval true if the I2C has received a byte
|
||||
* \retval false if the I2C has not received a byte
|
||||
*/
|
||||
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */
|
@ -0,0 +1,124 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Init related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_INIT_H_INCLUDED
|
||||
#define _HPL_INIT_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Init
|
||||
*
|
||||
* \section hpl_init_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initializes clock sources
|
||||
*/
|
||||
void _sysctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initializes Power Manager
|
||||
*/
|
||||
void _pm_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize generators
|
||||
*/
|
||||
void _gclk_init_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize 32 kHz clock sources
|
||||
*/
|
||||
void _osc32kctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources
|
||||
*/
|
||||
void _oscctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources that need input reference clocks
|
||||
*/
|
||||
void _sysctrl_init_referenced_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources that need input reference clocks
|
||||
*/
|
||||
void _oscctrl_init_referenced_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize master clock generator
|
||||
*/
|
||||
void _mclk_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock generator
|
||||
*/
|
||||
void _lpmcu_misc_regs_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock generator
|
||||
*/
|
||||
void _pmc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set performance level
|
||||
*
|
||||
* \param[in] level The performance level to set
|
||||
*/
|
||||
void _set_performance_level(const uint8_t level);
|
||||
|
||||
/**
|
||||
* \brief Initialize the chip
|
||||
*/
|
||||
void _init_chip(void);
|
||||
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_INIT_H_INCLUDED */
|
@ -0,0 +1,116 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief IRQ related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_IRQ_H_INCLUDED
|
||||
#define _HPL_IRQ_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL IRQ
|
||||
*
|
||||
* \section hpl_irq_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief IRQ descriptor
|
||||
*/
|
||||
struct _irq_descriptor {
|
||||
void (*handler)(void *parameter);
|
||||
void *parameter;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Retrieve current IRQ number
|
||||
*
|
||||
* \return The current IRQ number
|
||||
*/
|
||||
uint8_t _irq_get_current(void);
|
||||
|
||||
/**
|
||||
* \brief Disable the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to disable
|
||||
*/
|
||||
void _irq_disable(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Set the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to set
|
||||
*/
|
||||
void _irq_set(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Clear the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to clear
|
||||
*/
|
||||
void _irq_clear(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Enable the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to enable
|
||||
*/
|
||||
void _irq_enable(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Register IRQ handler
|
||||
*
|
||||
* \param[in] number The number registered IRQ
|
||||
* \param[in] irq The pointer to irq handler to register
|
||||
*
|
||||
* \return The status of IRQ handler registering
|
||||
* \retval -1 Passed parameters were invalid
|
||||
* \retval 0 The registering is completed successfully
|
||||
*/
|
||||
void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_IRQ_H_INCLUDED */
|
@ -0,0 +1,37 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Family-dependent missing features expected by HAL
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, |