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almost got makefile working!

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stable
Penguin 5 years ago
parent 2ba980d833
commit 068e16b549
442 changed files with 282931 additions and 0 deletions
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2
software/firmware/oracle_e54_edition/.gdb_history
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q
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6
software/firmware/oracle_e54_edition/AtmelStart.env_conf
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<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
</device-packs>
</environment>

215
software/firmware/oracle_e54_edition/AtmelStart.gpdsc
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<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
<vendor>Atmel</vendor>
<name>My Project</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
<releases>
<release version="1.0.1">Initial version</release>
</releases>
<taxonomy>
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
</taxonomy>
<generators>
<generator id="AtmelStart">
<description>Atmel Start</description>
<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
<command>http://start.atmel.com/</command>
<files>
<file category="generator" name="atmel_start_config.atstart"/>
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
</files>
</generator>
</generators>
<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
</condition>
<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="GCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
<files>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/timer.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gmac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_timer.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_timer.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_async.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
</files>
</component>
</components>
</package>

865
software/firmware/oracle_e54_edition/CMSIS/Core/Include/cmsis_armcc.h
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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software/firmware/oracle_e54_edition/CMSIS/Core/Include/cmsis_iccarm.h
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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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software/firmware/oracle_e54_edition/CMSIS/Core/Include/cmsis_version.h
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.5
* @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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software/firmware/oracle_e54_edition/CMSIS/Core/Include/mpu_armv8.h
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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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<div id="projectname">CMSIS-Core (Cortex-M)
&#160;<span id="projectnumber">Version 5.1.2</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
<ul>
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
</ul>
<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
<ul>
<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone&reg; for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li>
<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
</ul>
<hr/>
<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2>
<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p>
<table class="doxtable">
<tr>
<th>File/Folder </th><th>Content </th></tr>
<tr>
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
<tr>
<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
<tr>
<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr>
<tr>
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr>
</table>
<hr/>
<h1><a class="anchor" id="ref_v6-v8M"></a>
Processor Support</h1>
<p>CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.</p>
<h2><a class="anchor" id="ref_man_sec"></a>
Cortex-M Reference Manuals</h2>
<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
<ul>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
</ul>
<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p>
<ul>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li>
</ul>
<h2><a class="anchor" id="ARMv8M"></a>
Armv8-M Architecture</h2>
<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.</p>
<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
<hr/>
<h1><a class="anchor" id="tested_tools_sec"></a>
Tested and Verified Toolchains</h1>
<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p>
<ul>
<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)</li>
<li>Arm: Arm Compiler 6.9</li>
<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)</li>
<li>GNU: GNU Tools for Arm Embedded 6.3.1 20170620</li>
<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li>
</ul>
<hr/>
</div></div><!-- contents -->
</div><!-- doc-content -->
<!-- start footer part -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
<ul>
<li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved.
<!--
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6
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</ul>
</div>
</body>
</html>

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software/firmware/oracle_e54_edition/Makefile
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##
# Project Title
#
# @file
# @version 0.1
NAME=oracle_e54_ed
TOOLCHAIN=arm-none-eabi-
CC=gcc
print-% : ; @echo $* = $($*)
#DIR_INCLUDES = \
#-I"./" \
-I"./config" \
-I"./hal/include" \
-I"./hal/utils/include" \
-I"./hpl/cmcc" \
-I"./hpl/core" \
-I"./hpl/dmac" \
-I"./hpl/eic" \
-I"./hpl/gclk" \
-I"./hpl/mclk" \
-I"./hpl/osc32kctrl" \
-I"./hpl/oscctrl" \
-I"./hpl/pm" \
-I"./hpl/port" \
-I"./hpl/ramecc" \
-I"./hpl/sercom" \
-I"./hpl/tc" \
-I"./hri" \
-I"./CMSIS/Core/Include" \
-I"./include"
#INC=$(shell find . -type f -name '*.h' -printf "-I\"./%h\" \\\ \n" | sort -u)
#INC=$(shell find . -type f -name '*.h' -printf "-I\"./%h\"\0" | sort -zu | sed -z 's/$/\n/')
INC=$(shell find . -type f -name '*.h' -printf '-I./%h\0' | uniq -z | sort -zu | tr '\0' ' ')
OUTPUT_FILE_NAME=$(NAME)
OUTPUT_FILE_PATH+=$(OUTPUT_FILE_NAME).elf
SRC:=$(shell find ./ -type f -name '*.c')
OBJ:=$(patsubst %.c, %.o, $(SRC))
DEPS:=$(OBJ:%.o=%.d)
#all targets
all: $(OUTPUT_FILE_PATH)
#linker target
$(OUTPUT_FILE_PATH): $(OBJ)
@echo Building target: $@
@echo Invoking: ARM/GNU Linker
"$(TOOLCHAIN)$(CC)" -o $(OUTPUT_FILE_NAME).elf $(OBJ)
# compiler targets
%.o: %.c
@echo Building file: $<
@echo ARM/GNU C Compiler
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
$(INC) \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.s
@echo Building file: $<
@echo ARM/GNU Assembler
$(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
$(INC) \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.S
@echo Building file: $<
@echo ARM/GNU Preprocessing Assembler
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
$(INC) \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
# Detect changes in the dependent files and recompile the respective object files.
# end

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software/firmware/oracle_e54_edition/armcc/Makefile
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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
ifdef SystemRoot
SHELL = cmd.exe
MK_DIR = mkdir
else
ifeq ($(shell uname), Linux)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
MK_DIR = mkdir -p
endif
endif
# List the subdirectories for creating object files
SUB_DIRS += \
\
hpl/pm \
hpl/tc \
hpl/osc32kctrl \
hpl/ramecc \
hpl/dmac \
hal/src \
hpl/mclk \
hpl/eic \
hpl/sercom \
examples \
hpl/gclk \
hpl/oscctrl \
hal/utils/src \
armcc/arm_addon/armcc/arm \
armcc/arm_addon/armcc \
hpl/core \
hpl/cmcc
# List the object files
OBJS += \
hal/src/hal_io.o \
armcc/arm_addon/armcc/system_same54.o \
hpl/eic/hpl_eic.o \
hpl/core/hpl_core_m4.o \
hal/src/hal_timer.o \
hal/src/hal_i2c_m_sync.o \
hal/src/hal_delay.o \
hpl/pm/hpl_pm.o \
hpl/core/hpl_init.o \
hpl/ramecc/hpl_ramecc.o \
hal/utils/src/utils_list.o \
hal/utils/src/utils_assert.o \
hpl/dmac/hpl_dmac.o \
hpl/oscctrl/hpl_oscctrl.o \
hpl/mclk/hpl_mclk.o \
hpl/sercom/hpl_sercom.o \
hpl/gclk/hpl_gclk.o \
hal/src/hal_init.o \
main.o \
hpl/osc32kctrl/hpl_osc32kctrl.o \
examples/driver_examples.o \
driver_init.o \
hal/src/hal_usart_async.o \
hal/src/hal_ext_irq.o \
hal/utils/src/utils_ringbuffer.o \
hal/src/hal_gpio.o \
hal/utils/src/utils_event.o \
hal/src/hal_sleep.o \
hal/src/hal_cache.o \
hpl/cmcc/hpl_cmcc.o \
atmel_start.o \
hpl/tc/hpl_tc.o \
hal/src/hal_atomic.o \
armcc/arm_addon/armcc/arm/startup_same54.o
OBJS_AS_ARGS += \
"hal/src/hal_io.o" \
"armcc/arm_addon/armcc/system_same54.o" \
"hpl/eic/hpl_eic.o" \
"hpl/core/hpl_core_m4.o" \
"hal/src/hal_timer.o" \
"hal/src/hal_i2c_m_sync.o" \
"hal/src/hal_delay.o" \
"hpl/pm/hpl_pm.o" \
"hpl/core/hpl_init.o" \
"hpl/ramecc/hpl_ramecc.o" \
"hal/utils/src/utils_list.o" \
"hal/utils/src/utils_assert.o" \
"hpl/dmac/hpl_dmac.o" \
"hpl/oscctrl/hpl_oscctrl.o" \
"hpl/mclk/hpl_mclk.o" \
"hpl/sercom/hpl_sercom.o" \
"hpl/gclk/hpl_gclk.o" \
"hal/src/hal_init.o" \
"main.o" \
"hpl/osc32kctrl/hpl_osc32kctrl.o" \
"examples/driver_examples.o" \
"driver_init.o" \
"hal/src/hal_usart_async.o" \
"hal/src/hal_ext_irq.o" \
"hal/utils/src/utils_ringbuffer.o" \
"hal/src/hal_gpio.o" \
"hal/utils/src/utils_event.o" \
"hal/src/hal_sleep.o" \
"hal/src/hal_cache.o" \
"hpl/cmcc/hpl_cmcc.o" \
"atmel_start.o" \
"hpl/tc/hpl_tc.o" \
"hal/src/hal_atomic.o" \
"armcc/arm_addon/armcc/arm/startup_same54.o"
# List the dependency files
DEPS := $(OBJS:%.o=%.d)
DEPS_AS_ARGS += \
"hal/utils/src/utils_event.d" \
"hal/src/hal_io.d" \
"armcc/arm_addon/armcc/system_same54.d" \
"hpl/ramecc/hpl_ramecc.d" \
"hpl/core/hpl_core_m4.d" \
"hpl/eic/hpl_eic.d" \
"hal/src/hal_i2c_m_sync.d" \
"hal/src/hal_timer.d" \
"hal/utils/src/utils_list.d" \
"hpl/cmcc/hpl_cmcc.d" \
"hpl/dmac/hpl_dmac.d" \
"hal/utils/src/utils_assert.d" \
"hal/src/hal_delay.d" \
"hpl/core/hpl_init.d" \
"hpl/pm/hpl_pm.d" \
"hpl/gclk/hpl_gclk.d" \
"hpl/sercom/hpl_sercom.d" \
"hal/src/hal_init.d" \
"hpl/mclk/hpl_mclk.d" \
"driver_init.d" \
"hal/src/hal_usart_async.d" \
"hpl/osc32kctrl/hpl_osc32kctrl.d" \
"main.d" \
"examples/driver_examples.d" \
"hal/src/hal_cache.d" \
"hal/src/hal_sleep.d" \
"hal/utils/src/utils_ringbuffer.d" \
"hal/src/hal_ext_irq.d" \
"hal/src/hal_gpio.d" \
"hal/src/hal_atomic.d" \
"hpl/tc/hpl_tc.d" \
"hpl/oscctrl/hpl_oscctrl.d" \
"armcc/arm_addon/armcc/arm/startup_same54.d" \
"atmel_start.d"
OUTPUT_FILE_NAME :=AtmelStart
QUOTE := "
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
vpath %.c ../
vpath %.s ../
vpath %.S ../
# All Target
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
# Linker target
$(OUTPUT_FILE_PATH): $(OBJS)
@echo Building target: $@
@echo Invoking: ARMCC Linker
$(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \
--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \
--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \
-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \
$(OBJS_AS_ARGS)
@echo Finished building target: $@
# Compiler target(s)
%.o: %.c
@echo Building file: $<
@echo ARMCC Compiler
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
--depend "$@" -o "$@" "$<"
@echo Finished building: $<
%.o: %.s
@echo Building file: $<
@echo ARMCC Assembler
$(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAME54P20A__ SETA 1" \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
--depend "$(@:%.o=%.d)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.S
@echo Building file: $<
@echo ARMCC Preprocessing Assembler
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
--depend "$@" -o "$@" "$<"
@echo Finished building: $<
# Detect changes in the dependent files and recompile the respective object files.
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(DEPS)),)
-include $(DEPS)
endif
endif
$(SUB_DIRS):
$(MK_DIR) "$@"
clean:
rm -f $(OBJS_AS_ARGS)
rm -f $(OUTPUT_FILE_PATH)
rm -f $(DEPS_AS_ARGS)
rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf

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software/firmware/oracle_e54_edition/armcc/arm_addon/armcc/arm/startup_same54.s
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;/*****************************************************************************
; * @file startup_SAME54.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Atmel SAME54 Device Series
; * @version V1.0.0
; * @date 16. January 2017
; *
; * @note
; * Copyright (C) 2017 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD MCLK_Handler ; 1 Main Clock
DCD OSCCTRL_0_Handler ; 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0
DCD OSCCTRL_1_Handler ; 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1
DCD OSCCTRL_2_Handler ; 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY
DCD OSCCTRL_3_Handler ; 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0
DCD OSCCTRL_4_Handler ; 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1
DCD OSC32KCTRL_Handler ; 7 32kHz Oscillators Control
DCD SUPC_0_Handler ; 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY
DCD SUPC_1_Handler ; 9 SUPC_BOD12DET, SUPC_BOD33DET
DCD WDT_Handler ; 10 Watchdog Timer
DCD RTC_Handler ; 11 Real-Time Counter
DCD EIC_0_Handler ; 12 EIC_EXTINT_0
DCD EIC_1_Handler ; 13 EIC_EXTINT_1
DCD EIC_2_Handler ; 14 EIC_EXTINT_2
DCD EIC_3_Handler ; 15 EIC_EXTINT_3
DCD EIC_4_Handler ; 16 EIC_EXTINT_4
DCD EIC_5_Handler ; 17 EIC_EXTINT_5
DCD EIC_6_Handler ; 18 EIC_EXTINT_6
DCD EIC_7_Handler ; 19 EIC_EXTINT_7
DCD EIC_8_Handler ; 20 EIC_EXTINT_8
DCD EIC_9_Handler ; 21 EIC_EXTINT_9
DCD EIC_10_Handler ; 22 EIC_EXTINT_10
DCD EIC_11_Handler ; 23 EIC_EXTINT_11
DCD EIC_12_Handler ; 24 EIC_EXTINT_12
DCD EIC_13_Handler ; 25 EIC_EXTINT_13
DCD EIC_14_Handler ; 26 EIC_EXTINT_14
DCD EIC_15_Handler ; 27 EIC_EXTINT_15
DCD FREQM_Handler ; 28 Frequency Meter
DCD NVMCTRL_0_Handler ; 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7
DCD NVMCTRL_1_Handler ; 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9
DCD DMAC_0_Handler ; 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0
DCD DMAC_1_Handler ; 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1
DCD DMAC_2_Handler ; 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2
DCD DMAC_3_Handler ; 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3
DCD DMAC_4_Handler ; 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9
DCD EVSYS_0_Handler ; 36 EVSYS_EVD_0, EVSYS_OVR_0
DCD EVSYS_1_Handler ; 37 EVSYS_EVD_1, EVSYS_OVR_1
DCD EVSYS_2_Handler ; 38 EVSYS_EVD_2, EVSYS_OVR_2
DCD EVSYS_3_Handler ; 39 EVSYS_EVD_3, EVSYS_OVR_3
DCD EVSYS_4_Handler ; 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9
DCD PAC_Handler ; 41 Peripheral Access Controller
DCD TAL_0_Handler ; 42 TAL_BRK
DCD TAL_1_Handler ; 43 TAL_IPS_0, TAL_IPS_1
DCD 0 ; 44 Reserved
DCD RAMECC_Handler ; 45 RAM ECC
DCD SERCOM0_0_Handler ; 46 SERCOM0_0
DCD SERCOM0_1_Handler ; 47 SERCOM0_1
DCD SERCOM0_2_Handler ; 48 SERCOM0_2
DCD SERCOM0_3_Handler ; 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6
DCD SERCOM1_0_Handler ; 50 SERCOM1_0
DCD SERCOM1_1_Handler ; 51 SERCOM1_1
DCD SERCOM1_2_Handler ; 52 SERCOM1_2
DCD SERCOM1_3_Handler ; 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6
DCD SERCOM2_0_Handler ; 54 SERCOM2_0
DCD SERCOM2_1_Handler ; 55 SERCOM2_1
DCD SERCOM2_2_Handler ; 56 SERCOM2_2
DCD SERCOM2_3_Handler ; 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6
DCD SERCOM3_0_Handler ; 58 SERCOM3_0
DCD SERCOM3_1_Handler ; 59 SERCOM3_1
DCD SERCOM3_2_Handler ; 60 SERCOM3_2
DCD SERCOM3_3_Handler ; 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6
DCD SERCOM4_0_Handler ; 62 SERCOM4_0
DCD SERCOM4_1_Handler ; 63 SERCOM4_1
DCD SERCOM4_2_Handler ; 64 SERCOM4_2
DCD SERCOM4_3_Handler ; 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6
DCD SERCOM5_0_Handler ; 66 SERCOM5_0
DCD SERCOM5_1_Handler ; 67 SERCOM5_1
DCD SERCOM5_2_Handler ; 68 SERCOM5_2
DCD SERCOM5_3_Handler ; 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6
DCD SERCOM6_0_Handler ; 70 SERCOM6_0
DCD SERCOM6_1_Handler ; 71 SERCOM6_1
DCD SERCOM6_2_Handler ; 72 SERCOM6_2
DCD SERCOM6_3_Handler ; 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6
DCD SERCOM7_0_Handler ; 74 SERCOM7_0
DCD SERCOM7_1_Handler ; 75 SERCOM7_1
DCD SERCOM7_2_Handler ; 76 SERCOM7_2
DCD SERCOM7_3_Handler ; 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6
DCD CAN0_Handler ; 78 Control Area Network 0
DCD CAN1_Handler ; 79 Control Area Network 1
DCD USB_0_Handler ; 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP
DCD USB_1_Handler ; 81 USB_SOF_HSOF
DCD USB_2_Handler ; 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7
DCD USB_3_Handler ; 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7
DCD GMAC_Handler ; 84 Ethernet MAC
DCD TCC0_0_Handler ; 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A
DCD TCC0_1_Handler ; 86 TCC0_MC_0
DCD TCC0_2_Handler ; 87 TCC0_MC_1
DCD TCC0_3_Handler ; 88 TCC0_MC_2
DCD TCC0_4_Handler ; 89 TCC0_MC_3
DCD TCC0_5_Handler ; 90 TCC0_MC_4
DCD TCC0_6_Handler ; 91 TCC0_MC_5
DCD TCC1_0_Handler ; 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A
DCD TCC1_1_Handler ; 93 TCC1_MC_0
DCD TCC1_2_Handler ; 94 TCC1_MC_1
DCD TCC1_3_Handler ; 95 TCC1_MC_2
DCD TCC1_4_Handler ; 96 TCC1_MC_3
DCD TCC2_0_Handler ; 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A
DCD TCC2_1_Handler ; 98 TCC2_MC_0
DCD TCC2_2_Handler ; 99 TCC2_MC_1
DCD TCC2_3_Handler ; 100 TCC2_MC_2
DCD TCC3_0_Handler ; 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A
DCD TCC3_1_Handler ; 102 TCC3_MC_0
DCD TCC3_2_Handler ; 103 TCC3_MC_1
DCD TCC4_0_Handler ; 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A
DCD TCC4_1_Handler ; 105 TCC4_MC_0
DCD TCC4_2_Handler ; 106 TCC4_MC_1
DCD TC0_Handler ; 107 Basic Timer Counter 0
DCD TC1_Handler ; 108 Basic Timer Counter 1
DCD TC2_Handler ; 109 Basic Timer Counter 2
DCD TC3_Handler ; 110 Basic Timer Counter 3
DCD TC4_Handler ; 111 Basic Timer Counter 4
DCD TC5_Handler ; 112 Basic Timer Counter 5
DCD TC6_Handler ; 113 Basic Timer Counter 6
DCD TC7_Handler ; 114 Basic Timer Counter 7
DCD PDEC_0_Handler ; 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A
DCD PDEC_1_Handler ; 116 PDEC_MC_0
DCD PDEC_2_Handler ; 117 PDEC_MC_1
DCD ADC0_0_Handler ; 118 ADC0_OVERRUN, ADC0_WINMON
DCD ADC0_1_Handler ; 119 ADC0_RESRDY
DCD ADC1_0_Handler ; 120 ADC1_OVERRUN, ADC1_WINMON
DCD ADC1_1_Handler ; 121 ADC1_RESRDY
DCD AC_Handler ; 122 Analog Comparators
DCD DAC_0_Handler ; 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1
DCD DAC_1_Handler ; 124 DAC_EMPTY_0
DCD DAC_2_Handler ; 125 DAC_EMPTY_1
DCD DAC_3_Handler ; 126 DAC_RESRDY_0
DCD DAC_4_Handler ; 127 DAC_RESRDY_1
DCD I2S_Handler ; 128 Inter-IC Sound Interface
DCD PCC_Handler ; 129 Parallel Capture Controller
DCD AES_Handler ; 130 Advanced Encryption Standard
DCD TRNG_Handler ; 131 True Random Generator
DCD ICM_Handler ; 132 Integrity Check Monitor
DCD PUKCC_Handler ; 133 PUblic-Key Cryptography Controller
DCD QSPI_Handler ; 134 Quad SPI interface
DCD SDHC0_Handler ; 135 SD/MMC Host Controller 0
DCD SDHC1_Handler ; 136 SD/MMC Host Controller 1
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT MCLK_Handler [WEAK]
EXPORT OSCCTRL_0_Handler [WEAK]
EXPORT OSCCTRL_1_Handler [WEAK]
EXPORT OSCCTRL_2_Handler [WEAK]
EXPORT OSCCTRL_3_Handler [WEAK]
EXPORT OSCCTRL_4_Handler [WEAK]
EXPORT OSC32KCTRL_Handler [WEAK]
EXPORT SUPC_0_Handler [WEAK]
EXPORT SUPC_1_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_0_Handler [WEAK]
EXPORT EIC_1_Handler [WEAK]
EXPORT EIC_2_Handler [WEAK]
EXPORT EIC_3_Handler [WEAK]
EXPORT EIC_4_Handler [WEAK]
EXPORT EIC_5_Handler [WEAK]
EXPORT EIC_6_Handler [WEAK]
EXPORT EIC_7_Handler [WEAK]
EXPORT EIC_8_Handler [WEAK]
EXPORT EIC_9_Handler [WEAK]
EXPORT EIC_10_Handler [WEAK]
EXPORT EIC_11_Handler [WEAK]
EXPORT EIC_12_Handler [WEAK]
EXPORT EIC_13_Handler [WEAK]
EXPORT EIC_14_Handler [WEAK]
EXPORT EIC_15_Handler [WEAK]
EXPORT FREQM_Handler [WEAK]
EXPORT NVMCTRL_0_Handler [WEAK]
EXPORT NVMCTRL_1_Handler [WEAK]
EXPORT DMAC_0_Handler [WEAK]
EXPORT DMAC_1_Handler [WEAK]
EXPORT DMAC_2_Handler [WEAK]
EXPORT DMAC_3_Handler [WEAK]
EXPORT DMAC_4_Handler [WEAK]
EXPORT EVSYS_0_Handler [WEAK]
EXPORT EVSYS_1_Handler [WEAK]
EXPORT EVSYS_2_Handler [WEAK]
EXPORT EVSYS_3_Handler [WEAK]
EXPORT EVSYS_4_Handler [WEAK]
EXPORT PAC_Handler [WEAK]
EXPORT TAL_0_Handler [WEAK]
EXPORT TAL_1_Handler [WEAK]
EXPORT RAMECC_Handler [WEAK]
EXPORT SERCOM0_0_Handler [WEAK]
EXPORT SERCOM0_1_Handler [WEAK]
EXPORT SERCOM0_2_Handler [WEAK]
EXPORT SERCOM0_3_Handler [WEAK]
EXPORT SERCOM1_0_Handler [WEAK]
EXPORT SERCOM1_1_Handler [WEAK]
EXPORT SERCOM1_2_Handler [WEAK]
EXPORT SERCOM1_3_Handler [WEAK]
EXPORT SERCOM2_0_Handler [WEAK]
EXPORT SERCOM2_1_Handler [WEAK]
EXPORT SERCOM2_2_Handler [WEAK]
EXPORT SERCOM2_3_Handler [WEAK]
EXPORT SERCOM3_0_Handler [WEAK]
EXPORT SERCOM3_1_Handler [WEAK]
EXPORT SERCOM3_2_Handler [WEAK]
EXPORT SERCOM3_3_Handler [WEAK]
EXPORT SERCOM4_0_Handler [WEAK]
EXPORT SERCOM4_1_Handler [WEAK]
EXPORT SERCOM4_2_Handler [WEAK]
EXPORT SERCOM4_3_Handler [WEAK]
EXPORT SERCOM5_0_Handler [WEAK]
EXPORT SERCOM5_1_Handler [WEAK]
EXPORT SERCOM5_2_Handler [WEAK]
EXPORT SERCOM5_3_Handler [WEAK]
EXPORT SERCOM6_0_Handler [WEAK]
EXPORT SERCOM6_1_Handler [WEAK]
EXPORT SERCOM6_2_Handler [WEAK]
EXPORT SERCOM6_3_Handler [WEAK]
EXPORT SERCOM7_0_Handler [WEAK]
EXPORT SERCOM7_1_Handler [WEAK]
EXPORT SERCOM7_2_Handler [WEAK]
EXPORT SERCOM7_3_Handler [WEAK]
EXPORT CAN0_Handler [WEAK]
EXPORT CAN1_Handler [WEAK]
EXPORT USB_0_Handler [WEAK]
EXPORT USB_1_Handler [WEAK]
EXPORT USB_2_Handler [WEAK]
EXPORT USB_3_Handler [WEAK]
EXPORT GMAC_Handler [WEAK]
EXPORT TCC0_0_Handler [WEAK]
EXPORT TCC0_1_Handler [WEAK]
EXPORT TCC0_2_Handler [WEAK]
EXPORT TCC0_3_Handler [WEAK]
EXPORT TCC0_4_Handler [WEAK]
EXPORT TCC0_5_Handler [WEAK]
EXPORT TCC0_6_Handler [WEAK]
EXPORT TCC1_0_Handler [WEAK]
EXPORT TCC1_1_Handler [WEAK]
EXPORT TCC1_2_Handler [WEAK]
EXPORT TCC1_3_Handler [WEAK]
EXPORT TCC1_4_Handler [WEAK]
EXPORT TCC2_0_Handler [WEAK]
EXPORT TCC2_1_Handler [WEAK]
EXPORT TCC2_2_Handler [WEAK]
EXPORT TCC2_3_Handler [WEAK]
EXPORT TCC3_0_Handler [WEAK]
EXPORT TCC3_1_Handler [WEAK]
EXPORT TCC3_2_Handler [WEAK]
EXPORT TCC4_0_Handler [WEAK]
EXPORT TCC4_1_Handler [WEAK]
EXPORT TCC4_2_Handler [WEAK]
EXPORT TC0_Handler [WEAK]
EXPORT TC1_Handler [WEAK]
EXPORT TC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT PDEC_0_Handler [WEAK]
EXPORT PDEC_1_Handler [WEAK]
EXPORT PDEC_2_Handler [WEAK]
EXPORT ADC0_0_Handler [WEAK]
EXPORT ADC0_1_Handler [WEAK]
EXPORT ADC1_0_Handler [WEAK]
EXPORT ADC1_1_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_0_Handler [WEAK]
EXPORT DAC_1_Handler [WEAK]
EXPORT DAC_2_Handler [WEAK]
EXPORT DAC_3_Handler [WEAK]
EXPORT DAC_4_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT PCC_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
EXPORT ICM_Handler [WEAK]
EXPORT PUKCC_Handler [WEAK]
EXPORT QSPI_Handler [WEAK]
EXPORT SDHC0_Handler [WEAK]
EXPORT SDHC1_Handler [WEAK]
PM_Handler
MCLK_Handler
OSCCTRL_0_Handler
OSCCTRL_1_Handler
OSCCTRL_2_Handler
OSCCTRL_3_Handler
OSCCTRL_4_Handler
OSC32KCTRL_Handler
SUPC_0_Handler
SUPC_1_Handler
WDT_Handler
RTC_Handler
EIC_0_Handler
EIC_1_Handler
EIC_2_Handler
EIC_3_Handler
EIC_4_Handler
EIC_5_Handler
EIC_6_Handler
EIC_7_Handler
EIC_8_Handler
EIC_9_Handler
EIC_10_Handler
EIC_11_Handler
EIC_12_Handler
EIC_13_Handler
EIC_14_Handler
EIC_15_Handler
FREQM_Handler
NVMCTRL_0_Handler
NVMCTRL_1_Handler
DMAC_0_Handler
DMAC_1_Handler
DMAC_2_Handler
DMAC_3_Handler
DMAC_4_Handler
EVSYS_0_Handler
EVSYS_1_Handler
EVSYS_2_Handler
EVSYS_3_Handler
EVSYS_4_Handler
PAC_Handler
TAL_0_Handler
TAL_1_Handler
RAMECC_Handler
SERCOM0_0_Handler
SERCOM0_1_Handler
SERCOM0_2_Handler
SERCOM0_3_Handler
SERCOM1_0_Handler
SERCOM1_1_Handler
SERCOM1_2_Handler
SERCOM1_3_Handler
SERCOM2_0_Handler
SERCOM2_1_Handler
SERCOM2_2_Handler
SERCOM2_3_Handler
SERCOM3_0_Handler
SERCOM3_1_Handler
SERCOM3_2_Handler
SERCOM3_3_Handler
SERCOM4_0_Handler
SERCOM4_1_Handler
SERCOM4_2_Handler
SERCOM4_3_Handler
SERCOM5_0_Handler
SERCOM5_1_Handler
SERCOM5_2_Handler
SERCOM5_3_Handler
SERCOM6_0_Handler
SERCOM6_1_Handler
SERCOM6_2_Handler
SERCOM6_3_Handler
SERCOM7_0_Handler
SERCOM7_1_Handler
SERCOM7_2_Handler
SERCOM7_3_Handler
CAN0_Handler
CAN1_Handler
USB_0_Handler
USB_1_Handler
USB_2_Handler
USB_3_Handler
GMAC_Handler
TCC0_0_Handler
TCC0_1_Handler
TCC0_2_Handler
TCC0_3_Handler
TCC0_4_Handler
TCC0_5_Handler
TCC0_6_Handler
TCC1_0_Handler
TCC1_1_Handler
TCC1_2_Handler
TCC1_3_Handler
TCC1_4_Handler
TCC2_0_Handler
TCC2_1_Handler
TCC2_2_Handler
TCC2_3_Handler
TCC3_0_Handler
TCC3_1_Handler
TCC3_2_Handler
TCC4_0_Handler
TCC4_1_Handler
TCC4_2_Handler
TC0_Handler
TC1_Handler
TC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
PDEC_0_Handler
PDEC_1_Handler
PDEC_2_Handler
ADC0_0_Handler
ADC0_1_Handler
ADC1_0_Handler
ADC1_1_Handler
AC_Handler
DAC_0_Handler
DAC_1_Handler
DAC_2_Handler
DAC_3_Handler
DAC_4_Handler
I2S_Handler
PCC_Handler
AES_Handler
TRNG_Handler
ICM_Handler
PUKCC_Handler
QSPI_Handler
SDHC0_Handler
SDHC1_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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software/firmware/oracle_e54_edition/armcc/arm_addon/armcc/system_same54.c
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/**
* \file
*
* \brief Low-level initialization functions called upon chip startup.
*
* Copyright (c) 2016 Atmel Corporation,
* a wholly owned subsidiary of Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "same54.h"
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
#if __FPU_USED
/* Enable FPU */
SCB->CPACR |= (0xFu << 20);
__DSB();
__ISB();
#endif
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}

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software/firmware/oracle_e54_edition/armcc/arm_addon/armcc/system_same54.d
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armcc/arm_addon/armcc/system_same54.d \
armcc/arm_addon/armcc/system_same54.o: \
armcc/arm_addon/armcc/system_same54.c include/same54.h \
include/same54p20a.h /usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h CMSIS/Core/Include/core_cm4.h \
CMSIS/Core/Include/cmsis_version.h CMSIS/Core/Include/cmsis_compiler.h \
CMSIS/Core/Include/cmsis_gcc.h CMSIS/Core/Include/mpu_armv7.h \
include/system_same54.h include/component/ac.h include/component/adc.h \
include/component/aes.h include/component/can.h include/component/ccl.h \
include/component/cmcc.h include/component/dac.h \
include/component/dmac.h include/component/dsu.h include/component/eic.h \
include/component/evsys.h include/component/freqm.h \
include/component/gclk.h include/component/gmac.h \
include/component/hmatrixb.h include/component/icm.h \
include/component/i2s.h include/component/mclk.h \
include/component/nvmctrl.h include/component/oscctrl.h \
include/component/osc32kctrl.h include/component/pac.h \
include/component/pcc.h include/component/pdec.h include/component/pm.h \
include/component/port.h include/component/qspi.h \
include/component/ramecc.h include/component/rstc.h \
include/component/rtc.h include/component/sdhc.h \
include/component/sercom.h include/component/supc.h \
include/component/tc.h include/component/tcc.h include/component/trng.h \
include/component/usb.h include/component/wdt.h include/instance/ac.h \
include/instance/adc0.h include/instance/adc1.h include/instance/aes.h \
include/instance/can0.h include/instance/can1.h include/instance/ccl.h \
include/instance/cmcc.h include/instance/dac.h include/instance/dmac.h \
include/instance/dsu.h include/instance/eic.h include/instance/evsys.h \
include/instance/freqm.h include/instance/gclk.h include/instance/gmac.h \
include/instance/hmatrix.h include/instance/icm.h include/instance/i2s.h \
include/instance/mclk.h include/instance/nvmctrl.h \
include/instance/oscctrl.h include/instance/osc32kctrl.h \
include/instance/pac.h include/instance/pcc.h include/instance/pdec.h \
include/instance/pm.h include/instance/port.h include/instance/pukcc.h \
include/instance/qspi.h include/instance/ramecc.h \
include/instance/rstc.h include/instance/rtc.h include/instance/sdhc0.h \
include/instance/sdhc1.h include/instance/sercom0.h \
include/instance/sercom1.h include/instance/sercom2.h \
include/instance/sercom3.h include/instance/sercom4.h \
include/instance/sercom5.h include/instance/sercom6.h \
include/instance/sercom7.h include/instance/supc.h \
include/instance/tc0.h include/instance/tc1.h include/instance/tc2.h \
include/instance/tc3.h include/instance/tc4.h include/instance/tc5.h \
include/instance/tc6.h include/instance/tc7.h include/instance/tcc0.h \
include/instance/tcc1.h include/instance/tcc2.h include/instance/tcc3.h \
include/instance/tcc4.h include/instance/trng.h include/instance/usb.h \
include/instance/wdt.h include/pio/same54p20a.h
include/same54.h:
include/same54p20a.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
CMSIS/Core/Include/core_cm4.h:
CMSIS/Core/Include/cmsis_version.h:
CMSIS/Core/Include/cmsis_compiler.h:
CMSIS/Core/Include/cmsis_gcc.h:
CMSIS/Core/Include/mpu_armv7.h:
include/system_same54.h:
include/component/ac.h:
include/component/adc.h:
include/component/aes.h:
include/component/can.h:
include/component/ccl.h:
include/component/cmcc.h:
include/component/dac.h:
include/component/dmac.h:
include/component/dsu.h:
include/component/eic.h:
include/component/evsys.h:
include/component/freqm.h:
include/component/gclk.h:
include/component/gmac.h:
include/component/hmatrixb.h:
include/component/icm.h:
include/component/i2s.h:
include/component/mclk.h:
include/component/nvmctrl.h:
include/component/oscctrl.h:
include/component/osc32kctrl.h:
include/component/pac.h:
include/component/pcc.h:
include/component/pdec.h:
include/component/pm.h:
include/component/port.h:
include/component/qspi.h:
include/component/ramecc.h:
include/component/rstc.h:
include/component/rtc.h:
include/component/sdhc.h:
include/component/sercom.h:
include/component/supc.h:
include/component/tc.h:
include/component/tcc.h:
include/component/trng.h:
include/component/usb.h:
include/component/wdt.h:
include/instance/ac.h:
include/instance/adc0.h:
include/instance/adc1.h:
include/instance/aes.h:
include/instance/can0.h:
include/instance/can1.h:
include/instance/ccl.h:
include/instance/cmcc.h:
include/instance/dac.h:
include/instance/dmac.h:
include/instance/dsu.h:
include/instance/eic.h:
include/instance/evsys.h:
include/instance/freqm.h:
include/instance/gclk.h:
include/instance/gmac.h:
include/instance/hmatrix.h:
include/instance/icm.h:
include/instance/i2s.h:
include/instance/mclk.h:
include/instance/nvmctrl.h:
include/instance/oscctrl.h:
include/instance/osc32kctrl.h:
include/instance/pac.h:
include/instance/pcc.h:
include/instance/pdec.h:
include/instance/pm.h:
include/instance/port.h:
include/instance/pukcc.h:
include/instance/qspi.h:
include/instance/ramecc.h:
include/instance/rstc.h:
include/instance/rtc.h:
include/instance/sdhc0.h:
include/instance/sdhc1.h:
include/instance/sercom0.h:
include/instance/sercom1.h:
include/instance/sercom2.h:
include/instance/sercom3.h:
include/instance/sercom4.h:
include/instance/sercom5.h:
include/instance/sercom6.h:
include/instance/sercom7.h:
include/instance/supc.h:
include/instance/tc0.h:
include/instance/tc1.h:
include/instance/tc2.h:
include/instance/tc3.h:
include/instance/tc4.h:
include/instance/tc5.h:
include/instance/tc6.h:
include/instance/tc7.h:
include/instance/tcc0.h:
include/instance/tcc1.h:
include/instance/tcc2.h:
include/instance/tcc3.h:
include/instance/tcc4.h:
include/instance/trng.h:
include/instance/usb.h:
include/instance/wdt.h:
include/pio/same54p20a.h:

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software/firmware/oracle_e54_edition/atmel_start.c
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#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
}

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software/firmware/oracle_e54_edition/atmel_start.d
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atmel_start.d atmel_start.o: atmel_start.c atmel_start.h driver_init.h \
atmel_start_pins.h hal/include/hal_gpio.h hal/include/hpl_gpio.h \
hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
hal/utils/include/parts.h include/same54.h include/same54p20a.h \
CMSIS/Core/Include/core_cm4.h CMSIS/Core/Include/cmsis_version.h \
CMSIS/Core/Include/cmsis_compiler.h CMSIS/Core/Include/cmsis_gcc.h \
CMSIS/Core/Include/mpu_armv7.h include/system_same54.h \
include/component/ac.h include/component/adc.h include/component/aes.h \
include/component/can.h include/component/ccl.h include/component/cmcc.h \
include/component/dac.h include/component/dmac.h include/component/dsu.h \
include/component/eic.h include/component/evsys.h \
include/component/freqm.h include/component/gclk.h \
include/component/gmac.h include/component/hmatrixb.h \
include/component/icm.h include/component/i2s.h include/component/mclk.h \
include/component/nvmctrl.h include/component/oscctrl.h \
include/component/osc32kctrl.h include/component/pac.h \
include/component/pcc.h include/component/pdec.h include/component/pm.h \
include/component/port.h include/component/qspi.h \
include/component/ramecc.h include/component/rstc.h \
include/component/rtc.h include/component/sdhc.h \
include/component/sercom.h include/component/supc.h \
include/component/tc.h include/component/tcc.h include/component/trng.h \
include/component/usb.h include/component/wdt.h include/instance/ac.h \
include/instance/adc0.h include/instance/adc1.h include/instance/aes.h \
include/instance/can0.h include/instance/can1.h include/instance/ccl.h \
include/instance/cmcc.h include/instance/dac.h include/instance/dmac.h \
include/instance/dsu.h include/instance/eic.h include/instance/evsys.h \
include/instance/freqm.h include/instance/gclk.h include/instance/gmac.h \
include/instance/hmatrix.h include/instance/icm.h include/instance/i2s.h \
include/instance/mclk.h include/instance/nvmctrl.h \
include/instance/oscctrl.h include/instance/osc32kctrl.h \
include/instance/pac.h include/instance/pcc.h include/instance/pdec.h \
include/instance/pm.h include/instance/port.h include/instance/pukcc.h \
include/instance/qspi.h include/instance/ramecc.h \
include/instance/rstc.h include/instance/rtc.h include/instance/sdhc0.h \
include/instance/sdhc1.h include/instance/sercom0.h \
include/instance/sercom1.h include/instance/sercom2.h \
include/instance/sercom3.h include/instance/sercom4.h \
include/instance/sercom5.h include/instance/sercom6.h \
include/instance/sercom7.h include/instance/supc.h \
include/instance/tc0.h include/instance/tc1.h include/instance/tc2.h \
include/instance/tc3.h include/instance/tc4.h include/instance/tc5.h \
include/instance/tc6.h include/instance/tc7.h include/instance/tcc0.h \
include/instance/tcc1.h include/instance/tcc2.h include/instance/tcc3.h \
include/instance/tcc4.h include/instance/trng.h include/instance/usb.h \
include/instance/wdt.h include/pio/same54p20a.h hri/hri_e54.h \
include/sam.h hri/hri_ac_e54.h hal/include/hal_atomic.h \
hri/hri_adc_e54.h hri/hri_aes_e54.h hri/hri_can_e54.h hri/hri_ccl_e54.h \
hri/hri_cmcc_e54.h hri/hri_dac_e54.h hri/hri_dmac_e54.h \
hri/hri_dsu_e54.h hri/hri_eic_e54.h hri/hri_evsys_e54.h \
hri/hri_freqm_e54.h hri/hri_gclk_e54.h hri/hri_gmac_e54.h \
hri/hri_hmatrixb_e54.h hri/hri_i2s_e54.h hri/hri_icm_e54.h \
hri/hri_mclk_e54.h hri/hri_nvmctrl_e54.h hri/hri_osc32kctrl_e54.h \
hri/hri_oscctrl_e54.h hri/hri_pac_e54.h hri/hri_pcc_e54.h \
hri/hri_pdec_e54.h hri/hri_pm_e54.h hri/hri_port_e54.h \
hri/hri_qspi_e54.h hri/hri_ramecc_e54.h hri/hri_rstc_e54.h \
hri/hri_rtc_e54.h hri/hri_sdhc_e54.h hri/hri_sercom_e54.h \
hri/hri_supc_e54.h hri/hri_tc_e54.h hri/hri_tcc_e54.h hri/hri_trng_e54.h \
hri/hri_usb_e54.h hri/hri_wdt_e54.h hal/utils/include/err_codes.h \
hpl/port/hpl_gpio_base.h hal/utils/include/utils_assert.h \
config/hpl_port_config.h hal/include/hal_delay.h hal/include/hpl_irq.h \
hal/include/hpl_reset.h hal/include/hpl_sleep.h hal/include/hal_init.h \
hal/include/hpl_init.h hal/include/hal_io.h hal/include/hal_sleep.h \
hal/include/hal_ext_irq.h hal/include/hpl_ext_irq.h \
hal/include/hal_usart_async.h hal/include/hal_io.h \
hal/include/hpl_usart_async.h hal/include/hpl_usart.h \
hal/include/hpl_irq.h hal/utils/include/utils_ringbuffer.h \
hal/utils/include/compiler.h hal/utils/include/utils_assert.h \
hal/include/hal_i2c_m_sync.h hal/include/hpl_i2c_m_sync.h \
hal/include/hal_timer.h hal/utils/include/utils_list.h \
hal/include/hpl_timer.h hpl/tc/hpl_tc_base.h hal/include/hpl_pwm.h
atmel_start.h:
driver_init.h:
atmel_start_pins.h:
hal/include/hal_gpio.h:
hal/include/hpl_gpio.h:
hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
hal/utils/include/parts.h:
include/same54.h:
include/same54p20a.h:
CMSIS/Core/Include/core_cm4.h:
CMSIS/Core/Include/cmsis_version.h:
CMSIS/Core/Include/cmsis_compiler.h:
CMSIS/Core/Include/cmsis_gcc.h:
CMSIS/Core/Include/mpu_armv7.h:
include/system_same54.h:
include/component/ac.h:
include/component/adc.h:
include/component/aes.h:
include/component/can.h:
include/component/ccl.h:
include/component/cmcc.h:
include/component/dac.h:
include/component/dmac.h:
include/component/dsu.h:
include/component/eic.h:
include/component/evsys.h:
include/component/freqm.h:
include/component/gclk.h:
include/component/gmac.h:
include/component/hmatrixb.h:
include/component/icm.h:
include/component/i2s.h:
include/component/mclk.h:
include/component/nvmctrl.h:
include/component/oscctrl.h:
include/component/osc32kctrl.h:
include/component/pac.h:
include/component/pcc.h:
include/component/pdec.h:
include/component/pm.h:
include/component/port.h:
include/component/qspi.h:
include/component/ramecc.h:
include/component/rstc.h:
include/component/rtc.h:
include/component/sdhc.h:
include/component/sercom.h:
include/component/supc.h:
include/component/tc.h:
include/component/tcc.h:
include/component/trng.h:
include/component/usb.h:
include/component/wdt.h:
include/instance/ac.h:
include/instance/adc0.h:
include/instance/adc1.h:
include/instance/aes.h:
include/instance/can0.h:
include/instance/can1.h:
include/instance/ccl.h:
include/instance/cmcc.h:
include/instance/dac.h:
include/instance/dmac.h:
include/instance/dsu.h:
include/instance/eic.h:
include/instance/evsys.h:
include/instance/freqm.h:
include/instance/gclk.h:
include/instance/gmac.h:
include/instance/hmatrix.h:
include/instance/icm.h:
include/instance/i2s.h:
include/instance/mclk.h:
include/instance/nvmctrl.h:
include/instance/oscctrl.h:
include/instance/osc32kctrl.h:
include/instance/pac.h:
include/instance/pcc.h:
include/instance/pdec.h:
include/instance/pm.h:
include/instance/port.h:
include/instance/pukcc.h:
include/instance/qspi.h:
include/instance/ramecc.h:
include/instance/rstc.h:
include/instance/rtc.h:
include/instance/sdhc0.h:
include/instance/sdhc1.h:
include/instance/sercom0.h:
include/instance/sercom1.h:
include/instance/sercom2.h:
include/instance/sercom3.h:
include/instance/sercom4.h:
include/instance/sercom5.h:
include/instance/sercom6.h:
include/instance/sercom7.h:
include/instance/supc.h:
include/instance/tc0.h:
include/instance/tc1.h:
include/instance/tc2.h:
include/instance/tc3.h:
include/instance/tc4.h:
include/instance/tc5.h:
include/instance/tc6.h:
include/instance/tc7.h:
include/instance/tcc0.h:
include/instance/tcc1.h:
include/instance/tcc2.h:
include/instance/tcc3.h:
include/instance/tcc4.h:
include/instance/trng.h:
include/instance/usb.h:
include/instance/wdt.h:
include/pio/same54p20a.h:
hri/hri_e54.h:
include/sam.h:
hri/hri_ac_e54.h:
hal/include/hal_atomic.h:
hri/hri_adc_e54.h:
hri/hri_aes_e54.h:
hri/hri_can_e54.h:
hri/hri_ccl_e54.h:
hri/hri_cmcc_e54.h:
hri/hri_dac_e54.h:
hri/hri_dmac_e54.h:
hri/hri_dsu_e54.h:
hri/hri_eic_e54.h:
hri/hri_evsys_e54.h:
hri/hri_freqm_e54.h:
hri/hri_gclk_e54.h:
hri/hri_gmac_e54.h:
hri/hri_hmatrixb_e54.h:
hri/hri_i2s_e54.h:
hri/hri_icm_e54.h:
hri/hri_mclk_e54.h:
hri/hri_nvmctrl_e54.h:
hri/hri_osc32kctrl_e54.h:
hri/hri_oscctrl_e54.h:
hri/hri_pac_e54.h:
hri/hri_pcc_e54.h:
hri/hri_pdec_e54.h:
hri/hri_pm_e54.h:
hri/hri_port_e54.h:
hri/hri_qspi_e54.h:
hri/hri_ramecc_e54.h:
hri/hri_rstc_e54.h:
hri/hri_rtc_e54.h:
hri/hri_sdhc_e54.h:
hri/hri_sercom_e54.h:
hri/hri_supc_e54.h:
hri/hri_tc_e54.h:
hri/hri_tcc_e54.h:
hri/hri_trng_e54.h:
hri/hri_usb_e54.h:
hri/hri_wdt_e54.h:
hal/utils/include/err_codes.h:
hpl/port/hpl_gpio_base.h:
hal/utils/include/utils_assert.h:
config/hpl_port_config.h:
hal/include/hal_delay.h:
hal/include/hpl_irq.h:
hal/include/hpl_reset.h:
hal/include/hpl_sleep.h:
hal/include/hal_init.h:
hal/include/hpl_init.h:
hal/include/hal_io.h:
hal/include/hal_sleep.h:
hal/include/hal_ext_irq.h:
hal/include/hpl_ext_irq.h:
hal/include/hal_usart_async.h:
hal/include/hal_io.h:
hal/include/hpl_usart_async.h:
hal/include/hpl_usart.h:
hal/include/hpl_irq.h:
hal/utils/include/utils_ringbuffer.h:
hal/utils/include/compiler.h:
hal/utils/include/utils_assert.h:
hal/include/hal_i2c_m_sync.h:
hal/include/hpl_i2c_m_sync.h:
hal/include/hal_timer.h:
hal/utils/include/utils_list.h:
hal/include/hpl_timer.h:
hpl/tc/hpl_tc_base.h:
hal/include/hpl_pwm.h:

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software/firmware/oracle_e54_edition/atmel_start.h
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#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif

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software/firmware/oracle_e54_edition/atmel_start_config.atstart
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software/firmware/oracle_e54_edition/atmel_start_pins.h
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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#include <hal_gpio.h>
// SAME54 has 14 pin functions
#define GPIO_PIN_FUNCTION_A 0
#define GPIO_PIN_FUNCTION_B 1
#define GPIO_PIN_FUNCTION_C 2
#define GPIO_PIN_FUNCTION_D 3
#define GPIO_PIN_FUNCTION_E 4
#define GPIO_PIN_FUNCTION_F 5
#define GPIO_PIN_FUNCTION_G 6
#define GPIO_PIN_FUNCTION_H 7
#define GPIO_PIN_FUNCTION_I 8
#define GPIO_PIN_FUNCTION_J 9
#define GPIO_PIN_FUNCTION_K 10
#define GPIO_PIN_FUNCTION_L 11
#define GPIO_PIN_FUNCTION_M 12
#define GPIO_PIN_FUNCTION_N 13
#define PA22 GPIO(GPIO_PORTA, 22)
#define PA23 GPIO(GPIO_PORTA, 23)
#define PB24 GPIO(GPIO_PORTB, 24)
#define PB25 GPIO(GPIO_PORTB, 25)
#endif // ATMEL_START_PINS_H_INCLUDED

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software/firmware/oracle_e54_edition/config/hpl_cmcc_config.h
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/* Auto-generated config file hpl_cmcc_config.h */
#ifndef HPL_CMCC_CONFIG_H
#define HPL_CMCC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Configuration
// <q> Cache enable
//<i> Defines the cache should be enabled or not.
// <id> cmcc_enable
#ifndef CONF_CMCC_ENABLE
#define CONF_CMCC_ENABLE 0x0
#endif
// <o> Cache Size
//<i> Defines the cache memory size to be configured.
// <0x0=>1 KB
// <0x1=>2 KB
// <0x2=>4 KB
// <id> cache_size
#ifndef CONF_CMCC_CACHE_SIZE
#define CONF_CMCC_CACHE_SIZE 0x2
#endif
// <e> Advanced Configuration
// <id> cmcc_advanced_configuration
// <q> Data cache disable
//<i> Defines the data cache should be disabled or not.
// <id> cmcc_data_cache_disable
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
#endif
// <q> Instruction cache disable
//<i> Defines the Instruction cache should be disabled or not.
// <id> cmcc_inst_cache_disable
#ifndef CONF_CMCC_INST_CACHE_DISABLE
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
#endif
// <q> Clock Gating disable
//<i> Defines the clock gating should be disabled or not.
// <id> cmcc_clock_gating_disable
#ifndef CONF_CMCC_CLK_GATING_DISABLE
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_CMCC_CONFIG_H

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software/firmware/oracle_e54_edition/config/hpl_dmac_config.h
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software/firmware/oracle_e54_edition/config/hpl_eic_config.h
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/* Auto-generated config file hpl_eic_config.h */
#ifndef HPL_EIC_CONFIG_H
#define HPL_EIC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Settings
// <o> Clock Selection
// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
// <i> either by CLK_ULP32K when power consumption is the priority.
// <0x0=> Clocked by GCLK
// <0x1=> Clocked by ULPOSC32K
// <id> eic_arch_cksel
#ifndef CONF_EIC_CKSEL
#define CONF_EIC_CKSEL 0
#endif
// <o> Pin Sampler frequency selection
// <i> Indicates the sampling rate of the EXTINT pin.
// <0x0=> The sampling rate is EIC clock
// <0x1=> The sampling rate is the prescaled clock
// <id> eic_arch_tickon
#ifndef CONF_EIC_TICKON
#define CONF_EIC_TICKON 0
#endif
// </h>
// <e> Non-Maskable Interrupt Control
// <id> eic_arch_nmi_ctrl
#ifndef CONF_EIC_ENABLE_NMI_CTRL
#define CONF_EIC_ENABLE_NMI_CTRL 0
#endif
// <q> Non-Maskable Interrupt Filter Enable
// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
// <id> eic_arch_nmifilten
#ifndef CONF_EIC_NMIFILTEN
#define CONF_EIC_NMIFILTEN 0
#endif
// <y> Non-Maskable Interrupt Sense
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines non-maskable interrupt sense
// <id> eic_arch_nmisense
#ifndef CONF_EIC_NMISENSE
#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> Asynchronous Edge Detection Mode
// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
// <id> eic_arch_nmiasynch
#ifndef CONF_EIC_NMIASYNCH
#define CONF_EIC_NMIASYNCH 0
#endif
// </e>
// <e> Interrupt 0 Settings
// <id> eic_arch_enable_irq_setting0
#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
#define CONF_EIC_ENABLE_IRQ_SETTING0 0
#endif
// <q> External Interrupt 0 Filter Enable
// <i> Indicates whether the external interrupt 0 filter is enabled or not
// <id> eic_arch_filten0
#ifndef CONF_EIC_FILTEN0
#define CONF_EIC_FILTEN0 0
#endif
// <q> External Interrupt 0 Debounce Enable
// <i> Indicates whether the external interrupt 0 debounce is enabled or not
// <id> eic_arch_debounce_enable0
#ifndef CONF_EIC_DEBOUNCE_ENABLE0
#define CONF_EIC_DEBOUNCE_ENABLE0 0
#endif
// <q> External Interrupt 0 Event Output Enable
// <i> Indicates whether the external interrupt 0 event output is enabled or not
// <id> eic_arch_extinteo0
#ifndef CONF_EIC_EXTINTEO0
#define CONF_EIC_EXTINTEO0 0
#endif
// <y> Input 0 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense0
#ifndef CONF_EIC_SENSE0
#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 0 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch0
#ifndef CONF_EIC_ASYNCH0
#define CONF_EIC_ASYNCH0 0
#endif
// </e>
// <e> Interrupt 1 Settings
// <id> eic_arch_enable_irq_setting1
#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
#define CONF_EIC_ENABLE_IRQ_SETTING1 0
#endif
// <q> External Interrupt 1 Filter Enable
// <i> Indicates whether the external interrupt 1 filter is enabled or not
// <id> eic_arch_filten1
#ifndef CONF_EIC_FILTEN1
#define CONF_EIC_FILTEN1 0
#endif
// <q> External Interrupt 1 Debounce Enable
// <i> Indicates whether the external interrupt 1 debounce is enabled or not
// <id> eic_arch_debounce_enable1
#ifndef CONF_EIC_DEBOUNCE_ENABLE1
#define CONF_EIC_DEBOUNCE_ENABLE1 0
#endif
// <q> External Interrupt 1 Event Output Enable
// <i> Indicates whether the external interrupt 1 event output is enabled or not
// <id> eic_arch_extinteo1
#ifndef CONF_EIC_EXTINTEO1
#define CONF_EIC_EXTINTEO1 0
#endif
// <y> Input 1 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense1
#ifndef CONF_EIC_SENSE1
#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 1 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch1
#ifndef CONF_EIC_ASYNCH1
#define CONF_EIC_ASYNCH1 0
#endif
// </e>
// <e> Interrupt 2 Settings
// <id> eic_arch_enable_irq_setting2
#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
#define CONF_EIC_ENABLE_IRQ_SETTING2 0
#endif
// <q> External Interrupt 2 Filter Enable
// <i> Indicates whether the external interrupt 2 filter is enabled or not
// <id> eic_arch_filten2
#ifndef CONF_EIC_FILTEN2
#define CONF_EIC_FILTEN2 0
#endif
// <q> External Interrupt 2 Debounce Enable
// <i> Indicates whether the external interrupt 2 debounce is enabled or not
// <id> eic_arch_debounce_enable2
#ifndef CONF_EIC_DEBOUNCE_ENABLE2
#define CONF_EIC_DEBOUNCE_ENABLE2 0
#endif
// <q> External Interrupt 2 Event Output Enable
// <i> Indicates whether the external interrupt 2 event output is enabled or not
// <id> eic_arch_extinteo2
#ifndef CONF_EIC_EXTINTEO2
#define CONF_EIC_EXTINTEO2 0
#endif
// <y> Input 2 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense2
#ifndef CONF_EIC_SENSE2
#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 2 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch2
#ifndef CONF_EIC_ASYNCH2
#define CONF_EIC_ASYNCH2 0
#endif
// </e>
// <e> Interrupt 3 Settings
// <id> eic_arch_enable_irq_setting3
#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
#define CONF_EIC_ENABLE_IRQ_SETTING3 0
#endif
// <q> External Interrupt 3 Filter Enable
// <i> Indicates whether the external interrupt 3 filter is enabled or not
// <id> eic_arch_filten3
#ifndef CONF_EIC_FILTEN3
#define CONF_EIC_FILTEN3 0
#endif
// <q> External Interrupt 3 Debounce Enable
// <i> Indicates whether the external interrupt 3 debounce is enabled or not
// <id> eic_arch_debounce_enable3
#ifndef CONF_EIC_DEBOUNCE_ENABLE3
#define CONF_EIC_DEBOUNCE_ENABLE3 0
#endif
// <q> External Interrupt 3 Event Output Enable
// <i> Indicates whether the external interrupt 3 event output is enabled or not
// <id> eic_arch_extinteo3
#ifndef CONF_EIC_EXTINTEO3
#define CONF_EIC_EXTINTEO3 0
#endif
// <y> Input 3 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense3
#ifndef CONF_EIC_SENSE3
#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 3 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch3
#ifndef CONF_EIC_ASYNCH3
#define CONF_EIC_ASYNCH3 0
#endif
// </e>
// <e> Interrupt 4 Settings
// <id> eic_arch_enable_irq_setting4
#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
#define CONF_EIC_ENABLE_IRQ_SETTING4 0
#endif
// <q> External Interrupt 4 Filter Enable
// <i> Indicates whether the external interrupt 4 filter is enabled or not
// <id> eic_arch_filten4
#ifndef CONF_EIC_FILTEN4
#define CONF_EIC_FILTEN4 0
#endif
// <q> External Interrupt 4 Debounce Enable
// <i> Indicates whether the external interrupt 4 debounce is enabled or not
// <id> eic_arch_debounce_enable4
#ifndef CONF_EIC_DEBOUNCE_ENABLE4
#define CONF_EIC_DEBOUNCE_ENABLE4 0
#endif
// <q> External Interrupt 4 Event Output Enable
// <i> Indicates whether the external interrupt 4 event output is enabled or not
// <id> eic_arch_extinteo4
#ifndef CONF_EIC_EXTINTEO4
#define CONF_EIC_EXTINTEO4 0
#endif
// <y> Input 4 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense4
#ifndef CONF_EIC_SENSE4
#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 4 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch4
#ifndef CONF_EIC_ASYNCH4
#define CONF_EIC_ASYNCH4 0
#endif
// </e>
// <e> Interrupt 5 Settings
// <id> eic_arch_enable_irq_setting5
#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
#define CONF_EIC_ENABLE_IRQ_SETTING5 0
#endif
// <q> External Interrupt 5 Filter Enable
// <i> Indicates whether the external interrupt 5 filter is enabled or not
// <id> eic_arch_filten5
#ifndef CONF_EIC_FILTEN5
#define CONF_EIC_FILTEN5 0
#endif
// <q> External Interrupt 5 Debounce Enable
// <i> Indicates whether the external interrupt 5 debounce is enabled or not
// <id> eic_arch_debounce_enable5
#ifndef CONF_EIC_DEBOUNCE_ENABLE5
#define CONF_EIC_DEBOUNCE_ENABLE5 0
#endif
// <q> External Interrupt 5 Event Output Enable
// <i> Indicates whether the external interrupt 5 event output is enabled or not
// <id> eic_arch_extinteo5
#ifndef CONF_EIC_EXTINTEO5
#define CONF_EIC_EXTINTEO5 0
#endif
// <y> Input 5 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense5
#ifndef CONF_EIC_SENSE5
#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 5 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch5
#ifndef CONF_EIC_ASYNCH5
#define CONF_EIC_ASYNCH5 0
#endif
// </e>
// <e> Interrupt 6 Settings
// <id> eic_arch_enable_irq_setting6
#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
#define CONF_EIC_ENABLE_IRQ_SETTING6 0
#endif
// <q> External Interrupt 6 Filter Enable
// <i> Indicates whether the external interrupt 6 filter is enabled or not
// <id> eic_arch_filten6
#ifndef CONF_EIC_FILTEN6
#define CONF_EIC_FILTEN6 0
#endif
// <q> External Interrupt 6 Debounce Enable
// <i> Indicates whether the external interrupt 6 debounce is enabled or not
// <id> eic_arch_debounce_enable6
#ifndef CONF_EIC_DEBOUNCE_ENABLE6
#define CONF_EIC_DEBOUNCE_ENABLE6 0
#endif
// <q> External Interrupt 6 Event Output Enable
// <i> Indicates whether the external interrupt 6 event output is enabled or not
// <id> eic_arch_extinteo6
#ifndef CONF_EIC_EXTINTEO6
#define CONF_EIC_EXTINTEO6 0
#endif
// <y> Input 6 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense6
#ifndef CONF_EIC_SENSE6
#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 6 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch6
#ifndef CONF_EIC_ASYNCH6
#define CONF_EIC_ASYNCH6 0
#endif
// </e>
// <e> Interrupt 7 Settings
// <id> eic_arch_enable_irq_setting7
#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
#define CONF_EIC_ENABLE_IRQ_SETTING7 0
#endif
// <q> External Interrupt 7 Filter Enable
// <i> Indicates whether the external interrupt 7 filter is enabled or not
// <id> eic_arch_filten7
#ifndef CONF_EIC_FILTEN7
#define CONF_EIC_FILTEN7 0
#endif
// <q> External Interrupt 7 Debounce Enable
// <i> Indicates whether the external interrupt 7 debounce is enabled or not
// <id> eic_arch_debounce_enable7
#ifndef CONF_EIC_DEBOUNCE_ENABLE7
#define CONF_EIC_DEBOUNCE_ENABLE7 0
#endif
// <q> External Interrupt 7 Event Output Enable
// <i> Indicates whether the external interrupt 7 event output is enabled or not
// <id> eic_arch_extinteo7
#ifndef CONF_EIC_EXTINTEO7
#define CONF_EIC_EXTINTEO7 0
#endif
// <y> Input 7 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense7
#ifndef CONF_EIC_SENSE7
#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 7 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch7
#ifndef CONF_EIC_ASYNCH7
#define CONF_EIC_ASYNCH7 0
#endif
// </e>
// <e> Interrupt 8 Settings
// <id> eic_arch_enable_irq_setting8
#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
#define CONF_EIC_ENABLE_IRQ_SETTING8 0
#endif
// <q> External Interrupt 8 Filter Enable
// <i> Indicates whether the external interrupt 8 filter is enabled or not
// <id> eic_arch_filten8
#ifndef CONF_EIC_FILTEN8
#define CONF_EIC_FILTEN8 0
#endif
// <q> External Interrupt 8 Debounce Enable
// <i> Indicates whether the external interrupt 8 debounce is enabled or not
// <id> eic_arch_debounce_enable8
#ifndef CONF_EIC_DEBOUNCE_ENABLE8
#define CONF_EIC_DEBOUNCE_ENABLE8 0
#endif
// <q> External Interrupt 8 Event Output Enable
// <i> Indicates whether the external interrupt 8 event output is enabled or not
// <id> eic_arch_extinteo8
#ifndef CONF_EIC_EXTINTEO8
#define CONF_EIC_EXTINTEO8 0
#endif
// <y> Input 8 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense8
#ifndef CONF_EIC_SENSE8
#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 8 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch8
#ifndef CONF_EIC_ASYNCH8
#define CONF_EIC_ASYNCH8 0
#endif
// </e>
// <e> Interrupt 9 Settings
// <id> eic_arch_enable_irq_setting9
#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
#define CONF_EIC_ENABLE_IRQ_SETTING9 0
#endif
// <q> External Interrupt 9 Filter Enable
// <i> Indicates whether the external interrupt 9 filter is enabled or not
// <id> eic_arch_filten9
#ifndef CONF_EIC_FILTEN9
#define CONF_EIC_FILTEN9 0
#endif
// <q> External Interrupt 9 Debounce Enable
// <i> Indicates whether the external interrupt 9 debounce is enabled or not
// <id> eic_arch_debounce_enable9
#ifndef CONF_EIC_DEBOUNCE_ENABLE9
#define CONF_EIC_DEBOUNCE_ENABLE9 0
#endif
// <q> External Interrupt 9 Event Output Enable
// <i> Indicates whether the external interrupt 9 event output is enabled or not
// <id> eic_arch_extinteo9
#ifndef CONF_EIC_EXTINTEO9
#define CONF_EIC_EXTINTEO9 0
#endif
// <y> Input 9 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense9
#ifndef CONF_EIC_SENSE9
#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 9 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch9
#ifndef CONF_EIC_ASYNCH9
#define CONF_EIC_ASYNCH9 0
#endif
// </e>
// <e> Interrupt 10 Settings
// <id> eic_arch_enable_irq_setting10
#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
#define CONF_EIC_ENABLE_IRQ_SETTING10 0
#endif
// <q> External Interrupt 10 Filter Enable
// <i> Indicates whether the external interrupt 10 filter is enabled or not
// <id> eic_arch_filten10
#ifndef CONF_EIC_FILTEN10
#define CONF_EIC_FILTEN10 0
#endif
// <q> External Interrupt 10 Debounce Enable
// <i> Indicates whether the external interrupt 10 debounce is enabled or not
// <id> eic_arch_debounce_enable10
#ifndef CONF_EIC_DEBOUNCE_ENABLE10
#define CONF_EIC_DEBOUNCE_ENABLE10 0
#endif
// <q> External Interrupt 10 Event Output Enable
// <i> Indicates whether the external interrupt 10 event output is enabled or not
// <id> eic_arch_extinteo10
#ifndef CONF_EIC_EXTINTEO10
#define CONF_EIC_EXTINTEO10 0
#endif
// <y> Input 10 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense10
#ifndef CONF_EIC_SENSE10
#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 10 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch10
#ifndef CONF_EIC_ASYNCH10
#define CONF_EIC_ASYNCH10 0
#endif
// </e>
// <e> Interrupt 11 Settings
// <id> eic_arch_enable_irq_setting11
#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
#define CONF_EIC_ENABLE_IRQ_SETTING11 0
#endif
// <q> External Interrupt 11 Filter Enable
// <i> Indicates whether the external interrupt 11 filter is enabled or not
// <id> eic_arch_filten11
#ifndef CONF_EIC_FILTEN11
#define CONF_EIC_FILTEN11 0
#endif
// <q> External Interrupt 11 Debounce Enable
// <i> Indicates whether the external interrupt 11 debounce is enabled or not
// <id> eic_arch_debounce_enable11
#ifndef CONF_EIC_DEBOUNCE_ENABLE11
#define CONF_EIC_DEBOUNCE_ENABLE11 0
#endif
// <q> External Interrupt 11 Event Output Enable
// <i> Indicates whether the external interrupt 11 event output is enabled or not
// <id> eic_arch_extinteo11
#ifndef CONF_EIC_EXTINTEO11
#define CONF_EIC_EXTINTEO11 0
#endif
// <y> Input 11 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense11
#ifndef CONF_EIC_SENSE11
#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 11 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch11
#ifndef CONF_EIC_ASYNCH11
#define CONF_EIC_ASYNCH11 0
#endif
// </e>
// <e> Interrupt 12 Settings
// <id> eic_arch_enable_irq_setting12
#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
#define CONF_EIC_ENABLE_IRQ_SETTING12 0
#endif
// <q> External Interrupt 12 Filter Enable
// <i> Indicates whether the external interrupt 12 filter is enabled or not
// <id> eic_arch_filten12
#ifndef CONF_EIC_FILTEN12
#define CONF_EIC_FILTEN12 0
#endif
// <q> External Interrupt 12 Debounce Enable
// <i> Indicates whether the external interrupt 12 debounce is enabled or not
// <id> eic_arch_debounce_enable12
#ifndef CONF_EIC_DEBOUNCE_ENABLE12
#define CONF_EIC_DEBOUNCE_ENABLE12 0
#endif
// <q> External Interrupt 12 Event Output Enable
// <i> Indicates whether the external interrupt 12 event output is enabled or not
// <id> eic_arch_extinteo12
#ifndef CONF_EIC_EXTINTEO12
#define CONF_EIC_EXTINTEO12 0
#endif
// <y> Input 12 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense12
#ifndef CONF_EIC_SENSE12
#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 12 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch12
#ifndef CONF_EIC_ASYNCH12
#define CONF_EIC_ASYNCH12 0
#endif
// </e>
// <e> Interrupt 13 Settings
// <id> eic_arch_enable_irq_setting13
#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
#define CONF_EIC_ENABLE_IRQ_SETTING13 0
#endif
// <q> External Interrupt 13 Filter Enable
// <i> Indicates whether the external interrupt 13 filter is enabled or not
// <id> eic_arch_filten13
#ifndef CONF_EIC_FILTEN13
#define CONF_EIC_FILTEN13 0
#endif
// <q> External Interrupt 13 Debounce Enable
// <i> Indicates whether the external interrupt 13 debounce is enabled or not
// <id> eic_arch_debounce_enable13
#ifndef CONF_EIC_DEBOUNCE_ENABLE13
#define CONF_EIC_DEBOUNCE_ENABLE13 0
#endif
// <q> External Interrupt 13 Event Output Enable
// <i> Indicates whether the external interrupt 13 event output is enabled or not
// <id> eic_arch_extinteo13
#ifndef CONF_EIC_EXTINTEO13
#define CONF_EIC_EXTINTEO13 0
#endif
// <y> Input 13 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense13
#ifndef CONF_EIC_SENSE13
#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 13 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch13
#ifndef CONF_EIC_ASYNCH13
#define CONF_EIC_ASYNCH13 0
#endif
// </e>
// <e> Interrupt 14 Settings
// <id> eic_arch_enable_irq_setting14
#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
#define CONF_EIC_ENABLE_IRQ_SETTING14 0
#endif
// <q> External Interrupt 14 Filter Enable
// <i> Indicates whether the external interrupt 14 filter is enabled or not
// <id> eic_arch_filten14
#ifndef CONF_EIC_FILTEN14
#define CONF_EIC_FILTEN14 0
#endif
// <q> External Interrupt 14 Debounce Enable
// <i> Indicates whether the external interrupt 14 debounce is enabled or not
// <id> eic_arch_debounce_enable14
#ifndef CONF_EIC_DEBOUNCE_ENABLE14
#define CONF_EIC_DEBOUNCE_ENABLE14 0
#endif
// <q> External Interrupt 14 Event Output Enable
// <i> Indicates whether the external interrupt 14 event output is enabled or not
// <id> eic_arch_extinteo14
#ifndef CONF_EIC_EXTINTEO14
#define CONF_EIC_EXTINTEO14 0
#endif
// <y> Input 14 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense14
#ifndef CONF_EIC_SENSE14
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 14 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch14
#ifndef CONF_EIC_ASYNCH14
#define CONF_EIC_ASYNCH14 0
#endif
// </e>
// <e> Interrupt 15 Settings
// <id> eic_arch_enable_irq_setting15
#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
#define CONF_EIC_ENABLE_IRQ_SETTING15 0
#endif
// <q> External Interrupt 15 Filter Enable
// <i> Indicates whether the external interrupt 15 filter is enabled or not
// <id> eic_arch_filten15
#ifndef CONF_EIC_FILTEN15
#define CONF_EIC_FILTEN15 0
#endif
// <q> External Interrupt 15 Debounce Enable
// <i> Indicates whether the external interrupt 15 debounce is enabled or not
// <id> eic_arch_debounce_enable15
#ifndef CONF_EIC_DEBOUNCE_ENABLE15
#define CONF_EIC_DEBOUNCE_ENABLE15 0
#endif
// <q> External Interrupt 15 Event Output Enable
// <i> Indicates whether the external interrupt 15 event output is enabled or not
// <id> eic_arch_extinteo15
#ifndef CONF_EIC_EXTINTEO15
#define CONF_EIC_EXTINTEO15 0
#endif
// <y> Input 15 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense15
#ifndef CONF_EIC_SENSE15
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 15 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch15
#ifndef CONF_EIC_ASYNCH15
#define CONF_EIC_ASYNCH15 0
#endif
// </e>
// <h> Debouncer 0 Settings
// <o> Debouncer Frequency Selection
// <0x0=>Divided by 2
// <0x1=>Divided by 4
// <0x2=>Divided by 8
// <0x3=>Divided by 16
// <0x4=>Divided by 32
// <0x5=>Divided by 64
// <0x6=>Divided by 128
// <0x7=>Divided by 256
// <i> Select the debouncer low frequency clock for pins
// <i> EXTINT[7:0].
// <id> eic_arch_prescaler0
#ifndef CONF_EIC_DPRESCALER0
#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0)
#endif
// <o> Low frequency samples
// <0x0=>3
// <0x1=>7
// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
// <i> current pin state to next pin state in synchronous debouncing mode.
// <id> eic_arch_states0
#ifndef CONF_EIC_STATES0
#define CONF_EIC_STATES0 0x0
#endif
// </h>
// <h> Debouncer 1 Settings
// <o> Debouncer Frequency Selection
// <0x0=>Divided by 2
// <0x1=>Divided by 4
// <0x2=>Divided by 8
// <0x3=>Divided by 16
// <0x4=>Divided by 32
// <0x5=>Divided by 64
// <0x6=>Divided by 128
// <0x7=>Divided by 256
// <i> Select the debouncer low frequency clock for pins
// <i> EXTINT[15:8].
// <id> eic_arch_prescaler1
#ifndef CONF_EIC_DPRESCALER1
#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0)
#endif
// <o> Low frequency samples
// <0x0=>3
// <0x1=>7
// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
// <i> current pin state to next pin state in synchronous debouncing mode.
// <id> eic_arch_states1
#ifndef CONF_EIC_STATES1
#define CONF_EIC_STATES1 0x0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_EIC_CONFIG_H

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software/firmware/oracle_e54_edition/config/hpl_gclk_config.h
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/* Auto-generated config file hpl_gclk_config.h */
#ifndef HPL_GCLK_CONFIG_H
#define HPL_GCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> Generic clock generator 0 configuration
// <i> Indicates whether generic clock 0 configuration is enabled or not
// <id> enable_gclk_gen_0
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
#define CONF_GCLK_GENERATOR_0_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 0 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 0
// <id> gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SOURCE
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_0_runstdby
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
#define CONF_GCLK_GEN_0_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_0_div_sel
#ifndef CONF_GCLK_GEN_0_DIVSEL
#define CONF_GCLK_GEN_0_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_0_oe
#ifndef CONF_GCLK_GEN_0_OE
#define CONF_GCLK_GEN_0_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_0_oov
#ifndef CONF_GCLK_GEN_0_OOV
#define CONF_GCLK_GEN_0_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_0_idc
#ifndef CONF_GCLK_GEN_0_IDC
#define CONF_GCLK_GEN_0_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_0_enable
#ifndef CONF_GCLK_GEN_0_GENEN
#define CONF_GCLK_GEN_0_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
// <id> gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 1 configuration
// <i> Indicates whether generic clock 1 configuration is enabled or not
// <id> enable_gclk_gen_1
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
#define CONF_GCLK_GENERATOR_1_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 1 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SOURCE
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_1_runstdby
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
#define CONF_GCLK_GEN_1_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_1_div_sel
#ifndef CONF_GCLK_GEN_1_DIVSEL
#define CONF_GCLK_GEN_1_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_1_oe
#ifndef CONF_GCLK_GEN_1_OE
#define CONF_GCLK_GEN_1_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_1_oov
#ifndef CONF_GCLK_GEN_1_OOV
#define CONF_GCLK_GEN_1_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_1_idc
#ifndef CONF_GCLK_GEN_1_IDC
#define CONF_GCLK_GEN_1_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_1_enable
#ifndef CONF_GCLK_GEN_1_GENEN
#define CONF_GCLK_GEN_1_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
// <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 2 configuration
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 2 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 2
// <id> gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SOURCE
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_2_runstdby
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
#define CONF_GCLK_GEN_2_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
#define CONF_GCLK_GEN_2_DIVSEL 1
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_2_oe
#ifndef CONF_GCLK_GEN_2_OE
#define CONF_GCLK_GEN_2_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_2_oov
#ifndef CONF_GCLK_GEN_2_OOV
#define CONF_GCLK_GEN_2_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_2_idc
#ifndef CONF_GCLK_GEN_2_IDC
#define CONF_GCLK_GEN_2_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
// <id> gclk_gen_2_div
#ifndef CONF_GCLK_GEN_2_DIV
#define CONF_GCLK_GEN_2_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 3 configuration
// <i> Indicates whether generic clock 3 configuration is enabled or not
// <id> enable_gclk_gen_3
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
#define CONF_GCLK_GENERATOR_3_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 3 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_runstdby
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
#define CONF_GCLK_GEN_3_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_3_div_sel
#ifndef CONF_GCLK_GEN_3_DIVSEL
#define CONF_GCLK_GEN_3_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_3_oe
#ifndef CONF_GCLK_GEN_3_OE
#define CONF_GCLK_GEN_3_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_3_oov
#ifndef CONF_GCLK_GEN_3_OOV
#define CONF_GCLK_GEN_3_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_3_idc
#ifndef CONF_GCLK_GEN_3_IDC
#define CONF_GCLK_GEN_3_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_3_enable
#ifndef CONF_GCLK_GEN_3_GENEN
#define CONF_GCLK_GEN_3_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
// <id> gclk_gen_3_div
#ifndef CONF_GCLK_GEN_3_DIV
#define CONF_GCLK_GEN_3_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 4 configuration
// <i> Indicates whether generic clock 4 configuration is enabled or not
// <id> enable_gclk_gen_4
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
#define CONF_GCLK_GENERATOR_4_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 4 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_4_runstdby
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
#define CONF_GCLK_GEN_4_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_4_div_sel
#ifndef CONF_GCLK_GEN_4_DIVSEL
#define CONF_GCLK_GEN_4_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
#define CONF_GCLK_GEN_4_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_4_oov
#ifndef CONF_GCLK_GEN_4_OOV
#define CONF_GCLK_GEN_4_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_4_idc
#ifndef CONF_GCLK_GEN_4_IDC
#define CONF_GCLK_GEN_4_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_4_enable
#ifndef CONF_GCLK_GEN_4_GENEN
#define CONF_GCLK_GEN_4_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 5 configuration
// <i> Indicates whether generic clock 5 configuration is enabled or not
// <id> enable_gclk_gen_5
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
#define CONF_GCLK_GENERATOR_5_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 5 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 5
// <id> gclk_gen_5_oscillator
#ifndef CONF_GCLK_GEN_5_SOURCE
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_5_runstdby
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
#define CONF_GCLK_GEN_5_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_5_div_sel
#ifndef CONF_GCLK_GEN_5_DIVSEL
#define CONF_GCLK_GEN_5_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_5_oe
#ifndef CONF_GCLK_GEN_5_OE
#define CONF_GCLK_GEN_5_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_5_oov
#ifndef CONF_GCLK_GEN_5_OOV
#define CONF_GCLK_GEN_5_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_5_idc
#ifndef CONF_GCLK_GEN_5_IDC
#define CONF_GCLK_GEN_5_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_5_enable
#ifndef CONF_GCLK_GEN_5_GENEN
#define CONF_GCLK_GEN_5_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
// <id> gclk_gen_5_div
#ifndef CONF_GCLK_GEN_5_DIV
#define CONF_GCLK_GEN_5_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 6 configuration
// <i> Indicates whether generic clock 6 configuration is enabled or not
// <id> enable_gclk_gen_6
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
#define CONF_GCLK_GENERATOR_6_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 6 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 6
// <id> gclk_gen_6_oscillator
#ifndef CONF_GCLK_GEN_6_SOURCE
#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_6_runstdby
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
#define CONF_GCLK_GEN_6_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_6_div_sel
#ifndef CONF_GCLK_GEN_6_DIVSEL
#define CONF_GCLK_GEN_6_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_6_oe
#ifndef CONF_GCLK_GEN_6_OE
#define CONF_GCLK_GEN_6_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_6_oov
#ifndef CONF_GCLK_GEN_6_OOV
#define CONF_GCLK_GEN_6_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_6_idc
#ifndef CONF_GCLK_GEN_6_IDC
#define CONF_GCLK_GEN_6_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_6_enable
#ifndef CONF_GCLK_GEN_6_GENEN
#define CONF_GCLK_GEN_6_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
// <id> gclk_gen_6_div
#ifndef CONF_GCLK_GEN_6_DIV
#define CONF_GCLK_GEN_6_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 7 configuration
// <i> Indicates whether generic clock 7 configuration is enabled or not
// <id> enable_gclk_gen_7
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
#define CONF_GCLK_GENERATOR_7_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 7 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 7
// <id> gclk_gen_7_oscillator
#ifndef CONF_GCLK_GEN_7_SOURCE
#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_7_runstdby
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
#define CONF_GCLK_GEN_7_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_7_div_sel
#ifndef CONF_GCLK_GEN_7_DIVSEL
#define CONF_GCLK_GEN_7_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_7_oe
#ifndef CONF_GCLK_GEN_7_OE
#define CONF_GCLK_GEN_7_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_7_oov
#ifndef CONF_GCLK_GEN_7_OOV
#define CONF_GCLK_GEN_7_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_7_idc
#ifndef CONF_GCLK_GEN_7_IDC
#define CONF_GCLK_GEN_7_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_7_enable
#ifndef CONF_GCLK_GEN_7_GENEN
#define CONF_GCLK_GEN_7_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
// <id> gclk_gen_7_div
#ifndef CONF_GCLK_GEN_7_DIV
#define CONF_GCLK_GEN_7_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 8 configuration
// <i> Indicates whether generic clock 8 configuration is enabled or not
// <id> enable_gclk_gen_8
#ifndef CONF_GCLK_GENERATOR_8_CONFIG
#define CONF_GCLK_GENERATOR_8_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 8 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 8
// <id> gclk_gen_8_oscillator
#ifndef CONF_GCLK_GEN_8_SOURCE
#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_8_runstdby
#ifndef CONF_GCLK_GEN_8_RUNSTDBY
#define CONF_GCLK_GEN_8_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_8_div_sel
#ifndef CONF_GCLK_GEN_8_DIVSEL
#define CONF_GCLK_GEN_8_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_8_oe
#ifndef CONF_GCLK_GEN_8_OE
#define CONF_GCLK_GEN_8_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_8_oov
#ifndef CONF_GCLK_GEN_8_OOV
#define CONF_GCLK_GEN_8_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_8_idc
#ifndef CONF_GCLK_GEN_8_IDC
#define CONF_GCLK_GEN_8_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_8_enable
#ifndef CONF_GCLK_GEN_8_GENEN
#define CONF_GCLK_GEN_8_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 8 division <0x0000-0xFFFF>
// <id> gclk_gen_8_div
#ifndef CONF_GCLK_GEN_8_DIV
#define CONF_GCLK_GEN_8_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 9 configuration
// <i> Indicates whether generic clock 9 configuration is enabled or not
// <id> enable_gclk_gen_9
#ifndef CONF_GCLK_GENERATOR_9_CONFIG
#define CONF_GCLK_GENERATOR_9_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 9 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 9
// <id> gclk_gen_9_oscillator
#ifndef CONF_GCLK_GEN_9_SOURCE
#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_9_runstdby
#ifndef CONF_GCLK_GEN_9_RUNSTDBY
#define CONF_GCLK_GEN_9_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_9_div_sel
#ifndef CONF_GCLK_GEN_9_DIVSEL
#define CONF_GCLK_GEN_9_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_9_oe
#ifndef CONF_GCLK_GEN_9_OE
#define CONF_GCLK_GEN_9_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_9_oov
#ifndef CONF_GCLK_GEN_9_OOV
#define CONF_GCLK_GEN_9_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_9_idc
#ifndef CONF_GCLK_GEN_9_IDC
#define CONF_GCLK_GEN_9_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_9_enable
#ifndef CONF_GCLK_GEN_9_GENEN
#define CONF_GCLK_GEN_9_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 9 division <0x0000-0xFFFF>
// <id> gclk_gen_9_div
#ifndef CONF_GCLK_GEN_9_DIV
#define CONF_GCLK_GEN_9_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 10 configuration
// <i> Indicates whether generic clock 10 configuration is enabled or not
// <id> enable_gclk_gen_10
#ifndef CONF_GCLK_GENERATOR_10_CONFIG
#define CONF_GCLK_GENERATOR_10_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 10 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 10
// <id> gclk_gen_10_oscillator
#ifndef CONF_GCLK_GEN_10_SOURCE
#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_10_runstdby
#ifndef CONF_GCLK_GEN_10_RUNSTDBY
#define CONF_GCLK_GEN_10_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_10_div_sel
#ifndef CONF_GCLK_GEN_10_DIVSEL
#define CONF_GCLK_GEN_10_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_10_oe
#ifndef CONF_GCLK_GEN_10_OE
#define CONF_GCLK_GEN_10_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_10_oov
#ifndef CONF_GCLK_GEN_10_OOV
#define CONF_GCLK_GEN_10_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_10_idc
#ifndef CONF_GCLK_GEN_10_IDC
#define CONF_GCLK_GEN_10_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_10_enable
#ifndef CONF_GCLK_GEN_10_GENEN
#define CONF_GCLK_GEN_10_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 10 division <0x0000-0xFFFF>
// <id> gclk_gen_10_div
#ifndef CONF_GCLK_GEN_10_DIV
#define CONF_GCLK_GEN_10_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 11 configuration
// <i> Indicates whether generic clock 11 configuration is enabled or not
// <id> enable_gclk_gen_11
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
#define CONF_GCLK_GENERATOR_11_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 11 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 11
// <id> gclk_gen_11_oscillator
#ifndef CONF_GCLK_GEN_11_SOURCE
#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_11_runstdby
#ifndef CONF_GCLK_GEN_11_RUNSTDBY
#define CONF_GCLK_GEN_11_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_11_div_sel
#ifndef CONF_GCLK_GEN_11_DIVSEL
#define CONF_GCLK_GEN_11_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_11_oe
#ifndef CONF_GCLK_GEN_11_OE
#define CONF_GCLK_GEN_11_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_11_oov
#ifndef CONF_GCLK_GEN_11_OOV
#define CONF_GCLK_GEN_11_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_11_idc
#ifndef CONF_GCLK_GEN_11_IDC
#define CONF_GCLK_GEN_11_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_11_enable
#ifndef CONF_GCLK_GEN_11_GENEN
#define CONF_GCLK_GEN_11_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
// <id> gclk_gen_11_div
#ifndef CONF_GCLK_GEN_11_DIV
#define CONF_GCLK_GEN_11_DIV 1
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_GCLK_CONFIG_H

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software/firmware/oracle_e54_edition/config/hpl_mclk_config.h
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/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
#endif
// <y> Low Power Clock Division
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_lpdiv
#ifndef CONF_MCLK_LPDIV
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
#endif
// <y> High-Speed Clock Division
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
// <id> mclk_arch_hsdiv
#ifndef CONF_MCLK_HSDIV
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 5
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H

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software/firmware/oracle_e54_edition/config/hpl_osc32kctrl_config.h
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/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 0
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x3
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 1
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// <o> Control Gain Mode
// <0x0=>Low Power mode
// <0x1=>Standard mode
// <0x2=>High Speed mode
// <id> xosc32k_arch_cgm
#ifndef CONF_XOSC32K_CGM
#define CONF_XOSC32K_CGM 0x1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x3F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H

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software/firmware/oracle_e54_edition/config/hpl_oscctrl_config.h
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/* Auto-generated config file hpl_oscctrl_config.h */
#ifndef HPL_OSCCTRL_CONFIG_H
#define HPL_OSCCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC0 is enabled or not
// <id> enable_xosc0
#ifndef CONF_XOSC0_CONFIG
#define CONF_XOSC0_CONFIG 0
#endif
// <o> Frequency <8000000-48000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc0_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC0_FREQUENCY 12000000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc0_arch_enable
#ifndef CONF_XOSC0_ENABLE
#define CONF_XOSC0_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc0_arch_startup
#ifndef CONF_XOSC0_STARTUP
#define CONF_XOSC0_STARTUP 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc0_arch_swben
#ifndef CONF_XOSC0_SWBEN
#define CONF_XOSC0_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc0_arch_cfden
#ifndef CONF_XOSC0_CFDEN
#define CONF_XOSC0_CFDEN 0
#endif
// <q> Automatic Loop Control Enable
// <i> Indicates whether Automatic Loop Control is enabled or not
// <id> xosc0_arch_enalc
#ifndef CONF_XOSC0_ENALC
#define CONF_XOSC0_ENALC 0
#endif
// <q> Low Buffer Gain Enable
// <i> Indicates whether Low Buffer Gain is enabled or not
// <id> xosc0_arch_lowbufgain
#ifndef CONF_XOSC0_LOWBUFGAIN
#define CONF_XOSC0_LOWBUFGAIN 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc0_arch_ondemand
#ifndef CONF_XOSC0_ONDEMAND
#define CONF_XOSC0_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc0_arch_runstdby
#ifndef CONF_XOSC0_RUNSTDBY
#define CONF_XOSC0_RUNSTDBY 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc0_arch_xtalen
#ifndef CONF_XOSC0_XTALEN
#define CONF_XOSC0_XTALEN 0
#endif
//</h>
//</e>
#if CONF_XOSC0_FREQUENCY >= 32000000
#define CONF_XOSC0_CFDPRESC 0x0
#define CONF_XOSC0_IMULT 0x7
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 24000000
#define CONF_XOSC0_CFDPRESC 0x1
#define CONF_XOSC0_IMULT 0x6
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 16000000
#define CONF_XOSC0_CFDPRESC 0x2
#define CONF_XOSC0_IMULT 0x5
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 8000000
#define CONF_XOSC0_CFDPRESC 0x3
#define CONF_XOSC0_IMULT 0x4
#define CONF_XOSC0_IPTAT 0x3
#endif
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC1 is enabled or not
// <id> enable_xosc1
#ifndef CONF_XOSC1_CONFIG
#define CONF_XOSC1_CONFIG 0
#endif
// <o> Frequency <8000000-48000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc1_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC1_FREQUENCY 12000000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc1_arch_enable
#ifndef CONF_XOSC1_ENABLE
#define CONF_XOSC1_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc1_arch_startup
#ifndef CONF_XOSC1_STARTUP
#define CONF_XOSC1_STARTUP 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc1_arch_swben
#ifndef CONF_XOSC1_SWBEN
#define CONF_XOSC1_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc1_arch_cfden
#ifndef CONF_XOSC1_CFDEN
#define CONF_XOSC1_CFDEN 0
#endif
// <q> Automatic Loop Control Enable
// <i> Indicates whether Automatic Loop Control is enabled or not
// <id> xosc1_arch_enalc
#ifndef CONF_XOSC1_ENALC
#define CONF_XOSC1_ENALC 0
#endif
// <q> Low Buffer Gain Enable
// <i> Indicates whether Low Buffer Gain is enabled or not
// <id> xosc1_arch_lowbufgain
#ifndef CONF_XOSC1_LOWBUFGAIN
#define CONF_XOSC1_LOWBUFGAIN 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc1_arch_ondemand
#ifndef CONF_XOSC1_ONDEMAND
#define CONF_XOSC1_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc1_arch_runstdby
#ifndef CONF_XOSC1_RUNSTDBY
#define CONF_XOSC1_RUNSTDBY 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc1_arch_xtalen
#ifndef CONF_XOSC1_XTALEN
#define CONF_XOSC1_XTALEN 1
#endif
//</h>
//</e>
#if CONF_XOSC1_FREQUENCY >= 32000000
#define CONF_XOSC1_CFDPRESC 0x0
#define CONF_XOSC1_IMULT 0x7
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 24000000
#define CONF_XOSC1_CFDPRESC 0x1
#define CONF_XOSC1_IMULT 0x6
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 16000000
#define CONF_XOSC1_CFDPRESC 0x2
#define CONF_XOSC1_IMULT 0x5
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 8000000
#define CONF_XOSC1_CFDPRESC 0x3
#define CONF_XOSC1_IMULT 0x4
#define CONF_XOSC1_IPTAT 0x3
#endif
// <e> DFLL Configuration
// <i> Indicates whether configuration for DFLL is enabled or not
// <id> enable_dfll
#ifndef CONF_DFLL_CONFIG
#define CONF_DFLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source
// <id> dfll_ref_clock
#ifndef CONF_DFLL_GCLK
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
// <h> Digital Frequency Locked Loop Control
// <q> DFLL Enable
// <i> Indicates whether DFLL is enabled or not
// <id> dfll_arch_enable
#ifndef CONF_DFLL_ENABLE
#define CONF_DFLL_ENABLE 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> dfll_arch_ondemand
#ifndef CONF_DFLL_ONDEMAND
#define CONF_DFLL_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> dfll_arch_runstdby
#ifndef CONF_DFLL_RUNSTDBY
#define CONF_DFLL_RUNSTDBY 0
#endif
// <q> USB Clock Recovery Mode
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
// <id> dfll_arch_usbcrm
#ifndef CONF_DFLL_USBCRM
#define CONF_DFLL_USBCRM 0
#endif
// <q> Wait Lock
// <i> Indicates whether Wait Lock is enabled or not
// <id> dfll_arch_waitlock
#ifndef CONF_DFLL_WAITLOCK
#define CONF_DFLL_WAITLOCK 1
#endif
// <q> Bypass Coarse Lock
// <i> Indicates whether Bypass Coarse Lock is enabled or not
// <id> dfll_arch_bplckc
#ifndef CONF_DFLL_BPLCKC
#define CONF_DFLL_BPLCKC 0
#endif
// <q> Quick Lock Disable
// <i> Indicates whether Quick Lock Disable is enabled or not
// <id> dfll_arch_qldis
#ifndef CONF_DFLL_QLDIS
#define CONF_DFLL_QLDIS 0
#endif
// <q> Chill Cycle Disable
// <i> Indicates whether Chill Cycle Disable is enabled or not
// <id> dfll_arch_ccdis
#ifndef CONF_DFLL_CCDIS
#define CONF_DFLL_CCDIS 0
#endif
// <q> Lose Lock After Wake
// <i> Indicates whether Lose Lock After Wake is enabled or not
// <id> dfll_arch_llaw
#ifndef CONF_DFLL_LLAW
#define CONF_DFLL_LLAW 0
#endif
// <q> Stable DFLL Frequency
// <i> Indicates whether Stable DFLL Frequency is enabled or not
// <id> dfll_arch_stable
#ifndef CONF_DFLL_STABLE
#define CONF_DFLL_STABLE 0
#endif
// <o> Operating Mode Selection
// <0=>Open Loop Mode
// <1=>Closed Loop Mode
// <id> dfll_mode
#ifndef CONF_DFLL_MODE
#define CONF_DFLL_MODE 0x0
#endif
// <o> Coarse Maximum Step <0x0-0x1F>
// <id> dfll_arch_cstep
#ifndef CONF_DFLL_CSTEP
#define CONF_DFLL_CSTEP 0x1
#endif
// <o> Fine Maximum Step <0x0-0xFF>
// <id> dfll_arch_fstep
#ifndef CONF_DFLL_FSTEP
#define CONF_DFLL_FSTEP 0x1
#endif
// <o> DFLL Multiply Factor <0x0-0xFFFF>
// <id> dfll_mul
#ifndef CONF_DFLL_MUL
#define CONF_DFLL_MUL 0x0
#endif
// <e> DFLL Calibration Overwrite
// <i> Indicates whether Overwrite Calibration value of DFLL
// <id> dfll_arch_calibration
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
#endif
// <o> Coarse Value <0x0-0x3F>
// <id> dfll_arch_coarse
#ifndef CONF_DFLL_COARSE
#define CONF_DFLL_COARSE (0x1f / 4)
#endif
// <o> Fine Value <0x0-0xFF>
// <id> dfll_arch_fine
#ifndef CONF_DFLL_FINE
#define CONF_DFLL_FINE (0x80)
#endif
//</e>
//</h>
//</e>
// <e> FDPLL0 Configuration
// <i> Indicates whether configuration for FDPLL0 is enabled or not
// <id> enable_fdpll0
#ifndef CONF_FDPLL0_CONFIG
#define CONF_FDPLL0_CONFIG 1
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source.
// <id> fdpll0_ref_clock
#ifndef CONF_FDPLL0_GCLK
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll0_arch_enable
#ifndef CONF_FDPLL0_ENABLE
#define CONF_FDPLL0_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll0_arch_ondemand
#ifndef CONF_FDPLL0_ONDEMAND
#define CONF_FDPLL0_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll0_arch_runstdby
#ifndef CONF_FDPLL0_RUNSTDBY
#define CONF_FDPLL0_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll0_ldrfrac
#ifndef CONF_FDPLL0_LDRFRAC
#define CONF_FDPLL0_LDRFRAC 0x1
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll0_ldr
#ifndef CONF_FDPLL0_LDR
#define CONF_FDPLL0_LDR 0xe4d
#endif
// <o> Clock Divider <0x0-0x7FF>
// <i> This Clock divider is only for XOSC clock input to DPLL
// <id> fdpll0_clock_div
#ifndef CONF_FDPLL0_DIV
#define CONF_FDPLL0_DIV 0x0
#endif
// <q> DCO Filter Enable
// <i> Indicates whether DCO Filter Enable is enabled or not
// <id> fdpll0_arch_dcoen
#ifndef CONF_FDPLL0_DCOEN
#define CONF_FDPLL0_DCOEN 0
#endif
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
// <id> fdpll0_clock_dcofilter
#ifndef CONF_FDPLL0_DCOFILTER
#define CONF_FDPLL0_DCOFILTER 0x0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll0_arch_lbypass
#ifndef CONF_FDPLL0_LBYPASS
#define CONF_FDPLL0_LBYPASS 1
#endif
// <o> Lock Time
// <0x0=>No time-out, automatic lock
// <0x4=>The Time-out if no lock within 800 us
// <0x5=>The Time-out if no lock within 900 us
// <0x6=>The Time-out if no lock within 1 ms
// <0x7=>The Time-out if no lock within 11 ms
// <id> fdpll0_arch_ltime
#ifndef CONF_FDPLL0_LTIME
#define CONF_FDPLL0_LTIME 0x0
#endif
// <o> Reference Clock Selection
// <0x0=>GCLK clock reference
// <0x1=>XOSC32K clock reference
// <0x2=>XOSC0 clock reference
// <0x3=>XOSC1 clock reference
// <id> fdpll0_arch_refclk
#ifndef CONF_FDPLL0_REFCLK
#define CONF_FDPLL0_REFCLK 0x1
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll0_arch_wuf
#ifndef CONF_FDPLL0_WUF
#define CONF_FDPLL0_WUF 0
#endif
// <o> Proportional Integral Filter Selection <0x0-0xF>
// <id> fdpll0_arch_filter
#ifndef CONF_FDPLL0_FILTER
#define CONF_FDPLL0_FILTER 0x0
#endif
//</h>
//</e>
// <e> FDPLL1 Configuration
// <i> Indicates whether configuration for FDPLL1 is enabled or not
// <id> enable_fdpll1
#ifndef CONF_FDPLL1_CONFIG
#define CONF_FDPLL1_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source.
// <id> fdpll1_ref_clock
#ifndef CONF_FDPLL1_GCLK
#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll1_arch_enable
#ifndef CONF_FDPLL1_ENABLE
#define CONF_FDPLL1_ENABLE 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll1_arch_ondemand
#ifndef CONF_FDPLL1_ONDEMAND
#define CONF_FDPLL1_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll1_arch_runstdby
#ifndef CONF_FDPLL1_RUNSTDBY
#define CONF_FDPLL1_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldrfrac
#ifndef CONF_FDPLL1_LDRFRAC
#define CONF_FDPLL1_LDRFRAC 0xd
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldr
#ifndef CONF_FDPLL1_LDR
#define CONF_FDPLL1_LDR 0x5b7
#endif
// <o> Clock Divider <0x0-0x7FF>
// <i> This Clock divider is only for XOSC clock input to DPLL
// <id> fdpll1_clock_div
#ifndef CONF_FDPLL1_DIV
#define CONF_FDPLL1_DIV 0x0
#endif
// <q> DCO Filter Enable
// <i> Indicates whether DCO Filter Enable is enabled or not
// <id> fdpll1_arch_dcoen
#ifndef CONF_FDPLL1_DCOEN
#define CONF_FDPLL1_DCOEN 0
#endif
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
// <id> fdpll1_clock_dcofilter
#ifndef CONF_FDPLL1_DCOFILTER
#define CONF_FDPLL1_DCOFILTER 0x0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll1_arch_lbypass
#ifndef CONF_FDPLL1_LBYPASS
#define CONF_FDPLL1_LBYPASS 0
#endif
// <o> Lock Time
// <0x0=>No time-out, automatic lock
// <0x4=>The Time-out if no lock within 800 us
// <0x5=>The Time-out if no lock within 900 us
// <0x6=>The Time-out if no lock within 1 ms
// <0x7=>The Time-out if no lock within 11 ms
// <id> fdpll1_arch_ltime
#ifndef CONF_FDPLL1_LTIME
#define CONF_FDPLL1_LTIME 0x0
#endif
// <o> Reference Clock Selection
// <0x0=>GCLK clock reference
// <0x1=>XOSC32K clock reference
// <0x2=>XOSC0 clock reference
// <0x3=>XOSC1 clock reference
// <id> fdpll1_arch_refclk
#ifndef CONF_FDPLL1_REFCLK
#define CONF_FDPLL1_REFCLK 0x1
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll1_arch_wuf
#ifndef CONF_FDPLL1_WUF
#define CONF_FDPLL1_WUF 0
#endif
// <o> Proportional Integral Filter Selection <0x0-0xF>
// <id> fdpll1_arch_filter
#ifndef CONF_FDPLL1_FILTER
#define CONF_FDPLL1_FILTER 0x0
#endif
//</h>
//</e>
// <<< end of configuration section >>>
#endif // HPL_OSCCTRL_CONFIG_H

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software/firmware/oracle_e54_edition/config/hpl_port_config.h
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/* Auto-generated config file hpl_port_config.h */
#ifndef HPL_PORT_CONFIG_H
#define HPL_PORT_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> PORT Input Event 0 configuration
// <id> enable_port_input_event_0
#ifndef CONF_PORT_EVCTRL_PORT_0
#define CONF_PORT_EVCTRL_PORT_0 0
#endif
// <h> PORT Input Event 0 configuration on PORT A
// <q> PORTA Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
// <id> porta_input_event_enable_0
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_0
#ifndef CONF_PORTA_EVCTRL_PID_0
#define CONF_PORTA_EVCTRL_PID_0 0x0
#endif
// <o> PORTA Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 0
// <id> porta_event_action_0
#ifndef CONF_PORTA_EVCTRL_EVACT_0
#define CONF_PORTA_EVCTRL_EVACT_0 0
#endif
// </h>
// <h> PORT Input Event 0 configuration on PORT B
// <q> PORTB Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
// <id> portb_input_event_enable_0
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_0
#ifndef CONF_PORTB_EVCTRL_PID_0
#define CONF_PORTB_EVCTRL_PID_0 0x0
#endif
// <o> PORTB Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 0
// <id> portb_event_action_0
#ifndef CONF_PORTB_EVCTRL_EVACT_0
#define CONF_PORTB_EVCTRL_EVACT_0 0
#endif
// </h>
// <h> PORT Input Event 0 configuration on PORT C
// <q> PORTC Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled
// <id> portc_input_event_enable_0
#ifndef CONF_PORTC_EVCTRL_PORTEI_0
#define CONF_PORTC_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTC Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port C on which the event action will be performed
// <id> portc_event_pin_identifier_0
#ifndef CONF_PORTC_EVCTRL_PID_0
#define CONF_PORTC_EVCTRL_PID_0 0x0
#endif
// <o> PORTC Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT C will perform on event input 0
// <id> portc_event_action_0
#ifndef CONF_PORTC_EVCTRL_EVACT_0
#define CONF_PORTC_EVCTRL_EVACT_0 0
#endif
// </h>
// <h> PORT Input Event 0 configuration on PORT D
// <q> PORTD Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled
// <id> portd_input_event_enable_0
#ifndef CONF_PORTD_EVCTRL_PORTEI_0
#define CONF_PORTD_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTD Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port D on which the event action will be performed
// <id> portd_event_pin_identifier_0
#ifndef CONF_PORTD_EVCTRL_PID_0
#define CONF_PORTD_EVCTRL_PID_0 0x0
#endif
// <o> PORTD Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT D will perform on event input 0
// <id> portd_event_action_0
#ifndef CONF_PORTD_EVCTRL_EVACT_0
#define CONF_PORTD_EVCTRL_EVACT_0 0
#endif
// </h>
// </e>
// <e> PORT Input Event 1 configuration
// <id> enable_port_input_event_1
#ifndef CONF_PORT_EVCTRL_PORT_1
#define CONF_PORT_EVCTRL_PORT_1 0
#endif
// <h> PORT Input Event 1 configuration on PORT A
// <q> PORTA Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
// <id> porta_input_event_enable_1
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_1
#ifndef CONF_PORTA_EVCTRL_PID_1
#define CONF_PORTA_EVCTRL_PID_1 0x0
#endif
// <o> PORTA Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 1
// <id> porta_event_action_1
#ifndef CONF_PORTA_EVCTRL_EVACT_1
#define CONF_PORTA_EVCTRL_EVACT_1 0
#endif
// </h>
// <h> PORT Input Event 1 configuration on PORT B
// <q> PORTB Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
// <id> portb_input_event_enable_1
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_1
#ifndef CONF_PORTB_EVCTRL_PID_1
#define CONF_PORTB_EVCTRL_PID_1 0x0
#endif
// <o> PORTB Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 1
// <id> portb_event_action_1
#ifndef CONF_PORTB_EVCTRL_EVACT_1
#define CONF_PORTB_EVCTRL_EVACT_1 0
#endif
// </h>
// <h> PORT Input Event 1 configuration on PORT C
// <q> PORTC Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled
// <id> portc_input_event_enable_1
#ifndef CONF_PORTC_EVCTRL_PORTEI_1
#define CONF_PORTC_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTC Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port C on which the event action will be performed
// <id> portc_event_pin_identifier_1
#ifndef CONF_PORTC_EVCTRL_PID_1
#define CONF_PORTC_EVCTRL_PID_1 0x0
#endif
// <o> PORTC Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT C will perform on event input 1
// <id> portc_event_action_1
#ifndef CONF_PORTC_EVCTRL_EVACT_1
#define CONF_PORTC_EVCTRL_EVACT_1 0
#endif
// </h>
// <h> PORT Input Event 1 configuration on PORT D
// <q> PORTD Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled
// <id> portd_input_event_enable_1
#ifndef CONF_PORTD_EVCTRL_PORTEI_1
#define CONF_PORTD_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTD Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port D on which the event action will be performed
// <id> portd_event_pin_identifier_1
#ifndef CONF_PORTD_EVCTRL_PID_1
#define CONF_PORTD_EVCTRL_PID_1 0x0
#endif
// <o> PORTD Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT D will perform on event input 1
// <id> portd_event_action_1
#ifndef CONF_PORTD_EVCTRL_EVACT_1
#define CONF_PORTD_EVCTRL_EVACT_1 0
#endif
// </h>
// </e>
// <e> PORT Input Event 2 configuration
// <id> enable_port_input_event_2
#ifndef CONF_PORT_EVCTRL_PORT_2
#define CONF_PORT_EVCTRL_PORT_2 0
#endif
// <h> PORT Input Event 2 configuration on PORT A
// <q> PORTA Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
// <id> porta_input_event_enable_2
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_2
#ifndef CONF_PORTA_EVCTRL_PID_2
#define CONF_PORTA_EVCTRL_PID_2 0x0
#endif
// <o> PORTA Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 2
// <id> porta_event_action_2
#ifndef CONF_PORTA_EVCTRL_EVACT_2
#define CONF_PORTA_EVCTRL_EVACT_2 0
#endif
// </h>
// <h> PORT Input Event 2 configuration on PORT B
// <q> PORTB Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
// <id> portb_input_event_enable_2
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_2
#ifndef CONF_PORTB_EVCTRL_PID_2
#define CONF_PORTB_EVCTRL_PID_2 0x0
#endif
// <o> PORTB Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 2
// <id> portb_event_action_2
#ifndef CONF_PORTB_EVCTRL_EVACT_2
#define CONF_PORTB_EVCTRL_EVACT_2 0
#endif
// </h>
// <h> PORT Input Event 2 configuration on PORT C
// <q> PORTC Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled
// <id> portc_input_event_enable_2
#ifndef CONF_PORTC_EVCTRL_PORTEI_2
#define CONF_PORTC_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTC Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port C on which the event action will be performed
// <id> portc_event_pin_identifier_2
#ifndef CONF_PORTC_EVCTRL_PID_2
#define CONF_PORTC_EVCTRL_PID_2 0x0
#endif
// <o> PORTC Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT C will perform on event input 2
// <id> portc_event_action_2
#ifndef CONF_PORTC_EVCTRL_EVACT_2
#define CONF_PORTC_EVCTRL_EVACT_2 0
#endif
// </h>
// <h> PORT Input Event 2 configuration on PORT D
// <q> PORTD Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled
// <id> portd_input_event_enable_2
#ifndef CONF_PORTD_EVCTRL_PORTEI_2
#define CONF_PORTD_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTD Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port D on which the event action will be performed
// <id> portd_event_pin_identifier_2
#ifndef CONF_PORTD_EVCTRL_PID_2
#define CONF_PORTD_EVCTRL_PID_2 0x0
#endif
// <o> PORTD Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT D will perform on event input 2
// <id> portd_event_action_2
#ifndef CONF_PORTD_EVCTRL_EVACT_2
#define CONF_PORTD_EVCTRL_EVACT_2 0
#endif
// </h>
// </e>
// <e> PORT Input Event 3 configuration
// <id> enable_port_input_event_3
#ifndef CONF_PORT_EVCTRL_PORT_3
#define CONF_PORT_EVCTRL_PORT_3 0
#endif
// <h> PORT Input Event 3 configuration on PORT A
// <q> PORTA Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
// <id> porta_input_event_enable_3
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_3
#ifndef CONF_PORTA_EVCTRL_PID_3
#define CONF_PORTA_EVCTRL_PID_3 0x0
#endif
// <o> PORTA Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 3
// <id> porta_event_action_3
#ifndef CONF_PORTA_EVCTRL_EVACT_3
#define CONF_PORTA_EVCTRL_EVACT_3 0
#endif
// </h>
// <h> PORT Input Event 3 configuration on PORT B
// <q> PORTB Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
// <id> portb_input_event_enable_3
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_3
#ifndef CONF_PORTB_EVCTRL_PID_3
#define CONF_PORTB_EVCTRL_PID_3 0x0
#endif
// <o> PORTB Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 3
// <id> portb_event_action_3
#ifndef CONF_PORTB_EVCTRL_EVACT_3
#define CONF_PORTB_EVCTRL_EVACT_3 0
#endif
// </h>
// <h> PORT Input Event 3 configuration on PORT C
// <q> PORTC Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled
// <id> portc_input_event_enable_3
#ifndef CONF_PORTC_EVCTRL_PORTEI_3
#define CONF_PORTC_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTC Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port C on which the event action will be performed
// <id> portc_event_pin_identifier_3
#ifndef CONF_PORTC_EVCTRL_PID_3
#define CONF_PORTC_EVCTRL_PID_3 0x0
#endif
// <o> PORTC Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT C will perform on event input 3
// <id> portc_event_action_3
#ifndef CONF_PORTC_EVCTRL_EVACT_3
#define CONF_PORTC_EVCTRL_EVACT_3 0
#endif
// </h>
// <h> PORT Input Event 3 configuration on PORT D
// <q> PORTD Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled
// <id> portd_input_event_enable_3
#ifndef CONF_PORTD_EVCTRL_PORTEI_3
#define CONF_PORTD_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTD Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port D on which the event action will be performed
// <id> portd_event_pin_identifier_3
#ifndef CONF_PORTD_EVCTRL_PID_3
#define CONF_PORTD_EVCTRL_PID_3 0x0
#endif
// <o> PORTD Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT D will perform on event input 3
// <id> portd_event_action_3
#ifndef CONF_PORTD_EVCTRL_EVACT_3
#define CONF_PORTD_EVCTRL_EVACT_3 0
#endif
// </h>
// </e>
#define CONF_PORTA_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
#define CONF_PORTB_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
#define CONF_PORTC_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \
| CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \
| CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3))
#define CONF_PORTD_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \
| CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \
| CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3))
// <<< end of configuration section >>>
#endif // HPL_PORT_CONFIG_H

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software/firmware/oracle_e54_edition/config/hpl_sercom_config.h
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/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef CONF_SERCOM_2_USART_ENABLE
#define CONF_SERCOM_2_USART_ENABLE 1
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
#ifndef CONF_SERCOM_2_USART_RXEN
#define CONF_SERCOM_2_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
#ifndef CONF_SERCOM_2_USART_TXEN
#define CONF_SERCOM_2_USART_TXEN 1
#endif
// <o> Frame parity
// <0x0=>No parity
// <0x1=>Even parity
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
#ifndef CONF_SERCOM_2_USART_PARITY
#define CONF_SERCOM_2_USART_PARITY 0x0
#endif
// <o> Character Size
// <0x0=>8 bits
// <0x1=>9 bits
// <0x5=>5 bits
// <0x6=>6 bits
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
#ifndef CONF_SERCOM_2_USART_CHSIZE
#define CONF_SERCOM_2_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
// <0=>One stop bit
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
#ifndef CONF_SERCOM_2_USART_SBMODE
#define CONF_SERCOM_2_USART_SBMODE 0
#endif
// <o> Baud rate <1-6250000>
// <i> USART baud rate setting
// <id> usart_baud_rate
#ifndef CONF_SERCOM_2_USART_BAUD
#define CONF_SERCOM_2_USART_BAUD 115200
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
#define CONF_SERCOM_2_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
#ifndef CONF_SERCOM_2_USART_IBON
#define CONF_SERCOM_2_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
#ifndef CONF_SERCOM_2_USART_SFDE
#define CONF_SERCOM_2_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
#ifndef CONF_SERCOM_2_USART_CLODEN
#define CONF_SERCOM_2_USART_CLODEN 0
#endif
// <o> Operating Mode
// <0x0=>USART with external clock
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
#ifndef CONF_SERCOM_2_USART_MODE
#define CONF_SERCOM_2_USART_MODE 0x1
#endif
// <o> Sample Rate
// <0x0=>16x arithmetic
// <0x1=>16x fractional
// <0x2=>8x arithmetic
// <0x3=>8x fractional
// <0x4=>3x arithmetic
// <i> How many over-sampling bits used when sampling data state
// <id> usart_arch_sampr
#ifndef CONF_SERCOM_2_USART_SAMPR
#define CONF_SERCOM_2_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
#ifndef CONF_SERCOM_2_USART_SAMPA
#define CONF_SERCOM_2_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
// <0=>MSB is transmitted first
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
#ifndef CONF_SERCOM_2_USART_DORD
#define CONF_SERCOM_2_USART_DORD 1
#endif
// Does not do anything in UART mode
#define CONF_SERCOM_2_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
#ifndef CONF_SERCOM_2_USART_ENC
#define CONF_SERCOM_2_USART_ENC 0
#endif
// <o> LIN Slave Enable
// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
// <0=>Disable
// <1=>Enable
// <id> usart_arch_lin_slave_enable
#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_2_USART_INACK
#define CONF_SERCOM_2_USART_INACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_DSNACK
#define CONF_SERCOM_2_USART_DSNACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_MAXITER
#define CONF_SERCOM_2_USART_MAXITER 0x7
#endif
#ifndef CONF_SERCOM_2_USART_GTIME
#define CONF_SERCOM_2_USART_GTIME 0x2
#endif
#define CONF_SERCOM_2_USART_RXINV 0x0
#define CONF_SERCOM_2_USART_TXINV 0x0
#ifndef CONF_SERCOM_2_USART_CMODE
#define CONF_SERCOM_2_USART_CMODE 0
#endif
#ifndef CONF_SERCOM_2_USART_RXPO
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
#endif
#ifndef CONF_SERCOM_2_USART_TXPO
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 4
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 5
#endif
#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 0
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 1
#endif
#endif
// Calculate BAUD register value in UART mode
#if CONF_SERCOM_2_USART_SAMPR == 0
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 1
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 2
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 3
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 4
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_3_I2CM_ENABLE
#define CONF_SERCOM_3_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_3_I2CM_BAUD
#define CONF_SERCOM_3_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN
#define CONF_SERCOM_3_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN
#define CONF_SERCOM_3_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_3_I2CM_LOWTOUT
#define CONF_SERCOM_3_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_3_I2CM_INACTOUT
#define CONF_SERCOM_3_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_3_I2CM_SDAHOLD
#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY
#define CONF_SERCOM_3_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_3_I2CM_SPEED
#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_3_I2CM_TRISE
#define CONF_SERCOM_3_I2CM_TRISE 215U
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \
- (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \
/ 1000U)) \
* 10U \
+ 5U) \
/ (CONF_SERCOM_3_I2CM_BAUD * 10U))
#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE
#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_3_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_3_I2CM_BAUD_RATE \
((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

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/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 1
#endif
#include "peripheral_clk_config.h"
// <h> Basic configuration
// <o> Prescaler
// <0x0=> No division
// <0x1=> Divide by 2
// <0x2=> Divide by 4
// <0x3=> Divide by 8
// <0x4=> Divide by 16
// <0x5=> Divide by 64
// <0x6=> Divide by 256
// <0x7=> Divide by 1024
// <i> This defines the prescaler value
// <id> timer_prescaler
#ifndef CONF_TC0_PRESCALER
#define CONF_TC0_PRESCALER 0x3
#endif
// <o> Length of one timer tick in uS <0-4294967295>
// <id> timer_tick
#ifndef CONF_TC0_TIMER_TICK
#define CONF_TC0_TIMER_TICK 1000
#endif
// </h>
// <e> Advanced configuration
// <id> timer_advanced_configuration
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC0_PRESCSYNC
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <q> Run in standby
// <i> Indicates whether the module will continue to run in standby sleep mode
// <id> tc_arch_runstdby
#ifndef CONF_TC0_RUNSTDBY
#define CONF_TC0_RUNSTDBY 0
#endif
// <q> Run in debug mode
// <i> Indicates whether the module will run in debug mode
// <id> tc_arch_dbgrun
#ifndef CONF_TC0_DBGRUN
#define CONF_TC0_DBGRUN 0
#endif
// <q> Run on demand
// <i> Run if requested by some other peripheral in the device
// <id> tc_arch_ondemand
#ifndef CONF_TC0_ONDEMAND
#define CONF_TC0_ONDEMAND 0
#endif
// </e>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
#endif
// <q> Output Event On Match or Capture on Channel 0
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo0
#ifndef CONF_TC0_MCEO0
#define CONF_TC0_MCEO0 0
#endif
// <q> Output Event On Match or Capture on Channel 1
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo1
#ifndef CONF_TC0_MCEO1
#define CONF_TC0_MCEO1 0
#endif
// <q> Output Event On Timer Tick
// <i> Enable output of event on timer tick
// <id> tc_arch_ovfeo
#ifndef CONF_TC0_OVFEO
#define CONF_TC0_OVFEO 0
#endif
// <q> Event Input
// <i> Enable asynchronous input events
// <id> tc_arch_tcei
#ifndef CONF_TC0_TCEI
#define CONF_TC0_TCEI 0
#endif
// <q> Inverted Event Input
// <i> Invert the asynchronous input events
// <id> tc_arch_tcinv
#ifndef CONF_TC0_TCINV
#define CONF_TC0_TCINV 0
#endif
// <o> Event action
// <0=> Event action disabled
// <1=> Start, restart or re-trigger TC on event
// <2=> Count on event
// <3=> Start on event
// <4=> Time stamp capture
// <5=> Period captured in CC0, pulse width in CC1
// <6=> Period captured in CC1, pulse width in CC0
// <7=> Pulse width capture
// <i> Event which will be performed on an event
//<id> tc_arch_evact
#ifndef CONF_TC0_EVACT
#define CONF_TC0_EVACT 0
#endif
// </e>
// Default values which the driver needs in order to work correctly
// Mode set to 32-bit
#ifndef CONF_TC0_MODE
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
#endif
// CC 1 register set to 0
#ifndef CONF_TC0_CC1
#define CONF_TC0_CC1 0
#endif
#ifndef CONF_TC0_ALOCK
#define CONF_TC0_ALOCK 0
#endif
// Not used in 32-bit mode
#define CONF_TC0_PER 0
// Calculating correct top value based on requested tick interval.
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
// Prescaler set to 64
#if CONF_TC0_PRESCALER > 0x4
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 64
#endif
// Prescaler set to 256
#if CONF_TC0_PRESCALER > 0x5
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 256
#endif
// Prescaler set to 1024
#if CONF_TC0_PRESCALER > 0x6
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 1024
#endif
#ifndef CONF_TC0_CC0
#define CONF_TC0_CC0 \
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
#endif
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H

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software/firmware/oracle_e54_edition/config/peripheral_clk_config.h
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/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> EIC Clock Source
// <id> eic_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for EIC.
#ifndef CONF_GCLK_EIC_SRC
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_EIC_FREQUENCY
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 119997440
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 119997440
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
* \brief SERCOM2's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM3_CORE_SRC
#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
* \brief SERCOM3's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440
#endif
/**
* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
* \brief SERCOM3's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC0_SRC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC0_FREQUENCY
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 119997440
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

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software/firmware/oracle_e54_edition/driver_init.c
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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
/*! The buffer size for USART */
#define USART_0_BUFFER_SIZE 16
struct usart_async_descriptor USART_0;
struct timer_descriptor TIMER_0;
static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE];
struct i2c_m_sync_desc I2C_0;
void EXTERNAL_IRQ_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
ext_irq_init();
}
/**
* \brief USART Clock initialization function
*
* Enables register interface and peripheral clock
*/
void USART_0_CLOCK_init()
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
/**
* \brief USART pinmux initialization function
*
* Set each required pin to USART functionality
*/
void USART_0_PORT_init()
{
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
/**
* \brief USART initialization function
*
* Enables USART peripheral, clocks and initializes USART driver
*/
void USART_0_init(void)
{
USART_0_CLOCK_init();
usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL);
USART_0_PORT_init();
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_pull_mode(PA22,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0);
gpio_set_pin_pull_mode(PA23,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1);
}
void I2C_0_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, SERCOM3);
I2C_0_PORT_init();
}
/**
* \brief Timer initialization function
*
* Enables Timer peripheral, clocks and initializes Timer driver
*/
static void TIMER_0_init(void)
{
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
timer_init(&TIMER_0, TC0, _tc_get_timer());
}
void system_init(void)
{
init_mcu();
EXTERNAL_IRQ_0_init();
USART_0_init();
I2C_0_init();
TIMER_0_init();
}

469
software/firmware/oracle_e54_edition/driver_init.d
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driver_init.d driver_init.o: driver_init.c driver_init.h \
atmel_start_pins.h hal/include/hal_gpio.h hal/include/hpl_gpio.h \
hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
hal/utils/include/parts.h include/same54.h include/same54p20a.h \
CMSIS/Core/Include/core_cm4.h CMSIS/Core/Include/cmsis_version.h \
CMSIS/Core/Include/cmsis_compiler.h CMSIS/Core/Include/cmsis_gcc.h \
CMSIS/Core/Include/mpu_armv7.h include/system_same54.h \
include/component/ac.h include/component/adc.h include/component/aes.h \
include/component/can.h include/component/ccl.h include/component/cmcc.h \
include/component/dac.h include/component/dmac.h include/component/dsu.h \
include/component/eic.h include/component/evsys.h \
include/component/freqm.h include/component/gclk.h \
include/component/gmac.h include/component/hmatrixb.h \
include/component/icm.h include/component/i2s.h include/component/mclk.h \
include/component/nvmctrl.h include/component/oscctrl.h \
include/component/osc32kctrl.h include/component/pac.h \
include/component/pcc.h include/component/pdec.h include/component/pm.h \
include/component/port.h include/component/qspi.h \
include/component/ramecc.h include/component/rstc.h \
include/component/rtc.h include/component/sdhc.h \
include/component/sercom.h include/component/supc.h \
include/component/tc.h include/component/tcc.h include/component/trng.h \
include/component/usb.h include/component/wdt.h include/instance/ac.h \
include/instance/adc0.h include/instance/adc1.h include/instance/aes.h \
include/instance/can0.h include/instance/can1.h include/instance/ccl.h \
include/instance/cmcc.h include/instance/dac.h include/instance/dmac.h \
include/instance/dsu.h include/instance/eic.h include/instance/evsys.h \
include/instance/freqm.h include/instance/gclk.h include/instance/gmac.h \
include/instance/hmatrix.h include/instance/icm.h include/instance/i2s.h \
include/instance/mclk.h include/instance/nvmctrl.h \
include/instance/oscctrl.h include/instance/osc32kctrl.h \
include/instance/pac.h include/instance/pcc.h include/instance/pdec.h \
include/instance/pm.h include/instance/port.h include/instance/pukcc.h \
include/instance/qspi.h include/instance/ramecc.h \
include/instance/rstc.h include/instance/rtc.h include/instance/sdhc0.h \
include/instance/sdhc1.h include/instance/sercom0.h \
include/instance/sercom1.h include/instance/sercom2.h \
include/instance/sercom3.h include/instance/sercom4.h \
include/instance/sercom5.h include/instance/sercom6.h \
include/instance/sercom7.h include/instance/supc.h \
include/instance/tc0.h include/instance/tc1.h include/instance/tc2.h \
include/instance/tc3.h include/instance/tc4.h include/instance/tc5.h \
include/instance/tc6.h include/instance/tc7.h include/instance/tcc0.h \
include/instance/tcc1.h include/instance/tcc2.h include/instance/tcc3.h \
include/instance/tcc4.h include/instance/trng.h include/instance/usb.h \
include/instance/wdt.h include/pio/same54p20a.h hri/hri_e54.h \
include/sam.h hri/hri_ac_e54.h hal/include/hal_atomic.h \
hri/hri_adc_e54.h hri/hri_aes_e54.h hri/hri_can_e54.h hri/hri_ccl_e54.h \
hri/hri_cmcc_e54.h hri/hri_dac_e54.h hri/hri_dmac_e54.h \
hri/hri_dsu_e54.h hri/hri_eic_e54.h hri/hri_evsys_e54.h \
hri/hri_freqm_e54.h hri/hri_gclk_e54.h hri/hri_gmac_e54.h \
hri/hri_hmatrixb_e54.h hri/hri_i2s_e54.h hri/hri_icm_e54.h \
hri/hri_mclk_e54.h hri/hri_nvmctrl_e54.h hri/hri_osc32kctrl_e54.h \
hri/hri_oscctrl_e54.h hri/hri_pac_e54.h hri/hri_pcc_e54.h \
hri/hri_pdec_e54.h hri/hri_pm_e54.h hri/hri_port_e54.h \
hri/hri_qspi_e54.h hri/hri_ramecc_e54.h hri/hri_rstc_e54.h \
hri/hri_rtc_e54.h hri/hri_sdhc_e54.h hri/hri_sercom_e54.h \
hri/hri_supc_e54.h hri/hri_tc_e54.h hri/hri_tcc_e54.h hri/hri_trng_e54.h \
hri/hri_usb_e54.h hri/hri_wdt_e54.h hal/utils/include/err_codes.h \
hpl/port/hpl_gpio_base.h hal/utils/include/utils_assert.h \
config/hpl_port_config.h hal/include/hal_delay.h hal/include/hpl_irq.h \
hal/include/hpl_reset.h hal/include/hpl_sleep.h hal/include/hal_init.h \
hal/include/hpl_init.h hal/include/hal_io.h hal/include/hal_sleep.h \
hal/include/hal_ext_irq.h hal/include/hpl_ext_irq.h \
hal/include/hal_usart_async.h hal/include/hal_io.h \
hal/include/hpl_usart_async.h hal/include/hpl_usart.h \
hal/include/hpl_irq.h hal/utils/include/utils_ringbuffer.h \
hal/utils/include/compiler.h hal/utils/include/utils_assert.h \
hal/include/hal_i2c_m_sync.h hal/include/hpl_i2c_m_sync.h \
hal/include/hal_timer.h hal/utils/include/utils_list.h \
hal/include/hpl_timer.h hpl/tc/hpl_tc_base.h hal/include/hpl_pwm.h \
config/peripheral_clk_config.h hal/utils/include/utils.h
driver_init.h:
atmel_start_pins.h:
hal/include/hal_gpio.h:
hal/include/hpl_gpio.h:
hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
hal/utils/include/parts.h:
include/same54.h:
include/same54p20a.h:
CMSIS/Core/Include/core_cm4.h:
CMSIS/Core/Include/cmsis_version.h:
CMSIS/Core/Include/cmsis_compiler.h:
CMSIS/Core/Include/cmsis_gcc.h:
CMSIS/Core/Include/mpu_armv7.h:
include/system_same54.h:
include/component/ac.h:
include/component/adc.h:
include/component/aes.h:
include/component/can.h:
include/component/ccl.h:
include/component/cmcc.h:
include/component/dac.h:
include/component/dmac.h:
include/component/dsu.h:
include/component/eic.h:
include/component/evsys.h:
include/component/freqm.h:
include/component/gclk.h:
include/component/gmac.h:
include/component/hmatrixb.h:
include/component/icm.h:
include/component/i2s.h:
include/component/mclk.h:
include/component/nvmctrl.h:
include/component/oscctrl.h:
include/component/osc32kctrl.h:
include/component/pac.h:
include/component/pcc.h:
include/component/pdec.h:
include/component/pm.h:
include/component/port.h:
include/component/qspi.h:
include/component/ramecc.h:
include/component/rstc.h:
include/component/rtc.h:
include/component/sdhc.h:
include/component/sercom.h:
include/component/supc.h:
include/component/tc.h:
include/component/tcc.h:
include/component/trng.h:
include/component/usb.h:
include/component/wdt.h:
include/instance/ac.h:
include/instance/adc0.h:
include/instance/adc1.h:
include/instance/aes.h:
include/instance/can0.h:
include/instance/can1.h:
include/instance/ccl.h:
include/instance/cmcc.h:
include/instance/dac.h:
include/instance/dmac.h:
include/instance/dsu.h:
include/instance/eic.h:
include/instance/evsys.h:
include/instance/freqm.h:
include/instance/gclk.h:
include/instance/gmac.h:
include/instance/hmatrix.h:
include/instance/icm.h:
include/instance/i2s.h:
include/instance/mclk.h:
include/instance/nvmctrl.h:
include/instance/oscctrl.h:
include/instance/osc32kctrl.h:
include/instance/pac.h:
include/instance/pcc.h:
include/instance/pdec.h:
include/instance/pm.h:
include/instance/port.h:
include/instance/pukcc.h:
include/instance/qspi.h:
include/instance/ramecc.h:
include/instance/rstc.h:
include/instance/rtc.h:
include/instance/sdhc0.h:
include/instance/sdhc1.h:
include/instance/sercom0.h:
include/instance/sercom1.h:
include/instance/sercom2.h:
include/instance/sercom3.h:
include/instance/sercom4.h:
include/instance/sercom5.h:
include/instance/sercom6.h:
include/instance/sercom7.h:
include/instance/supc.h:
include/instance/tc0.h:
include/instance/tc1.h:
include/instance/tc2.h:
include/instance/tc3.h:
include/instance/tc4.h:
include/instance/tc5.h:
include/instance/tc6.h:
include/instance/tc7.h:
include/instance/tcc0.h:
include/instance/tcc1.h:
include/instance/tcc2.h:
include/instance/tcc3.h:
include/instance/tcc4.h:
include/instance/trng.h:
include/instance/usb.h:
include/instance/wdt.h:
include/pio/same54p20a.h:
hri/hri_e54.h:
include/sam.h:
hri/hri_ac_e54.h:
hal/include/hal_atomic.h:
hri/hri_adc_e54.h:
hri/hri_aes_e54.h:
hri/hri_can_e54.h:
hri/hri_ccl_e54.h:
hri/hri_cmcc_e54.h:
hri/hri_dac_e54.h:
hri/hri_dmac_e54.h:
hri/hri_dsu_e54.h:
hri/hri_eic_e54.h:
hri/hri_evsys_e54.h:
hri/hri_freqm_e54.h:
hri/hri_gclk_e54.h:
hri/hri_gmac_e54.h:
hri/hri_hmatrixb_e54.h:
hri/hri_i2s_e54.h:
hri/hri_icm_e54.h:
hri/hri_mclk_e54.h:
hri/hri_nvmctrl_e54.h:
hri/hri_osc32kctrl_e54.h:
hri/hri_oscctrl_e54.h:
hri/hri_pac_e54.h:
hri/hri_pcc_e54.h:
hri/hri_pdec_e54.h:
hri/hri_pm_e54.h:
hri/hri_port_e54.h:
hri/hri_qspi_e54.h:
hri/hri_ramecc_e54.h:
hri/hri_rstc_e54.h:
hri/hri_rtc_e54.h:
hri/hri_sdhc_e54.h:
hri/hri_sercom_e54.h:
hri/hri_supc_e54.h:
hri/hri_tc_e54.h:
hri/hri_tcc_e54.h:
hri/hri_trng_e54.h:
hri/hri_usb_e54.h:
hri/hri_wdt_e54.h:
hal/utils/include/err_codes.h:
hpl/port/hpl_gpio_base.h:
hal/utils/include/utils_assert.h:
config/hpl_port_config.h:
hal/include/hal_delay.h:
hal/include/hpl_irq.h:
hal/include/hpl_reset.h:
hal/include/hpl_sleep.h:
hal/include/hal_init.h:
hal/include/hpl_init.h:
hal/include/hal_io.h:
hal/include/hal_sleep.h:
hal/include/hal_ext_irq.h:
hal/include/hpl_ext_irq.h:
hal/include/hal_usart_async.h:
hal/include/hal_io.h:
hal/include/hpl_usart_async.h:
hal/include/hpl_usart.h:
hal/include/hpl_irq.h:
hal/utils/include/utils_ringbuffer.h:
hal/utils/include/compiler.h:
hal/utils/include/utils_assert.h:
hal/include/hal_i2c_m_sync.h:
hal/include/hpl_i2c_m_sync.h:
hal/include/hal_timer.h:
hal/utils/include/utils_list.h:
hal/include/hpl_timer.h:
hpl/tc/hpl_tc_base.h:
hal/include/hpl_pwm.h:
config/peripheral_clk_config.h:
hal/utils/include/utils.h:

54
software/firmware/oracle_e54_edition/driver_init.h
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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_ext_irq.h>
#include <hal_usart_async.h>
#include <hal_i2c_m_sync.h>
#include <hal_timer.h>
#include <hpl_tc_base.h>
extern struct usart_async_descriptor USART_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct timer_descriptor TIMER_0;
void USART_0_PORT_init(void);
void USART_0_CLOCK_init(void);
void USART_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED

BIN
software/firmware/oracle_e54_edition/driver_init.o
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84
software/firmware/oracle_e54_edition/examples/driver_examples.c
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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using EXTERNAL_IRQ_0
*/
void EXTERNAL_IRQ_0_example(void)
{
}
/**
* Example of using USART_0 to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_USART_0[12] = "Hello World!";
static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr)
{
/* Transfer completed */
}
void USART_0_example(void)
{
struct io_descriptor *io;
usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0);
/*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb);
usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/
usart_async_get_io_descriptor(&USART_0, &io);
usart_async_enable(&USART_0);
io_write(io, example_USART_0, 12);
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
static struct timer_task TIMER_0_task1, TIMER_0_task2;
/**
* Example of using TIMER_0.
*/
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
{
}
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
{
}
void TIMER_0_example(void)
{
TIMER_0_task1.interval = 100;
TIMER_0_task1.cb = TIMER_0_task1_cb;
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
TIMER_0_task2.interval = 200;
TIMER_0_task2.cb = TIMER_0_task2_cb;
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
timer_add_task(&TIMER_0, &TIMER_0_task1);
timer_add_task(&TIMER_0, &TIMER_0_task2);
timer_start(&TIMER_0);
}

470
software/firmware/oracle_e54_edition/examples/driver_examples.d
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examples/driver_examples.d examples/driver_examples.o: \
examples/driver_examples.c examples/driver_examples.h driver_init.h \
atmel_start_pins.h hal/include/hal_gpio.h hal/include/hpl_gpio.h \
hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
hal/utils/include/parts.h include/same54.h include/same54p20a.h \
CMSIS/Core/Include/core_cm4.h CMSIS/Core/Include/cmsis_version.h \
CMSIS/Core/Include/cmsis_compiler.h CMSIS/Core/Include/cmsis_gcc.h \
CMSIS/Core/Include/mpu_armv7.h include/system_same54.h \
include/component/ac.h include/component/adc.h include/component/aes.h \
include/component/can.h include/component/ccl.h include/component/cmcc.h \
include/component/dac.h include/component/dmac.h include/component/dsu.h \
include/component/eic.h include/component/evsys.h \
include/component/freqm.h include/component/gclk.h \
include/component/gmac.h include/component/hmatrixb.h \
include/component/icm.h include/component/i2s.h include/component/mclk.h \
include/component/nvmctrl.h include/component/oscctrl.h \
include/component/osc32kctrl.h include/component/pac.h \
include/component/pcc.h include/component/pdec.h include/component/pm.h \
include/component/port.h include/component/qspi.h \
include/component/ramecc.h include/component/rstc.h \
include/component/rtc.h include/component/sdhc.h \
include/component/sercom.h include/component/supc.h \
include/component/tc.h include/component/tcc.h include/component/trng.h \
include/component/usb.h include/component/wdt.h include/instance/ac.h \
include/instance/adc0.h include/instance/adc1.h include/instance/aes.h \
include/instance/can0.h include/instance/can1.h include/instance/ccl.h \
include/instance/cmcc.h include/instance/dac.h include/instance/dmac.h \
include/instance/dsu.h include/instance/eic.h include/instance/evsys.h \
include/instance/freqm.h include/instance/gclk.h include/instance/gmac.h \
include/instance/hmatrix.h include/instance/icm.h include/instance/i2s.h \
include/instance/mclk.h include/instance/nvmctrl.h \
include/instance/oscctrl.h include/instance/osc32kctrl.h \
include/instance/pac.h include/instance/pcc.h include/instance/pdec.h \
include/instance/pm.h include/instance/port.h include/instance/pukcc.h \
include/instance/qspi.h include/instance/ramecc.h \
include/instance/rstc.h include/instance/rtc.h include/instance/sdhc0.h \
include/instance/sdhc1.h include/instance/sercom0.h \
include/instance/sercom1.h include/instance/sercom2.h \
include/instance/sercom3.h include/instance/sercom4.h \
include/instance/sercom5.h include/instance/sercom6.h \
include/instance/sercom7.h include/instance/supc.h \
include/instance/tc0.h include/instance/tc1.h include/instance/tc2.h \
include/instance/tc3.h include/instance/tc4.h include/instance/tc5.h \
include/instance/tc6.h include/instance/tc7.h include/instance/tcc0.h \
include/instance/tcc1.h include/instance/tcc2.h include/instance/tcc3.h \
include/instance/tcc4.h include/instance/trng.h include/instance/usb.h \
include/instance/wdt.h include/pio/same54p20a.h hri/hri_e54.h \
include/sam.h hri/hri_ac_e54.h hal/include/hal_atomic.h \
hri/hri_adc_e54.h hri/hri_aes_e54.h hri/hri_can_e54.h hri/hri_ccl_e54.h \
hri/hri_cmcc_e54.h hri/hri_dac_e54.h hri/hri_dmac_e54.h \
hri/hri_dsu_e54.h hri/hri_eic_e54.h hri/hri_evsys_e54.h \
hri/hri_freqm_e54.h hri/hri_gclk_e54.h hri/hri_gmac_e54.h \
hri/hri_hmatrixb_e54.h hri/hri_i2s_e54.h hri/hri_icm_e54.h \
hri/hri_mclk_e54.h hri/hri_nvmctrl_e54.h hri/hri_osc32kctrl_e54.h \
hri/hri_oscctrl_e54.h hri/hri_pac_e54.h hri/hri_pcc_e54.h \
hri/hri_pdec_e54.h hri/hri_pm_e54.h hri/hri_port_e54.h \
hri/hri_qspi_e54.h hri/hri_ramecc_e54.h hri/hri_rstc_e54.h \
hri/hri_rtc_e54.h hri/hri_sdhc_e54.h hri/hri_sercom_e54.h \
hri/hri_supc_e54.h hri/hri_tc_e54.h hri/hri_tcc_e54.h hri/hri_trng_e54.h \
hri/hri_usb_e54.h hri/hri_wdt_e54.h hal/utils/include/err_codes.h \
hpl/port/hpl_gpio_base.h hal/utils/include/utils_assert.h \
config/hpl_port_config.h hal/include/hal_delay.h hal/include/hpl_irq.h \
hal/include/hpl_reset.h hal/include/hpl_sleep.h hal/include/hal_init.h \
hal/include/hpl_init.h hal/include/hal_io.h hal/include/hal_sleep.h \
hal/include/hal_ext_irq.h hal/include/hpl_ext_irq.h \
hal/include/hal_usart_async.h hal/include/hal_io.h \
hal/include/hpl_usart_async.h hal/include/hpl_usart.h \
hal/include/hpl_irq.h hal/utils/include/utils_ringbuffer.h \
hal/utils/include/compiler.h hal/utils/include/utils_assert.h \
hal/include/hal_i2c_m_sync.h hal/include/hpl_i2c_m_sync.h \
hal/include/hal_timer.h hal/utils/include/utils_list.h \
hal/include/hpl_timer.h hpl/tc/hpl_tc_base.h hal/include/hpl_pwm.h \
hal/utils/include/utils.h
examples/driver_examples.h:
driver_init.h:
atmel_start_pins.h:
hal/include/hal_gpio.h:
hal/include/hpl_gpio.h:
hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
hal/utils/include/parts.h:
include/same54.h:
include/same54p20a.h:
CMSIS/Core/Include/core_cm4.h:
CMSIS/Core/Include/cmsis_version.h:
CMSIS/Core/Include/cmsis_compiler.h:
CMSIS/Core/Include/cmsis_gcc.h:
CMSIS/Core/Include/mpu_armv7.h:
include/system_same54.h:
include/component/ac.h:
include/component/adc.h:
include/component/aes.h:
include/component/can.h:
include/component/ccl.h:
include/component/cmcc.h:
include/component/dac.h:
include/component/dmac.h:
include/component/dsu.h:
include/component/eic.h:
include/component/evsys.h:
include/component/freqm.h:
include/component/gclk.h:
include/component/gmac.h:
include/component/hmatrixb.h:
include/component/icm.h:
include/component/i2s.h:
include/component/mclk.h:
include/component/nvmctrl.h:
include/component/oscctrl.h:
include/component/osc32kctrl.h:
include/component/pac.h:
include/component/pcc.h:
include/component/pdec.h:
include/component/pm.h:
include/component/port.h:
include/component/qspi.h:
include/component/ramecc.h:
include/component/rstc.h:
include/component/rtc.h:
include/component/sdhc.h:
include/component/sercom.h:
include/component/supc.h:
include/component/tc.h:
include/component/tcc.h:
include/component/trng.h:
include/component/usb.h:
include/component/wdt.h:
include/instance/ac.h:
include/instance/adc0.h:
include/instance/adc1.h:
include/instance/aes.h:
include/instance/can0.h:
include/instance/can1.h:
include/instance/ccl.h:
include/instance/cmcc.h:
include/instance/dac.h:
include/instance/dmac.h:
include/instance/dsu.h:
include/instance/eic.h:
include/instance/evsys.h:
include/instance/freqm.h:
include/instance/gclk.h:
include/instance/gmac.h:
include/instance/hmatrix.h:
include/instance/icm.h:
include/instance/i2s.h:
include/instance/mclk.h:
include/instance/nvmctrl.h:
include/instance/oscctrl.h:
include/instance/osc32kctrl.h:
include/instance/pac.h:
include/instance/pcc.h:
include/instance/pdec.h:
include/instance/pm.h:
include/instance/port.h:
include/instance/pukcc.h:
include/instance/qspi.h:
include/instance/ramecc.h:
include/instance/rstc.h:
include/instance/rtc.h:
include/instance/sdhc0.h:
include/instance/sdhc1.h:
include/instance/sercom0.h:
include/instance/sercom1.h:
include/instance/sercom2.h:
include/instance/sercom3.h:
include/instance/sercom4.h:
include/instance/sercom5.h:
include/instance/sercom6.h:
include/instance/sercom7.h:
include/instance/supc.h:
include/instance/tc0.h:
include/instance/tc1.h:
include/instance/tc2.h:
include/instance/tc3.h:
include/instance/tc4.h:
include/instance/tc5.h:
include/instance/tc6.h:
include/instance/tc7.h:
include/instance/tcc0.h:
include/instance/tcc1.h:
include/instance/tcc2.h:
include/instance/tcc3.h:
include/instance/tcc4.h:
include/instance/trng.h:
include/instance/usb.h:
include/instance/wdt.h:
include/pio/same54p20a.h:
hri/hri_e54.h:
include/sam.h:
hri/hri_ac_e54.h:
hal/include/hal_atomic.h:
hri/hri_adc_e54.h:
hri/hri_aes_e54.h:
hri/hri_can_e54.h:
hri/hri_ccl_e54.h:
hri/hri_cmcc_e54.h:
hri/hri_dac_e54.h:
hri/hri_dmac_e54.h:
hri/hri_dsu_e54.h:
hri/hri_eic_e54.h:
hri/hri_evsys_e54.h:
hri/hri_freqm_e54.h:
hri/hri_gclk_e54.h:
hri/hri_gmac_e54.h:
hri/hri_hmatrixb_e54.h:
hri/hri_i2s_e54.h:
hri/hri_icm_e54.h:
hri/hri_mclk_e54.h:
hri/hri_nvmctrl_e54.h:
hri/hri_osc32kctrl_e54.h:
hri/hri_oscctrl_e54.h:
hri/hri_pac_e54.h:
hri/hri_pcc_e54.h:
hri/hri_pdec_e54.h:
hri/hri_pm_e54.h:
hri/hri_port_e54.h:
hri/hri_qspi_e54.h:
hri/hri_ramecc_e54.h:
hri/hri_rstc_e54.h:
hri/hri_rtc_e54.h:
hri/hri_sdhc_e54.h:
hri/hri_sercom_e54.h:
hri/hri_supc_e54.h:
hri/hri_tc_e54.h:
hri/hri_tcc_e54.h:
hri/hri_trng_e54.h:
hri/hri_usb_e54.h:
hri/hri_wdt_e54.h:
hal/utils/include/err_codes.h:
hpl/port/hpl_gpio_base.h:
hal/utils/include/utils_assert.h:
config/hpl_port_config.h:
hal/include/hal_delay.h:
hal/include/hpl_irq.h:
hal/include/hpl_reset.h:
hal/include/hpl_sleep.h:
hal/include/hal_init.h:
hal/include/hpl_init.h:
hal/include/hal_io.h:
hal/include/hal_sleep.h:
hal/include/hal_ext_irq.h:
hal/include/hpl_ext_irq.h:
hal/include/hal_usart_async.h:
hal/include/hal_io.h:
hal/include/hpl_usart_async.h:
hal/include/hpl_usart.h:
hal/include/hpl_irq.h:
hal/utils/include/utils_ringbuffer.h:
hal/utils/include/compiler.h:
hal/utils/include/utils_assert.h:
hal/include/hal_i2c_m_sync.h:
hal/include/hpl_i2c_m_sync.h:
hal/include/hal_timer.h:
hal/utils/include/utils_list.h:
hal/include/hpl_timer.h:
hpl/tc/hpl_tc_base.h:
hal/include/hpl_pwm.h:
hal/utils/include/utils.h:

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void EXTERNAL_IRQ_0_example(void);
void USART_0_example(void);
void I2C_0_example(void);
void TIMER_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED

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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
ifdef SystemRoot
SHELL = cmd.exe
MK_DIR = mkdir
else
ifeq ($(shell uname), Linux)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), DARWIN)
MK_DIR = mkdir -p
endif
endif
# List the subdirectories for creating object files
SUB_DIRS += \
\
hpl/pm \
hpl/tc \
hpl/osc32kctrl \
hpl/ramecc \
hpl/dmac \
hal/src \
gcc \
hpl/mclk \
hpl/eic \
hpl/sercom \
examples \
hpl/gclk \
hpl/oscctrl \
hal/utils/src \
gcc/gcc \
hpl/core \
hpl/cmcc
# List the object files
OBJS += \
hal/src/hal_io.o \
hpl/eic/hpl_eic.o \
hpl/core/hpl_core_m4.o \
hal/utils/src/utils_syscalls.o \
hal/src/hal_timer.o \
gcc/system_same54.o \
hal/src/hal_i2c_m_sync.o \
hal/src/hal_delay.o \
hpl/pm/hpl_pm.o \
hpl/core/hpl_init.o \
hpl/ramecc/hpl_ramecc.o \
hal/utils/src/utils_list.o \
hal/utils/src/utils_assert.o \
hpl/dmac/hpl_dmac.o \
hpl/oscctrl/hpl_oscctrl.o \
hpl/mclk/hpl_mclk.o \
hpl/sercom/hpl_sercom.o \
hpl/gclk/hpl_gclk.o \
hal/src/hal_init.o \
gcc/gcc/startup_same54.o \
main.o \
hpl/osc32kctrl/hpl_osc32kctrl.o \
examples/driver_examples.o \
driver_init.o \
hal/src/hal_usart_async.o \
hal/src/hal_ext_irq.o \
hal/utils/src/utils_ringbuffer.o \
hal/src/hal_gpio.o \
hal/utils/src/utils_event.o \
hal/src/hal_sleep.o \
hal/src/hal_cache.o \
hpl/cmcc/hpl_cmcc.o \
atmel_start.o \
hpl/tc/hpl_tc.o \
hal/src/hal_atomic.o
OBJS_AS_ARGS += \
"hal/src/hal_io.o" \
"hpl/eic/hpl_eic.o" \
"hpl/core/hpl_core_m4.o" \
"hal/utils/src/utils_syscalls.o" \
"hal/src/hal_timer.o" \
"gcc/system_same54.o" \
"hal/src/hal_i2c_m_sync.o" \
"hal/src/hal_delay.o" \
"hpl/pm/hpl_pm.o" \
"hpl/core/hpl_init.o" \
"hpl/ramecc/hpl_ramecc.o" \
"hal/utils/src/utils_list.o" \
"hal/utils/src/utils_assert.o" \
"hpl/dmac/hpl_dmac.o" \
"hpl/oscctrl/hpl_oscctrl.o" \
"hpl/mclk/hpl_mclk.o" \
"hpl/sercom/hpl_sercom.o" \
"hpl/gclk/hpl_gclk.o" \
"hal/src/hal_init.o" \
"gcc/gcc/startup_same54.o" \
"main.o" \
"hpl/osc32kctrl/hpl_osc32kctrl.o" \
"examples/driver_examples.o" \
"driver_init.o" \
"hal/src/hal_usart_async.o" \
"hal/src/hal_ext_irq.o" \
"hal/utils/src/utils_ringbuffer.o" \
"hal/src/hal_gpio.o" \
"hal/utils/src/utils_event.o" \
"hal/src/hal_sleep.o" \
"hal/src/hal_cache.o" \
"hpl/cmcc/hpl_cmcc.o" \
"atmel_start.o" \
"hpl/tc/hpl_tc.o" \
"hal/src/hal_atomic.o"
# List the directories containing header files
DIR_INCLUDES += \
-I"../" \
-I"../config" \
-I"../examples" \
-I"../hal/include" \
-I"../hal/utils/include" \
-I"../hpl/cmcc" \
-I"../hpl/core" \
-I"../hpl/dmac" \
-I"../hpl/eic" \
-I"../hpl/gclk" \
-I"../hpl/mclk" \
-I"../hpl/osc32kctrl" \
-I"../hpl/oscctrl" \
-I"../hpl/pm" \
-I"../hpl/port" \
-I"../hpl/ramecc" \
-I"../hpl/sercom" \
-I"../hpl/tc" \
-I"../hri" \
-I"../" \
-I"../CMSIS/Core/Include" \
-I"../include"
# List the dependency files
DEPS := $(OBJS:%.o=%.d)
DEPS_AS_ARGS += \
"hal/utils/src/utils_event.d" \
"hal/src/hal_io.d" \
"hpl/ramecc/hpl_ramecc.d" \
"hpl/core/hpl_core_m4.d" \
"hpl/eic/hpl_eic.d" \
"hal/utils/src/utils_syscalls.d" \
"hal/src/hal_i2c_m_sync.d" \
"hal/src/hal_timer.d" \
"hal/utils/src/utils_list.d" \
"hpl/cmcc/hpl_cmcc.d" \
"hpl/dmac/hpl_dmac.d" \
"hal/utils/src/utils_assert.d" \
"hal/src/hal_delay.d" \
"hpl/core/hpl_init.d" \
"hpl/pm/hpl_pm.d" \
"hpl/gclk/hpl_gclk.d" \
"hpl/sercom/hpl_sercom.d" \
"gcc/gcc/startup_same54.d" \
"hal/src/hal_init.d" \
"hpl/mclk/hpl_mclk.d" \
"driver_init.d" \
"hal/src/hal_usart_async.d" \
"hpl/osc32kctrl/hpl_osc32kctrl.d" \
"main.d" \
"examples/driver_examples.d" \
"hal/src/hal_cache.d" \
"hal/src/hal_sleep.d" \
"hal/utils/src/utils_ringbuffer.d" \
"hal/src/hal_ext_irq.d" \
"hal/src/hal_gpio.d" \
"hal/src/hal_atomic.d" \
"hpl/tc/hpl_tc.d" \
"hpl/oscctrl/hpl_oscctrl.d" \
"gcc/system_same54.d" \
"atmel_start.d"
OUTPUT_FILE_NAME :=AtmelStart
QUOTE := "
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
vpath %.c ../
vpath %.s ../
vpath %.S ../
# All Target
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
# Linker target
$(OUTPUT_FILE_PATH): $(OBJS)
@echo Building target: $@
@echo Invoking: ARM/GNU Linker
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \
-Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \
\
-T"../gcc/gcc/same54p20a_flash.ld" \
-L"../gcc/gcc"
@echo Finished building target: $@
"arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin"
"arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \
"$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex"
"arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \
.eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \
"$(OUTPUT_FILE_NAME).eep" || exit 0
"arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss"
"arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf"
# Compiler targets
%.o: %.c
@echo Building file: $<
@echo ARM/GNU C Compiler
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
$(DIR_INCLUDES) \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.s
@echo Building file: $<
@echo ARM/GNU Assembler
$(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
$(DIR_INCLUDES) \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.S
@echo Building file: $<
@echo ARM/GNU Preprocessing Assembler
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
$(DIR_INCLUDES) \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
# Detect changes in the dependent files and recompile the respective object files.
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(DEPS)),)
-include $(DEPS)
endif
endif
$(SUB_DIRS):
$(MK_DIR) "$@"
clean:
rm -f $(OBJS_AS_ARGS)
rm -f $(OUTPUT_FILE_PATH)
rm -f $(DEPS_AS_ARGS)
rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \
$(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \
$(OUTPUT_FILE_NAME).srec

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atmel_start.d atmel_start.o: ../atmel_start.c ../atmel_start.h \
../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \
../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
../hal/include/hal_init.h ../hal/include/hpl_init.h \
../hal/include/hal_io.h ../hal/include/hal_sleep.h \
../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \
../hal/include/hal_usart_async.h ../hal/include/hal_io.h \
../hal/include/hpl_usart_async.h ../hal/include/hpl_usart.h \
../hal/include/hpl_irq.h ../hal/utils/include/utils_ringbuffer.h \
../hal/utils/include/compiler.h ../hal/utils/include/utils_assert.h \
../hal/include/hal_i2c_m_sync.h ../hal/include/hpl_i2c_m_sync.h \
../hal/include/hal_timer.h ../hal/utils/include/utils_list.h \
../hal/include/hpl_timer.h ../hpl/tc/hpl_tc_base.h \
../hal/include/hpl_pwm.h
../atmel_start.h:
../driver_init.h:
../atmel_start_pins.h:
../hal/include/hal_gpio.h:
../hal/include/hpl_gpio.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hpl/port/hpl_gpio_base.h:
../hal/utils/include/utils_assert.h:
../config/hpl_port_config.h:
../hal/include/hal_delay.h:
../hal/include/hpl_irq.h:
../hal/include/hpl_reset.h:
../hal/include/hpl_sleep.h:
../hal/include/hal_init.h:
../hal/include/hpl_init.h:
../hal/include/hal_io.h:
../hal/include/hal_sleep.h:
../hal/include/hal_ext_irq.h:
../hal/include/hpl_ext_irq.h:
../hal/include/hal_usart_async.h:
../hal/include/hal_io.h:
../hal/include/hpl_usart_async.h:
../hal/include/hpl_usart.h:
../hal/include/hpl_irq.h:
../hal/utils/include/utils_ringbuffer.h:
../hal/utils/include/compiler.h:
../hal/utils/include/utils_assert.h:
../hal/include/hal_i2c_m_sync.h:
../hal/include/hpl_i2c_m_sync.h:
../hal/include/hal_timer.h:
../hal/utils/include/utils_list.h:
../hal/include/hpl_timer.h:
../hpl/tc/hpl_tc_base.h:
../hal/include/hpl_pwm.h:

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driver_init.d driver_init.o: ../driver_init.c ../driver_init.h \
../atmel_start_pins.h ../hal/include/hal_gpio.h \
../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
../hal/include/hal_init.h ../hal/include/hpl_init.h \
../hal/include/hal_io.h ../hal/include/hal_sleep.h \
../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \
../hal/include/hal_usart_async.h ../hal/include/hal_io.h \
../hal/include/hpl_usart_async.h ../hal/include/hpl_usart.h \
../hal/include/hpl_irq.h ../hal/utils/include/utils_ringbuffer.h \
../hal/utils/include/compiler.h ../hal/utils/include/utils_assert.h \
../hal/include/hal_i2c_m_sync.h ../hal/include/hpl_i2c_m_sync.h \
../hal/include/hal_timer.h ../hal/utils/include/utils_list.h \
../hal/include/hpl_timer.h ../hpl/tc/hpl_tc_base.h \
../hal/include/hpl_pwm.h ../config/peripheral_clk_config.h \
../hal/utils/include/utils.h
../driver_init.h:
../atmel_start_pins.h:
../hal/include/hal_gpio.h:
../hal/include/hpl_gpio.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hpl/port/hpl_gpio_base.h:
../hal/utils/include/utils_assert.h:
../config/hpl_port_config.h:
../hal/include/hal_delay.h:
../hal/include/hpl_irq.h:
../hal/include/hpl_reset.h:
../hal/include/hpl_sleep.h:
../hal/include/hal_init.h:
../hal/include/hpl_init.h:
../hal/include/hal_io.h:
../hal/include/hal_sleep.h:
../hal/include/hal_ext_irq.h:
../hal/include/hpl_ext_irq.h:
../hal/include/hal_usart_async.h:
../hal/include/hal_io.h:
../hal/include/hpl_usart_async.h:
../hal/include/hpl_usart.h:
../hal/include/hpl_irq.h:
../hal/utils/include/utils_ringbuffer.h:
../hal/utils/include/compiler.h:
../hal/utils/include/utils_assert.h:
../hal/include/hal_i2c_m_sync.h:
../hal/include/hpl_i2c_m_sync.h:
../hal/include/hal_timer.h:
../hal/utils/include/utils_list.h:
../hal/include/hpl_timer.h:
../hpl/tc/hpl_tc_base.h:
../hal/include/hpl_pwm.h:
../config/peripheral_clk_config.h:
../hal/utils/include/utils.h:

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examples/driver_examples.d examples/driver_examples.o: \
../examples/driver_examples.c ../examples/driver_examples.h \
../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \
../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
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../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
../hal/include/hal_init.h ../hal/include/hpl_init.h \
../hal/include/hal_io.h ../hal/include/hal_sleep.h \
../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \
../hal/include/hal_usart_async.h ../hal/include/hal_io.h \
../hal/include/hpl_usart_async.h ../hal/include/hpl_usart.h \
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../hal/utils/include/compiler.h ../hal/utils/include/utils_assert.h \
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../hal/include/hal_timer.h ../hal/utils/include/utils_list.h \
../hal/include/hpl_timer.h ../hpl/tc/hpl_tc_base.h \
../hal/include/hpl_pwm.h ../hal/utils/include/utils.h
../examples/driver_examples.h:
../driver_init.h:
../atmel_start_pins.h:
../hal/include/hal_gpio.h:
../hal/include/hpl_gpio.h:
../hal/utils/include/compiler.h:
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/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
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/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
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../include/same54p20a.h:
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../CMSIS/Core/Include/cmsis_version.h:
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../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
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../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
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../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
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../include/component/wdt.h:
../include/instance/ac.h:
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../include/instance/can1.h:
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../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
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../include/instance/i2s.h:
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../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
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../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
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../include/instance/supc.h:
../include/instance/tc0.h:
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../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
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../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
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../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
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../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
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../hri/hri_oscctrl_e54.h:
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../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
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../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
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../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
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../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
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../hal/utils/include/err_codes.h:
../hpl/port/hpl_gpio_base.h:
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../config/hpl_port_config.h:
../hal/include/hal_delay.h:
../hal/include/hpl_irq.h:
../hal/include/hpl_reset.h:
../hal/include/hpl_sleep.h:
../hal/include/hal_init.h:
../hal/include/hpl_init.h:
../hal/include/hal_io.h:
../hal/include/hal_sleep.h:
../hal/include/hal_ext_irq.h:
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../hal/include/hal_i2c_m_sync.h:
../hal/include/hpl_i2c_m_sync.h:
../hal/include/hal_timer.h:
../hal/utils/include/utils_list.h:
../hal/include/hpl_timer.h:
../hpl/tc/hpl_tc_base.h:
../hal/include/hpl_pwm.h:
../hal/utils/include/utils.h:

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gcc/gcc/startup_same54.d gcc/gcc/startup_same54.o: \
../gcc/gcc/startup_same54.c ../include/same54.h ../include/same54p20a.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
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../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h
../include/same54.h:
../include/same54p20a.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
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../include/component/aes.h:
../include/component/can.h:
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../include/component/dac.h:
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../include/component/qspi.h:
../include/component/ramecc.h:
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../include/instance/supc.h:
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../include/instance/tc3.h:
../include/instance/tc4.h:
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../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:

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/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME54P20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
software/firmware/oracle_e54_edition/gcc/gcc/same54p20a_sram.ld
Unescape Escape View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAME54P20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

678
software/firmware/oracle_e54_edition/gcc/gcc/startup_same54.c
Unescape Escape View File

@ -0,0 +1,678 @@
/**
* \file
*
* \brief gcc starttup file for SAME54
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "same54.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void MemManagement_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SVCall_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void MCLK_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void OSCCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
void OSCCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
void OSCCTRL_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF,
OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS,
OSCCTRL_DFLLRDY */
void OSCCTRL_3_Handler(void) __attribute__((
weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
void OSCCTRL_4_Handler(void) __attribute__((
weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
void OSC32KCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SUPC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY,
SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY
*/
void SUPC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void EIC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
void EIC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
void EIC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
void EIC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
void EIC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
void EIC_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
void EIC_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
void EIC_7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
void EIC_8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
void EIC_9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
void EIC_10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
void EIC_11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
void EIC_12_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
void EIC_13_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
void EIC_14_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
void EIC_15_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2,
NVMCTRL_3, NVMCTRL_4, NVMCTRL_5,
NVMCTRL_6, NVMCTRL_7 */
void NVMCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
void DMAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
void DMAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
void DMAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
void DMAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
void DMAC_4_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14,
DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19,
DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24,
DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29,
DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6,
DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11,
DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15,
DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19,
DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23,
DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27,
DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31,
DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8,
DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13,
DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18,
DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23,
DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28,
DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5,
DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
void EVSYS_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
void EVSYS_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
void EVSYS_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
void EVSYS_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
void EVSYS_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4,
EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7,
EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10,
EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5,
EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8,
EVSYS_OVR_9 */
void PAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void RAMECC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
void SERCOM0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
void SERCOM0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
void SERCOM0_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
void SERCOM1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
void SERCOM1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
void SERCOM1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
void SERCOM1_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
void SERCOM2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
void SERCOM2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
void SERCOM2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
void SERCOM2_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
void SERCOM3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
void SERCOM3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
void SERCOM3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
void SERCOM3_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
#ifdef ID_SERCOM4
void SERCOM4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
void SERCOM4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
void SERCOM4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
void SERCOM4_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
#endif
#ifdef ID_SERCOM5
void SERCOM5_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
void SERCOM5_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
void SERCOM5_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
void SERCOM5_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
#endif
#ifdef ID_SERCOM6
void SERCOM6_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
void SERCOM6_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
void SERCOM6_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
void SERCOM6_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
#endif
#ifdef ID_SERCOM7
void SERCOM7_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
void SERCOM7_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
void SERCOM7_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
void SERCOM7_3_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
#endif
#ifdef ID_CAN0
void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_CAN1
void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_USB
void USB_0_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN,
USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1,
USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4,
USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7,
USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2,
USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5,
USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1,
USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6,
USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1,
USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4,
USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7,
USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2,
USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5,
USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
void USB_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
void USB_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2,
USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5,
USB_TRCPT0_6, USB_TRCPT0_7 */
void USB_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2,
USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5,
USB_TRCPT1_6, USB_TRCPT1_7 */
#endif
#ifdef ID_GMAC
void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
void TCC0_0_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A,
TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
void TCC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
void TCC0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
void TCC0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
void TCC0_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
void TCC0_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
void TCC0_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
void TCC1_0_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A,
TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
void TCC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
void TCC1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
void TCC1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
void TCC1_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
void TCC2_0_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A,
TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
void TCC2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
void TCC2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
void TCC2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
#ifdef ID_TCC3
void TCC3_0_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A,
TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
void TCC3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
void TCC3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
#endif
#ifdef ID_TCC4
void TCC4_0_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A,
TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
void TCC4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
void TCC4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
#endif
void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#ifdef ID_TC4
void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC5
void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC6
void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC7
void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
void PDEC_0_Handler(void)
__attribute__((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
void PDEC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
void PDEC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
void ADC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
void ADC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
void ADC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
void ADC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void DAC_0_Handler(void)
__attribute__((weak,
alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
void DAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
void DAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
void DAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
void DAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
#ifdef ID_I2S
void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
void PCC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#ifdef ID_ICM
void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_PUKCC
void PUKCC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#ifdef ID_SDHC0
void SDHC0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_SDHC1
void SDHC1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
/* Exception Table */
__attribute__((section(".vectors"))) const DeviceVectors exception_table
= {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void *)(&_estack),
.pfnReset_Handler = (void *)Reset_Handler,
.pfnNonMaskableInt_Handler = (void *)NonMaskableInt_Handler,
.pfnHardFault_Handler = (void *)HardFault_Handler,
.pfnMemManagement_Handler = (void *)MemManagement_Handler,
.pfnBusFault_Handler = (void *)BusFault_Handler,
.pfnUsageFault_Handler = (void *)UsageFault_Handler,
.pvReservedM9 = (void *)(0UL), /* Reserved */
.pvReservedM8 = (void *)(0UL), /* Reserved */
.pvReservedM7 = (void *)(0UL), /* Reserved */
.pvReservedM6 = (void *)(0UL), /* Reserved */
.pfnSVCall_Handler = (void *)SVCall_Handler,
.pfnDebugMonitor_Handler = (void *)DebugMonitor_Handler,
.pvReservedM3 = (void *)(0UL), /* Reserved */
.pfnPendSV_Handler = (void *)PendSV_Handler,
.pfnSysTick_Handler = (void *)SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void *)MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_0_Handler = (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
.pfnOSCCTRL_1_Handler = (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
.pfnOSCCTRL_2_Handler
= (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS,
OSCCTRL_DFLLRDY */
.pfnOSCCTRL_3_Handler = (void *)
OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
.pfnOSCCTRL_4_Handler = (void *)
OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
.pfnOSC32KCTRL_Handler = (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_0_Handler = (void *)SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY,
SUPC_VCORERDY, SUPC_VREGRDY */
.pfnSUPC_1_Handler = (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
.pfnWDT_Handler = (void *)WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void *)RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_0_Handler = (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */
.pfnEIC_1_Handler = (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */
.pfnEIC_2_Handler = (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */
.pfnEIC_3_Handler = (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */
.pfnEIC_4_Handler = (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */
.pfnEIC_5_Handler = (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */
.pfnEIC_6_Handler = (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */
.pfnEIC_7_Handler = (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */
.pfnEIC_8_Handler = (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */
.pfnEIC_9_Handler = (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */
.pfnEIC_10_Handler = (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */
.pfnEIC_11_Handler = (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */
.pfnEIC_12_Handler = (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */
.pfnEIC_13_Handler = (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */
.pfnEIC_14_Handler = (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */
.pfnEIC_15_Handler = (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */
.pfnFREQM_Handler = (void *)FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void *)
NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6,
NVMCTRL_7 */
.pfnNVMCTRL_1_Handler = (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
.pfnDMAC_0_Handler = (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
.pfnDMAC_1_Handler = (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
.pfnDMAC_2_Handler = (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
.pfnDMAC_3_Handler = (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
.pfnDMAC_4_Handler = (void *)DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13,
DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17,
DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21,
DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25,
DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29,
DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5,
DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9,
DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13,
DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17,
DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21,
DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25,
DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29,
DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5,
DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9,
DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13,
DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17,
DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21,
DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25,
DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29,
DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5,
DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
.pfnEVSYS_0_Handler = (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
.pfnEVSYS_1_Handler = (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
.pfnEVSYS_2_Handler = (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
.pfnEVSYS_3_Handler = (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
.pfnEVSYS_4_Handler = (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5,
EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9,
EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5,
EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
.pfnPAC_Handler = (void *)PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void *)(0UL), /* 42 Reserved */
.pvReserved43 = (void *)(0UL), /* 43 Reserved */
.pvReserved44 = (void *)(0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void *)RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */
.pfnSERCOM0_1_Handler = (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */
.pfnSERCOM0_2_Handler = (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */
.pfnSERCOM0_3_Handler = (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
.pfnSERCOM1_0_Handler = (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */
.pfnSERCOM1_1_Handler = (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */
.pfnSERCOM1_2_Handler = (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */
.pfnSERCOM1_3_Handler = (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
.pfnSERCOM2_0_Handler = (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */
.pfnSERCOM2_1_Handler = (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */
.pfnSERCOM2_2_Handler = (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */
.pfnSERCOM2_3_Handler = (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
.pfnSERCOM3_0_Handler = (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */
.pfnSERCOM3_1_Handler = (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */
.pfnSERCOM3_2_Handler = (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */
.pfnSERCOM3_3_Handler = (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
#ifdef ID_SERCOM4
.pfnSERCOM4_0_Handler = (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */
.pfnSERCOM4_1_Handler = (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */
.pfnSERCOM4_2_Handler = (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */
.pfnSERCOM4_3_Handler = (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
#else
.pvReserved62 = (void *)(0UL), /* 62 Reserved */
.pvReserved63 = (void *)(0UL), /* 63 Reserved */
.pvReserved64 = (void *)(0UL), /* 64 Reserved */
.pvReserved65 = (void *)(0UL), /* 65 Reserved */
#endif
#ifdef ID_SERCOM5
.pfnSERCOM5_0_Handler = (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */
.pfnSERCOM5_1_Handler = (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */
.pfnSERCOM5_2_Handler = (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */
.pfnSERCOM5_3_Handler = (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
#else
.pvReserved66 = (void *)(0UL), /* 66 Reserved */
.pvReserved67 = (void *)(0UL), /* 67 Reserved */
.pvReserved68 = (void *)(0UL), /* 68 Reserved */
.pvReserved69 = (void *)(0UL), /* 69 Reserved */
#endif
#ifdef ID_SERCOM6
.pfnSERCOM6_0_Handler = (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */
.pfnSERCOM6_1_Handler = (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */
.pfnSERCOM6_2_Handler = (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */
.pfnSERCOM6_3_Handler = (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
#else
.pvReserved70 = (void *)(0UL), /* 70 Reserved */
.pvReserved71 = (void *)(0UL), /* 71 Reserved */
.pvReserved72 = (void *)(0UL), /* 72 Reserved */
.pvReserved73 = (void *)(0UL), /* 73 Reserved */
#endif
#ifdef ID_SERCOM7
.pfnSERCOM7_0_Handler = (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */
.pfnSERCOM7_1_Handler = (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */
.pfnSERCOM7_2_Handler = (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */
.pfnSERCOM7_3_Handler = (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
#else
.pvReserved74 = (void *)(0UL), /* 74 Reserved */
.pvReserved75 = (void *)(0UL), /* 75 Reserved */
.pvReserved76 = (void *)(0UL), /* 76 Reserved */
.pvReserved77 = (void *)(0UL), /* 77 Reserved */
#endif
#ifdef ID_CAN0
.pfnCAN0_Handler = (void *)CAN0_Handler, /* 78 Control Area Network 0 */
#else
.pvReserved78 = (void *)(0UL), /* 78 Reserved */
#endif
#ifdef ID_CAN1
.pfnCAN1_Handler = (void *)CAN1_Handler, /* 79 Control Area Network 1 */
#else
.pvReserved79 = (void *)(0UL), /* 79 Reserved */
#endif
#ifdef ID_USB
.pfnUSB_0_Handler = (void *)
USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF,
USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3,
USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7,
USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3,
USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7,
USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5,
USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1,
USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5,
USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1,
USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5,
USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
.pfnUSB_1_Handler = (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */
.pfnUSB_2_Handler = (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3,
USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
.pfnUSB_3_Handler = (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3,
USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
#else
.pvReserved80 = (void *)(0UL), /* 80 Reserved */
.pvReserved81 = (void *)(0UL), /* 81 Reserved */
.pvReserved82 = (void *)(0UL), /* 82 Reserved */
.pvReserved83 = (void *)(0UL), /* 83 Reserved */
#endif
#ifdef ID_GMAC
.pfnGMAC_Handler = (void *)GMAC_Handler, /* 84 Ethernet MAC */
#else
.pvReserved84 = (void *)(0UL), /* 84 Reserved */
#endif
.pfnTCC0_0_Handler = (void *)
TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A,
TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
.pfnTCC0_1_Handler = (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */
.pfnTCC0_2_Handler = (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */
.pfnTCC0_3_Handler = (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */
.pfnTCC0_4_Handler = (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */
.pfnTCC0_5_Handler = (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */
.pfnTCC0_6_Handler = (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */
.pfnTCC1_0_Handler = (void *)
TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A,
TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
.pfnTCC1_1_Handler = (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */
.pfnTCC1_2_Handler = (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */
.pfnTCC1_3_Handler = (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */
.pfnTCC1_4_Handler = (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */
.pfnTCC2_0_Handler = (void *)
TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A,
TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
.pfnTCC2_1_Handler = (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */
.pfnTCC2_2_Handler = (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */
.pfnTCC2_3_Handler = (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */
#ifdef ID_TCC3
.pfnTCC3_0_Handler
= (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A,
TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
.pfnTCC3_1_Handler = (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */
.pfnTCC3_2_Handler = (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */
#else
.pvReserved101 = (void *)(0UL), /* 101 Reserved */
.pvReserved102 = (void *)(0UL), /* 102 Reserved */
.pvReserved103 = (void *)(0UL), /* 103 Reserved */
#endif
#ifdef ID_TCC4
.pfnTCC4_0_Handler
= (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A,
TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
.pfnTCC4_1_Handler = (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */
.pfnTCC4_2_Handler = (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */
#else
.pvReserved104 = (void *)(0UL), /* 104 Reserved */
.pvReserved105 = (void *)(0UL), /* 105 Reserved */
.pvReserved106 = (void *)(0UL), /* 106 Reserved */
#endif
.pfnTC0_Handler = (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */
.pfnTC1_Handler = (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */
.pfnTC2_Handler = (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */
.pfnTC3_Handler = (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */
#ifdef ID_TC4
.pfnTC4_Handler = (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */
#else
.pvReserved111 = (void *)(0UL), /* 111 Reserved */
#endif
#ifdef ID_TC5
.pfnTC5_Handler = (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */
#else
.pvReserved112 = (void *)(0UL), /* 112 Reserved */
#endif
#ifdef ID_TC6
.pfnTC6_Handler = (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */
#else
.pvReserved113 = (void *)(0UL), /* 113 Reserved */
#endif
#ifdef ID_TC7
.pfnTC7_Handler = (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */
#else
.pvReserved114 = (void *)(0UL), /* 114 Reserved */
#endif
.pfnPDEC_0_Handler = (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
.pfnPDEC_1_Handler = (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */
.pfnPDEC_2_Handler = (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */
.pfnADC0_0_Handler = (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
.pfnADC0_1_Handler = (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */
.pfnADC1_0_Handler = (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
.pfnADC1_1_Handler = (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */
.pfnAC_Handler = (void *)AC_Handler, /* 122 Analog Comparators */
.pfnDAC_0_Handler
= (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
.pfnDAC_1_Handler = (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */
.pfnDAC_2_Handler = (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */
.pfnDAC_3_Handler = (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */
.pfnDAC_4_Handler = (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */
#ifdef ID_I2S
.pfnI2S_Handler = (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */
#else
.pvReserved128 = (void *)(0UL), /* 128 Reserved */
#endif
.pfnPCC_Handler = (void *)PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void *)AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void *)TRNG_Handler, /* 131 True Random Generator */
#ifdef ID_ICM
.pfnICM_Handler = (void *)ICM_Handler, /* 132 Integrity Check Monitor */
#else
.pvReserved132 = (void *)(0UL), /* 132 Reserved */
#endif
#ifdef ID_PUKCC
.pfnPUKCC_Handler = (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
#else
.pvReserved133 = (void *)(0UL), /* 133 Reserved */
#endif
.pfnQSPI_Handler = (void *)QSPI_Handler, /* 134 Quad SPI interface */
#ifdef ID_SDHC0
.pfnSDHC0_Handler = (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
#else
.pvReserved135 = (void *)(0UL), /* 135 Reserved */
#endif
#ifdef ID_SDHC1
.pfnSDHC1_Handler = (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
#else
.pvReserved136 = (void *)(0UL) /* 136 Reserved */
#endif
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *)&_sfixed;
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
#if __FPU_USED
/* Enable FPU */
SCB->CPACR |= (0xFu << 20);
__DSB();
__ISB();
#endif
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1)
;
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

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gcc/gcc/startup_same54.d gcc/gcc/startup_same54.o: \
gcc/gcc/startup_same54.c include/same54.h include/same54p20a.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h CMSIS/Core/Include/core_cm4.h \
CMSIS/Core/Include/cmsis_version.h CMSIS/Core/Include/cmsis_compiler.h \
CMSIS/Core/Include/cmsis_gcc.h CMSIS/Core/Include/mpu_armv7.h \
include/system_same54.h include/component/ac.h include/component/adc.h \
include/component/aes.h include/component/can.h include/component/ccl.h \
include/component/cmcc.h include/component/dac.h \
include/component/dmac.h include/component/dsu.h include/component/eic.h \
include/component/evsys.h include/component/freqm.h \
include/component/gclk.h include/component/gmac.h \
include/component/hmatrixb.h include/component/icm.h \
include/component/i2s.h include/component/mclk.h \
include/component/nvmctrl.h include/component/oscctrl.h \
include/component/osc32kctrl.h include/component/pac.h \
include/component/pcc.h include/component/pdec.h include/component/pm.h \
include/component/port.h include/component/qspi.h \
include/component/ramecc.h include/component/rstc.h \
include/component/rtc.h include/component/sdhc.h \
include/component/sercom.h include/component/supc.h \
include/component/tc.h include/component/tcc.h include/component/trng.h \
include/component/usb.h include/component/wdt.h include/instance/ac.h \
include/instance/adc0.h include/instance/adc1.h include/instance/aes.h \
include/instance/can0.h include/instance/can1.h include/instance/ccl.h \
include/instance/cmcc.h include/instance/dac.h include/instance/dmac.h \
include/instance/dsu.h include/instance/eic.h include/instance/evsys.h \
include/instance/freqm.h include/instance/gclk.h include/instance/gmac.h \
include/instance/hmatrix.h include/instance/icm.h include/instance/i2s.h \
include/instance/mclk.h include/instance/nvmctrl.h \
include/instance/oscctrl.h include/instance/osc32kctrl.h \
include/instance/pac.h include/instance/pcc.h include/instance/pdec.h \
include/instance/pm.h include/instance/port.h include/instance/pukcc.h \
include/instance/qspi.h include/instance/ramecc.h \
include/instance/rstc.h include/instance/rtc.h include/instance/sdhc0.h \
include/instance/sdhc1.h include/instance/sercom0.h \
include/instance/sercom1.h include/instance/sercom2.h \
include/instance/sercom3.h include/instance/sercom4.h \
include/instance/sercom5.h include/instance/sercom6.h \
include/instance/sercom7.h include/instance/supc.h \
include/instance/tc0.h include/instance/tc1.h include/instance/tc2.h \
include/instance/tc3.h include/instance/tc4.h include/instance/tc5.h \
include/instance/tc6.h include/instance/tc7.h include/instance/tcc0.h \
include/instance/tcc1.h include/instance/tcc2.h include/instance/tcc3.h \
include/instance/tcc4.h include/instance/trng.h include/instance/usb.h \
include/instance/wdt.h include/pio/same54p20a.h
include/same54.h:
include/same54p20a.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
CMSIS/Core/Include/core_cm4.h:
CMSIS/Core/Include/cmsis_version.h:
CMSIS/Core/Include/cmsis_compiler.h:
CMSIS/Core/Include/cmsis_gcc.h:
CMSIS/Core/Include/mpu_armv7.h:
include/system_same54.h:
include/component/ac.h:
include/component/adc.h:
include/component/aes.h:
include/component/can.h:
include/component/ccl.h:
include/component/cmcc.h:
include/component/dac.h:
include/component/dmac.h:
include/component/dsu.h:
include/component/eic.h:
include/component/evsys.h:
include/component/freqm.h:
include/component/gclk.h:
include/component/gmac.h:
include/component/hmatrixb.h:
include/component/icm.h:
include/component/i2s.h:
include/component/mclk.h:
include/component/nvmctrl.h:
include/component/oscctrl.h:
include/component/osc32kctrl.h:
include/component/pac.h:
include/component/pcc.h:
include/component/pdec.h:
include/component/pm.h:
include/component/port.h:
include/component/qspi.h:
include/component/ramecc.h:
include/component/rstc.h:
include/component/rtc.h:
include/component/sdhc.h:
include/component/sercom.h:
include/component/supc.h:
include/component/tc.h:
include/component/tcc.h:
include/component/trng.h:
include/component/usb.h:
include/component/wdt.h:
include/instance/ac.h:
include/instance/adc0.h:
include/instance/adc1.h:
include/instance/aes.h:
include/instance/can0.h:
include/instance/can1.h:
include/instance/ccl.h:
include/instance/cmcc.h:
include/instance/dac.h:
include/instance/dmac.h:
include/instance/dsu.h:
include/instance/eic.h:
include/instance/evsys.h:
include/instance/freqm.h:
include/instance/gclk.h:
include/instance/gmac.h:
include/instance/hmatrix.h:
include/instance/icm.h:
include/instance/i2s.h:
include/instance/mclk.h:
include/instance/nvmctrl.h:
include/instance/oscctrl.h:
include/instance/osc32kctrl.h:
include/instance/pac.h:
include/instance/pcc.h:
include/instance/pdec.h:
include/instance/pm.h:
include/instance/port.h:
include/instance/pukcc.h:
include/instance/qspi.h:
include/instance/ramecc.h:
include/instance/rstc.h:
include/instance/rtc.h:
include/instance/sdhc0.h:
include/instance/sdhc1.h:
include/instance/sercom0.h:
include/instance/sercom1.h:
include/instance/sercom2.h:
include/instance/sercom3.h:
include/instance/sercom4.h:
include/instance/sercom5.h:
include/instance/sercom6.h:
include/instance/sercom7.h:
include/instance/supc.h:
include/instance/tc0.h:
include/instance/tc1.h:
include/instance/tc2.h:
include/instance/tc3.h:
include/instance/tc4.h:
include/instance/tc5.h:
include/instance/tc6.h:
include/instance/tc7.h:
include/instance/tcc0.h:
include/instance/tcc1.h:
include/instance/tcc2.h:
include/instance/tcc3.h:
include/instance/tcc4.h:
include/instance/trng.h:
include/instance/usb.h:
include/instance/wdt.h:
include/pio/same54p20a.h:

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gcc/system_same54.d gcc/system_same54.o: ../gcc/system_same54.c \
../include/same54.h ../include/same54p20a.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h
../include/same54.h:
../include/same54p20a.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:

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hal/src/hal_atomic.d hal/src/hal_atomic.o: ../hal/src/hal_atomic.c \
../hal/include/hal_atomic.h ../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hri/hri_adc_e54.h ../hri/hri_aes_e54.h \
../hri/hri_can_e54.h ../hri/hri_ccl_e54.h ../hri/hri_cmcc_e54.h \
../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h ../hri/hri_dsu_e54.h \
../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h ../hri/hri_freqm_e54.h \
../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h ../hri/hri_hmatrixb_e54.h \
../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h ../hri/hri_mclk_e54.h \
../hri/hri_nvmctrl_e54.h ../hri/hri_osc32kctrl_e54.h \
../hri/hri_oscctrl_e54.h ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h \
../hri/hri_pdec_e54.h ../hri/hri_pm_e54.h ../hri/hri_port_e54.h \
../hri/hri_qspi_e54.h ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h \
../hri/hri_rtc_e54.h ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h \
../hri/hri_supc_e54.h ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h \
../hri/hri_trng_e54.h ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h
../hal/include/hal_atomic.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:

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software/firmware/oracle_e54_edition/gcc/hal/src/hal_cache.d
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hal/src/hal_cache.d hal/src/hal_cache.o: ../hal/src/hal_cache.c \
../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hal/include/hpl_cmcc.h
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hal/include/hpl_cmcc.h:

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hal/src/hal_delay.d hal/src/hal_delay.o: ../hal/src/hal_delay.c \
../hal/include/hpl_irq.h ../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hal/include/hpl_reset.h \
../hal/include/hpl_sleep.h ../hal/include/hal_delay.h \
../hal/include/hpl_delay.h
../hal/include/hpl_irq.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hal/include/hpl_reset.h:
../hal/include/hpl_sleep.h:
../hal/include/hal_delay.h:
../hal/include/hpl_delay.h:

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hal/src/hal_ext_irq.d hal/src/hal_ext_irq.o: ../hal/src/hal_ext_irq.c \
../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \
../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h
../hal/include/hal_ext_irq.h:
../hal/include/hpl_ext_irq.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:

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hal/src/hal_gpio.d hal/src/hal_gpio.o: ../hal/src/hal_gpio.c \
../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
../hal/utils/include/utils_assert.h ../config/hpl_port_config.h
../hal/include/hal_gpio.h:
../hal/include/hpl_gpio.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hpl/port/hpl_gpio_base.h:
../hal/utils/include/utils_assert.h:
../config/hpl_port_config.h:

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hal/src/hal_i2c_m_sync.d hal/src/hal_i2c_m_sync.o: \
../hal/src/hal_i2c_m_sync.c ../hal/include/hal_i2c_m_sync.h \
../hal/include/hpl_i2c_m_sync.h ../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hal/include/hal_io.h \
../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h
../hal/include/hal_i2c_m_sync.h:
../hal/include/hpl_i2c_m_sync.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hal/include/hal_io.h:
../hal/utils/include/utils.h:
../hal/utils/include/utils_assert.h:

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hal/src/hal_init.d hal/src/hal_init.o: ../hal/src/hal_init.c \
../hal/include/hal_init.h ../hal/include/hpl_init.h \
../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h
../hal/include/hal_init.h:
../hal/include/hpl_init.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:

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hal/src/hal_io.d hal/src/hal_io.o: ../hal/src/hal_io.c \
../hal/include/hal_io.h ../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
../hal/include/hal_io.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hal/utils/include/utils_assert.h:

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hal/src/hal_sleep.d hal/src/hal_sleep.o: ../hal/src/hal_sleep.c \
../hal/include/hal_sleep.h ../hal/include/hpl_sleep.h \
../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
../include/component/ccl.h ../include/component/cmcc.h \
../include/component/dac.h ../include/component/dmac.h \
../include/component/dsu.h ../include/component/eic.h \
../include/component/evsys.h ../include/component/freqm.h \
../include/component/gclk.h ../include/component/gmac.h \
../include/component/hmatrixb.h ../include/component/icm.h \
../include/component/i2s.h ../include/component/mclk.h \
../include/component/nvmctrl.h ../include/component/oscctrl.h \
../include/component/osc32kctrl.h ../include/component/pac.h \
../include/component/pcc.h ../include/component/pdec.h \
../include/component/pm.h ../include/component/port.h \
../include/component/qspi.h ../include/component/ramecc.h \
../include/component/rstc.h ../include/component/rtc.h \
../include/component/sdhc.h ../include/component/sercom.h \
../include/component/supc.h ../include/component/tc.h \
../include/component/tcc.h ../include/component/trng.h \
../include/component/usb.h ../include/component/wdt.h \
../include/instance/ac.h ../include/instance/adc0.h \
../include/instance/adc1.h ../include/instance/aes.h \
../include/instance/can0.h ../include/instance/can1.h \
../include/instance/ccl.h ../include/instance/cmcc.h \
../include/instance/dac.h ../include/instance/dmac.h \
../include/instance/dsu.h ../include/instance/eic.h \
../include/instance/evsys.h ../include/instance/freqm.h \
../include/instance/gclk.h ../include/instance/gmac.h \
../include/instance/hmatrix.h ../include/instance/icm.h \
../include/instance/i2s.h ../include/instance/mclk.h \
../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
../include/instance/osc32kctrl.h ../include/instance/pac.h \
../include/instance/pcc.h ../include/instance/pdec.h \
../include/instance/pm.h ../include/instance/port.h \
../include/instance/pukcc.h ../include/instance/qspi.h \
../include/instance/ramecc.h ../include/instance/rstc.h \
../include/instance/rtc.h ../include/instance/sdhc0.h \
../include/instance/sdhc1.h ../include/instance/sercom0.h \
../include/instance/sercom1.h ../include/instance/sercom2.h \
../include/instance/sercom3.h ../include/instance/sercom4.h \
../include/instance/sercom5.h ../include/instance/sercom6.h \
../include/instance/sercom7.h ../include/instance/supc.h \
../include/instance/tc0.h ../include/instance/tc1.h \
../include/instance/tc2.h ../include/instance/tc3.h \
../include/instance/tc4.h ../include/instance/tc5.h \
../include/instance/tc6.h ../include/instance/tc7.h \
../include/instance/tcc0.h ../include/instance/tcc1.h \
../include/instance/tcc2.h ../include/instance/tcc3.h \
../include/instance/tcc4.h ../include/instance/trng.h \
../include/instance/usb.h ../include/instance/wdt.h \
../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
../hal/utils/include/err_codes.h
../hal/include/hal_sleep.h:
../hal/include/hpl_sleep.h:
../hal/utils/include/compiler.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h:
/usr/arm-none-eabi/include/stdint.h:
/usr/arm-none-eabi/include/machine/_default_types.h:
/usr/arm-none-eabi/include/sys/features.h:
/usr/arm-none-eabi/include/_newlib_version.h:
/usr/arm-none-eabi/include/sys/_intsup.h:
/usr/arm-none-eabi/include/sys/_stdint.h:
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h:
../hal/utils/include/parts.h:
../include/same54.h:
../include/same54p20a.h:
../CMSIS/Core/Include/core_cm4.h:
../CMSIS/Core/Include/cmsis_version.h:
../CMSIS/Core/Include/cmsis_compiler.h:
../CMSIS/Core/Include/cmsis_gcc.h:
../CMSIS/Core/Include/mpu_armv7.h:
../include/system_same54.h:
../include/component/ac.h:
../include/component/adc.h:
../include/component/aes.h:
../include/component/can.h:
../include/component/ccl.h:
../include/component/cmcc.h:
../include/component/dac.h:
../include/component/dmac.h:
../include/component/dsu.h:
../include/component/eic.h:
../include/component/evsys.h:
../include/component/freqm.h:
../include/component/gclk.h:
../include/component/gmac.h:
../include/component/hmatrixb.h:
../include/component/icm.h:
../include/component/i2s.h:
../include/component/mclk.h:
../include/component/nvmctrl.h:
../include/component/oscctrl.h:
../include/component/osc32kctrl.h:
../include/component/pac.h:
../include/component/pcc.h:
../include/component/pdec.h:
../include/component/pm.h:
../include/component/port.h:
../include/component/qspi.h:
../include/component/ramecc.h:
../include/component/rstc.h:
../include/component/rtc.h:
../include/component/sdhc.h:
../include/component/sercom.h:
../include/component/supc.h:
../include/component/tc.h:
../include/component/tcc.h:
../include/component/trng.h:
../include/component/usb.h:
../include/component/wdt.h:
../include/instance/ac.h:
../include/instance/adc0.h:
../include/instance/adc1.h:
../include/instance/aes.h:
../include/instance/can0.h:
../include/instance/can1.h:
../include/instance/ccl.h:
../include/instance/cmcc.h:
../include/instance/dac.h:
../include/instance/dmac.h:
../include/instance/dsu.h:
../include/instance/eic.h:
../include/instance/evsys.h:
../include/instance/freqm.h:
../include/instance/gclk.h:
../include/instance/gmac.h:
../include/instance/hmatrix.h:
../include/instance/icm.h:
../include/instance/i2s.h:
../include/instance/mclk.h:
../include/instance/nvmctrl.h:
../include/instance/oscctrl.h:
../include/instance/osc32kctrl.h:
../include/instance/pac.h:
../include/instance/pcc.h:
../include/instance/pdec.h:
../include/instance/pm.h:
../include/instance/port.h:
../include/instance/pukcc.h:
../include/instance/qspi.h:
../include/instance/ramecc.h:
../include/instance/rstc.h:
../include/instance/rtc.h:
../include/instance/sdhc0.h:
../include/instance/sdhc1.h:
../include/instance/sercom0.h:
../include/instance/sercom1.h:
../include/instance/sercom2.h:
../include/instance/sercom3.h:
../include/instance/sercom4.h:
../include/instance/sercom5.h:
../include/instance/sercom6.h:
../include/instance/sercom7.h:
../include/instance/supc.h:
../include/instance/tc0.h:
../include/instance/tc1.h:
../include/instance/tc2.h:
../include/instance/tc3.h:
../include/instance/tc4.h:
../include/instance/tc5.h:
../include/instance/tc6.h:
../include/instance/tc7.h:
../include/instance/tcc0.h:
../include/instance/tcc1.h:
../include/instance/tcc2.h:
../include/instance/tcc3.h:
../include/instance/tcc4.h:
../include/instance/trng.h:
../include/instance/usb.h:
../include/instance/wdt.h:
../include/pio/same54p20a.h:
../hri/hri_e54.h:
../include/sam.h:
../hri/hri_ac_e54.h:
../hal/include/hal_atomic.h:
../hri/hri_adc_e54.h:
../hri/hri_aes_e54.h:
../hri/hri_can_e54.h:
../hri/hri_ccl_e54.h:
../hri/hri_cmcc_e54.h:
../hri/hri_dac_e54.h:
../hri/hri_dmac_e54.h:
../hri/hri_dsu_e54.h:
../hri/hri_eic_e54.h:
../hri/hri_evsys_e54.h:
../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:

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hal/src/hal_timer.d hal/src/hal_timer.o: ../hal/src/hal_timer.c \
../hal/include/hal_timer.h ../hal/utils/include/utils_list.h \
../hal/utils/include/compiler.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stddef.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdint.h \
/usr/arm-none-eabi/include/stdint.h \
/usr/arm-none-eabi/include/machine/_default_types.h \
/usr/arm-none-eabi/include/sys/features.h \
/usr/arm-none-eabi/include/_newlib_version.h \
/usr/arm-none-eabi/include/sys/_intsup.h \
/usr/arm-none-eabi/include/sys/_stdint.h \
/usr/lib/gcc/arm-none-eabi/9.3.0/include/stdbool.h \
../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
../include/component/ac.h ../include/component/adc.h \
../include/component/aes.h ../include/component/can.h \
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../hri/hri_freqm_e54.h:
../hri/hri_gclk_e54.h:
../hri/hri_gmac_e54.h:
../hri/hri_hmatrixb_e54.h:
../hri/hri_i2s_e54.h:
../hri/hri_icm_e54.h:
../hri/hri_mclk_e54.h:
../hri/hri_nvmctrl_e54.h:
../hri/hri_osc32kctrl_e54.h:
../hri/hri_oscctrl_e54.h:
../hri/hri_pac_e54.h:
../hri/hri_pcc_e54.h:
../hri/hri_pdec_e54.h:
../hri/hri_pm_e54.h:
../hri/hri_port_e54.h:
../hri/hri_qspi_e54.h:
../hri/hri_ramecc_e54.h:
../hri/hri_rstc_e54.h:
../hri/hri_rtc_e54.h:
../hri/hri_sdhc_e54.h:
../hri/hri_sercom_e54.h:
../hri/hri_supc_e54.h:
../hri/hri_tc_e54.h:
../hri/hri_tcc_e54.h:
../hri/hri_trng_e54.h:
../hri/hri_usb_e54.h:
../hri/hri_wdt_e54.h:
../hal/utils/include/err_codes.h:
../hal/include/hpl_usart_async.h:
../hal/include/hpl_usart.h:
../hal/include/hpl_irq.h:
../hal/utils/include/utils_ringbuffer.h:
../hal/utils/include/compiler.h:
../hal/utils/include/utils_assert.h:
../hal/utils/include/utils_assert.h:
../hal/utils/include/utils.h:

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software/firmware/oracle_e54_edition/gcc/hal/src/hal_usart_async.o
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