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259 lines
9.2 KiB
C
259 lines
9.2 KiB
C
3 years ago
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/**
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* \file
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*
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* \brief EIC related functionality implementation.
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <compiler.h>
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#include <hpl_eic_config.h>
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#include <hpl_ext_irq.h>
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#include <string.h>
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#include <utils.h>
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#include <utils_assert.h>
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#ifdef __MINGW32__
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#define ffs __builtin_ffs
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#endif
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#if defined(__CC_ARM) || defined(__ICCARM__)
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/* Find the first bit set */
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static int ffs(int v)
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{
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int i, bit = 1;
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for (i = 0; i < sizeof(int) * 8; i++) {
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if (v & bit) {
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return i + 1;
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}
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bit <<= 1;
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}
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return 0;
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}
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#endif
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/**
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* \brief Invalid external interrupt and pin numbers
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*/
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#define INVALID_EXTINT_NUMBER 0xFF
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#define INVALID_PIN_NUMBER 0xFFFFFFFF
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#ifndef CONFIG_EIC_EXTINT_MAP
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/** Dummy mapping to pass compiling. */
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#define CONFIG_EIC_EXTINT_MAP \
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{ \
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INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER \
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}
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#endif
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#define EXT_IRQ_AMOUNT 0
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/**
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* \brief EXTINTx and pin number map
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*/
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struct _eic_map {
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uint8_t extint;
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uint32_t pin;
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};
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/**
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* \brief PIN and EXTINT map for enabled external interrupts
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*/
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static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP};
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/**
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* \brief The callback to upper layer's interrupt processing routine
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*/
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static void (*callback)(const uint32_t pin);
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static void _ext_irq_handler(void);
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/**
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* \brief Initialize external interrupt module
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*/
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int32_t _ext_irq_init(void (*cb)(const uint32_t pin))
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{
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if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) {
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if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) {
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hri_eic_clear_CTRLA_ENABLE_bit(EIC);
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hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE);
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}
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hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST);
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}
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hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST);
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hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL);
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hri_eic_write_NMICTRL_reg(EIC,
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(CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos)
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| EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH)
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| 0);
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hri_eic_write_EVCTRL_reg(EIC,
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(CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2)
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| (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5)
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| (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8)
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| (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11)
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| (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13)
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| (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0);
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hri_eic_write_ASYNCH_reg(EIC,
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(CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2)
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| (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5)
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| (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8)
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| (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11)
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| (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14)
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| (CONF_EIC_ASYNCH15 << 15) | 0);
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hri_eic_write_DEBOUNCEN_reg(
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EIC,
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(CONF_EIC_DEBOUNCE_ENABLE0 << 0) | (CONF_EIC_DEBOUNCE_ENABLE1 << 1) | (CONF_EIC_DEBOUNCE_ENABLE2 << 2)
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| (CONF_EIC_DEBOUNCE_ENABLE3 << 3) | (CONF_EIC_DEBOUNCE_ENABLE4 << 4) | (CONF_EIC_DEBOUNCE_ENABLE5 << 5)
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| (CONF_EIC_DEBOUNCE_ENABLE6 << 6) | (CONF_EIC_DEBOUNCE_ENABLE7 << 7) | (CONF_EIC_DEBOUNCE_ENABLE8 << 8)
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| (CONF_EIC_DEBOUNCE_ENABLE9 << 9) | (CONF_EIC_DEBOUNCE_ENABLE10 << 10) | (CONF_EIC_DEBOUNCE_ENABLE11 << 11)
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| (CONF_EIC_DEBOUNCE_ENABLE12 << 12) | (CONF_EIC_DEBOUNCE_ENABLE13 << 13)
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| (CONF_EIC_DEBOUNCE_ENABLE14 << 14) | (CONF_EIC_DEBOUNCE_ENABLE15 << 15) | 0);
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hri_eic_write_DPRESCALER_reg(
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EIC,
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(EIC_DPRESCALER_PRESCALER0(CONF_EIC_DPRESCALER0)) | (CONF_EIC_STATES0 << EIC_DPRESCALER_STATES0_Pos)
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| (EIC_DPRESCALER_PRESCALER1(CONF_EIC_DPRESCALER1)) | (CONF_EIC_STATES1 << EIC_DPRESCALER_STATES1_Pos)
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| CONF_EIC_TICKON << EIC_DPRESCALER_TICKON_Pos | 0);
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hri_eic_write_CONFIG_reg(EIC,
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0,
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(CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0)
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| (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1)
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| (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2)
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| (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3)
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| (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4)
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| (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5)
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| (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6)
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| (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7)
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| 0);
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hri_eic_write_CONFIG_reg(EIC,
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1,
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(CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8)
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| (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9)
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| (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10)
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| (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11)
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| (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12)
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| (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13)
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| (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14)
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| (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15)
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| 0);
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hri_eic_set_CTRLA_ENABLE_bit(EIC);
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callback = cb;
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return ERR_NONE;
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}
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/**
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* \brief De-initialize external interrupt module
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*/
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int32_t _ext_irq_deinit(void)
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{
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callback = NULL;
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hri_eic_clear_CTRLA_ENABLE_bit(EIC);
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hri_eic_set_CTRLA_SWRST_bit(EIC);
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return ERR_NONE;
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}
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/**
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* \brief Enable / disable external irq
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*/
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int32_t _ext_irq_enable(const uint32_t pin, const bool enable)
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{
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uint8_t extint = INVALID_EXTINT_NUMBER;
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uint8_t i = 0;
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for (; i < ARRAY_SIZE(_map); i++) {
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if (_map[i].pin == pin) {
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extint = _map[i].extint;
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break;
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}
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}
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if (INVALID_EXTINT_NUMBER == extint) {
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return -1;
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}
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if (enable) {
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hri_eic_set_INTEN_reg(EIC, 1ul << extint);
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} else {
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hri_eic_clear_INTEN_reg(EIC, 1ul << extint);
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hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint);
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}
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return ERR_NONE;
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}
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/**
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* \brief Inter EIC interrupt handler
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*/
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static void _ext_irq_handler(void)
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{
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volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC);
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int8_t pos;
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uint32_t pin = INVALID_PIN_NUMBER;
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hri_eic_clear_INTFLAG_reg(EIC, flags);
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ASSERT(callback);
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while (flags) {
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pos = ffs(flags) - 1;
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while (-1 != pos) {
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uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
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while (upper >= lower) {
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middle = (upper + lower) >> 1;
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if (_map[middle].extint == pos) {
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pin = _map[middle].pin;
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break;
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}
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if (_map[middle].extint < pos) {
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lower = middle + 1;
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} else {
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upper = middle - 1;
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}
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}
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if (INVALID_PIN_NUMBER != pin) {
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callback(pin);
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}
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flags &= ~(1ul << pos);
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pos = ffs(flags) - 1;
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}
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flags = hri_eic_read_INTFLAG_reg(EIC);
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hri_eic_clear_INTFLAG_reg(EIC, flags);
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}
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}
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