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3 years ago
AtmelStart.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 0000069c 00000000 00000000 00010000 2**2
3 years ago
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 00000000 20000000 20000000 0001069c 2**0
3 years ago
CONTENTS
2 .bss 00000028 20000000 20000000 00020000 2**2
ALLOC
3 .stack 00002000 20000028 20000028 00020000 2**0
ALLOC
4 .ARM.attributes 00000028 00000000 00000000 0001069c 2**0
3 years ago
CONTENTS, READONLY
5 .comment 00000064 00000000 00000000 000106c4 2**0
3 years ago
CONTENTS, READONLY
6 .debug_info 00017fc9 00000000 00000000 00010728 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
7 .debug_abbrev 000019c0 00000000 00000000 000286f1 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
8 .debug_aranges 000006f8 00000000 00000000 0002a0b1 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
9 .debug_rnglists 00000c33 00000000 00000000 0002a7a9 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
10 .debug_macro 00004179 00000000 00000000 0002b3dc 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
11 .debug_line 0000a266 00000000 00000000 0002f555 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
12 .debug_str 000836b7 00000000 00000000 000397bb 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_frame 00001350 00000000 00000000 000bce74 2**2
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_loclists 000046a0 00000000 00000000 000be1c4 2**0
3 years ago
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
00000000 <exception_table>:
/**
* \brief Set the sleep mode for the device
*/
int32_t _set_sleep_mode(const uint8_t mode)
{
switch (mode) {
0: 28 20 00 20 51 01 00 00 4d 01 00 00 4d 01 00 00 ( . Q...M...M...
3 years ago
...
case 2:
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PM->SLEEP.reg = mode;
return ERR_NONE;
case 3:
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
2c: 4d 01 00 00 00 00 00 00 00 00 00 00 4d 01 00 00 M...........M...
};
}
static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
{
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
3c: 4d 01 00 00 4d 01 00 00 4d 01 00 00 4d 01 00 00 M...M...M...M...
static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw,
hri_sercomi2cm_ctrla_reg_t mask)
{
uint32_t tmp;
hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
4c: 4d 01 00 00 4d 01 00 00 4d 01 00 00 4d 01 00 00 M...M...M...M...
}
if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
5c: 4d 01 00 00 4d 01 00 00 4d 01 00 00 4d 01 00 00 M...M...M...M...
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
}
hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
6c: 4d 01 00 00 4d 01 00 00 4d 01 00 00 4d 01 00 00 M...M...M...M...
}
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
7c: 4d 01 00 00 4d 01 00 00 4d 01 00 00 4d 01 00 00 M...M...M...M...
ASSERT(hw && regs);
8c: 4d 01 00 00 4d 01 00 00 4d 01 00 00 4d 01 00 00 M...M...M...M...
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
9c: 4d 01 00 00 4d 01 00 00 4d 01 00 00 4d 01 00 00 M...M...M...M...
hri_sercomspi_write_CTRLA_reg(
ac: 4d 01 00 00 00 00 00 00 M.......
000000b4 <deregister_tm_clones>:
(regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN))
b4: 4804 ldr r0, [pc, #16] ; (c8 <deregister_tm_clones+0x14>)
b6: 4b05 ldr r3, [pc, #20] ; (cc <deregister_tm_clones+0x18>)
b8: b510 push {r4, lr}
ba: 4283 cmp r3, r0
static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.CTRLB.reg = data;
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
bc: d003 beq.n c6 <deregister_tm_clones+0x12>
be: 4b04 ldr r3, [pc, #16] ; (d0 <deregister_tm_clones+0x1c>)
3 years ago
c0: 2b00 cmp r3, #0
c2: d000 beq.n c6 <deregister_tm_clones+0x12>
c4: 4798 blx r3
c6: bd10 pop {r4, pc}
c8: 0000069c .word 0x0000069c
| (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN));
cc: 0000069c .word 0x0000069c
hri_sercomspi_write_CTRLB_reg(hw,
d0: 00000000 .word 0x00000000
000000d4 <register_tm_clones>:
d4: 4806 ldr r0, [pc, #24] ; (f0 <register_tm_clones+0x1c>)
d6: 4907 ldr r1, [pc, #28] ; (f4 <register_tm_clones+0x20>)
hri_sercomspi_write_ADDR_reg(hw, regs->addr);
d8: 1a09 subs r1, r1, r0
da: 108b asrs r3, r1, #2
dc: 0fc9 lsrs r1, r1, #31
de: 18c9 adds r1, r1, r3
e0: b510 push {r4, lr}
e2: 1049 asrs r1, r1, #1
e4: d003 beq.n ee <register_tm_clones+0x1a>
e6: 4b04 ldr r3, [pc, #16] ; (f8 <register_tm_clones+0x24>)
e8: 2b00 cmp r3, #0
ea: d000 beq.n ee <register_tm_clones+0x1a>
}
static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.ADDR.reg = data;
ec: 4798 blx r3
}
static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.DBGCTRL.reg = data;
ee: bd10 pop {r4, pc}
hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
f0: 0000069c .word 0x0000069c
f4: 0000069c .word 0x0000069c
while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF))
f8: 00000000 .word 0x00000000
000000fc <__do_global_dtors_aux>:
} else {
_spi_load_regs_master(hw, regs);
}
/* Load character size from default hardware configuration */
dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
fc: b510 push {r4, lr}
fe: 4c07 ldr r4, [pc, #28] ; (11c <__do_global_dtors_aux+0x20>)
dev->dummy_byte = regs->dummy_byte;
return ERR_NONE;
100: 7823 ldrb r3, [r4, #0]
dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
102: 2b00 cmp r3, #0
104: d109 bne.n 11a <__do_global_dtors_aux+0x1e>
106: f7ff ffd5 bl b4 <deregister_tm_clones>
10a: 4b05 ldr r3, [pc, #20] ; (120 <__do_global_dtors_aux+0x24>)
dev->dummy_byte = regs->dummy_byte;
10c: 2b00 cmp r3, #0
10e: d002 beq.n 116 <__do_global_dtors_aux+0x1a>
110: 4804 ldr r0, [pc, #16] ; (124 <__do_global_dtors_aux+0x28>)
112: e000 b.n 116 <__do_global_dtors_aux+0x1a>
114: bf00 nop
}
116: 2301 movs r3, #1
118: 7023 strb r3, [r4, #0]
ASSERT(hw && regs);
11a: bd10 pop {r4, pc}
11c: 20000000 .word 0x20000000
120: 00000000 .word 0x00000000
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
124: 0000069c .word 0x0000069c
00000128 <frame_dummy>:
128: 4b05 ldr r3, [pc, #20] ; (140 <frame_dummy+0x18>)
12a: b510 push {r4, lr}
12c: 2b00 cmp r3, #0
12e: d003 beq.n 138 <frame_dummy+0x10>
130: 4904 ldr r1, [pc, #16] ; (144 <frame_dummy+0x1c>)
132: 4805 ldr r0, [pc, #20] ; (148 <frame_dummy+0x20>)
134: e000 b.n 138 <frame_dummy+0x10>
136: bf00 nop
hri_sercomspi_write_CTRLA_reg(
138: f7ff ffcc bl d4 <register_tm_clones>
13c: bd10 pop {r4, pc}
13e: 46c0 nop ; (mov r8, r8)
(regs->ctrlb
140: 00000000 .word 0x00000000
144: 20000004 .word 0x20000004
148: 0000069c .word 0x0000069c
0000014c <Dummy_Handler>:
3 years ago
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
14c: e7fe b.n 14c <Dummy_Handler>
3 years ago
...
00000150 <Reset_Handler>:
3 years ago
if (pSrc != pDest) {
150: 4924 ldr r1, [pc, #144] ; (1e4 <Reset_Handler+0x94>)
152: 4825 ldr r0, [pc, #148] ; (1e8 <Reset_Handler+0x98>)
3 years ago
{
154: b570 push {r4, r5, r6, lr}
3 years ago
if (pSrc != pDest) {
156: 4281 cmp r1, r0
158: d00a beq.n 170 <Reset_Handler+0x20>
3 years ago
*pDest++ = *pSrc++;
15a: 4b24 ldr r3, [pc, #144] ; (1ec <Reset_Handler+0x9c>)
15c: 1ec4 subs r4, r0, #3
15e: 2200 movs r2, #0
160: 42a3 cmp r3, r4
162: d303 bcc.n 16c <Reset_Handler+0x1c>
164: 3303 adds r3, #3
166: 1a1a subs r2, r3, r0
168: 0892 lsrs r2, r2, #2
16a: 0092 lsls r2, r2, #2
16c: 4b20 ldr r3, [pc, #128] ; (1f0 <Reset_Handler+0xa0>)
16e: 4798 blx r3
3 years ago
*pDest++ = 0;
170: 4820 ldr r0, [pc, #128] ; (1f4 <Reset_Handler+0xa4>)
172: 4b21 ldr r3, [pc, #132] ; (1f8 <Reset_Handler+0xa8>)
174: 1ec1 subs r1, r0, #3
176: 2200 movs r2, #0
178: 4299 cmp r1, r3
17a: d803 bhi.n 184 <Reset_Handler+0x34>
17c: 3303 adds r3, #3
17e: 1a1a subs r2, r3, r0
180: 0892 lsrs r2, r2, #2
182: 0092 lsls r2, r2, #2
184: 2100 movs r1, #0
186: 4b1d ldr r3, [pc, #116] ; (1fc <Reset_Handler+0xac>)
188: 4798 blx r3
3 years ago
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
18a: 22ff movs r2, #255 ; 0xff
18c: 4b1c ldr r3, [pc, #112] ; (200 <Reset_Handler+0xb0>)
3 years ago
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
18e: 2103 movs r1, #3
3 years ago
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
190: 4393 bics r3, r2
192: 4a1c ldr r2, [pc, #112] ; (204 <Reset_Handler+0xb4>)
3 years ago
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
194: 250c movs r5, #12
3 years ago
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
196: 6093 str r3, [r2, #8]
3 years ago
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
198: 2202 movs r2, #2
3 years ago
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
19a: 2408 movs r4, #8
3 years ago
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
19c: 4b1a ldr r3, [pc, #104] ; (208 <Reset_Handler+0xb8>)
3 years ago
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
19e: 481b ldr r0, [pc, #108] ; (20c <Reset_Handler+0xbc>)
3 years ago
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
1a0: 625a str r2, [r3, #36] ; 0x24
3 years ago
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
1a2: 78c3 ldrb r3, [r0, #3]
1a4: 438b bics r3, r1
1a6: 4313 orrs r3, r2
1a8: 70c3 strb r3, [r0, #3]
3 years ago
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
1aa: 78c3 ldrb r3, [r0, #3]
1ac: 43ab bics r3, r5
1ae: 4323 orrs r3, r4
1b0: 70c3 strb r3, [r0, #3]
3 years ago
DMAC->QOSCTRL.bit.DQOS = 2;
1b2: 2030 movs r0, #48 ; 0x30
1b4: 4b16 ldr r3, [pc, #88] ; (210 <Reset_Handler+0xc0>)
1b6: 7b9e ldrb r6, [r3, #14]
1b8: 4386 bics r6, r0
1ba: 3810 subs r0, #16
1bc: 4330 orrs r0, r6
1be: 7398 strb r0, [r3, #14]
3 years ago
DMAC->QOSCTRL.bit.FQOS = 2;
1c0: 7b98 ldrb r0, [r3, #14]
1c2: 43a8 bics r0, r5
1c4: 4304 orrs r4, r0
1c6: 739c strb r4, [r3, #14]
3 years ago
DMAC->QOSCTRL.bit.WRBQOS = 2;
1c8: 7b98 ldrb r0, [r3, #14]
1ca: 4388 bics r0, r1
1cc: 4302 orrs r2, r0
1ce: 739a strb r2, [r3, #14]
3 years ago
NVMCTRL->CTRLB.bit.MANW = 1;
1d0: 2380 movs r3, #128 ; 0x80
1d2: 4a10 ldr r2, [pc, #64] ; (214 <Reset_Handler+0xc4>)
1d4: 6851 ldr r1, [r2, #4]
1d6: 430b orrs r3, r1
1d8: 6053 str r3, [r2, #4]
3 years ago
__libc_init_array();
1da: 4b0f ldr r3, [pc, #60] ; (218 <Reset_Handler+0xc8>)
1dc: 4798 blx r3
3 years ago
main();
1de: 4b0f ldr r3, [pc, #60] ; (21c <Reset_Handler+0xcc>)
1e0: 4798 blx r3
3 years ago
while (1)
1e2: e7fe b.n 1e2 <Reset_Handler+0x92>
1e4: 0000069c .word 0x0000069c
1e8: 20000000 .word 0x20000000
1ec: 20000000 .word 0x20000000
1f0: 00000621 .word 0x00000621
1f4: 20000000 .word 0x20000000
1f8: 20000028 .word 0x20000028
1fc: 00000633 .word 0x00000633
200: 00000000 .word 0x00000000
204: e000ed00 .word 0xe000ed00
208: 410070fc .word 0x410070fc
20c: 41005000 .word 0x41005000
210: 41004800 .word 0x41004800
214: 41004000 .word 0x41004000
218: 000005d9 .word 0x000005d9
21c: 00000405 .word 0x00000405
00000220 <_pm_init>:
3 years ago
}
static inline void hri_pm_set_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CPUSEL.reg |= PM_CPUSEL_CPUDIV(mask);
220: 4b06 ldr r3, [pc, #24] ; (23c <_pm_init+0x1c>)
222: 7a1a ldrb r2, [r3, #8]
224: b2d2 uxtb r2, r2
226: 721a strb r2, [r3, #8]
3 years ago
}
static inline void hri_pm_set_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->APBASEL.reg |= PM_APBASEL_APBADIV(mask);
228: 7a5a ldrb r2, [r3, #9]
22a: b2d2 uxtb r2, r2
22c: 725a strb r2, [r3, #9]
3 years ago
}
static inline void hri_pm_set_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->APBBSEL.reg |= PM_APBBSEL_APBBDIV(mask);
22e: 7a9a ldrb r2, [r3, #10]
230: b2d2 uxtb r2, r2
232: 729a strb r2, [r3, #10]
3 years ago
}
static inline void hri_pm_set_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->APBCSEL.reg |= PM_APBCSEL_APBCDIV(mask);
234: 7ada ldrb r2, [r3, #11]
236: b2d2 uxtb r2, r2
238: 72da strb r2, [r3, #11]
3 years ago
{
hri_pm_set_CPUSEL_CPUDIV_bf(PM, CONF_CPU_DIV);
hri_pm_set_APBASEL_APBADIV_bf(PM, CONF_APBA_DIV);
hri_pm_set_APBBSEL_APBBDIV_bf(PM, CONF_APBB_DIV);
hri_pm_set_APBCSEL_APBCDIV_bf(PM, CONF_APBC_DIV);
}
23a: 4770 bx lr
23c: 40000400 .word 0x40000400
3 years ago
00000240 <_init_chip>:
3 years ago
}
static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
{
NVMCTRL_CRITICAL_SECTION_ENTER();
((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
240: 4b06 ldr r3, [pc, #24] ; (25c <_init_chip+0x1c>)
3 years ago
/**
* \brief Initialize the hardware abstraction layer
*/
void _init_chip(void)
{
242: b510 push {r4, lr}
244: 685a ldr r2, [r3, #4]
246: 605a str r2, [r3, #4]
3 years ago
hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
_pm_init();
248: 4b05 ldr r3, [pc, #20] ; (260 <_init_chip+0x20>)
24a: 4798 blx r3
3 years ago
_sysctrl_init_sources();
24c: 4b05 ldr r3, [pc, #20] ; (264 <_init_chip+0x24>)
24e: 4798 blx r3
3 years ago
#if _GCLK_INIT_1ST
_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
#endif
_sysctrl_init_referenced_generators();
250: 4b05 ldr r3, [pc, #20] ; (268 <_init_chip+0x28>)
252: 4798 blx r3
3 years ago
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
254: 20ff movs r0, #255 ; 0xff
256: 4b05 ldr r3, [pc, #20] ; (26c <_init_chip+0x2c>)
258: 4798 blx r3
3 years ago
#if CONF_DMAC_ENABLE
_pm_enable_bus_clock(PM_BUS_AHB, DMAC);
_pm_enable_bus_clock(PM_BUS_APBB, DMAC);
_dma_init();
#endif
}
25a: bd10 pop {r4, pc}
25c: 41004000 .word 0x41004000
260: 00000221 .word 0x00000221
264: 00000279 .word 0x00000279
268: 000002c1 .word 0x000002c1
26c: 000003e5 .word 0x000003e5
00000270 <assert>:
3 years ago
/**
* \brief Assert function
*/
void assert(const bool condition, const char *const file, const int line)
{
if (!(condition)) {
270: 2800 cmp r0, #0
272: d100 bne.n 276 <assert+0x6>
3 years ago
__asm("BKPT #0");
274: be00 bkpt 0x0000
3 years ago
}
(void)file;
(void)line;
}
276: 4770 bx lr
3 years ago
00000278 <_sysctrl_init_sources>:
3 years ago
}
static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_CALIB_bf(const void *const hw)
{
uint32_t tmp;
tmp = ((Sysctrl *)hw)->OSC8M.reg;
278: 4b0e ldr r3, [pc, #56] ; (2b4 <_sysctrl_init_sources+0x3c>)
3 years ago
hri_sysctrl_write_OSC8M_reg(hw,
SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) |
#if CONF_OSC8M_OVERWRITE_CALIBRATION == 1
SYSCTRL_OSC8M_CALIB(CONF_OSC8M_CALIB) |
#else
SYSCTRL_OSC8M_CALIB(calib) |
27a: 480f ldr r0, [pc, #60] ; (2b8 <_sysctrl_init_sources+0x40>)
27c: 6a19 ldr r1, [r3, #32]
}
static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_FRANGE_bf(const void *const hw)
{
uint32_t tmp;
tmp = ((Sysctrl *)hw)->OSC8M.reg;
27e: 6a1a ldr r2, [r3, #32]
280: 4001 ands r1, r0
3 years ago
SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) |
282: 0f92 lsrs r2, r2, #30
284: 0792 lsls r2, r2, #30
286: 430a orrs r2, r1
3 years ago
hri_sysctrl_write_OSC8M_reg(hw,
288: 490c ldr r1, [pc, #48] ; (2bc <_sysctrl_init_sources+0x44>)
28a: 430a orrs r2, r1
3 years ago
}
static inline void hri_sysctrl_write_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t data)
{
SYSCTRL_CRITICAL_SECTION_ENTER();
((Sysctrl *)hw)->OSC8M.reg = data;
28c: 621a str r2, [r3, #32]
3 years ago
((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
28e: 2202 movs r2, #2
290: 6999 ldr r1, [r3, #24]
292: 430a orrs r2, r1
3 years ago
tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos;
294: 211f movs r1, #31
3 years ago
((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
296: 619a str r2, [r3, #24]
3 years ago
tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
298: 7f1a ldrb r2, [r3, #28]
3 years ago
tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos;
29a: 400a ands r2, r1
3 years ago
((Sysctrl *)hw)->OSCULP32K.reg = data;
29c: 771a strb r2, [r3, #28]
3 years ago
return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) >> SYSCTRL_PCLKSR_OSC8MRDY_Pos;
29e: 391e subs r1, #30
2a0: 68da ldr r2, [r3, #12]
2a2: 08d2 lsrs r2, r2, #3
3 years ago
#endif
#endif
#if CONF_OSC8M_CONFIG == 1
#if CONF_OSC8M_ENABLE == 1
while (!hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(hw))
2a4: 420a tst r2, r1
2a6: d0fb beq.n 2a0 <_sysctrl_init_sources+0x28>
3 years ago
((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ONDEMAND;
2a8: 2280 movs r2, #128 ; 0x80
2aa: 6a19 ldr r1, [r3, #32]
2ac: 430a orrs r2, r1
2ae: 621a str r2, [r3, #32]
3 years ago
hri_sysctrl_set_OSC8M_ONDEMAND_bit(hw);
#endif
#endif
(void)calib, (void)hw;
}
2b0: 4770 bx lr
2b2: 46c0 nop ; (mov r8, r8)
2b4: 40000800 .word 0x40000800
2b8: 0fff0000 .word 0x0fff0000
2bc: 00000302 .word 0x00000302
3 years ago
000002c0 <_sysctrl_init_referenced_generators>:
3 years ago
((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
2c0: 2102 movs r1, #2
2c2: 4a02 ldr r2, [pc, #8] ; (2cc <_sysctrl_init_referenced_generators+0xc>)
2c4: 6993 ldr r3, [r2, #24]
2c6: 438b bics r3, r1
2c8: 6193 str r3, [r2, #24]
3 years ago
/* Disable after all possible configurations needs sync written. */
hri_sysctrl_clear_OSC32K_ENABLE_bit(hw);
#endif
(void)hw;
}
2ca: 4770 bx lr
2cc: 40000800 .word 0x40000800
3 years ago
000002d0 <usart_sync_write>:
3 years ago
* \param[in] length The number of bytes to write
*
* \return The number of bytes written.
*/
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
2d0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
2d2: 0006 movs r6, r0
2d4: 000d movs r5, r1
2d6: 0014 movs r4, r2
3 years ago
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
2d8: 2800 cmp r0, #0
2da: d004 beq.n 2e6 <usart_sync_write+0x16>
2dc: 1e08 subs r0, r1, #0
2de: d002 beq.n 2e6 <usart_sync_write+0x16>
2e0: 0010 movs r0, r2
2e2: 1e43 subs r3, r0, #1
2e4: 4198 sbcs r0, r3
2e6: 22f1 movs r2, #241 ; 0xf1
2e8: 4911 ldr r1, [pc, #68] ; (330 <usart_sync_write+0x60>)
2ea: 4b12 ldr r3, [pc, #72] ; (334 <usart_sync_write+0x64>)
2ec: 4798 blx r3
3 years ago
while (!_usart_sync_is_ready_to_send(&descr->device))
2ee: 0037 movs r7, r6
2f0: 4b11 ldr r3, [pc, #68] ; (338 <usart_sync_write+0x68>)
2f2: 3708 adds r7, #8
2f4: 0038 movs r0, r7
2f6: 9301 str r3, [sp, #4]
2f8: 4798 blx r3
2fa: 2800 cmp r0, #0
2fc: d0f7 beq.n 2ee <usart_sync_write+0x1e>
3 years ago
uint32_t offset = 0;
2fe: 2600 movs r6, #0
3 years ago
;
do {
_usart_sync_write_byte(&descr->device, buf[offset]);
300: 0038 movs r0, r7
302: 5da9 ldrb r1, [r5, r6]
304: 4b0d ldr r3, [pc, #52] ; (33c <usart_sync_write+0x6c>)
306: 4798 blx r3
3 years ago
while (!_usart_sync_is_ready_to_send(&descr->device))
308: 0038 movs r0, r7
30a: 9b01 ldr r3, [sp, #4]
30c: 4798 blx r3
30e: 2800 cmp r0, #0
310: d0fa beq.n 308 <usart_sync_write+0x38>
3 years ago
;
} while (++offset < length);
312: 3601 adds r6, #1
314: 42b4 cmp r4, r6
316: d8f3 bhi.n 300 <usart_sync_write+0x30>
318: 2501 movs r5, #1
31a: 2c00 cmp r4, #0
31c: d000 beq.n 320 <usart_sync_write+0x50>
31e: 0025 movs r5, r4
3 years ago
while (!_usart_sync_is_transmit_done(&descr->device))
320: 0038 movs r0, r7
322: 4b07 ldr r3, [pc, #28] ; (340 <usart_sync_write+0x70>)
324: 4798 blx r3
326: 2800 cmp r0, #0
328: d0fa beq.n 320 <usart_sync_write+0x50>
3 years ago
;
return (int32_t)offset;
}
32a: 0028 movs r0, r5
32c: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
32e: 46c0 nop ; (mov r8, r8)
330: 00000642 .word 0x00000642
334: 00000271 .word 0x00000271
338: 000005af .word 0x000005af
33c: 000005a1 .word 0x000005a1
340: 000005b9 .word 0x000005b9
00000344 <usart_sync_read>:
3 years ago
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
{
344: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
346: 0005 movs r5, r0
348: 0014 movs r4, r2
34a: 9101 str r1, [sp, #4]
3 years ago
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
34c: 2800 cmp r0, #0
34e: d004 beq.n 35a <usart_sync_read+0x16>
350: 1e08 subs r0, r1, #0
352: d002 beq.n 35a <usart_sync_read+0x16>
354: 0010 movs r0, r2
356: 1e43 subs r3, r0, #1
358: 4198 sbcs r0, r3
35a: 2286 movs r2, #134 ; 0x86
35c: 490c ldr r1, [pc, #48] ; (390 <usart_sync_read+0x4c>)
35e: 4b0d ldr r3, [pc, #52] ; (394 <usart_sync_read+0x50>)
360: 0052 lsls r2, r2, #1
362: 4798 blx r3
3 years ago
uint32_t offset = 0;
364: 2600 movs r6, #0
3 years ago
do {
while (!_usart_sync_is_byte_received(&descr->device))
366: 002f movs r7, r5
368: 3708 adds r7, #8
36a: 0038 movs r0, r7
36c: 4b0a ldr r3, [pc, #40] ; (398 <usart_sync_read+0x54>)
36e: 4798 blx r3
370: 2800 cmp r0, #0
372: d0f8 beq.n 366 <usart_sync_read+0x22>
3 years ago
;
buf[offset] = _usart_sync_read_byte(&descr->device);
374: 4b09 ldr r3, [pc, #36] ; (39c <usart_sync_read+0x58>)
376: 0038 movs r0, r7
378: 4798 blx r3
37a: 9b01 ldr r3, [sp, #4]
37c: 5598 strb r0, [r3, r6]
3 years ago
} while (++offset < length);
37e: 3601 adds r6, #1
380: 42b4 cmp r4, r6
382: d8f0 bhi.n 366 <usart_sync_read+0x22>
384: 2001 movs r0, #1
386: 2c00 cmp r4, #0
388: d000 beq.n 38c <usart_sync_read+0x48>
38a: 0020 movs r0, r4
3 years ago
return (int32_t)offset;
}
38c: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
38e: 46c0 nop ; (mov r8, r8)
390: 00000642 .word 0x00000642
394: 00000271 .word 0x00000271
398: 000005c3 .word 0x000005c3
39c: 000005a7 .word 0x000005a7
000003a0 <usart_sync_init>:
3 years ago
{
3a0: b570 push {r4, r5, r6, lr}
3a2: 0004 movs r4, r0
3a4: 000d movs r5, r1
3 years ago
ASSERT(descr && hw);
3a6: 2800 cmp r0, #0
3a8: d002 beq.n 3b0 <usart_sync_init+0x10>
3aa: 0008 movs r0, r1
3ac: 1e43 subs r3, r0, #1
3ae: 4198 sbcs r0, r3
3b0: 4907 ldr r1, [pc, #28] ; (3d0 <usart_sync_init+0x30>)
3b2: 4b08 ldr r3, [pc, #32] ; (3d4 <usart_sync_init+0x34>)
3b4: 2234 movs r2, #52 ; 0x34
3b6: 4798 blx r3
3 years ago
init_status = _usart_sync_init(&descr->device, hw);
3b8: 0020 movs r0, r4
3ba: 0029 movs r1, r5
3bc: 4b06 ldr r3, [pc, #24] ; (3d8 <usart_sync_init+0x38>)
3be: 3008 adds r0, #8
3c0: 4798 blx r3
3 years ago
if (init_status) {
3c2: 2800 cmp r0, #0
3c4: d103 bne.n 3ce <usart_sync_init+0x2e>
3 years ago
descr->io.read = usart_sync_read;
3c6: 4b05 ldr r3, [pc, #20] ; (3dc <usart_sync_init+0x3c>)
3c8: 6063 str r3, [r4, #4]
3 years ago
descr->io.write = usart_sync_write;
3ca: 4b05 ldr r3, [pc, #20] ; (3e0 <usart_sync_init+0x40>)
3cc: 6023 str r3, [r4, #0]
3 years ago
}
3ce: bd70 pop {r4, r5, r6, pc}
3d0: 00000642 .word 0x00000642
3d4: 00000271 .word 0x00000271
3d8: 00000579 .word 0x00000579
3dc: 00000345 .word 0x00000345
3e0: 000002d1 .word 0x000002d1
3 years ago
000003e4 <_gclk_init_generators_by_fref>:
3 years ago
void _gclk_init_generators_by_fref(uint32_t bm)
{
#if CONF_GCLK_GENERATOR_0_CONFIG == 1
if (bm & (1ul << 0)) {
3e4: 07c0 lsls r0, r0, #31
3e6: d509 bpl.n 3fc <_gclk_init_generators_by_fref+0x18>
3 years ago
}
static inline void hri_gclk_write_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENDIV.reg = data;
3e8: 2380 movs r3, #128 ; 0x80
3ea: 4a05 ldr r2, [pc, #20] ; (400 <_gclk_init_generators_by_fref+0x1c>)
3ec: 005b lsls r3, r3, #1
3ee: 6093 str r3, [r2, #8]
3 years ago
((Gclk *)hw)->GENCTRL.reg = data;
3f0: 2383 movs r3, #131 ; 0x83
3f2: 025b lsls r3, r3, #9
3f4: 6053 str r3, [r2, #4]
3 years ago
while (((const Gclk *)hw)->STATUS.bit.SYNCBUSY)
3f6: 7853 ldrb r3, [r2, #1]
3f8: 09db lsrs r3, r3, #7
3fa: d1fc bne.n 3f6 <_gclk_init_generators_by_fref+0x12>
3 years ago
| (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SRC | GCLK_GENCTRL_ID(8));
}
#endif
}
3fc: 4770 bx lr
3fe: 46c0 nop ; (mov r8, r8)
400: 40000c00 .word 0x40000c00
3 years ago
00000404 <main>:
3 years ago
#include <atmel_start.h>
int main(void)
{
404: b510 push {r4, lr}
3 years ago
/* Initializes MCU, drivers and middleware */
atmel_start_init();
406: 4b01 ldr r3, [pc, #4] ; (40c <main+0x8>)
408: 4798 blx r3
3 years ago
/* Replace with your application code */
while (1) {
40a: e7fe b.n 40a <main+0x6>
40c: 000005cd .word 0x000005cd
3 years ago
00000410 <USART_0_PORT_init>:
3 years ago
static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
bool value)
{
uint8_t tmp;
PORT_CRITICAL_SECTION_ENTER();
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
410: 4b0d ldr r3, [pc, #52] ; (448 <USART_0_PORT_init+0x38>)
3 years ago
tmp &= ~PORT_PINCFG_PMUXEN;
412: 2201 movs r2, #1
3 years ago
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
414: 0018 movs r0, r3
3 years ago
#include <hpl_pm_base.h>
struct usart_sync_descriptor USART_0;
void USART_0_PORT_init(void)
{
416: b530 push {r4, r5, lr}
418: 3044 adds r0, #68 ; 0x44
41a: 7801 ldrb r1, [r0, #0]
3 years ago
tmp &= ~PORT_PMUX_PMUXE_Msk;
41c: 240f movs r4, #15
3 years ago
tmp &= ~PORT_PINCFG_PMUXEN;
41e: 4391 bics r1, r2
3 years ago
tmp |= value << PORT_PINCFG_PMUXEN_Pos;
420: 4311 orrs r1, r2
3 years ago
((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
422: 7001 strb r1, [r0, #0]
3 years ago
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
424: 0019 movs r1, r3
3 years ago
tmp |= PORT_PMUX_PMUXE(data);
426: 2003 movs r0, #3
3 years ago
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
428: 3132 adds r1, #50 ; 0x32
42a: 780d ldrb r5, [r1, #0]
3 years ago
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
42c: 3345 adds r3, #69 ; 0x45
3 years ago
tmp &= ~PORT_PMUX_PMUXE_Msk;
42e: 43a5 bics r5, r4
3 years ago
tmp |= PORT_PMUX_PMUXE(data);
430: 4328 orrs r0, r5
3 years ago
((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
432: 7008 strb r0, [r1, #0]
3 years ago
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
434: 7818 ldrb r0, [r3, #0]
3 years ago
tmp &= ~PORT_PINCFG_PMUXEN;
436: 4390 bics r0, r2
3 years ago
tmp |= value << PORT_PINCFG_PMUXEN_Pos;
438: 4302 orrs r2, r0
3 years ago
((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
43a: 701a strb r2, [r3, #0]
tmp |= PORT_PMUX_PMUXO(data);
43c: 2330 movs r3, #48 ; 0x30
3 years ago
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
43e: 780a ldrb r2, [r1, #0]
3 years ago
tmp &= ~PORT_PMUX_PMUXO_Msk;
440: 4022 ands r2, r4
3 years ago
tmp |= PORT_PMUX_PMUXO(data);
442: 4313 orrs r3, r2
3 years ago
((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
444: 700b strb r3, [r1, #0]
3 years ago
gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0);
gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1);
}
446: bd30 pop {r4, r5, pc}
448: 41004400 .word 0x41004400
3 years ago
0000044c <USART_0_CLOCK_init>:
3 years ago
peripheral = (uint32_t)_pm_get_apbb_index(module);
PM->APBBMASK.reg |= 1 << peripheral;
}
break;
case PM_BUS_APBC:
PM->APBCMASK.reg |= 1 << peripheral;
44c: 2304 movs r3, #4
44e: 4a04 ldr r2, [pc, #16] ; (460 <USART_0_CLOCK_init+0x14>)
450: 6a11 ldr r1, [r2, #32]
452: 430b orrs r3, r1
454: 6213 str r3, [r2, #32]
3 years ago
((Gclk *)hw)->CLKCTRL.reg = data;
456: 4b03 ldr r3, [pc, #12] ; (464 <USART_0_CLOCK_init+0x18>)
458: 4a03 ldr r2, [pc, #12] ; (468 <USART_0_CLOCK_init+0x1c>)
45a: 805a strh r2, [r3, #2]
3 years ago
void USART_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, SERCOM0);
_gclk_enable_channel(SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC);
}
45c: 4770 bx lr
45e: 46c0 nop ; (mov r8, r8)
460: 40000400 .word 0x40000400
464: 40000c00 .word 0x40000c00
468: 00004014 .word 0x00004014
3 years ago
0000046c <USART_0_init>:
3 years ago
void USART_0_init(void)
{
46c: b510 push {r4, lr}
3 years ago
USART_0_CLOCK_init();
46e: 4b05 ldr r3, [pc, #20] ; (484 <USART_0_init+0x18>)
470: 4798 blx r3
3 years ago
usart_sync_init(&USART_0, SERCOM0, (void *)NULL);
472: 2200 movs r2, #0
474: 4904 ldr r1, [pc, #16] ; (488 <USART_0_init+0x1c>)
476: 4b05 ldr r3, [pc, #20] ; (48c <USART_0_init+0x20>)
478: 4805 ldr r0, [pc, #20] ; (490 <USART_0_init+0x24>)
47a: 4798 blx r3
3 years ago
USART_0_PORT_init();
47c: 4b05 ldr r3, [pc, #20] ; (494 <USART_0_init+0x28>)
47e: 4798 blx r3
3 years ago
}
480: bd10 pop {r4, pc}
482: 46c0 nop ; (mov r8, r8)
484: 0000044d .word 0x0000044d
488: 42000800 .word 0x42000800
48c: 000003a1 .word 0x000003a1
490: 2000001c .word 0x2000001c
494: 00000411 .word 0x00000411
3 years ago
00000498 <system_init>:
3 years ago
void system_init(void)
{
498: b510 push {r4, lr}
3 years ago
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
49a: 4b02 ldr r3, [pc, #8] ; (4a4 <system_init+0xc>)
49c: 4798 blx r3
3 years ago
init_mcu();
USART_0_init();
49e: 4b02 ldr r3, [pc, #8] ; (4a8 <system_init+0x10>)
4a0: 4798 blx r3
3 years ago
}
4a2: bd10 pop {r4, pc}
4a4: 00000241 .word 0x00000241
4a8: 0000046d .word 0x0000046d
000004ac <hri_sercomi2cm_wait_for_sync>:
while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
4ac: 69c3 ldr r3, [r0, #28]
4ae: 4219 tst r1, r3
4b0: d1fc bne.n 4ac <hri_sercomi2cm_wait_for_sync>
3 years ago
}
4b2: 4770 bx lr
3 years ago
000004b4 <hri_sercomi2cm_clear_CTRLA_ENABLE_bit>:
((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
4b4: 2202 movs r2, #2
3 years ago
{
4b6: b510 push {r4, lr}
((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
4b8: 6803 ldr r3, [r0, #0]
hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
4ba: 2103 movs r1, #3
((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
4bc: 4393 bics r3, r2
4be: 6003 str r3, [r0, #0]
hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
4c0: 4b01 ldr r3, [pc, #4] ; (4c8 <hri_sercomi2cm_clear_CTRLA_ENABLE_bit+0x14>)
4c2: 4798 blx r3
3 years ago
}
4c4: bd10 pop {r4, pc}
4c6: 46c0 nop ; (mov r8, r8)
4c8: 000004ad .word 0x000004ad
3 years ago
000004cc <hri_sercomi2cm_write_CTRLA_reg>:
3 years ago
{
4cc: b510 push {r4, lr}
((Sercom *)hw)->I2CM.CTRLA.reg = data;
4ce: 6001 str r1, [r0, #0]
hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
4d0: 4b01 ldr r3, [pc, #4] ; (4d8 <hri_sercomi2cm_write_CTRLA_reg+0xc>)
4d2: 2103 movs r1, #3
4d4: 4798 blx r3
3 years ago
}
4d6: bd10 pop {r4, pc}
4d8: 000004ad .word 0x000004ad
3 years ago
000004dc <_usart_init>:
3 years ago
{
4dc: b5f8 push {r3, r4, r5, r6, r7, lr}
3 years ago
return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10;
4de: 4b1b ldr r3, [pc, #108] ; (54c <_usart_init+0x70>)
3 years ago
{
4e0: 0004 movs r4, r0
3 years ago
return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10;
4e2: 18c3 adds r3, r0, r3
4e4: 0a9b lsrs r3, r3, #10
3 years ago
if (_usarts[i].number == sercom_offset) {
4e6: b2db uxtb r3, r3
4e8: 2b00 cmp r3, #0
4ea: d004 beq.n 4f6 <_usart_init+0x1a>
3 years ago
ASSERT(false);
4ec: 2000 movs r0, #0
4ee: 4918 ldr r1, [pc, #96] ; (550 <_usart_init+0x74>)
4f0: 4a18 ldr r2, [pc, #96] ; (554 <_usart_init+0x78>)
4f2: 4b19 ldr r3, [pc, #100] ; (558 <_usart_init+0x7c>)
4f4: 4798 blx r3
3 years ago
return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
4f6: 69e3 ldr r3, [r4, #28]
4f8: 4e18 ldr r6, [pc, #96] ; (55c <_usart_init+0x80>)
4fa: 4d19 ldr r5, [pc, #100] ; (560 <_usart_init+0x84>)
3 years ago
if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
4fc: 07db lsls r3, r3, #31
4fe: d410 bmi.n 522 <_usart_init+0x46>
3 years ago
tmp &= mask;
500: 2702 movs r7, #2
hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
502: 4b18 ldr r3, [pc, #96] ; (564 <_usart_init+0x88>)
504: 2103 movs r1, #3
506: 0020 movs r0, r4
508: 4798 blx r3
tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
50a: 6823 ldr r3, [r4, #0]
3 years ago
if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
50c: 423b tst r3, r7
50e: d005 beq.n 51c <_usart_init+0x40>
3 years ago
hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
510: 0020 movs r0, r4
512: 4b15 ldr r3, [pc, #84] ; (568 <_usart_init+0x8c>)
514: 4798 blx r3
3 years ago
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
516: 0039 movs r1, r7
518: 0020 movs r0, r4
51a: 47b0 blx r6
3 years ago
hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
51c: 2105 movs r1, #5
51e: 0020 movs r0, r4
520: 47a8 blx r5
3 years ago
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
522: 0020 movs r0, r4
524: 2101 movs r1, #1
526: 47b0 blx r6
hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a);
528: 0020 movs r0, r4
52a: 4910 ldr r1, [pc, #64] ; (56c <_usart_init+0x90>)
52c: 47a8 blx r5
((Sercom *)hw)->SPI.CTRLB.reg = data;
52e: 23c0 movs r3, #192 ; 0xc0
530: 029b lsls r3, r3, #10
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
532: 0020 movs r0, r4
((Sercom *)hw)->SPI.CTRLB.reg = data;
534: 6063 str r3, [r4, #4]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
536: 2107 movs r1, #7
538: 4b0d ldr r3, [pc, #52] ; (570 <_usart_init+0x94>)
53a: 4798 blx r3
3 years ago
((Sercom *)hw)->USART.RXPL.reg = data;
53c: 2000 movs r0, #0
3 years ago
((Sercom *)hw)->USART.BAUD.reg = data;
53e: 4b0d ldr r3, [pc, #52] ; (574 <_usart_init+0x98>)
540: 81a3 strh r3, [r4, #12]
3 years ago
((Sercom *)hw)->USART.RXPL.reg = data;
542: 73a0 strb r0, [r4, #14]
3 years ago
}
static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.DBGCTRL.reg = data;
544: 3430 adds r4, #48 ; 0x30
546: 7020 strb r0, [r4, #0]
3 years ago
}
548: bdf8 pop {r3, r4, r5, r6, r7, pc}
54a: 46c0 nop ; (mov r8, r8)
54c: bdfff800 .word 0xbdfff800
550: 0000065e .word 0x0000065e
554: 0000023a .word 0x0000023a
558: 00000271 .word 0x00000271
55c: 000004ad .word 0x000004ad
560: 000004cd .word 0x000004cd
564: 000004ad .word 0x000004ad
568: 000004b5 .word 0x000004b5
56c: 40100004 .word 0x40100004
570: 000004ad .word 0x000004ad
574: ffffd8ad .word 0xffffd8ad
00000578 <_usart_sync_init>:
3 years ago
{
578: b570 push {r4, r5, r6, lr}
57a: 0005 movs r5, r0
57c: 000c movs r4, r1
3 years ago
ASSERT(device);
57e: 22b4 movs r2, #180 ; 0xb4
580: 4904 ldr r1, [pc, #16] ; (594 <_usart_sync_init+0x1c>)
582: 2001 movs r0, #1
584: 4b04 ldr r3, [pc, #16] ; (598 <_usart_sync_init+0x20>)
586: 4798 blx r3
3 years ago
device->hw = hw;
588: 602c str r4, [r5, #0]
3 years ago
return _usart_init(hw);
58a: 0020 movs r0, r4
58c: 4b03 ldr r3, [pc, #12] ; (59c <_usart_sync_init+0x24>)
58e: 4798 blx r3
3 years ago
}
590: bd70 pop {r4, r5, r6, pc}
592: 46c0 nop ; (mov r8, r8)
594: 0000065e .word 0x0000065e
598: 00000271 .word 0x00000271
59c: 000004dd .word 0x000004dd
3 years ago
000005a0 <_usart_sync_write_byte>:
3 years ago
hri_sercomusart_write_DATA_reg(device->hw, data);
5a0: 6803 ldr r3, [r0, #0]
3 years ago
((Sercom *)hw)->USART.DATA.reg = data;
5a2: 8519 strh r1, [r3, #40] ; 0x28
3 years ago
}
5a4: 4770 bx lr
3 years ago
000005a6 <_usart_sync_read_byte>:
3 years ago
return hri_sercomusart_read_DATA_reg(device->hw);
5a6: 6803 ldr r3, [r0, #0]
3 years ago
return ((Sercom *)hw)->USART.DATA.reg;
5a8: 8d18 ldrh r0, [r3, #40] ; 0x28
5aa: b2c0 uxtb r0, r0
3 years ago
}
5ac: 4770 bx lr
3 years ago
000005ae <_usart_sync_is_ready_to_send>:
3 years ago
return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
5ae: 6803 ldr r3, [r0, #0]
3 years ago
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
5b0: 7e18 ldrb r0, [r3, #24]
5b2: 2301 movs r3, #1
5b4: 4018 ands r0, r3
3 years ago
}
5b6: 4770 bx lr
3 years ago
000005b8 <_usart_sync_is_transmit_done>:
3 years ago
return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
5b8: 6803 ldr r3, [r0, #0]
3 years ago
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
5ba: 7e18 ldrb r0, [r3, #24]
5bc: 0780 lsls r0, r0, #30
5be: 0fc0 lsrs r0, r0, #31
3 years ago
}
5c0: 4770 bx lr
3 years ago
000005c2 <_usart_sync_is_byte_received>:
3 years ago
return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
5c2: 6803 ldr r3, [r0, #0]
3 years ago
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
5c4: 7e18 ldrb r0, [r3, #24]
5c6: 0740 lsls r0, r0, #29
5c8: 0fc0 lsrs r0, r0, #31
3 years ago
}
5ca: 4770 bx lr
3 years ago
000005cc <atmel_start_init>:
3 years ago
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
5cc: b510 push {r4, lr}
3 years ago
system_init();
5ce: 4b01 ldr r3, [pc, #4] ; (5d4 <atmel_start_init+0x8>)
5d0: 4798 blx r3
3 years ago
}
5d2: bd10 pop {r4, pc}
5d4: 00000499 .word 0x00000499
000005d8 <__libc_init_array>:
5d8: b570 push {r4, r5, r6, lr}
5da: 2600 movs r6, #0
5dc: 4c0c ldr r4, [pc, #48] ; (610 <__libc_init_array+0x38>)
5de: 4d0d ldr r5, [pc, #52] ; (614 <__libc_init_array+0x3c>)
5e0: 1b64 subs r4, r4, r5
5e2: 10a4 asrs r4, r4, #2
5e4: 42a6 cmp r6, r4
5e6: d109 bne.n 5fc <__libc_init_array+0x24>
5e8: 2600 movs r6, #0
5ea: f000 f847 bl 67c <_init>
5ee: 4c0a ldr r4, [pc, #40] ; (618 <__libc_init_array+0x40>)
5f0: 4d0a ldr r5, [pc, #40] ; (61c <__libc_init_array+0x44>)
5f2: 1b64 subs r4, r4, r5
5f4: 10a4 asrs r4, r4, #2
5f6: 42a6 cmp r6, r4
5f8: d105 bne.n 606 <__libc_init_array+0x2e>
5fa: bd70 pop {r4, r5, r6, pc}
5fc: 00b3 lsls r3, r6, #2
5fe: 58eb ldr r3, [r5, r3]
600: 4798 blx r3
602: 3601 adds r6, #1
604: e7ee b.n 5e4 <__libc_init_array+0xc>
606: 00b3 lsls r3, r6, #2
608: 58eb ldr r3, [r5, r3]
60a: 4798 blx r3
60c: 3601 adds r6, #1
60e: e7f2 b.n 5f6 <__libc_init_array+0x1e>
610: 00000688 .word 0x00000688
614: 00000688 .word 0x00000688
618: 0000068c .word 0x0000068c
61c: 00000688 .word 0x00000688
00000620 <memcpy>:
620: 2300 movs r3, #0
622: b510 push {r4, lr}
624: 429a cmp r2, r3
626: d100 bne.n 62a <memcpy+0xa>
628: bd10 pop {r4, pc}
62a: 5ccc ldrb r4, [r1, r3]
62c: 54c4 strb r4, [r0, r3]
62e: 3301 adds r3, #1
630: e7f8 b.n 624 <memcpy+0x4>
00000632 <memset>:
632: 0003 movs r3, r0
634: 1882 adds r2, r0, r2
636: 4293 cmp r3, r2
638: d100 bne.n 63c <memset+0xa>
63a: 4770 bx lr
63c: 7019 strb r1, [r3, #0]
63e: 3301 adds r3, #1
640: e7f9 b.n 636 <memset+0x4>
642: 2e2e .short 0x2e2e
644: 6c61682f .word 0x6c61682f
648: 6372732f .word 0x6372732f
64c: 6c61682f .word 0x6c61682f
650: 6173755f .word 0x6173755f
654: 735f7472 .word 0x735f7472
658: 2e636e79 .word 0x2e636e79
65c: 0063 .short 0x0063
65e: 2e2e .short 0x2e2e
660: 6c70682f .word 0x6c70682f
664: 7265732f .word 0x7265732f
668: 2f6d6f63 .word 0x2f6d6f63
66c: 5f6c7068 .word 0x5f6c7068
670: 63726573 .word 0x63726573
674: 632e6d6f .word 0x632e6d6f
678: 00000000 .word 0x00000000
0000067c <_init>:
67c: b5f8 push {r3, r4, r5, r6, r7, lr}
67e: 46c0 nop ; (mov r8, r8)
680: bcf8 pop {r3, r4, r5, r6, r7}
682: bc08 pop {r3}
684: 469e mov lr, r3
686: 4770 bx lr
00000688 <__frame_dummy_init_array_entry>:
688: 0129 0000 )...
0000068c <_fini>:
68c: b5f8 push {r3, r4, r5, r6, r7, lr}
68e: 46c0 nop ; (mov r8, r8)
690: bcf8 pop {r3, r4, r5, r6, r7}
692: bc08 pop {r3}
694: 469e mov lr, r3
696: 4770 bx lr
00000698 <__do_global_dtors_aux_fini_array_entry>:
698: 00fd 0000 ....