linux: move to linux4microchip+fpga-2025.03

- Tweaked the pull urls
- Removed redundant patches

Signed-off-by: Lars Randers <lranders@mail.dk>

01_git_sync.sh

@@ -17,7 +17,7 @@ DT_BRANCH="v6.6.x-Beagle"
 DT_REPO="https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees.git"
 #DT_REPO="git@openbeagle.org:beagleboard/BeagleBoard-DeviceTrees.git"
 
-LINUX_BRANCH="linux4microchip+fpga-2024.09"
+LINUX_BRANCH="linux4microchip+fpga-2025.03"
 LINUX_REPO="https://github.com/linux4microchip/linux.git"
 #LINUX_REPO="https://openbeagle.org/beaglev-fire/beaglev-fire-linux.git"
 #LINUX_REPO="git@openbeagle.org:beaglev-fire/beaglev-fire-linux.git"

04_build_linux.sh

@@ -8,7 +8,6 @@ cd ./linux/
 
 if [ ! -f ./.patched ] ; then
 	if [ -f arch/riscv/configs/mpfs_defconfig ] ; then
-		git am ../patches/linux/linux-6.6.y/0002-PCIe-Change-controller-and-bridge-base-address.patch
 		git am ../patches/linux/0008-Add-wireless-regdb-regulatory-database-file.patch
 		git am ../patches/linux/linux-6.6.y/0011-can-mpfs_can-add-registration-string.patch
 		git am ../patches/linux/linux-6.6.y/0012-gpio-gpio-mpfs-add-registration-string.patch

patches/linux/linux-6.6.y/0002-PCIe-Change-controller-and-bridge-base-address.patch

@@ -1,27 +0,0 @@
-From 4c14a137c399cbdb29d121b6dcdc395976e38579 Mon Sep 17 00:00:00 2001
-From: vauban353 <vauban353@gmail.com>
-Date: Fri, 25 Oct 2024 09:17:26 +0000
-Subject: [PATCH] PCIe: Change controller and bridge base address.
-
----
- drivers/pci/controller/pcie-microchip-host.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
-index 4030a2bb0..1aa8aca7e 100644
---- a/drivers/pci/controller/pcie-microchip-host.c
-+++ b/drivers/pci/controller/pcie-microchip-host.c
-@@ -27,8 +27,8 @@
- #define MC_ATT_MASK				GENMASK_ULL(63, 31)
- 
- /* PCIe Bridge Phy and Controller Phy offsets */
--#define MC_PCIE1_BRIDGE_ADDR			0x00008000u
--#define MC_PCIE1_CTRL_ADDR			0x0000a000u
-+#define MC_PCIE1_BRIDGE_ADDR			0x00004000u
-+#define MC_PCIE1_CTRL_ADDR			0x00006000u
- 
- /* PCIe Bridge Phy Regs */
- #define PCIE_PCI_IRQ_DW0			0xa8
--- 
-2.39.2
-