cleanup: 03_build_u-boot.sh: better seperation between original and patched
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>default-cape-symlinks
Robert Nelson
1 year ago
parent
5268a7dee2
commit
35a6d71081
@ -1,32 +0,0 @@
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From 01d9d0ce7fc7f4c7adc8ec878d0be69ab23bcf9e Mon Sep 17 00:00:00 2001
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From: vauban353 <vauban353@gmail.com>
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Date: Sun, 16 Apr 2023 11:19:34 +0100
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Subject: [PATCH] Use MMUART0 for stdout.
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---
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arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
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index 09722a02a4..d6535df577 100644
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--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
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+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
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@@ -17,13 +17,13 @@
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"microchip,mpfs";
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aliases {
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- serial1 = &uart1;
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+ serial0 = &uart0;
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ethernet0 = &mac1;
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spi0 = &qspi;
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};
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chosen {
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- stdout-path = "serial1";
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+ stdout-path = "serial0";
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};
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cpus {
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--
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2.25.1
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@ -0,0 +1,215 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2021 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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*/
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/dts-v1/;
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#include "microchip-mpfs.dtsi"
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
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/ {
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model = "Microchip PolarFire-SoC Icicle Kit";
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compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
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"microchip,mpfs";
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aliases {
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serial1 = &uart1;
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ethernet0 = &mac1;
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spi0 = &qspi;
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};
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chosen {
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stdout-path = "serial1";
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};
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cpus {
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timebase-frequency = <RTCCLK_FREQ>;
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};
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kernel: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x4000000>;
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label = "kernel";
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};
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ddr_cached_low: memory@8a000000 {
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device_type = "memory";
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reg = <0x0 0x8a000000 0x0 0x8000000>;
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label = "cached-low";
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};
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ddr_non_cached_low: memory@c4000000 {
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device_type = "memory";
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reg = <0x0 0xc4000000 0x0 0x6000000>;
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label = "non-cached-low";
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};
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ddr_cached_high: memory@1022000000 {
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device_type = "memory";
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reg = <0x10 0x22000000 0x0 0x5e000000>;
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label = "cached-high";
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};
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ddr_non_cached_high: memory@1412000000 {
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device_type = "memory";
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reg = <0x14 0x12000000 0x0 0x10000000>;
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label = "non-cached-high";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hss: hss-buffer {
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compatible = "shared-dma-pool";
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reg = <0x10 0x3fc00000 0x0 0x400000>;
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no-map;
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};
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dma_non_cached_low: non-cached-low-buffer {
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compatible = "shared-dma-pool";
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size = <0x0 0x4000000>;
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no-map;
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linux,dma-default;
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alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>;
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dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>;
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};
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dma_non_cached_high: non-cached-high-buffer {
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compatible = "shared-dma-pool";
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size = <0x0 0x10000000>;
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no-map;
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linux,dma-default;
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alloc-ranges = <0x14 0x12000000 0x0 0x10000000>;
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dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>;
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};
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fabricbuf0ddrc: buffer@88000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x88000000 0x0 0x2000000>;
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no-map;
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};
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fabricbuf1ddrnc: buffer@c8000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xc8000000 0x0 0x2000000>;
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no-map;
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};
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fabricbuf2ddrncwcb: buffer@d8000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xd8000000 0x0 0x2000000>;
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no-map;
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};
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};
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udmabuf0 {
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compatible = "ikwzm,u-dma-buf";
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device-name = "udmabuf-ddr-c0";
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minor-number = <0>;
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size = <0x0 0x2000000>;
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memory-region = <&fabricbuf0ddrc>;
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sync-mode = <3>;
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};
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udmabuf1 {
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compatible = "ikwzm,u-dma-buf";
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device-name = "udmabuf-ddr-nc0";
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minor-number = <1>;
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size = <0x0 0x2000000>;
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memory-region = <&fabricbuf1ddrnc>;
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sync-mode = <3>;
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};
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udmabuf2 {
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compatible = "ikwzm,u-dma-buf";
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device-name = "udmabuf-ddr-nc-wcb0";
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minor-number = <2>;
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size = <0x0 0x2000000>;
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memory-region = <&fabricbuf2ddrncwcb>;
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sync-mode = <3>;
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};
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&uart1 {
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status = "okay";
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};
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&mmc {
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status = "okay";
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bus-width = <4>;
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disable-wp;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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pac193x: pac193x@10 {
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compatible = "microchip,pac1934";
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reg = <0x10>;
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samp-rate = <64>;
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status = "okay";
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ch1: channel0 {
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uohms-shunt-res = <10000>;
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rail-name = "VDDREG";
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channel_enabled;
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};
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ch2: channel1 {
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uohms-shunt-res = <10000>;
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rail-name = "VDDA25";
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channel_enabled;
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};
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ch3: channel2 {
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uohms-shunt-res = <10000>;
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rail-name = "VDD25";
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channel_enabled;
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};
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ch4: channel3 {
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uohms-shunt-res = <10000>;
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rail-name = "VDDA_REG";
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channel_enabled;
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};
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};
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};
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&mac1 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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phy1: ethernet-phy@9 {
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reg = <9>;
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};
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};
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&qspi {
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status = "okay";
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num-cs = <1>;
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flash0: spi-nand@0 {
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compatible = "spi-nand";
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reg = <0x0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <20000000>;
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spi-cpol;
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spi-cpha;
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};
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};
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@ -0,0 +1,77 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/sizes.h>
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
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/* Environment options */
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#if defined(CONFIG_CMD_DHCP)
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#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
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#else
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#define BOOT_TARGET_DEVICES_DHCP(func)
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#endif
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#if defined(CONFIG_CMD_MTD)
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# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
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#else
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# define BOOT_TARGET_DEVICES_QSPI(func)
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#endif
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#if defined(CONFIG_CMD_MMC)
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#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
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#else
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#define BOOT_TARGET_DEVICES_MMC(func)
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#endif
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#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
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"bootcmd_qspi=echo Trying to boot from QSPI...; "\
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"setenv scriptname boot.scr.uimg; " \
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"if mtd list; then setenv mtd_present true; " \
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"mtd read env ${scriptaddr} 0; " \
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"source ${scriptaddr}; setenv mtd_present; " \
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"fi\0 "
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#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
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"qspi "
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#define BOOT_TARGET_DEVICES(func) \
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BOOT_TARGET_DEVICES_QSPI(func)\
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BOOT_TARGET_DEVICES_MMC(func)\
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BOOT_TARGET_DEVICES_DHCP(func)
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#define BOOTENV_DESIGN_OVERLAYS \
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"design_overlays=" \
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"if test -n ${no_of_overlays}; then " \
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"setenv inc 1; " \
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"setenv idx 0; " \
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"fdt resize ${dtbo_size}; " \
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"while test $idx -ne ${no_of_overlays}; do " \
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"setenv dtbo_name dtbo_image${idx}; " \
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"setenv fdt_cmd \"fdt apply $\"$dtbo_name; " \
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"run fdt_cmd; " \
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"setexpr idx $inc + $idx; " \
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"done; " \
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"fi;\0 " \
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"scriptaddr=0x8e000000\0" \
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BOOTENV_DESIGN_OVERLAYS \
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BOOTENV \
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#endif /* __CONFIG_H */
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@ -0,0 +1,25 @@
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CONFIG_RISCV=y
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CONFIG_SYS_MALLOC_LEN=0x800000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ENV_SIZE=0x2000
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CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
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CONFIG_TARGET_MICROCHIP_ICICLE=y
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CONFIG_ARCH_RV64I=y
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CONFIG_RISCV_SMODE=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_SYS_LOAD_ADDR=0x80200000
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CONFIG_FIT=y
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_SYS_PROMPT="RISC-V # "
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_BOOTP_SEND_HOSTNAME=y
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CONFIG_DM_MTD=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:2m(payload),128k(env),119m(rootfs)"
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CONFIG_CMD_UBI=y
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CONFIG_CMD_UBIFS=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_WL_THRESHOLD=4096
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CONFIG_MTD_UBI_BEB_LIMIT=20
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CONFIG_OF_LIBFDT_OVERLAY=y
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