cleanup: 03_build_u-boot.sh: better seperation between original and patched

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

.gitignore

@@ -8,9 +8,9 @@ deploy/*-modules.tar.gz
 deploy/Image
 deploy/*.dtb
 deploy/debian*
-ignore/
+/ignore/
-mirror/
+/mirror/
-riscv-toolchain/
+/riscv-toolchain/
-hart-software-services/
+/hart-software-services/
-u-boot/
+/u-boot/
-linux/
+/linux/

03_build_u-boot.sh

@@ -7,28 +7,24 @@ CC=${CC:-"${wdir}/riscv-toolchain/bin/riscv64-linux-"}
 make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} distclean
 
 cd ./u-boot/
-#patch -p1 < ../patches/u-boot/0001-Use-MMUART0-for-stdout.patch
+#cp -v include/configs/microchip_mpfs_icicle.h ../patches/u-boot/original/
+#cp -v arch/riscv/dts/microchip-mpfs-icicle-kit.dts ../patches/u-boot/original/
+#cp -v configs/microchip_mpfs_icicle_defconfig ../patches/u-boot/original/
 #exit 2
-cp -v ../patches/u-boot/microchip_mpfs_icicle.h include/configs/microchip_mpfs_icicle.h
-cp -v ../patches/u-boot/microchip-mpfs-icicle-kit.dts arch/riscv/dts/
-cp -v ../patches/u-boot/microchip_mpfs_icicle_defconfig .config
-cd ../
 
-#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} microchip_mpfs_icicle
+cp -v ../patches/u-boot/beaglev-fire/microchip_mpfs_icicle.h include/configs/microchip_mpfs_icicle.h
-#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} olddefconfig
+cp -v ../patches/u-boot/beaglev-fire/microchip-mpfs-icicle-kit.dts arch/riscv/dts/
-#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} menuconfig
+cp -v ../patches/u-boot/beaglev-fire/microchip_mpfs_icicle_defconfig configs/microchip_mpfs_icicle_defconfig
-#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} savedefconfig
+cd ../
-#cp -v ./u-boot/defconfig ./u-boot/configs/microchip_mpfs_icicle_defconfig
-#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} distclean
 
-#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} microchip_mpfs_icicle_defconfig
+make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} microchip_mpfs_icicle_defconfig
 #make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} menuconfig
 
 make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} olddefconfig
 
 make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} savedefconfig
 cp -v ./u-boot/defconfig ./u-boot/configs/microchip_mpfs_icicle_defconfig
-cp -v ./u-boot/defconfig ./patches/u-boot/microchip_mpfs_icicle_defconfig
+cp -v ./u-boot/defconfig ./patches/u-boot/beaglev-fire/microchip_mpfs_icicle_defconfig
 
 echo "make -C u-boot -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} all"
 make -C u-boot -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} all
@@ -36,3 +32,4 @@ make -C u-boot -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} all
 cp -v ./u-boot/u-boot.bin ./deploy/
 cp -v ./u-boot/u-boot.bin ./deploy/src.bin
 
+#

patches/u-boot/0001-Use-MMUART0-for-stdout.patch

@@ -1,32 +0,0 @@
-From 01d9d0ce7fc7f4c7adc8ec878d0be69ab23bcf9e Mon Sep 17 00:00:00 2001
-From: vauban353 <vauban353@gmail.com>
-Date: Sun, 16 Apr 2023 11:19:34 +0100
-Subject: [PATCH] Use MMUART0 for stdout.
-
----
- arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
-index 09722a02a4..d6535df577 100644
---- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
-+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
-@@ -17,13 +17,13 @@
- 		     "microchip,mpfs";
- 
- 	aliases {
--		serial1 = &uart1;
-+		serial0 = &uart0;
- 		ethernet0 = &mac1;
- 		spi0 = &qspi;
- 	};
- 
- 	chosen {
--		stdout-path = "serial1";
-+		stdout-path = "serial0";
- 	};
- 
- 	cpus {
--- 
-2.25.1
-

patches/u-boot/original/microchip-mpfs-icicle-kit.dts

@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+/dts-v1/;
+
+#include "microchip-mpfs.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	model = "Microchip PolarFire-SoC Icicle Kit";
+	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+		     "microchip,mpfs";
+
+	aliases {
+		serial1 = &uart1;
+		ethernet0 = &mac1;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		stdout-path = "serial1";
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	kernel: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x4000000>;
+		label = "kernel";
+	};
+
+	ddr_cached_low: memory@8a000000 {
+		device_type = "memory";
+		reg = <0x0 0x8a000000 0x0 0x8000000>;
+		label = "cached-low";
+	};
+
+	ddr_non_cached_low: memory@c4000000 {
+		device_type = "memory";
+		reg = <0x0 0xc4000000 0x0 0x6000000>;
+		label = "non-cached-low";
+	};
+
+	ddr_cached_high: memory@1022000000 {
+		device_type = "memory";
+		reg = <0x10 0x22000000 0x0 0x5e000000>;
+		label = "cached-high";
+	};
+
+	ddr_non_cached_high: memory@1412000000 {
+		device_type = "memory";
+		reg = <0x14 0x12000000 0x0 0x10000000>;
+		label = "non-cached-high";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hss: hss-buffer {
+			compatible = "shared-dma-pool";
+			reg = <0x10 0x3fc00000 0x0 0x400000>;
+			no-map;
+		};
+
+		dma_non_cached_low: non-cached-low-buffer {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x4000000>;
+			no-map;
+			linux,dma-default;
+			alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>;
+			dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>;
+		};
+
+		dma_non_cached_high: non-cached-high-buffer {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x10000000>;
+			no-map;
+			linux,dma-default;
+			alloc-ranges = <0x14 0x12000000 0x0 0x10000000>;
+			dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>;
+		};
+
+		fabricbuf0ddrc: buffer@88000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x88000000 0x0 0x2000000>;
+			no-map;
+		};
+
+		fabricbuf1ddrnc: buffer@c8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0xc8000000 0x0 0x2000000>;
+			no-map;
+		};
+
+		fabricbuf2ddrncwcb: buffer@d8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0xd8000000 0x0 0x2000000>;
+			no-map;
+		};
+	};
+
+	udmabuf0 {
+		compatible = "ikwzm,u-dma-buf";
+		device-name = "udmabuf-ddr-c0";
+		minor-number = <0>;
+		size = <0x0 0x2000000>;
+		memory-region = <&fabricbuf0ddrc>;
+		sync-mode = <3>;
+	};
+
+	udmabuf1 {
+		compatible = "ikwzm,u-dma-buf";
+		device-name = "udmabuf-ddr-nc0";
+		minor-number = <1>;
+		size = <0x0 0x2000000>;
+		memory-region = <&fabricbuf1ddrnc>;
+		sync-mode = <3>;
+	};
+
+	udmabuf2 {
+		compatible = "ikwzm,u-dma-buf";
+		device-name = "udmabuf-ddr-nc-wcb0";
+		minor-number = <2>;
+		size = <0x0 0x2000000>;
+		memory-region = <&fabricbuf2ddrncwcb>;
+		sync-mode = <3>;
+	};
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&mmc {
+	status = "okay";
+	bus-width = <4>;
+	disable-wp;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	pac193x: pac193x@10 {
+		compatible = "microchip,pac1934";
+		reg = <0x10>;
+		samp-rate = <64>;
+		status = "okay";
+		ch1: channel0 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDDREG";
+			channel_enabled;
+		};
+		ch2: channel1 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDDA25";
+			channel_enabled;
+		};
+		ch3: channel2 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDD25";
+			channel_enabled;
+		};
+		ch4: channel3 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDDA_REG";
+			channel_enabled;
+		};
+	};
+};
+
+&mac1 {
+	status = "okay";
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	num-cs = <1>;
+	flash0: spi-nand@0 {
+		compatible = "spi-nand";
+		reg = <0x0>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <20000000>;
+		spi-cpol;
+		spi-cpha;
+	};
+};

patches/u-boot/original/microchip_mpfs_icicle.h

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_SDRAM_BASE       0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR     (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_BOOTM_LEN        SZ_64M
+
+#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
+
+/* Environment options */
+
+#if defined(CONFIG_CMD_DHCP)
+#define BOOT_TARGET_DEVICES_DHCP(func)	func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
+#if defined(CONFIG_CMD_MTD)
+# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+# define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#if defined(CONFIG_CMD_MMC)
+#define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+	"bootcmd_qspi=echo Trying to boot from QSPI...; "\
+			"setenv scriptname boot.scr.uimg; " \
+			"if mtd list; then setenv mtd_present true; " \
+			"mtd read env ${scriptaddr} 0; " \
+			"source ${scriptaddr}; setenv mtd_present; " \
+			"fi\0 "
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+	"qspi "
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_QSPI(func)\
+	BOOT_TARGET_DEVICES_MMC(func)\
+	BOOT_TARGET_DEVICES_DHCP(func)
+
+#define BOOTENV_DESIGN_OVERLAYS \
+	"design_overlays=" \
+	"if test -n ${no_of_overlays}; then " \
+		"setenv inc 1; " \
+		"setenv idx 0; " \
+		"fdt resize ${dtbo_size}; " \
+		"while test $idx -ne ${no_of_overlays}; do " \
+			"setenv dtbo_name dtbo_image${idx}; " \
+			"setenv fdt_cmd \"fdt apply $\"$dtbo_name; " \
+			"run fdt_cmd; " \
+			"setexpr idx $inc + $idx; " \
+		"done; " \
+	"fi;\0 " \
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"scriptaddr=0x8e000000\0" \
+	BOOTENV_DESIGN_OVERLAYS \
+	BOOTENV \
+
+#endif /* __CONFIG_H */

patches/u-boot/original/microchip_mpfs_icicle_defconfig

@@ -0,0 +1,25 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
+CONFIG_TARGET_MICROCHIP_ICICLE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:2m(payload),128k(env),119m(rootfs)"
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBIFS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_OF_LIBFDT_OVERLAY=y