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91 lines
3.9 KiB
C
91 lines
3.9 KiB
C
/**
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* \file
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*
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* \brief Component description for PAC
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_PAC_COMPONENT_
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#define _SAMD21_PAC_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR PAC */
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/* ========================================================================== */
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/** \addtogroup SAMD21_PAC Peripheral Access Controller */
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/*@{*/
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#define PAC_U2211
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#define REV_PAC 0x101
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/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t :1; /*!< bit: 0 Reserved */
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uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} PAC_WPCLR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */
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#define PAC_WPCLR_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
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#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
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#define PAC_WPCLR_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPCLR_WP_Pos)
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#define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
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#define PAC_WPCLR_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */
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/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t :1; /*!< bit: 0 Reserved */
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uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} PAC_WPSET_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */
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#define PAC_WPSET_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPSET reset_value) Write Protection Set */
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#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
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#define PAC_WPSET_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPSET_WP_Pos)
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#define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
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#define PAC_WPSET_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */
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/** \brief PAC hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
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__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
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} Pac;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAMD21_PAC_COMPONENT_ */
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