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86 lines
5.4 KiB
C
86 lines
5.4 KiB
C
/**
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* \file
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*
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* \brief Instance description for DSU
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_DSU_INSTANCE_
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#define _SAMD21_DSU_INSTANCE_
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/* ========== Register definition for DSU peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */
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#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */
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#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */
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#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */
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#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */
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#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */
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#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
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#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
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#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
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#define REG_DSU_ENTRY (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
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#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
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#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
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#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
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#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
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#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
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#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
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#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
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#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
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#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
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#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
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#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
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#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
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#else
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#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
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#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
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#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
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#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */
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#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */
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#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */
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#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
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#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
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#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
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#define REG_DSU_ENTRY (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
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#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
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#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
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#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
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#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
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#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
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#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
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#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
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#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
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#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
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#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
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#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
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#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for DSU peripheral ========== */
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#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register
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#endif /* _SAMD21_DSU_INSTANCE_ */
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