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Aquatic-Robotic-Courier/software/cfg/arc-v4.atstart

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format_version: '2'
name: USB CDC Echo
versions:
api: '1.0'
backend: 1.8.457
commit: c39d50a8c7c22fe58c921178843d3cbb666dc04b
content: unknown
content_pack_name: unknown
format: '2'
frontend: 1.8.457
packs_version_avr8: 1.0.1441
packs_version_qtouch: unknown
packs_version_sam: 1.0.1726
version_backend: 1.8.457
version_frontend: ''
board:
identifier: SAMD21XplainedPro
device: SAMD21J18A-AU
details: null
application:
definition: 'Atmel:Application_Examples:0.0.1::Application:USB_CDC_Echo:'
configuration: {}
middlewares:
USB_CHAPTER_9:
user_label: USB_CHAPTER_9
configuration: {}
definition: Atmel:USB:0.0.1::USB_Chapter_9
functionality: USB_Chapter_9
api: USB:Protocol:Core
dependencies: {}
USB_CLASS_CDC:
user_label: USB_CLASS_CDC
configuration: {}
definition: Atmel:USB:0.0.1::USB_Class_CDC
functionality: USB_Class_CDC
api: USB:Protocol:CDC
dependencies:
USB Chapter 9: USB_CHAPTER_9
USB_DEVICE_CORE:
user_label: USB_DEVICE_CORE
configuration:
usbd_hs_sp: false
definition: Atmel:USB:0.0.1::USB_Device_Core
functionality: USB_Device_Core
api: USB:Device:Core
dependencies:
USB Chapter 9: USB_CHAPTER_9
USB Device instance: TARGET_USB
USB_DEVICE_CDC_ACM:
user_label: USB_DEVICE_CDC_ACM
configuration:
usb_cdcd_acm_bcddevice: 256
usb_cdcd_acm_bcdusb: USB 2.0 version
usb_cdcd_acm_bconfigval: 1
usb_cdcd_acm_bmattri: Bus power supply, not support for remote wakeup
usb_cdcd_acm_bmaxpksz0: 64 bytes
usb_cdcd_acm_bmaxpower: 50
usb_cdcd_acm_bnumconfig: 1
usb_cdcd_acm_comm_baltset: 0
usb_cdcd_acm_comm_bifcnum: 0
usb_cdcd_acm_comm_iifc: 0
usb_cdcd_acm_comm_int_interval: 10
usb_cdcd_acm_comm_int_maxpksz: 64 bytes
usb_cdcd_acm_data_baltset: 0
usb_cdcd_acm_data_bifcnum: 1
usb_cdcd_acm_data_buckout_maxpksz: 64 bytes
usb_cdcd_acm_data_buckout_maxpksz_hs: 512 bytes
usb_cdcd_acm_data_builin_maxpksz: 64 bytes
usb_cdcd_acm_data_builin_maxpksz_hs: 512 bytes
usb_cdcd_acm_data_bulkin_epaddr: EndpointAddress = 0x81
usb_cdcd_acm_data_bulkout_epaddr: EndpointAddress = 0x01
usb_cdcd_acm_data_iifc: 0
usb_cdcd_acm_epaddr: EndpointAddress = 0x82
usb_cdcd_acm_iconfig_en: false
usb_cdcd_acm_iconfig_str: ''
usb_cdcd_acm_idproduct: 9220
usb_cdcd_acm_idvender: 1003
usb_cdcd_acm_imanufact_en: false
usb_cdcd_acm_imanufact_str: Atmel
usb_cdcd_acm_iproduct_en: false
usb_cdcd_acm_iproduct_str: CDC ACM Serial Bridge Demo
usb_cdcd_acm_iserialnum_en: false
usb_cdcd_acm_iserialnum_str: 123456789ABCDEF
usb_cdcd_acm_langid: '0x0409'
usb_cdcd_acm_str_en: false
definition: Atmel:USB:0.0.1::USB_Device_CDC_ACM
functionality: USB_Device_CDC_ACM
api: USB:Device:CDC_ACM
dependencies:
USB Device Stack Core Instance: USB_DEVICE_CORE
USB Class CDC: USB_CLASS_CDC
drivers:
GCLK:
user_label: GCLK
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21J18A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
functionality: System
api: HAL:HPL:GCLK
configuration:
$input: 48000000
$input_id: Digital Frequency Locked Loop (DFLL48M)
RESERVED_InputFreq: 48000000
RESERVED_InputFreq_id: Digital Frequency Locked Loop (DFLL48M)
_$freq_output_Generic clock generator 0: 8000000
_$freq_output_Generic clock generator 1: 8000000
_$freq_output_Generic clock generator 2: 32768
_$freq_output_Generic clock generator 3: 32768
_$freq_output_Generic clock generator 4: 32768
_$freq_output_Generic clock generator 5: 32768
_$freq_output_Generic clock generator 6: 32768
_$freq_output_Generic clock generator 7: 48000000
enable_gclk_gen_0: true
enable_gclk_gen_0__externalclock: 1000000
enable_gclk_gen_1: false
enable_gclk_gen_1__externalclock: 1000000
enable_gclk_gen_2: false
enable_gclk_gen_2__externalclock: 1000000
enable_gclk_gen_3: true
enable_gclk_gen_3__externalclock: 1000000
enable_gclk_gen_4: false
enable_gclk_gen_4__externalclock: 1000000
enable_gclk_gen_5: false
enable_gclk_gen_5__externalclock: 1000000
enable_gclk_gen_6: false
enable_gclk_gen_6__externalclock: 1000000
enable_gclk_gen_7: true
enable_gclk_gen_7__externalclock: 1000000
gclk_arch_gen_0_RUNSTDBY: false
gclk_arch_gen_0_enable: true
gclk_arch_gen_0_idc: false
gclk_arch_gen_0_oe: false
gclk_arch_gen_0_oov: false
gclk_arch_gen_1_RUNSTDBY: false
gclk_arch_gen_1_enable: false
gclk_arch_gen_1_idc: false
gclk_arch_gen_1_oe: false
gclk_arch_gen_1_oov: false
gclk_arch_gen_2_RUNSTDBY: false
gclk_arch_gen_2_enable: false
gclk_arch_gen_2_idc: false
gclk_arch_gen_2_oe: false
gclk_arch_gen_2_oov: false
gclk_arch_gen_3_RUNSTDBY: false
gclk_arch_gen_3_enable: true
gclk_arch_gen_3_idc: false
gclk_arch_gen_3_oe: false
gclk_arch_gen_3_oov: false
gclk_arch_gen_4_RUNSTDBY: false
gclk_arch_gen_4_enable: false
gclk_arch_gen_4_idc: false
gclk_arch_gen_4_oe: false
gclk_arch_gen_4_oov: false
gclk_arch_gen_5_RUNSTDBY: false
gclk_arch_gen_5_enable: false
gclk_arch_gen_5_idc: false
gclk_arch_gen_5_oe: false
gclk_arch_gen_5_oov: false
gclk_arch_gen_6_RUNSTDBY: false
gclk_arch_gen_6_enable: false
gclk_arch_gen_6_idc: false
gclk_arch_gen_6_oe: false
gclk_arch_gen_6_oov: false
gclk_arch_gen_7_RUNSTDBY: true
gclk_arch_gen_7_enable: true
gclk_arch_gen_7_idc: false
gclk_arch_gen_7_oe: false
gclk_arch_gen_7_oov: false
gclk_gen_0_div: 1
gclk_gen_0_div_sel: false
gclk_gen_0_oscillator: 8MHz Internal Oscillator (OSC8M)
gclk_gen_1_div: 1
gclk_gen_1_div_sel: false
gclk_gen_1_oscillator: 8MHz Internal Oscillator (OSC8M)
gclk_gen_2_div: 1
gclk_gen_2_div_sel: false
gclk_gen_2_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K)
gclk_gen_3_div: 1
gclk_gen_3_div_sel: false
gclk_gen_3_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
gclk_gen_4_div: 1
gclk_gen_4_div_sel: false
gclk_gen_4_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
gclk_gen_5_div: 1
gclk_gen_5_div_sel: false
gclk_gen_5_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K)
gclk_gen_6_div: 1
gclk_gen_6_div_sel: false
gclk_gen_6_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K)
gclk_gen_7_div: 1
gclk_gen_7_div_sel: false
gclk_gen_7_oscillator: Digital Frequency Locked Loop (DFLL48M)
optional_signals: []
variant: null
clocks:
domain_group: null
PM:
user_label: PM
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21J18A-AU::PM::driver_config_definition::PM::HAL:HPL:PM
functionality: System
api: HAL:HPL:PM
configuration:
$input: 8000000
$input_id: Generic clock generator 0
RESERVED_InputFreq: 8000000
RESERVED_InputFreq_id: Generic clock generator 0
_$freq_output_CPU: 8000000
apba_div: '1'
apbb_div: '1'
apbc_div: '1'
cpu_clock_source: Generic clock generator 0
cpu_div: '1'
enable_cpu_clock: true
nvm_wait_states: '0'
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: CPU
input: CPU
external: false
external_frequency: 0
configuration: {}
DMAC:
user_label: DMAC
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21J18A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
functionality: System
api: HAL:HPL:DMAC
configuration:
dmac_beatsize_0: 8-bit bus transfer
dmac_beatsize_1: 8-bit bus transfer
dmac_beatsize_10: 8-bit bus transfer
dmac_beatsize_11: 8-bit bus transfer
dmac_beatsize_12: 8-bit bus transfer
dmac_beatsize_13: 8-bit bus transfer
dmac_beatsize_14: 8-bit bus transfer
dmac_beatsize_15: 8-bit bus transfer
dmac_beatsize_2: 8-bit bus transfer
dmac_beatsize_3: 8-bit bus transfer
dmac_beatsize_4: 8-bit bus transfer
dmac_beatsize_5: 8-bit bus transfer
dmac_beatsize_6: 8-bit bus transfer
dmac_beatsize_7: 8-bit bus transfer
dmac_beatsize_8: 8-bit bus transfer
dmac_beatsize_9: 8-bit bus transfer
dmac_blockact_0: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_10: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_11: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_12: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_13: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_14: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_15: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_2: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_4: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_5: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_6: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_7: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_8: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_9: Channel will be disabled if it is the last block transfer in
the transaction
dmac_channel_0_settings: false
dmac_channel_10_settings: false
dmac_channel_11_settings: false
dmac_channel_12_settings: false
dmac_channel_13_settings: false
dmac_channel_14_settings: false
dmac_channel_15_settings: false
dmac_channel_1_settings: false
dmac_channel_2_settings: false
dmac_channel_3_settings: false
dmac_channel_4_settings: false
dmac_channel_5_settings: false
dmac_channel_6_settings: false
dmac_channel_7_settings: false
dmac_channel_8_settings: false
dmac_channel_9_settings: false
dmac_dbgrun: false
dmac_dstinc_0: false
dmac_dstinc_1: false
dmac_dstinc_10: false
dmac_dstinc_11: false
dmac_dstinc_12: false
dmac_dstinc_13: false
dmac_dstinc_14: false
dmac_dstinc_15: false
dmac_dstinc_2: false
dmac_dstinc_3: false
dmac_dstinc_4: false
dmac_dstinc_5: false
dmac_dstinc_6: false
dmac_dstinc_7: false
dmac_dstinc_8: false
dmac_dstinc_9: false
dmac_enable: false
dmac_enable_0: false
dmac_enable_1: false
dmac_enable_10: false
dmac_enable_11: false
dmac_enable_12: false
dmac_enable_13: false
dmac_enable_14: false
dmac_enable_15: false
dmac_enable_2: false
dmac_enable_3: false
dmac_enable_4: false
dmac_enable_5: false
dmac_enable_6: false
dmac_enable_7: false
dmac_enable_8: false
dmac_enable_9: false
dmac_evact_0: No action
dmac_evact_1: No action
dmac_evact_10: No action
dmac_evact_11: No action
dmac_evact_12: No action
dmac_evact_13: No action
dmac_evact_14: No action
dmac_evact_15: No action
dmac_evact_2: No action
dmac_evact_3: No action
dmac_evact_4: No action
dmac_evact_5: No action
dmac_evact_6: No action
dmac_evact_7: No action
dmac_evact_8: No action
dmac_evact_9: No action
dmac_evie_0: false
dmac_evie_1: false
dmac_evie_10: false
dmac_evie_11: false
dmac_evie_12: false
dmac_evie_13: false
dmac_evie_14: false
dmac_evie_15: false
dmac_evie_2: false
dmac_evie_3: false
dmac_evie_4: false
dmac_evie_5: false
dmac_evie_6: false
dmac_evie_7: false
dmac_evie_8: false
dmac_evie_9: false
dmac_evoe_0: false
dmac_evoe_1: false
dmac_evoe_10: false
dmac_evoe_11: false
dmac_evoe_12: false
dmac_evoe_13: false
dmac_evoe_14: false
dmac_evoe_15: false
dmac_evoe_2: false
dmac_evoe_3: false
dmac_evoe_4: false
dmac_evoe_5: false
dmac_evoe_6: false
dmac_evoe_7: false
dmac_evoe_8: false
dmac_evoe_9: false
dmac_evosel_0: Event generation disabled
dmac_evosel_1: Event generation disabled
dmac_evosel_10: Event generation disabled
dmac_evosel_11: Event generation disabled
dmac_evosel_12: Event generation disabled
dmac_evosel_13: Event generation disabled
dmac_evosel_14: Event generation disabled
dmac_evosel_15: Event generation disabled
dmac_evosel_2: Event generation disabled
dmac_evosel_3: Event generation disabled
dmac_evosel_4: Event generation disabled
dmac_evosel_5: Event generation disabled
dmac_evosel_6: Event generation disabled
dmac_evosel_7: Event generation disabled
dmac_evosel_8: Event generation disabled
dmac_evosel_9: Event generation disabled
dmac_lvl_0: Channel priority 0
dmac_lvl_1: Channel priority 0
dmac_lvl_10: Channel priority 0
dmac_lvl_11: Channel priority 0
dmac_lvl_12: Channel priority 0
dmac_lvl_13: Channel priority 0
dmac_lvl_14: Channel priority 0
dmac_lvl_15: Channel priority 0
dmac_lvl_2: Channel priority 0
dmac_lvl_3: Channel priority 0
dmac_lvl_4: Channel priority 0
dmac_lvl_5: Channel priority 0
dmac_lvl_6: Channel priority 0
dmac_lvl_7: Channel priority 0
dmac_lvl_8: Channel priority 0
dmac_lvl_9: Channel priority 0
dmac_lvlen0: false
dmac_lvlen1: false
dmac_lvlen2: false
dmac_lvlen3: false
dmac_lvlpri0: 0
dmac_lvlpri1: 0
dmac_lvlpri2: 0
dmac_lvlpri3: 0
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
dmac_srcinc_0: false
dmac_srcinc_1: false
dmac_srcinc_10: false
dmac_srcinc_11: false
dmac_srcinc_12: false
dmac_srcinc_13: false
dmac_srcinc_14: false
dmac_srcinc_15: false
dmac_srcinc_2: false
dmac_srcinc_3: false
dmac_srcinc_4: false
dmac_srcinc_5: false
dmac_srcinc_6: false
dmac_srcinc_7: false
dmac_srcinc_8: false
dmac_srcinc_9: false
dmac_stepsel_0: Step size settings apply to the destination address
dmac_stepsel_1: Step size settings apply to the destination address
dmac_stepsel_10: Step size settings apply to the destination address
dmac_stepsel_11: Step size settings apply to the destination address
dmac_stepsel_12: Step size settings apply to the destination address
dmac_stepsel_13: Step size settings apply to the destination address
dmac_stepsel_14: Step size settings apply to the destination address
dmac_stepsel_15: Step size settings apply to the destination address
dmac_stepsel_2: Step size settings apply to the destination address
dmac_stepsel_3: Step size settings apply to the destination address
dmac_stepsel_4: Step size settings apply to the destination address
dmac_stepsel_5: Step size settings apply to the destination address
dmac_stepsel_6: Step size settings apply to the destination address
dmac_stepsel_7: Step size settings apply to the destination address
dmac_stepsel_8: Step size settings apply to the destination address
dmac_stepsel_9: Step size settings apply to the destination address
dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_trifsrc_0: Only software/event triggers
dmac_trifsrc_1: Only software/event triggers
dmac_trifsrc_10: Only software/event triggers
dmac_trifsrc_11: Only software/event triggers
dmac_trifsrc_12: Only software/event triggers
dmac_trifsrc_13: Only software/event triggers
dmac_trifsrc_14: Only software/event triggers
dmac_trifsrc_15: Only software/event triggers
dmac_trifsrc_2: Only software/event triggers
dmac_trifsrc_3: Only software/event triggers
dmac_trifsrc_4: Only software/event triggers
dmac_trifsrc_5: Only software/event triggers
dmac_trifsrc_6: Only software/event triggers
dmac_trifsrc_7: Only software/event triggers
dmac_trifsrc_8: Only software/event triggers
dmac_trifsrc_9: Only software/event triggers
dmac_trigact_0: One trigger required for each block transfer
dmac_trigact_1: One trigger required for each block transfer
dmac_trigact_10: One trigger required for each block transfer
dmac_trigact_11: One trigger required for each block transfer
dmac_trigact_12: One trigger required for each block transfer
dmac_trigact_13: One trigger required for each block transfer
dmac_trigact_14: One trigger required for each block transfer
dmac_trigact_15: One trigger required for each block transfer
dmac_trigact_2: One trigger required for each block transfer
dmac_trigact_3: One trigger required for each block transfer
dmac_trigact_4: One trigger required for each block transfer
dmac_trigact_5: One trigger required for each block transfer
dmac_trigact_6: One trigger required for each block transfer
dmac_trigact_7: One trigger required for each block transfer
dmac_trigact_8: One trigger required for each block transfer
dmac_trigact_9: One trigger required for each block transfer
optional_signals: []
variant: null
clocks:
domain_group: null
SYSCTRL:
user_label: SYSCTRL
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21J18A-AU::SYSCTRL::driver_config_definition::SYSCTRL::HAL:HPL:SYSCTRL
functionality: System
api: HAL:HPL:SYSCTRL
configuration:
$input: 32768
$input_id: Generic clock generator 3
RESERVED_InputFreq: 32768
RESERVED_InputFreq_id: Generic clock generator 3
_$freq_output_8MHz Internal Oscillator (OSC8M): 8000000
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
_$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
_$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 47998976
dfll48m_arch_bplckc: false
dfll48m_arch_calibration: true
dfll48m_arch_ccdis: true
dfll48m_arch_coarse: 31
dfll48m_arch_enable: true
dfll48m_arch_fine: 512
dfll48m_arch_llaw: true
dfll48m_arch_ondemand: true
dfll48m_arch_qldis: false
dfll48m_arch_runstdby: false
dfll48m_arch_stable: false
dfll48m_arch_usbcrm: true
dfll48m_arch_waitlock: false
dfll48m_mode: Closed Loop Mode
dfll48m_mul: 48000
dfll48m_ref_clock: Generic clock generator 3
dfll_arch_cstep: 1
dfll_arch_fstep: 1
enable_dfll48m: true
enable_fdpll96m: false
enable_osc32k: false
enable_osc8m: true
enable_osculp32k: true
enable_xosc: false
enable_xosc32k: false
fdpll96m_arch_enable: false
fdpll96m_arch_lbypass: false
fdpll96m_arch_ondemand: true
fdpll96m_arch_runstdby: false
fdpll96m_clock_div: 0
fdpll96m_ldr: 1463
fdpll96m_ldrfrac: 13
fdpll96m_ref_clock: Generic clock generator 3
osc32k_arch_calib: 0
osc32k_arch_en1k: false
osc32k_arch_en32k: false
osc32k_arch_enable: false
osc32k_arch_ondemand: true
osc32k_arch_overwrite_calibration: false
osc32k_arch_runstdby: false
osc32k_arch_startup: 3 Clock Cycles (92us)
osc32k_arch_wrtlock: false
osc8m_arch_calib: 0
osc8m_arch_enable: true
osc8m_arch_ondemand: true
osc8m_arch_overwrite_calibration: false
osc8m_arch_runstdby: false
osc8m_presc: '1'
osculp32k_arch_calib: 0
osculp32k_arch_overwrite_calibration: false
osculp32k_arch_wrtlock: false
xosc32k_arch_aampen: false
xosc32k_arch_en1k: false
xosc32k_arch_en32k: false
xosc32k_arch_enable: false
xosc32k_arch_ondemand: true
xosc32k_arch_runstdby: false
xosc32k_arch_startup: 122 us
xosc32k_arch_wrtlock: false
xosc32k_arch_xtalen: false
xosc_arch_ampgc: false
xosc_arch_enable: false
xosc_arch_gain: 2Mhz
xosc_arch_ondemand: true
xosc_arch_runstdby: false
xosc_arch_startup: 31 us
xosc_arch_xtalen: false
xosc_frequency: 400000
optional_signals: []
variant: null
clocks:
domain_group: null
TARGET_USB:
user_label: TARGET_USB
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21J18A-AU::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device
functionality: USB
api: HAL:Driver:USB_Device
configuration:
usb_arch_ep0_cache: Cached by 64 bytes buffer
usb_arch_ep1_cache: Cached by 64 bytes buffer
usb_arch_ep2_cache: Cached by 64 bytes buffer
usb_arch_ep3_cache: Cached by 64 bytes buffer
usb_arch_ep4_cache: Cached by 64 bytes buffer
usb_arch_ep5_cache: Cached by 64 bytes buffer
usb_arch_ep6_cache: Cached by 64 bytes buffer
usb_arch_ep7_cache: Cached by 64 bytes buffer
usb_ep1_I_CACHE: No cache
usb_ep2_I_CACHE: No cache
usb_ep3_I_CACHE: No cache
usb_ep4_I_CACHE: No cache
usb_ep5_I_CACHE: No cache
usb_ep6_I_CACHE: No cache
usb_ep7_I_CACHE: No cache
usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02)
usbd_arch_speed: Full speed
usbd_num_ep_sp: Max possible (by "Max Endpoint Number" config)
optional_signals: []
variant:
specification: default
required_signals:
- name: USB/DM
pad: PA24
label: Data-
- name: USB/DP
pad: PA25
label: Data+
clocks:
domain_group:
nodes:
- name: USB
input: Generic clock generator 7
external: false
external_frequency: 0
configuration:
usb_gclk_selection: Generic clock generator 7
pads:
USB_DM:
name: PA24
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21J18A-AU::pad::PA24
mode: Advanced
user_label: USB_DM
configuration: null
USB_DP:
name: PA25
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21J18A-AU::pad::PA25
mode: Advanced
user_label: USB_DP
configuration: null
toolchain_options: []