laying down components for power

electrical/ARC-Brain/ARC-Brain.kicad_pcb

@@ -100,25 +100,25 @@
     (uvia_drill 0.1)
   )
 
-  (gr_arc (start 105.41 65.024) (end 106.426 65.024) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 611E8D40))
+  (gr_arc (start 143.51 65.024) (end 144.526 65.024) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 611E8D40))
   (gr_arc (start 82.042 65.024) (end 82.042 64.008) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 611E8D34))
   (gr_arc (start 82.042 113.792) (end 81.026 113.792) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 611E8D2A))
-  (gr_arc (start 105.41 113.792) (end 105.41 114.808) (angle -90) (layer Edge.Cuts) (width 0.05))
-  (gr_line (start 105.41 114.808) (end 82.042 114.808) (layer Edge.Cuts) (width 0.05) (tstamp 611E8C9E))
-  (gr_line (start 106.426 65.024) (end 106.426 113.792) (layer Edge.Cuts) (width 0.05))
-  (gr_line (start 82.042 64.008) (end 105.41 64.008) (layer Edge.Cuts) (width 0.05))
+  (gr_arc (start 143.51 113.792) (end 143.51 114.808) (angle -90) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 143.51 114.808) (end 82.042 114.808) (layer Edge.Cuts) (width 0.05) (tstamp 611E8C9E))
+  (gr_line (start 144.526 65.024) (end 144.526 113.792) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 82.042 64.008) (end 143.51 64.008) (layer Edge.Cuts) (width 0.05))
   (gr_line (start 81.026 65.024) (end 81.026 113.792) (layer Edge.Cuts) (width 0.05))
-  (dimension 25.4 (width 0.15) (layer Dwgs.User)
-    (gr_text "1.0000 in" (at 93.726 60.168) (layer Dwgs.User)
+  (dimension 63.5 (width 0.15) (layer Dwgs.User)
+    (gr_text "2.5000 in" (at 112.776 59.914) (layer Dwgs.User)
       (effects (font (size 1 1) (thickness 0.15)))
     )
-    (feature1 (pts (xy 106.426 64.008) (xy 106.426 60.881579)))
-    (feature2 (pts (xy 81.026 64.008) (xy 81.026 60.881579)))
-    (crossbar (pts (xy 81.026 61.468) (xy 106.426 61.468)))
-    (arrow1a (pts (xy 106.426 61.468) (xy 105.299496 62.054421)))
-    (arrow1b (pts (xy 106.426 61.468) (xy 105.299496 60.881579)))
-    (arrow2a (pts (xy 81.026 61.468) (xy 82.152504 62.054421)))
-    (arrow2b (pts (xy 81.026 61.468) (xy 82.152504 60.881579)))
+    (feature1 (pts (xy 144.526 64.008) (xy 144.526 60.627579)))
+    (feature2 (pts (xy 81.026 64.008) (xy 81.026 60.627579)))
+    (crossbar (pts (xy 81.026 61.214) (xy 144.526 61.214)))
+    (arrow1a (pts (xy 144.526 61.214) (xy 143.399496 61.800421)))
+    (arrow1b (pts (xy 144.526 61.214) (xy 143.399496 60.627579)))
+    (arrow2a (pts (xy 81.026 61.214) (xy 82.152504 61.800421)))
+    (arrow2b (pts (xy 81.026 61.214) (xy 82.152504 60.627579)))
   )
   (dimension 50.8 (width 0.15) (layer Dwgs.User)
     (gr_text "2.0000 in" (at 77.694001 89.408 270) (layer Dwgs.User)

electrical/ARC-Brain/ARC-Brain.kicad_pcb-bak

@@ -2,7 +2,7 @@
 
   (general
     (thickness 1.6)
-    (drawings 6)
+    (drawings 10)
     (tracks 0)
     (zones 0)
     (modules 0)
@@ -100,10 +100,14 @@
     (uvia_drill 0.1)
   )
 
-  (gr_line (start 106.426 114.808) (end 81.026 114.808) (layer Edge.Cuts) (width 0.05) (tstamp 611E8C9E))
-  (gr_line (start 106.426 64.008) (end 106.426 114.808) (layer Edge.Cuts) (width 0.05))
-  (gr_line (start 81.026 64.008) (end 106.426 64.008) (layer Edge.Cuts) (width 0.05))
-  (gr_line (start 81.026 64.008) (end 81.026 114.808) (layer Edge.Cuts) (width 0.05))
+  (gr_arc (start 105.41 65.024) (end 106.426 65.024) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 611E8D40))
+  (gr_arc (start 82.042 65.024) (end 82.042 64.008) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 611E8D34))
+  (gr_arc (start 82.042 113.792) (end 81.026 113.792) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 611E8D2A))
+  (gr_arc (start 105.41 113.792) (end 105.41 114.808) (angle -90) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 105.41 114.808) (end 82.042 114.808) (layer Edge.Cuts) (width 0.05) (tstamp 611E8C9E))
+  (gr_line (start 106.426 65.024) (end 106.426 113.792) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 82.042 64.008) (end 105.41 64.008) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 81.026 65.024) (end 81.026 113.792) (layer Edge.Cuts) (width 0.05))
   (dimension 25.4 (width 0.15) (layer Dwgs.User)
     (gr_text "1.0000 in" (at 93.726 60.168) (layer Dwgs.User)
       (effects (font (size 1 1) (thickness 0.15)))

electrical/ARC-Power/ARC-Power-cache.lib

@@ -21,11 +21,11 @@ X Pin_2 2 -200 -100 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Connector_Generic_Conn_02x04_Odd_Even
+# Connector_Generic_Conn_02x05_Odd_Even
 #
-DEF Connector_Generic_Conn_02x04_Odd_Even J 0 40 Y N 1 F N
-F0 "J" 50 200 50 H V C CNN
-F1 "Connector_Generic_Conn_02x04_Odd_Even" 50 -300 50 H V C CNN
+DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
+F0 "J" 50 300 50 H V C CNN
+F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
@@ -36,19 +36,23 @@ S -50 -195 0 -205 1 1 6 N
 S -50 -95 0 -105 1 1 6 N
 S -50 5 0 -5 1 1 6 N
 S -50 105 0 95 1 1 6 N
-S -50 150 150 -250 1 1 10 f
+S -50 205 0 195 1 1 6 N
+S -50 250 150 -250 1 1 10 f
 S 150 -195 100 -205 1 1 6 N
 S 150 -95 100 -105 1 1 6 N
 S 150 5 100 -5 1 1 6 N
 S 150 105 100 95 1 1 6 N
-X Pin_1 1 -200 100 150 R 50 50 1 1 P
-X Pin_2 2 300 100 150 L 50 50 1 1 P
-X Pin_3 3 -200 0 150 R 50 50 1 1 P
-X Pin_4 4 300 0 150 L 50 50 1 1 P
-X Pin_5 5 -200 -100 150 R 50 50 1 1 P
-X Pin_6 6 300 -100 150 L 50 50 1 1 P
-X Pin_7 7 -200 -200 150 R 50 50 1 1 P
-X Pin_8 8 300 -200 150 L 50 50 1 1 P
+S 150 205 100 195 1 1 6 N
+X Pin_1 1 -200 200 150 R 50 50 1 1 P
+X Pin_10 10 300 -200 150 L 50 50 1 1 P
+X Pin_2 2 300 200 150 L 50 50 1 1 P
+X Pin_3 3 -200 100 150 R 50 50 1 1 P
+X Pin_4 4 300 100 150 L 50 50 1 1 P
+X Pin_5 5 -200 0 150 R 50 50 1 1 P
+X Pin_6 6 300 0 150 L 50 50 1 1 P
+X Pin_7 7 -200 -100 150 R 50 50 1 1 P
+X Pin_8 8 300 -100 150 L 50 50 1 1 P
+X Pin_9 9 -200 -200 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
@@ -332,6 +336,22 @@ X D 3 0 200 100 D 50 50 1 1 B
 ENDDRAW
 ENDDEF
 #
+# power_+3.3V
+#
+DEF power_+3.3V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+3.3V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
 # power_+3V3
 #
 DEF power_+3V3 #PWR 0 0 Y Y 1 F P
@@ -339,7 +359,6 @@ F0 "#PWR" 0 -150 50 H I C CNN
 F1 "power_+3V3" 0 140 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
-ALIAS +3.3V
 DRAW
 P 2 0 1 0 -30 50 0 100 N
 P 2 0 1 0 0 0 0 100 N
@@ -378,20 +397,6 @@ X +BATT 1 0 0 0 U 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# power_-BATT
-#
-DEF power_-BATT #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -150 50 H I C CNN
-F1 "power_-BATT" 0 140 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 2 0 1 0 0 0 0 100 N
-P 4 0 1 0 30 50 -30 50 0 100 30 50 F
-X -BATT 1 0 0 0 U 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
 # power_GND
 #
 DEF power_GND #PWR 0 0 Y Y 1 F P

electrical/ARC-Power/ARC-Power.pro

@@ -1,29 +1,10 @@
-update=22/05/2015 07:44:53
+update=Thu 19 Aug 2021 01:51:40 PM CDT
 version=1
 last_client=kicad
 [general]
 version=1
 RootSch=
 BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
 [cvpcb]
 version=1
 NetIExt=net
@@ -31,3 +12,227 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.25
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25