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705 lines
26 KiB
Plaintext
705 lines
26 KiB
Plaintext
4 years ago
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format_version: '2'
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name: My Project
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versions:
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api: '1.0'
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backend: 1.8.457
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commit: c39d50a8c7c22fe58c921178843d3cbb666dc04b
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content: unknown
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content_pack_name: unknown
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format: '2'
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frontend: 1.8.449
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packs_version_avr8: 1.0.1441
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packs_version_qtouch: unknown
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packs_version_sam: 1.0.1726
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version_backend: 1.8.457
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version_frontend: ''
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board:
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identifier: CustomBoard
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device: SAMD21E18A-MF
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details: null
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application: null
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middlewares:
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USB_CHAPTER_9:
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user_label: USB_CHAPTER_9
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configuration: {}
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definition: Atmel:USB:0.0.1::USB_Chapter_9
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functionality: USB_Chapter_9
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api: USB:Protocol:Core
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dependencies: {}
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USB_CLASS_CDC:
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user_label: USB_CLASS_CDC
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configuration: {}
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definition: Atmel:USB:0.0.1::USB_Class_CDC
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functionality: USB_Class_CDC
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api: USB:Protocol:CDC
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dependencies:
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USB Chapter 9: USB_CHAPTER_9
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USB_DEVICE_STACK_CORE_INSTANCE:
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user_label: USB_DEVICE_STACK_CORE_INSTANCE
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configuration:
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usbd_hs_sp: false
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definition: Atmel:USB:0.0.1::USB_Device_Core
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functionality: USB_Device_Core
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api: USB:Device:Core
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dependencies:
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USB Chapter 9: USB_CHAPTER_9
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USB Device instance: USB_DEVICE_INSTANCE
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USB_DEVICE_CDC_ACM_0:
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user_label: USB_DEVICE_CDC_ACM_0
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configuration:
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usb_cdcd_acm_bcddevice: 256
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usb_cdcd_acm_bcdusb: USB 2.0 version
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usb_cdcd_acm_bconfigval: 1
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usb_cdcd_acm_bmattri: Bus power supply, not support for remote wakeup
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usb_cdcd_acm_bmaxpksz0: 64 bytes
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usb_cdcd_acm_bmaxpower: 50
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usb_cdcd_acm_bnumconfig: 1
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usb_cdcd_acm_comm_baltset: 0
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usb_cdcd_acm_comm_bifcnum: 0
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usb_cdcd_acm_comm_iifc: 0
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usb_cdcd_acm_comm_int_interval: 10
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usb_cdcd_acm_comm_int_maxpksz: 64 bytes
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usb_cdcd_acm_data_baltset: 0
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usb_cdcd_acm_data_bifcnum: 1
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usb_cdcd_acm_data_buckout_maxpksz: 64 bytes
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usb_cdcd_acm_data_buckout_maxpksz_hs: 512 bytes
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usb_cdcd_acm_data_builin_maxpksz: 64 bytes
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usb_cdcd_acm_data_builin_maxpksz_hs: 512 bytes
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usb_cdcd_acm_data_bulkin_epaddr: EndpointAddress = 0x81
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usb_cdcd_acm_data_bulkout_epaddr: EndpointAddress = 0x01
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usb_cdcd_acm_data_iifc: 0
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usb_cdcd_acm_epaddr: EndpointAddress = 0x82
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usb_cdcd_acm_iconfig_en: false
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usb_cdcd_acm_iconfig_str: ''
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usb_cdcd_acm_idproduct: 9220
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usb_cdcd_acm_idvender: 1003
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usb_cdcd_acm_imanufact_en: false
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usb_cdcd_acm_imanufact_str: Atmel
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usb_cdcd_acm_iproduct_en: false
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usb_cdcd_acm_iproduct_str: CDC ACM Serial Bridge Demo
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usb_cdcd_acm_iserialnum_en: false
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usb_cdcd_acm_iserialnum_str: 123456789ABCDEF
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usb_cdcd_acm_langid: '0x0409'
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usb_cdcd_acm_str_en: false
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definition: Atmel:USB:0.0.1::USB_Device_CDC_ACM
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functionality: USB_Device_CDC_ACM
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api: USB:Device:CDC_ACM
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dependencies:
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USB Device Stack Core Instance: USB_DEVICE_STACK_CORE_INSTANCE
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USB Class CDC: USB_CLASS_CDC
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drivers:
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GCLK:
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user_label: GCLK
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definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
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functionality: System
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api: HAL:HPL:GCLK
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configuration:
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$input: 32768
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$input_id: 32kHz External Crystal Oscillator (XOSC32K)
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RESERVED_InputFreq: 32768
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RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
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_$freq_output_Generic clock generator 0: 48005120
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_$freq_output_Generic clock generator 1: 32768
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_$freq_output_Generic clock generator 2: 400000
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_$freq_output_Generic clock generator 3: 400000
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_$freq_output_Generic clock generator 4: 400000
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_$freq_output_Generic clock generator 5: 400000
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_$freq_output_Generic clock generator 6: 400000
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_$freq_output_Generic clock generator 7: 400000
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enable_gclk_gen_0: true
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enable_gclk_gen_0__externalclock: 1000000
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enable_gclk_gen_1: true
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enable_gclk_gen_1__externalclock: 1000000
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enable_gclk_gen_2: false
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enable_gclk_gen_2__externalclock: 1000000
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enable_gclk_gen_3: false
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enable_gclk_gen_3__externalclock: 1000000
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enable_gclk_gen_4: false
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enable_gclk_gen_4__externalclock: 1000000
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enable_gclk_gen_5: false
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enable_gclk_gen_5__externalclock: 1000000
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enable_gclk_gen_6: false
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enable_gclk_gen_6__externalclock: 1000000
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enable_gclk_gen_7: false
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enable_gclk_gen_7__externalclock: 1000000
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gclk_arch_gen_0_RUNSTDBY: false
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gclk_arch_gen_0_enable: true
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gclk_arch_gen_0_idc: false
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gclk_arch_gen_0_oe: false
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gclk_arch_gen_0_oov: false
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gclk_arch_gen_1_RUNSTDBY: false
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gclk_arch_gen_1_enable: true
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gclk_arch_gen_1_idc: false
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gclk_arch_gen_1_oe: false
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gclk_arch_gen_1_oov: false
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gclk_arch_gen_2_RUNSTDBY: false
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gclk_arch_gen_2_enable: false
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gclk_arch_gen_2_idc: false
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gclk_arch_gen_2_oe: false
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gclk_arch_gen_2_oov: false
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gclk_arch_gen_3_RUNSTDBY: false
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gclk_arch_gen_3_enable: false
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gclk_arch_gen_3_idc: false
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gclk_arch_gen_3_oe: false
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gclk_arch_gen_3_oov: false
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gclk_arch_gen_4_RUNSTDBY: false
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gclk_arch_gen_4_enable: false
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gclk_arch_gen_4_idc: false
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gclk_arch_gen_4_oe: false
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gclk_arch_gen_4_oov: false
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gclk_arch_gen_5_RUNSTDBY: false
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gclk_arch_gen_5_enable: false
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gclk_arch_gen_5_idc: false
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gclk_arch_gen_5_oe: false
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gclk_arch_gen_5_oov: false
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gclk_arch_gen_6_RUNSTDBY: false
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gclk_arch_gen_6_enable: false
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gclk_arch_gen_6_idc: false
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gclk_arch_gen_6_oe: false
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gclk_arch_gen_6_oov: false
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gclk_arch_gen_7_RUNSTDBY: false
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gclk_arch_gen_7_enable: false
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gclk_arch_gen_7_idc: false
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gclk_arch_gen_7_oe: false
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gclk_arch_gen_7_oov: false
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gclk_gen_0_div: 1
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gclk_gen_0_div_sel: false
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gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
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gclk_gen_1_div: 1
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gclk_gen_1_div_sel: false
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gclk_gen_1_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
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gclk_gen_2_div: 1
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gclk_gen_2_div_sel: false
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gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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gclk_gen_3_div: 1
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gclk_gen_3_div_sel: false
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gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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gclk_gen_4_div: 1
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gclk_gen_4_div_sel: false
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gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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gclk_gen_5_div: 1
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gclk_gen_5_div_sel: false
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gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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gclk_gen_6_div: 1
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gclk_gen_6_div_sel: false
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gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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gclk_gen_7_div: 1
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gclk_gen_7_div_sel: false
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gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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optional_signals: []
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variant: null
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clocks:
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domain_group: null
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PM:
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user_label: PM
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definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::PM::driver_config_definition::PM::HAL:HPL:PM
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functionality: System
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api: HAL:HPL:PM
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configuration:
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$input: 48005120
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$input_id: Generic clock generator 0
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RESERVED_InputFreq: 48005120
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RESERVED_InputFreq_id: Generic clock generator 0
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_$freq_output_CPU: 48005120
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apba_div: '1'
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apbb_div: '1'
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apbc_div: '1'
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cpu_clock_source: Generic clock generator 0
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cpu_div: '1'
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enable_cpu_clock: true
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nvm_wait_states: '2'
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optional_signals: []
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variant: null
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clocks:
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domain_group:
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nodes:
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- name: CPU
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input: CPU
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external: false
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external_frequency: 0
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configuration: {}
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USART_0:
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user_label: USART_0
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definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::SERCOM3::driver_config_definition::UART::HAL:Driver:USART.Sync
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functionality: USART
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api: HAL:Driver:USART_Sync
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configuration:
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usart_advanced: false
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usart_arch_clock_mode: USART with internal clock
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usart_arch_cloden: false
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usart_arch_dbgstop: Keep running
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usart_arch_dord: LSB is transmitted first
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usart_arch_enc: No encoding
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usart_arch_fractional: 0
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usart_arch_ibon: false
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usart_arch_lin_slave_enable: Disable
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usart_arch_runstdby: false
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usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling)
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usart_arch_sampr: 16x arithmetic
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usart_arch_sfde: false
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usart_baud_rate: 115200
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usart_character_size: 8 bits
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usart_parity: No parity
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usart_rx_enable: true
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usart_stop_bit: One stop bit
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usart_tx_enable: true
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optional_signals: []
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variant:
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specification: TXPO=0, RXPO=1, CMODE=0
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required_signals:
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- name: SERCOM3/PAD/0
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pad: PA22
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label: TX
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- name: SERCOM3/PAD/1
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pad: PA23
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label: RX
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clocks:
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domain_group:
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nodes:
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- name: Core
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input: Generic clock generator 0
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external: false
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external_frequency: 0
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- name: Slow
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input: Generic clock generator 1
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external: false
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external_frequency: 0
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configuration:
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core_gclk_selection: Generic clock generator 0
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slow_gclk_selection: Generic clock generator 1
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DMAC:
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user_label: DMAC
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definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
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functionality: System
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api: HAL:HPL:DMAC
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configuration:
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dmac_beatsize_0: 8-bit bus transfer
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dmac_beatsize_1: 8-bit bus transfer
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dmac_beatsize_10: 8-bit bus transfer
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dmac_beatsize_11: 8-bit bus transfer
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dmac_beatsize_12: 8-bit bus transfer
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dmac_beatsize_13: 8-bit bus transfer
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dmac_beatsize_14: 8-bit bus transfer
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dmac_beatsize_15: 8-bit bus transfer
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dmac_beatsize_2: 8-bit bus transfer
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dmac_beatsize_3: 8-bit bus transfer
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dmac_beatsize_4: 8-bit bus transfer
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dmac_beatsize_5: 8-bit bus transfer
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dmac_beatsize_6: 8-bit bus transfer
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dmac_beatsize_7: 8-bit bus transfer
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dmac_beatsize_8: 8-bit bus transfer
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dmac_beatsize_9: 8-bit bus transfer
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dmac_blockact_0: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_1: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_10: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_11: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_12: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_13: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_14: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_15: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_2: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_3: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_4: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_5: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_6: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_7: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_8: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_9: Channel will be disabled if it is the last block transfer in
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the transaction
|
||
|
|
dmac_channel_0_settings: false
|
||
|
|
dmac_channel_10_settings: false
|
||
|
|
dmac_channel_11_settings: false
|
||
|
|
dmac_channel_12_settings: false
|
||
|
|
dmac_channel_13_settings: false
|
||
|
|
dmac_channel_14_settings: false
|
||
|
|
dmac_channel_15_settings: false
|
||
|
|
dmac_channel_1_settings: false
|
||
|
|
dmac_channel_2_settings: false
|
||
|
|
dmac_channel_3_settings: false
|
||
|
|
dmac_channel_4_settings: false
|
||
|
|
dmac_channel_5_settings: false
|
||
|
|
dmac_channel_6_settings: false
|
||
|
|
dmac_channel_7_settings: false
|
||
|
|
dmac_channel_8_settings: false
|
||
|
|
dmac_channel_9_settings: false
|
||
|
|
dmac_dbgrun: false
|
||
|
|
dmac_dstinc_0: false
|
||
|
|
dmac_dstinc_1: false
|
||
|
|
dmac_dstinc_10: false
|
||
|
|
dmac_dstinc_11: false
|
||
|
|
dmac_dstinc_12: false
|
||
|
|
dmac_dstinc_13: false
|
||
|
|
dmac_dstinc_14: false
|
||
|
|
dmac_dstinc_15: false
|
||
|
|
dmac_dstinc_2: false
|
||
|
|
dmac_dstinc_3: false
|
||
|
|
dmac_dstinc_4: false
|
||
|
|
dmac_dstinc_5: false
|
||
|
|
dmac_dstinc_6: false
|
||
|
|
dmac_dstinc_7: false
|
||
|
|
dmac_dstinc_8: false
|
||
|
|
dmac_dstinc_9: false
|
||
|
|
dmac_enable: false
|
||
|
|
dmac_enable_0: false
|
||
|
|
dmac_enable_1: false
|
||
|
|
dmac_enable_10: false
|
||
|
|
dmac_enable_11: false
|
||
|
|
dmac_enable_12: false
|
||
|
|
dmac_enable_13: false
|
||
|
|
dmac_enable_14: false
|
||
|
|
dmac_enable_15: false
|
||
|
|
dmac_enable_2: false
|
||
|
|
dmac_enable_3: false
|
||
|
|
dmac_enable_4: false
|
||
|
|
dmac_enable_5: false
|
||
|
|
dmac_enable_6: false
|
||
|
|
dmac_enable_7: false
|
||
|
|
dmac_enable_8: false
|
||
|
|
dmac_enable_9: false
|
||
|
|
dmac_evact_0: No action
|
||
|
|
dmac_evact_1: No action
|
||
|
|
dmac_evact_10: No action
|
||
|
|
dmac_evact_11: No action
|
||
|
|
dmac_evact_12: No action
|
||
|
|
dmac_evact_13: No action
|
||
|
|
dmac_evact_14: No action
|
||
|
|
dmac_evact_15: No action
|
||
|
|
dmac_evact_2: No action
|
||
|
|
dmac_evact_3: No action
|
||
|
|
dmac_evact_4: No action
|
||
|
|
dmac_evact_5: No action
|
||
|
|
dmac_evact_6: No action
|
||
|
|
dmac_evact_7: No action
|
||
|
|
dmac_evact_8: No action
|
||
|
|
dmac_evact_9: No action
|
||
|
|
dmac_evie_0: false
|
||
|
|
dmac_evie_1: false
|
||
|
|
dmac_evie_10: false
|
||
|
|
dmac_evie_11: false
|
||
|
|
dmac_evie_12: false
|
||
|
|
dmac_evie_13: false
|
||
|
|
dmac_evie_14: false
|
||
|
|
dmac_evie_15: false
|
||
|
|
dmac_evie_2: false
|
||
|
|
dmac_evie_3: false
|
||
|
|
dmac_evie_4: false
|
||
|
|
dmac_evie_5: false
|
||
|
|
dmac_evie_6: false
|
||
|
|
dmac_evie_7: false
|
||
|
|
dmac_evie_8: false
|
||
|
|
dmac_evie_9: false
|
||
|
|
dmac_evoe_0: false
|
||
|
|
dmac_evoe_1: false
|
||
|
|
dmac_evoe_10: false
|
||
|
|
dmac_evoe_11: false
|
||
|
|
dmac_evoe_12: false
|
||
|
|
dmac_evoe_13: false
|
||
|
|
dmac_evoe_14: false
|
||
|
|
dmac_evoe_15: false
|
||
|
|
dmac_evoe_2: false
|
||
|
|
dmac_evoe_3: false
|
||
|
|
dmac_evoe_4: false
|
||
|
|
dmac_evoe_5: false
|
||
|
|
dmac_evoe_6: false
|
||
|
|
dmac_evoe_7: false
|
||
|
|
dmac_evoe_8: false
|
||
|
|
dmac_evoe_9: false
|
||
|
|
dmac_evosel_0: Event generation disabled
|
||
|
|
dmac_evosel_1: Event generation disabled
|
||
|
|
dmac_evosel_10: Event generation disabled
|
||
|
|
dmac_evosel_11: Event generation disabled
|
||
|
|
dmac_evosel_12: Event generation disabled
|
||
|
|
dmac_evosel_13: Event generation disabled
|
||
|
|
dmac_evosel_14: Event generation disabled
|
||
|
|
dmac_evosel_15: Event generation disabled
|
||
|
|
dmac_evosel_2: Event generation disabled
|
||
|
|
dmac_evosel_3: Event generation disabled
|
||
|
|
dmac_evosel_4: Event generation disabled
|
||
|
|
dmac_evosel_5: Event generation disabled
|
||
|
|
dmac_evosel_6: Event generation disabled
|
||
|
|
dmac_evosel_7: Event generation disabled
|
||
|
|
dmac_evosel_8: Event generation disabled
|
||
|
|
dmac_evosel_9: Event generation disabled
|
||
|
|
dmac_lvl_0: Channel priority 0
|
||
|
|
dmac_lvl_1: Channel priority 0
|
||
|
|
dmac_lvl_10: Channel priority 0
|
||
|
|
dmac_lvl_11: Channel priority 0
|
||
|
|
dmac_lvl_12: Channel priority 0
|
||
|
|
dmac_lvl_13: Channel priority 0
|
||
|
|
dmac_lvl_14: Channel priority 0
|
||
|
|
dmac_lvl_15: Channel priority 0
|
||
|
|
dmac_lvl_2: Channel priority 0
|
||
|
|
dmac_lvl_3: Channel priority 0
|
||
|
|
dmac_lvl_4: Channel priority 0
|
||
|
|
dmac_lvl_5: Channel priority 0
|
||
|
|
dmac_lvl_6: Channel priority 0
|
||
|
|
dmac_lvl_7: Channel priority 0
|
||
|
|
dmac_lvl_8: Channel priority 0
|
||
|
|
dmac_lvl_9: Channel priority 0
|
||
|
|
dmac_lvlen0: false
|
||
|
|
dmac_lvlen1: false
|
||
|
|
dmac_lvlen2: false
|
||
|
|
dmac_lvlen3: false
|
||
|
|
dmac_lvlpri0: 0
|
||
|
|
dmac_lvlpri1: 0
|
||
|
|
dmac_lvlpri2: 0
|
||
|
|
dmac_lvlpri3: 0
|
||
|
|
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
|
||
|
|
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
|
||
|
|
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
|
||
|
|
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
|
||
|
|
dmac_srcinc_0: false
|
||
|
|
dmac_srcinc_1: false
|
||
|
|
dmac_srcinc_10: false
|
||
|
|
dmac_srcinc_11: false
|
||
|
|
dmac_srcinc_12: false
|
||
|
|
dmac_srcinc_13: false
|
||
|
|
dmac_srcinc_14: false
|
||
|
|
dmac_srcinc_15: false
|
||
|
|
dmac_srcinc_2: false
|
||
|
|
dmac_srcinc_3: false
|
||
|
|
dmac_srcinc_4: false
|
||
|
|
dmac_srcinc_5: false
|
||
|
|
dmac_srcinc_6: false
|
||
|
|
dmac_srcinc_7: false
|
||
|
|
dmac_srcinc_8: false
|
||
|
|
dmac_srcinc_9: false
|
||
|
|
dmac_stepsel_0: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_1: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_10: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_11: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_12: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_13: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_14: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_15: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_2: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_3: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_4: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_5: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_6: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_7: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_8: Step size settings apply to the destination address
|
||
|
|
dmac_stepsel_9: Step size settings apply to the destination address
|
||
|
|
dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||
|
|
dmac_trifsrc_0: Only software/event triggers
|
||
|
|
dmac_trifsrc_1: Only software/event triggers
|
||
|
|
dmac_trifsrc_10: Only software/event triggers
|
||
|
|
dmac_trifsrc_11: Only software/event triggers
|
||
|
|
dmac_trifsrc_12: Only software/event triggers
|
||
|
|
dmac_trifsrc_13: Only software/event triggers
|
||
|
|
dmac_trifsrc_14: Only software/event triggers
|
||
|
|
dmac_trifsrc_15: Only software/event triggers
|
||
|
|
dmac_trifsrc_2: Only software/event triggers
|
||
|
|
dmac_trifsrc_3: Only software/event triggers
|
||
|
|
dmac_trifsrc_4: Only software/event triggers
|
||
|
|
dmac_trifsrc_5: Only software/event triggers
|
||
|
|
dmac_trifsrc_6: Only software/event triggers
|
||
|
|
dmac_trifsrc_7: Only software/event triggers
|
||
|
|
dmac_trifsrc_8: Only software/event triggers
|
||
|
|
dmac_trifsrc_9: Only software/event triggers
|
||
|
|
dmac_trigact_0: One trigger required for each block transfer
|
||
|
|
dmac_trigact_1: One trigger required for each block transfer
|
||
|
|
dmac_trigact_10: One trigger required for each block transfer
|
||
|
|
dmac_trigact_11: One trigger required for each block transfer
|
||
|
|
dmac_trigact_12: One trigger required for each block transfer
|
||
|
|
dmac_trigact_13: One trigger required for each block transfer
|
||
|
|
dmac_trigact_14: One trigger required for each block transfer
|
||
|
|
dmac_trigact_15: One trigger required for each block transfer
|
||
|
|
dmac_trigact_2: One trigger required for each block transfer
|
||
|
|
dmac_trigact_3: One trigger required for each block transfer
|
||
|
|
dmac_trigact_4: One trigger required for each block transfer
|
||
|
|
dmac_trigact_5: One trigger required for each block transfer
|
||
|
|
dmac_trigact_6: One trigger required for each block transfer
|
||
|
|
dmac_trigact_7: One trigger required for each block transfer
|
||
|
|
dmac_trigact_8: One trigger required for each block transfer
|
||
|
|
dmac_trigact_9: One trigger required for each block transfer
|
||
|
|
optional_signals: []
|
||
|
|
variant: null
|
||
|
|
clocks:
|
||
|
|
domain_group: null
|
||
|
|
SYSCTRL:
|
||
|
|
user_label: SYSCTRL
|
||
|
|
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::SYSCTRL::driver_config_definition::SYSCTRL::HAL:HPL:SYSCTRL
|
||
|
|
functionality: System
|
||
|
|
api: HAL:HPL:SYSCTRL
|
||
|
|
configuration:
|
||
|
|
$input: 32768
|
||
|
|
$input_id: Generic clock generator 1
|
||
|
|
RESERVED_InputFreq: 32768
|
||
|
|
RESERVED_InputFreq_id: Generic clock generator 1
|
||
|
|
_$freq_output_8MHz Internal Oscillator (OSC8M): 1000000
|
||
|
|
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48005120
|
||
|
|
_$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): '400000'
|
||
|
|
_$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 585925000
|
||
|
|
dfll48m_arch_bplckc: false
|
||
|
|
dfll48m_arch_calibration: true
|
||
|
|
dfll48m_arch_ccdis: false
|
||
|
|
dfll48m_arch_coarse: 31
|
||
|
|
dfll48m_arch_enable: true
|
||
|
|
dfll48m_arch_fine: 512
|
||
|
|
dfll48m_arch_llaw: false
|
||
|
|
dfll48m_arch_ondemand: true
|
||
|
|
dfll48m_arch_qldis: false
|
||
|
|
dfll48m_arch_runstdby: false
|
||
|
|
dfll48m_arch_stable: false
|
||
|
|
dfll48m_arch_usbcrm: false
|
||
|
|
dfll48m_arch_waitlock: true
|
||
|
|
dfll48m_mode: Closed Loop Mode
|
||
|
|
dfll48m_mul: 1465
|
||
|
|
dfll48m_ref_clock: Generic clock generator 1
|
||
|
|
dfll_arch_cstep: 1
|
||
|
|
dfll_arch_fstep: 1
|
||
|
|
enable_dfll48m: true
|
||
|
|
enable_fdpll96m: false
|
||
|
|
enable_osc32k: false
|
||
|
|
enable_osc8m: false
|
||
|
|
enable_osculp32k: true
|
||
|
|
enable_xosc: false
|
||
|
|
enable_xosc32k: true
|
||
|
|
fdpll96m_arch_enable: false
|
||
|
|
fdpll96m_arch_lbypass: false
|
||
|
|
fdpll96m_arch_ondemand: true
|
||
|
|
fdpll96m_arch_runstdby: false
|
||
|
|
fdpll96m_clock_div: 0
|
||
|
|
fdpll96m_ldr: 1463
|
||
|
|
fdpll96m_ldrfrac: 13
|
||
|
|
fdpll96m_ref_clock: Generic clock generator 3
|
||
|
|
osc32k_arch_calib: 0
|
||
|
|
osc32k_arch_en1k: false
|
||
|
|
osc32k_arch_en32k: false
|
||
|
|
osc32k_arch_enable: false
|
||
|
|
osc32k_arch_ondemand: true
|
||
|
|
osc32k_arch_overwrite_calibration: false
|
||
|
|
osc32k_arch_runstdby: false
|
||
|
|
osc32k_arch_startup: 3 Clock Cycles (92us)
|
||
|
|
osc32k_arch_wrtlock: false
|
||
|
|
osc8m_arch_calib: 0
|
||
|
|
osc8m_arch_enable: false
|
||
|
|
osc8m_arch_ondemand: true
|
||
|
|
osc8m_arch_overwrite_calibration: false
|
||
|
|
osc8m_arch_runstdby: false
|
||
|
|
osc8m_presc: '8'
|
||
|
|
osculp32k_arch_calib: 0
|
||
|
|
osculp32k_arch_overwrite_calibration: false
|
||
|
|
osculp32k_arch_wrtlock: false
|
||
|
|
xosc32k_arch_aampen: false
|
||
|
|
xosc32k_arch_en1k: false
|
||
|
|
xosc32k_arch_en32k: true
|
||
|
|
xosc32k_arch_enable: true
|
||
|
|
xosc32k_arch_ondemand: false
|
||
|
|
xosc32k_arch_runstdby: false
|
||
|
|
xosc32k_arch_startup: 122 us
|
||
|
|
xosc32k_arch_wrtlock: false
|
||
|
|
xosc32k_arch_xtalen: true
|
||
|
|
xosc_arch_ampgc: false
|
||
|
|
xosc_arch_enable: false
|
||
|
|
xosc_arch_gain: 2Mhz
|
||
|
|
xosc_arch_ondemand: true
|
||
|
|
xosc_arch_runstdby: false
|
||
|
|
xosc_arch_startup: 31 us
|
||
|
|
xosc_arch_xtalen: false
|
||
|
|
xosc_frequency: 400000
|
||
|
|
optional_signals: []
|
||
|
|
variant: null
|
||
|
|
clocks:
|
||
|
|
domain_group: null
|
||
|
|
USB_DEVICE_INSTANCE:
|
||
|
|
user_label: USB_DEVICE_INSTANCE
|
||
|
|
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device
|
||
|
|
functionality: USB
|
||
|
|
api: HAL:Driver:USB_Device
|
||
|
|
configuration:
|
||
|
|
usb_arch_ep0_cache: Cached by 64 bytes buffer
|
||
|
|
usb_arch_ep1_cache: Cached by 64 bytes buffer
|
||
|
|
usb_arch_ep2_cache: Cached by 64 bytes buffer
|
||
|
|
usb_arch_ep3_cache: Cached by 64 bytes buffer
|
||
|
|
usb_arch_ep4_cache: Cached by 64 bytes buffer
|
||
|
|
usb_arch_ep5_cache: Cached by 64 bytes buffer
|
||
|
|
usb_arch_ep6_cache: Cached by 64 bytes buffer
|
||
|
|
usb_arch_ep7_cache: Cached by 64 bytes buffer
|
||
|
|
usb_ep1_I_CACHE: No cache
|
||
|
|
usb_ep2_I_CACHE: No cache
|
||
|
|
usb_ep3_I_CACHE: No cache
|
||
|
|
usb_ep4_I_CACHE: No cache
|
||
|
|
usb_ep5_I_CACHE: No cache
|
||
|
|
usb_ep6_I_CACHE: No cache
|
||
|
|
usb_ep7_I_CACHE: No cache
|
||
|
|
usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02)
|
||
|
|
usbd_arch_speed: Full speed
|
||
|
|
usbd_num_ep_sp: 4 (EP0 + 3 endpoints)
|
||
|
|
optional_signals: []
|
||
|
|
variant:
|
||
|
|
specification: default
|
||
|
|
required_signals:
|
||
|
|
- name: USB/DM
|
||
|
|
pad: PA24
|
||
|
|
label: Data-
|
||
|
|
- name: USB/DP
|
||
|
|
pad: PA25
|
||
|
|
label: Data+
|
||
|
|
clocks:
|
||
|
|
domain_group:
|
||
|
|
nodes:
|
||
|
|
- name: USB
|
||
|
|
input: Generic clock generator 0
|
||
|
|
external: false
|
||
|
|
external_frequency: 0
|
||
|
|
configuration:
|
||
|
|
usb_gclk_selection: Generic clock generator 0
|
||
|
|
pads:
|
||
|
|
PA22:
|
||
|
|
name: PA22
|
||
|
|
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::pad::PA22
|
||
|
|
mode: Peripheral IO
|
||
|
|
user_label: PA22
|
||
|
|
configuration: null
|
||
|
|
PA23:
|
||
|
|
name: PA23
|
||
|
|
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::pad::PA23
|
||
|
|
mode: Peripheral IO
|
||
|
|
user_label: PA23
|
||
|
|
configuration: null
|
||
|
|
PA24:
|
||
|
|
name: PA24
|
||
|
|
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::pad::PA24
|
||
|
|
mode: Advanced
|
||
|
|
user_label: PA24
|
||
|
|
configuration: null
|
||
|
|
PA25:
|
||
|
|
name: PA25
|
||
|
|
definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21E18A-MF::pad::PA25
|
||
|
|
mode: Advanced
|
||
|
|
user_label: PA25
|
||
|
|
configuration: null
|
||
|
|
toolchain_options: []
|