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<div id="projectname">SAME54P20A Test Project
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<div class="header">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Dsu Struct Reference</div> </div>
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<div class="contents">
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<p>DSU hardware registers.
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<a href="structDsu.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2dsu_8h_source.html">dsu.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a37a45b5734e68c25515884abbc7354bc"><td class="memItemLeft" align="right" valign="top"><a id="a37a45b5734e68c25515884abbc7354bc"></a>
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__O <a class="el" href="unionDSU__CTRL__Type.html">DSU_CTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a37a45b5734e68c25515884abbc7354bc">CTRL</a></td></tr>
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<tr class="memdesc:a37a45b5734e68c25515884abbc7354bc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0000 ( /W 8) Control. <br /></td></tr>
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<tr class="separator:a37a45b5734e68c25515884abbc7354bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af251ab6944603f4ffcc03a04c3a591af"><td class="memItemLeft" align="right" valign="top"><a id="af251ab6944603f4ffcc03a04c3a591af"></a>
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__IO <a class="el" href="unionDSU__STATUSA__Type.html">DSU_STATUSA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#af251ab6944603f4ffcc03a04c3a591af">STATUSA</a></td></tr>
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<tr class="memdesc:af251ab6944603f4ffcc03a04c3a591af"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0001 (R/W 8) Status A. <br /></td></tr>
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<tr class="separator:af251ab6944603f4ffcc03a04c3a591af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff3083b68480ee6d95d4213577136659"><td class="memItemLeft" align="right" valign="top"><a id="aff3083b68480ee6d95d4213577136659"></a>
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__I <a class="el" href="unionDSU__STATUSB__Type.html">DSU_STATUSB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#aff3083b68480ee6d95d4213577136659">STATUSB</a></td></tr>
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<tr class="memdesc:aff3083b68480ee6d95d4213577136659"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0002 (R/ 8) Status B. <br /></td></tr>
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<tr class="separator:aff3083b68480ee6d95d4213577136659"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61fc043e55c96393255e0aa0f7807fae"><td class="memItemLeft" align="right" valign="top"><a id="a61fc043e55c96393255e0aa0f7807fae"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x1]</td></tr>
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<tr class="separator:a61fc043e55c96393255e0aa0f7807fae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a453e7beb133d9b05320a24aba312f7f0"><td class="memItemLeft" align="right" valign="top"><a id="a453e7beb133d9b05320a24aba312f7f0"></a>
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__IO <a class="el" href="unionDSU__ADDR__Type.html">DSU_ADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a453e7beb133d9b05320a24aba312f7f0">ADDR</a></td></tr>
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<tr class="memdesc:a453e7beb133d9b05320a24aba312f7f0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0004 (R/W 32) Address. <br /></td></tr>
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<tr class="separator:a453e7beb133d9b05320a24aba312f7f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af13eeff822c0542965939b8a078bc496"><td class="memItemLeft" align="right" valign="top"><a id="af13eeff822c0542965939b8a078bc496"></a>
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__IO <a class="el" href="unionDSU__LENGTH__Type.html">DSU_LENGTH_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#af13eeff822c0542965939b8a078bc496">LENGTH</a></td></tr>
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<tr class="memdesc:af13eeff822c0542965939b8a078bc496"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0008 (R/W 32) Length. <br /></td></tr>
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<tr class="separator:af13eeff822c0542965939b8a078bc496"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a0cae05796695f78b4e5536792c8953"><td class="memItemLeft" align="right" valign="top"><a id="a0a0cae05796695f78b4e5536792c8953"></a>
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__IO <a class="el" href="unionDSU__DATA__Type.html">DSU_DATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a0a0cae05796695f78b4e5536792c8953">DATA</a></td></tr>
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<tr class="memdesc:a0a0cae05796695f78b4e5536792c8953"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000C (R/W 32) Data. <br /></td></tr>
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<tr class="separator:a0a0cae05796695f78b4e5536792c8953"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8cd3250ce850a65d90af4f8b31c6293c"><td class="memItemLeft" align="right" valign="top"><a id="a8cd3250ce850a65d90af4f8b31c6293c"></a>
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__IO <a class="el" href="unionDSU__DCC__Type.html">DSU_DCC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a8cd3250ce850a65d90af4f8b31c6293c">DCC</a> [2]</td></tr>
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<tr class="memdesc:a8cd3250ce850a65d90af4f8b31c6293c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0010 (R/W 32) Debug Communication Channel n. <br /></td></tr>
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<tr class="separator:a8cd3250ce850a65d90af4f8b31c6293c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae8a2a4525dd77831e3bba601b5eaf924"><td class="memItemLeft" align="right" valign="top"><a id="ae8a2a4525dd77831e3bba601b5eaf924"></a>
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__I <a class="el" href="unionDSU__DID__Type.html">DSU_DID_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#ae8a2a4525dd77831e3bba601b5eaf924">DID</a></td></tr>
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<tr class="memdesc:ae8a2a4525dd77831e3bba601b5eaf924"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0018 (R/ 32) Device Identification. <br /></td></tr>
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<tr class="separator:ae8a2a4525dd77831e3bba601b5eaf924"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a408f4b65eefa0933f2cce115230e3d"><td class="memItemLeft" align="right" valign="top"><a id="a0a408f4b65eefa0933f2cce115230e3d"></a>
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__IO <a class="el" href="unionDSU__CFG__Type.html">DSU_CFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a0a408f4b65eefa0933f2cce115230e3d">CFG</a></td></tr>
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<tr class="memdesc:a0a408f4b65eefa0933f2cce115230e3d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x001C (R/W 32) Configuration. <br /></td></tr>
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<tr class="separator:a0a408f4b65eefa0933f2cce115230e3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3bba1e7d463b5b35dfb34b8dbc8708c1"><td class="memItemLeft" align="right" valign="top"><a id="a3bba1e7d463b5b35dfb34b8dbc8708c1"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0xFE0]</td></tr>
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<tr class="separator:a3bba1e7d463b5b35dfb34b8dbc8708c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42805e1dcd37f9686cf024f3ab13e486"><td class="memItemLeft" align="right" valign="top"><a id="a42805e1dcd37f9686cf024f3ab13e486"></a>
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__I <a class="el" href="unionDSU__ENTRY0__Type.html">DSU_ENTRY0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a42805e1dcd37f9686cf024f3ab13e486">ENTRY0</a></td></tr>
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<tr class="memdesc:a42805e1dcd37f9686cf024f3ab13e486"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0. <br /></td></tr>
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<tr class="separator:a42805e1dcd37f9686cf024f3ab13e486"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d46a28676e73cd6c269d047ca71550e"><td class="memItemLeft" align="right" valign="top"><a id="a8d46a28676e73cd6c269d047ca71550e"></a>
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__I <a class="el" href="unionDSU__ENTRY1__Type.html">DSU_ENTRY1_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a8d46a28676e73cd6c269d047ca71550e">ENTRY1</a></td></tr>
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<tr class="memdesc:a8d46a28676e73cd6c269d047ca71550e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1. <br /></td></tr>
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<tr class="separator:a8d46a28676e73cd6c269d047ca71550e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae320db89e4b834b02befb5aa2867ce09"><td class="memItemLeft" align="right" valign="top"><a id="ae320db89e4b834b02befb5aa2867ce09"></a>
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__I <a class="el" href="unionDSU__END__Type.html">DSU_END_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#ae320db89e4b834b02befb5aa2867ce09">END</a></td></tr>
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<tr class="memdesc:ae320db89e4b834b02befb5aa2867ce09"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1008 (R/ 32) CoreSight ROM Table End. <br /></td></tr>
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<tr class="separator:ae320db89e4b834b02befb5aa2867ce09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3641d88dd084aec14c9a64e019a6daa1"><td class="memItemLeft" align="right" valign="top"><a id="a3641d88dd084aec14c9a64e019a6daa1"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0xFC0]</td></tr>
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<tr class="separator:a3641d88dd084aec14c9a64e019a6daa1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a408d8afc257ed78a3169ca958d24a5aa"><td class="memItemLeft" align="right" valign="top"><a id="a408d8afc257ed78a3169ca958d24a5aa"></a>
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__I <a class="el" href="unionDSU__MEMTYPE__Type.html">DSU_MEMTYPE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a408d8afc257ed78a3169ca958d24a5aa">MEMTYPE</a></td></tr>
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<tr class="memdesc:a408d8afc257ed78a3169ca958d24a5aa"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type. <br /></td></tr>
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<tr class="separator:a408d8afc257ed78a3169ca958d24a5aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af1aef1af23b9c04fa51bb38d3d49d980"><td class="memItemLeft" align="right" valign="top"><a id="af1aef1af23b9c04fa51bb38d3d49d980"></a>
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__I <a class="el" href="unionDSU__PID4__Type.html">DSU_PID4_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#af1aef1af23b9c04fa51bb38d3d49d980">PID4</a></td></tr>
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<tr class="memdesc:af1aef1af23b9c04fa51bb38d3d49d980"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FD0 (R/ 32) Peripheral Identification 4. <br /></td></tr>
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<tr class="separator:af1aef1af23b9c04fa51bb38d3d49d980"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a96116374ab1f4811e73ce3b53b2a4908"><td class="memItemLeft" align="right" valign="top"><a id="a96116374ab1f4811e73ce3b53b2a4908"></a>
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__I <a class="el" href="unionDSU__PID5__Type.html">DSU_PID5_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a96116374ab1f4811e73ce3b53b2a4908">PID5</a></td></tr>
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<tr class="memdesc:a96116374ab1f4811e73ce3b53b2a4908"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FD4 (R/ 32) Peripheral Identification 5. <br /></td></tr>
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<tr class="separator:a96116374ab1f4811e73ce3b53b2a4908"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:affd7dad98096b621d482b72f42fce5e8"><td class="memItemLeft" align="right" valign="top"><a id="affd7dad98096b621d482b72f42fce5e8"></a>
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__I <a class="el" href="unionDSU__PID6__Type.html">DSU_PID6_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#affd7dad98096b621d482b72f42fce5e8">PID6</a></td></tr>
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<tr class="memdesc:affd7dad98096b621d482b72f42fce5e8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FD8 (R/ 32) Peripheral Identification 6. <br /></td></tr>
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<tr class="separator:affd7dad98096b621d482b72f42fce5e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8a733fbde9d20baf89a47df500770071"><td class="memItemLeft" align="right" valign="top"><a id="a8a733fbde9d20baf89a47df500770071"></a>
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__I <a class="el" href="unionDSU__PID7__Type.html">DSU_PID7_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a8a733fbde9d20baf89a47df500770071">PID7</a></td></tr>
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<tr class="memdesc:a8a733fbde9d20baf89a47df500770071"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FDC (R/ 32) Peripheral Identification 7. <br /></td></tr>
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<tr class="separator:a8a733fbde9d20baf89a47df500770071"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60c2a9199ffaae85c76de6c28fc15ec1"><td class="memItemLeft" align="right" valign="top"><a id="a60c2a9199ffaae85c76de6c28fc15ec1"></a>
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__I <a class="el" href="unionDSU__PID0__Type.html">DSU_PID0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a60c2a9199ffaae85c76de6c28fc15ec1">PID0</a></td></tr>
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<tr class="memdesc:a60c2a9199ffaae85c76de6c28fc15ec1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FE0 (R/ 32) Peripheral Identification 0. <br /></td></tr>
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<tr class="separator:a60c2a9199ffaae85c76de6c28fc15ec1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeafe6f433e6983dedb1b78efe1508991"><td class="memItemLeft" align="right" valign="top"><a id="aeafe6f433e6983dedb1b78efe1508991"></a>
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__I <a class="el" href="unionDSU__PID1__Type.html">DSU_PID1_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#aeafe6f433e6983dedb1b78efe1508991">PID1</a></td></tr>
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<tr class="memdesc:aeafe6f433e6983dedb1b78efe1508991"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FE4 (R/ 32) Peripheral Identification 1. <br /></td></tr>
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<tr class="separator:aeafe6f433e6983dedb1b78efe1508991"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7543be9132a30e1a0a3d2585fa74ad7"><td class="memItemLeft" align="right" valign="top"><a id="ae7543be9132a30e1a0a3d2585fa74ad7"></a>
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__I <a class="el" href="unionDSU__PID2__Type.html">DSU_PID2_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#ae7543be9132a30e1a0a3d2585fa74ad7">PID2</a></td></tr>
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<tr class="memdesc:ae7543be9132a30e1a0a3d2585fa74ad7"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FE8 (R/ 32) Peripheral Identification 2. <br /></td></tr>
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<tr class="memitem:a12e3fc61b1f37f213768fded01011226"><td class="memItemLeft" align="right" valign="top"><a id="a12e3fc61b1f37f213768fded01011226"></a>
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__I <a class="el" href="unionDSU__PID3__Type.html">DSU_PID3_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a12e3fc61b1f37f213768fded01011226">PID3</a></td></tr>
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<tr class="memdesc:a12e3fc61b1f37f213768fded01011226"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FEC (R/ 32) Peripheral Identification 3. <br /></td></tr>
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__I <a class="el" href="unionDSU__CID0__Type.html">DSU_CID0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#acd4b45b637efcb62b9f67c877dcbb4ce">CID0</a></td></tr>
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<tr class="memdesc:acd4b45b637efcb62b9f67c877dcbb4ce"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FF0 (R/ 32) Component Identification 0. <br /></td></tr>
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__I <a class="el" href="unionDSU__CID1__Type.html">DSU_CID1_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#afeea7b5b5fee7f91ca2886b616f3d4c3">CID1</a></td></tr>
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<tr class="memdesc:afeea7b5b5fee7f91ca2886b616f3d4c3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FF4 (R/ 32) Component Identification 1. <br /></td></tr>
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<tr class="memitem:afaa3b33371d8b21883936c53a879d61f"><td class="memItemLeft" align="right" valign="top"><a id="afaa3b33371d8b21883936c53a879d61f"></a>
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__I <a class="el" href="unionDSU__CID2__Type.html">DSU_CID2_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#afaa3b33371d8b21883936c53a879d61f">CID2</a></td></tr>
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<tr class="memdesc:afaa3b33371d8b21883936c53a879d61f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FF8 (R/ 32) Component Identification 2. <br /></td></tr>
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__I <a class="el" href="unionDSU__CID3__Type.html">DSU_CID3_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html#a8ce289f77dfa3331bc94ae699c6031d7">CID3</a></td></tr>
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<tr class="memdesc:a8ce289f77dfa3331bc94ae699c6031d7"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1FFC (R/ 32) Component Identification 3. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>DSU hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2dsu_8h_source.html#l00613">613</a> of file <a class="el" href="component_2dsu_8h_source.html">dsu.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2dsu_8h_source.html">dsu.h</a></li>
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</ul>
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