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SAME54P20A Test Project
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DSU hardware registers. More...
#include <dsu.h>
Data Fields | |
| __O DSU_CTRL_Type | CTRL |
| Offset: 0x0000 ( /W 8) Control. | |
| __IO DSU_STATUSA_Type | STATUSA |
| Offset: 0x0001 (R/W 8) Status A. | |
| __I DSU_STATUSB_Type | STATUSB |
| Offset: 0x0002 (R/ 8) Status B. | |
| RoReg8 | Reserved1 [0x1] |
| __IO DSU_ADDR_Type | ADDR |
| Offset: 0x0004 (R/W 32) Address. | |
| __IO DSU_LENGTH_Type | LENGTH |
| Offset: 0x0008 (R/W 32) Length. | |
| __IO DSU_DATA_Type | DATA |
| Offset: 0x000C (R/W 32) Data. | |
| __IO DSU_DCC_Type | DCC [2] |
| Offset: 0x0010 (R/W 32) Debug Communication Channel n. | |
| __I DSU_DID_Type | DID |
| Offset: 0x0018 (R/ 32) Device Identification. | |
| __IO DSU_CFG_Type | CFG |
| Offset: 0x001C (R/W 32) Configuration. | |
| RoReg8 | Reserved2 [0xFE0] |
| __I DSU_ENTRY0_Type | ENTRY0 |
| Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0. | |
| __I DSU_ENTRY1_Type | ENTRY1 |
| Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1. | |
| __I DSU_END_Type | END |
| Offset: 0x1008 (R/ 32) CoreSight ROM Table End. | |
| RoReg8 | Reserved3 [0xFC0] |
| __I DSU_MEMTYPE_Type | MEMTYPE |
| Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type. | |
| __I DSU_PID4_Type | PID4 |
| Offset: 0x1FD0 (R/ 32) Peripheral Identification 4. | |
| __I DSU_PID5_Type | PID5 |
| Offset: 0x1FD4 (R/ 32) Peripheral Identification 5. | |
| __I DSU_PID6_Type | PID6 |
| Offset: 0x1FD8 (R/ 32) Peripheral Identification 6. | |
| __I DSU_PID7_Type | PID7 |
| Offset: 0x1FDC (R/ 32) Peripheral Identification 7. | |
| __I DSU_PID0_Type | PID0 |
| Offset: 0x1FE0 (R/ 32) Peripheral Identification 0. | |
| __I DSU_PID1_Type | PID1 |
| Offset: 0x1FE4 (R/ 32) Peripheral Identification 1. | |
| __I DSU_PID2_Type | PID2 |
| Offset: 0x1FE8 (R/ 32) Peripheral Identification 2. | |
| __I DSU_PID3_Type | PID3 |
| Offset: 0x1FEC (R/ 32) Peripheral Identification 3. | |
| __I DSU_CID0_Type | CID0 |
| Offset: 0x1FF0 (R/ 32) Component Identification 0. | |
| __I DSU_CID1_Type | CID1 |
| Offset: 0x1FF4 (R/ 32) Component Identification 1. | |
| __I DSU_CID2_Type | CID2 |
| Offset: 0x1FF8 (R/ 32) Component Identification 2. | |
| __I DSU_CID3_Type | CID3 |
| Offset: 0x1FFC (R/ 32) Component Identification 3. | |
1.8.20