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<div id="projectname">SAME54P20A Test Project
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<div class="header">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Can Struct Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>CAN APB hardware registers.
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<a href="structCan.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="can_8h_source.html">can.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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__I <a class="el" href="unionCAN__CREL__Type.html">CAN_CREL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a9b0658634d3f2a9dbd4b899c54893511">CREL</a></td></tr>
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<tr class="memdesc:a9b0658634d3f2a9dbd4b899c54893511"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/ 32) Core Release. <br /></td></tr>
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__I <a class="el" href="unionCAN__ENDN__Type.html">CAN_ENDN_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#af9f1bd8a5f75477014a0c318dbde4afd">ENDN</a></td></tr>
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<tr class="memdesc:af9f1bd8a5f75477014a0c318dbde4afd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/ 32) Endian. <br /></td></tr>
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<tr class="separator:af9f1bd8a5f75477014a0c318dbde4afd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab7fa0a31ab04ae87051dc557ddeb694"><td class="memItemLeft" align="right" valign="top"><a id="aab7fa0a31ab04ae87051dc557ddeb694"></a>
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__IO <a class="el" href="unionCAN__MRCFG__Type.html">CAN_MRCFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#aab7fa0a31ab04ae87051dc557ddeb694">MRCFG</a></td></tr>
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<tr class="memdesc:aab7fa0a31ab04ae87051dc557ddeb694"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) Message RAM Configuration. <br /></td></tr>
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<tr class="separator:aab7fa0a31ab04ae87051dc557ddeb694"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionCAN__DBTP__Type.html">CAN_DBTP_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a0aff7c4b3894648bccf20b6317edcb51">DBTP</a></td></tr>
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<tr class="memdesc:a0aff7c4b3894648bccf20b6317edcb51"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler. <br /></td></tr>
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__IO <a class="el" href="unionCAN__TEST__Type.html">CAN_TEST_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a0c8b071cd7a6ee23bd98b07230fd5e26">TEST</a></td></tr>
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__IO <a class="el" href="unionCAN__RWD__Type.html">CAN_RWD_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a8a678f0a9b73520e792f3d766925e735">RWD</a></td></tr>
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<tr class="memdesc:a8a678f0a9b73520e792f3d766925e735"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) RAM Watchdog. <br /></td></tr>
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<tr class="separator:a8a678f0a9b73520e792f3d766925e735"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionCAN__CCCR__Type.html">CAN_CCCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a8543cccb83aceb5f4cf9f7c3aad94b74">CCCR</a></td></tr>
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__IO <a class="el" href="unionCAN__TSCC__Type.html">CAN_TSCC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a4cfa6311a921ede3301e40539f56b8d1">TSCC</a></td></tr>
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<tr class="memdesc:a4cfa6311a921ede3301e40539f56b8d1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/W 32) Timestamp Counter Configuration. <br /></td></tr>
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__I <a class="el" href="unionCAN__TSCV__Type.html">CAN_TSCV_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#aaf28e968f2272b4ea2c1a521af60f80f">TSCV</a></td></tr>
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<tr class="memdesc:aaf28e968f2272b4ea2c1a521af60f80f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/ 32) Timestamp Counter Value. <br /></td></tr>
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__IO <a class="el" href="unionCAN__TOCC__Type.html">CAN_TOCC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#acece47570d136fbd51356dcc7b324ae6">TOCC</a></td></tr>
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<tr class="memdesc:acece47570d136fbd51356dcc7b324ae6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 32) Timeout Counter Configuration. <br /></td></tr>
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<tr class="separator:acece47570d136fbd51356dcc7b324ae6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addf10280c3999b8db02c8aee71110616"><td class="memItemLeft" align="right" valign="top"><a id="addf10280c3999b8db02c8aee71110616"></a>
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__IO <a class="el" href="unionCAN__TOCV__Type.html">CAN_TOCV_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#addf10280c3999b8db02c8aee71110616">TOCV</a></td></tr>
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<tr class="memdesc:addf10280c3999b8db02c8aee71110616"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2C (R/W 32) Timeout Counter Value. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x10]</td></tr>
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<tr class="separator:aa02d36d7b0df1fd3c83610dd8c520c65"><td class="memSeparator" colspan="2"> </td></tr>
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__I <a class="el" href="unionCAN__ECR__Type.html">CAN_ECR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#ad8302c90d6760af42285f20388625368">ECR</a></td></tr>
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<tr class="memdesc:ad8302c90d6760af42285f20388625368"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x40 (R/ 32) Error Counter. <br /></td></tr>
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<tr class="separator:ad8302c90d6760af42285f20388625368"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab94600b652697149682e8a2d9f174bfb"><td class="memItemLeft" align="right" valign="top"><a id="ab94600b652697149682e8a2d9f174bfb"></a>
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__I <a class="el" href="unionCAN__PSR__Type.html">CAN_PSR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#ab94600b652697149682e8a2d9f174bfb">PSR</a></td></tr>
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<tr class="memdesc:ab94600b652697149682e8a2d9f174bfb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x44 (R/ 32) Protocol Status. <br /></td></tr>
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<tr class="separator:ab94600b652697149682e8a2d9f174bfb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05cbfffe6a93716bdb6e82c67cb26531"><td class="memItemLeft" align="right" valign="top"><a id="a05cbfffe6a93716bdb6e82c67cb26531"></a>
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__IO <a class="el" href="unionCAN__TDCR__Type.html">CAN_TDCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a05cbfffe6a93716bdb6e82c67cb26531">TDCR</a></td></tr>
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<tr class="memdesc:a05cbfffe6a93716bdb6e82c67cb26531"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x48 (R/W 32) Extended ID Filter Configuration. <br /></td></tr>
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<tr class="separator:a05cbfffe6a93716bdb6e82c67cb26531"><td class="memSeparator" colspan="2"> </td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x4]</td></tr>
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<tr class="separator:a6538017469185739332992431bc4ddc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0511149cd3f2ad78c5ccdc4f6bfa7ce"><td class="memItemLeft" align="right" valign="top"><a id="ab0511149cd3f2ad78c5ccdc4f6bfa7ce"></a>
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__IO <a class="el" href="unionCAN__IR__Type.html">CAN_IR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#ab0511149cd3f2ad78c5ccdc4f6bfa7ce">IR</a></td></tr>
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<tr class="memdesc:ab0511149cd3f2ad78c5ccdc4f6bfa7ce"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x50 (R/W 32) Interrupt. <br /></td></tr>
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<tr class="separator:ab0511149cd3f2ad78c5ccdc4f6bfa7ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f25530a27200f9ad3d76253e0c1be02"><td class="memItemLeft" align="right" valign="top"><a id="a2f25530a27200f9ad3d76253e0c1be02"></a>
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__IO <a class="el" href="unionCAN__IE__Type.html">CAN_IE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a2f25530a27200f9ad3d76253e0c1be02">IE</a></td></tr>
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<tr class="memdesc:a2f25530a27200f9ad3d76253e0c1be02"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x54 (R/W 32) Interrupt Enable. <br /></td></tr>
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<tr class="separator:a2f25530a27200f9ad3d76253e0c1be02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4f984130d063d1a6294dc09ac26ab0d2"><td class="memItemLeft" align="right" valign="top"><a id="a4f984130d063d1a6294dc09ac26ab0d2"></a>
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__IO <a class="el" href="unionCAN__ILS__Type.html">CAN_ILS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a4f984130d063d1a6294dc09ac26ab0d2">ILS</a></td></tr>
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<tr class="memdesc:a4f984130d063d1a6294dc09ac26ab0d2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x58 (R/W 32) Interrupt Line Select. <br /></td></tr>
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<tr class="separator:a4f984130d063d1a6294dc09ac26ab0d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a865d9ffee377fe951bd4717009632ba0"><td class="memItemLeft" align="right" valign="top"><a id="a865d9ffee377fe951bd4717009632ba0"></a>
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__IO <a class="el" href="unionCAN__ILE__Type.html">CAN_ILE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a865d9ffee377fe951bd4717009632ba0">ILE</a></td></tr>
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<tr class="memdesc:a865d9ffee377fe951bd4717009632ba0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x5C (R/W 32) Interrupt Line Enable. <br /></td></tr>
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<tr class="memitem:aa10049592ce7ea540502021f4e43d4b7"><td class="memItemLeft" align="right" valign="top"><a id="aa10049592ce7ea540502021f4e43d4b7"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x20]</td></tr>
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__IO <a class="el" href="unionCAN__GFC__Type.html">CAN_GFC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a92f3f33da1f197b0c018f4d95e24a0eb">GFC</a></td></tr>
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<tr class="memdesc:a92f3f33da1f197b0c018f4d95e24a0eb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x80 (R/W 32) Global Filter Configuration. <br /></td></tr>
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<tr class="separator:a92f3f33da1f197b0c018f4d95e24a0eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac17e336260c9b087294260385dd4b196"><td class="memItemLeft" align="right" valign="top"><a id="ac17e336260c9b087294260385dd4b196"></a>
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__IO <a class="el" href="unionCAN__SIDFC__Type.html">CAN_SIDFC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#ac17e336260c9b087294260385dd4b196">SIDFC</a></td></tr>
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<tr class="memdesc:ac17e336260c9b087294260385dd4b196"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x84 (R/W 32) Standard ID Filter Configuration. <br /></td></tr>
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<tr class="separator:ac17e336260c9b087294260385dd4b196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeec13c348879f4f25d2489d0413cad1c"><td class="memItemLeft" align="right" valign="top"><a id="aeec13c348879f4f25d2489d0413cad1c"></a>
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__IO <a class="el" href="unionCAN__XIDFC__Type.html">CAN_XIDFC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#aeec13c348879f4f25d2489d0413cad1c">XIDFC</a></td></tr>
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<tr class="memdesc:aeec13c348879f4f25d2489d0413cad1c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x88 (R/W 32) Extended ID Filter Configuration. <br /></td></tr>
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<tr class="separator:aeec13c348879f4f25d2489d0413cad1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9fe44e1adfb5dcf6c0006c1a5ded99a8"><td class="memItemLeft" align="right" valign="top"><a id="a9fe44e1adfb5dcf6c0006c1a5ded99a8"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x4]</td></tr>
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<tr class="separator:a9fe44e1adfb5dcf6c0006c1a5ded99a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adcc98d3489676d9a137b81b087d35999"><td class="memItemLeft" align="right" valign="top"><a id="adcc98d3489676d9a137b81b087d35999"></a>
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__IO <a class="el" href="unionCAN__XIDAM__Type.html">CAN_XIDAM_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#adcc98d3489676d9a137b81b087d35999">XIDAM</a></td></tr>
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<tr class="memdesc:adcc98d3489676d9a137b81b087d35999"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x90 (R/W 32) Extended ID AND Mask. <br /></td></tr>
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<tr class="separator:adcc98d3489676d9a137b81b087d35999"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0e036ec4d58b56b6125028d6d9c69802"><td class="memItemLeft" align="right" valign="top"><a id="a0e036ec4d58b56b6125028d6d9c69802"></a>
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__I <a class="el" href="unionCAN__HPMS__Type.html">CAN_HPMS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a0e036ec4d58b56b6125028d6d9c69802">HPMS</a></td></tr>
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<tr class="memdesc:a0e036ec4d58b56b6125028d6d9c69802"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x94 (R/ 32) High Priority Message Status. <br /></td></tr>
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<tr class="separator:a0e036ec4d58b56b6125028d6d9c69802"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7d3508b2b5d43a0337c9fa6ec7a8e576"><td class="memItemLeft" align="right" valign="top"><a id="a7d3508b2b5d43a0337c9fa6ec7a8e576"></a>
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__IO <a class="el" href="unionCAN__NDAT1__Type.html">CAN_NDAT1_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a7d3508b2b5d43a0337c9fa6ec7a8e576">NDAT1</a></td></tr>
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<tr class="memdesc:a7d3508b2b5d43a0337c9fa6ec7a8e576"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x98 (R/W 32) New Data 1. <br /></td></tr>
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<tr class="separator:a7d3508b2b5d43a0337c9fa6ec7a8e576"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a24fb0c71b3f13fee5d2275f351b0974c"><td class="memItemLeft" align="right" valign="top"><a id="a24fb0c71b3f13fee5d2275f351b0974c"></a>
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__IO <a class="el" href="unionCAN__NDAT2__Type.html">CAN_NDAT2_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a24fb0c71b3f13fee5d2275f351b0974c">NDAT2</a></td></tr>
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<tr class="memdesc:a24fb0c71b3f13fee5d2275f351b0974c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x9C (R/W 32) New Data 2. <br /></td></tr>
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<tr class="separator:a24fb0c71b3f13fee5d2275f351b0974c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1e5c70184fcceb9cdd13ce609c997a40"><td class="memItemLeft" align="right" valign="top"><a id="a1e5c70184fcceb9cdd13ce609c997a40"></a>
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__IO <a class="el" href="unionCAN__RXF0C__Type.html">CAN_RXF0C_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a1e5c70184fcceb9cdd13ce609c997a40">RXF0C</a></td></tr>
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<tr class="memdesc:a1e5c70184fcceb9cdd13ce609c997a40"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration. <br /></td></tr>
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<tr class="separator:a1e5c70184fcceb9cdd13ce609c997a40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1010078a5ae0e51ee25af2541ffd39eb"><td class="memItemLeft" align="right" valign="top"><a id="a1010078a5ae0e51ee25af2541ffd39eb"></a>
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__I <a class="el" href="unionCAN__RXF0S__Type.html">CAN_RXF0S_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a1010078a5ae0e51ee25af2541ffd39eb">RXF0S</a></td></tr>
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<tr class="memdesc:a1010078a5ae0e51ee25af2541ffd39eb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xA4 (R/ 32) Rx FIFO 0 Status. <br /></td></tr>
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<tr class="separator:a1010078a5ae0e51ee25af2541ffd39eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abb1eff60658ddc21f22a084d0f422e80"><td class="memItemLeft" align="right" valign="top"><a id="abb1eff60658ddc21f22a084d0f422e80"></a>
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__IO <a class="el" href="unionCAN__RXF0A__Type.html">CAN_RXF0A_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#abb1eff60658ddc21f22a084d0f422e80">RXF0A</a></td></tr>
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<tr class="memdesc:abb1eff60658ddc21f22a084d0f422e80"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge. <br /></td></tr>
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<tr class="separator:abb1eff60658ddc21f22a084d0f422e80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a854dcb08122dff4283cccc22b1c7f4d9"><td class="memItemLeft" align="right" valign="top"><a id="a854dcb08122dff4283cccc22b1c7f4d9"></a>
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__IO <a class="el" href="unionCAN__RXBC__Type.html">CAN_RXBC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a854dcb08122dff4283cccc22b1c7f4d9">RXBC</a></td></tr>
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<tr class="memdesc:a854dcb08122dff4283cccc22b1c7f4d9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xAC (R/W 32) Rx Buffer Configuration. <br /></td></tr>
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<tr class="separator:a854dcb08122dff4283cccc22b1c7f4d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab986a3d0c5ccef2bf0fb3beca54f24ae"><td class="memItemLeft" align="right" valign="top"><a id="ab986a3d0c5ccef2bf0fb3beca54f24ae"></a>
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__IO <a class="el" href="unionCAN__RXF1C__Type.html">CAN_RXF1C_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#ab986a3d0c5ccef2bf0fb3beca54f24ae">RXF1C</a></td></tr>
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<tr class="memdesc:ab986a3d0c5ccef2bf0fb3beca54f24ae"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration. <br /></td></tr>
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<tr class="separator:ab986a3d0c5ccef2bf0fb3beca54f24ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abca7f3cb14912524d51d19bfa1db6351"><td class="memItemLeft" align="right" valign="top"><a id="abca7f3cb14912524d51d19bfa1db6351"></a>
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__I <a class="el" href="unionCAN__RXF1S__Type.html">CAN_RXF1S_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#abca7f3cb14912524d51d19bfa1db6351">RXF1S</a></td></tr>
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<tr class="memdesc:abca7f3cb14912524d51d19bfa1db6351"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xB4 (R/ 32) Rx FIFO 1 Status. <br /></td></tr>
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<tr class="separator:abca7f3cb14912524d51d19bfa1db6351"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a76e3a46608e7b543fd99ab24ed707b7e"><td class="memItemLeft" align="right" valign="top"><a id="a76e3a46608e7b543fd99ab24ed707b7e"></a>
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__IO <a class="el" href="unionCAN__RXF1A__Type.html">CAN_RXF1A_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a76e3a46608e7b543fd99ab24ed707b7e">RXF1A</a></td></tr>
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<tr class="memdesc:a76e3a46608e7b543fd99ab24ed707b7e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge. <br /></td></tr>
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<tr class="separator:a76e3a46608e7b543fd99ab24ed707b7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af13610caca89ec467f296dd54901db63"><td class="memItemLeft" align="right" valign="top"><a id="af13610caca89ec467f296dd54901db63"></a>
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__IO <a class="el" href="unionCAN__RXESC__Type.html">CAN_RXESC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#af13610caca89ec467f296dd54901db63">RXESC</a></td></tr>
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<tr class="memdesc:af13610caca89ec467f296dd54901db63"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration. <br /></td></tr>
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<tr class="separator:af13610caca89ec467f296dd54901db63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a94179b65025b66a06742261e213d1280"><td class="memItemLeft" align="right" valign="top"><a id="a94179b65025b66a06742261e213d1280"></a>
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__IO <a class="el" href="unionCAN__TXBC__Type.html">CAN_TXBC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a94179b65025b66a06742261e213d1280">TXBC</a></td></tr>
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|
<tr class="memdesc:a94179b65025b66a06742261e213d1280"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xC0 (R/W 32) Tx Buffer Configuration. <br /></td></tr>
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<tr class="separator:a94179b65025b66a06742261e213d1280"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0e723141a8973c89f0da7af0ca56d3c3"><td class="memItemLeft" align="right" valign="top"><a id="a0e723141a8973c89f0da7af0ca56d3c3"></a>
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__I <a class="el" href="unionCAN__TXFQS__Type.html">CAN_TXFQS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a0e723141a8973c89f0da7af0ca56d3c3">TXFQS</a></td></tr>
|
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<tr class="memdesc:a0e723141a8973c89f0da7af0ca56d3c3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status. <br /></td></tr>
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<tr class="separator:a0e723141a8973c89f0da7af0ca56d3c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a784663b5ade4d093b52f7a62eeae153f"><td class="memItemLeft" align="right" valign="top"><a id="a784663b5ade4d093b52f7a62eeae153f"></a>
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__IO <a class="el" href="unionCAN__TXESC__Type.html">CAN_TXESC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a784663b5ade4d093b52f7a62eeae153f">TXESC</a></td></tr>
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<tr class="memdesc:a784663b5ade4d093b52f7a62eeae153f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration. <br /></td></tr>
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<tr class="separator:a784663b5ade4d093b52f7a62eeae153f"><td class="memSeparator" colspan="2"> </td></tr>
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|
<tr class="memitem:a15032317053c17f8a8cab8a4c916d257"><td class="memItemLeft" align="right" valign="top"><a id="a15032317053c17f8a8cab8a4c916d257"></a>
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__I <a class="el" href="unionCAN__TXBRP__Type.html">CAN_TXBRP_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a15032317053c17f8a8cab8a4c916d257">TXBRP</a></td></tr>
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|
<tr class="memdesc:a15032317053c17f8a8cab8a4c916d257"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xCC (R/ 32) Tx Buffer Request Pending. <br /></td></tr>
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<tr class="separator:a15032317053c17f8a8cab8a4c916d257"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acce7358a70b835b8ba3650465898ba7a"><td class="memItemLeft" align="right" valign="top"><a id="acce7358a70b835b8ba3650465898ba7a"></a>
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__IO <a class="el" href="unionCAN__TXBAR__Type.html">CAN_TXBAR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#acce7358a70b835b8ba3650465898ba7a">TXBAR</a></td></tr>
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<tr class="memdesc:acce7358a70b835b8ba3650465898ba7a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xD0 (R/W 32) Tx Buffer Add Request. <br /></td></tr>
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<tr class="separator:acce7358a70b835b8ba3650465898ba7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab785e332dc614d6a999cdf30a20a5819"><td class="memItemLeft" align="right" valign="top"><a id="ab785e332dc614d6a999cdf30a20a5819"></a>
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__IO <a class="el" href="unionCAN__TXBCR__Type.html">CAN_TXBCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#ab785e332dc614d6a999cdf30a20a5819">TXBCR</a></td></tr>
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<tr class="memdesc:ab785e332dc614d6a999cdf30a20a5819"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request. <br /></td></tr>
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<tr class="separator:ab785e332dc614d6a999cdf30a20a5819"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b26e167850a3fec295af6bbe3e7ad66"><td class="memItemLeft" align="right" valign="top"><a id="a3b26e167850a3fec295af6bbe3e7ad66"></a>
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__I <a class="el" href="unionCAN__TXBTO__Type.html">CAN_TXBTO_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a3b26e167850a3fec295af6bbe3e7ad66">TXBTO</a></td></tr>
|
|
<tr class="memdesc:a3b26e167850a3fec295af6bbe3e7ad66"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred. <br /></td></tr>
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<tr class="separator:a3b26e167850a3fec295af6bbe3e7ad66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa76cf0ae7f23dd753d718bc86122a1eb"><td class="memItemLeft" align="right" valign="top"><a id="aa76cf0ae7f23dd753d718bc86122a1eb"></a>
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__I <a class="el" href="unionCAN__TXBCF__Type.html">CAN_TXBCF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#aa76cf0ae7f23dd753d718bc86122a1eb">TXBCF</a></td></tr>
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<tr class="memdesc:aa76cf0ae7f23dd753d718bc86122a1eb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished. <br /></td></tr>
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<tr class="separator:aa76cf0ae7f23dd753d718bc86122a1eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8dcf2f922a1e6d65632d37edd9df978"><td class="memItemLeft" align="right" valign="top"><a id="ad8dcf2f922a1e6d65632d37edd9df978"></a>
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__IO <a class="el" href="unionCAN__TXBTIE__Type.html">CAN_TXBTIE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#ad8dcf2f922a1e6d65632d37edd9df978">TXBTIE</a></td></tr>
|
|
<tr class="memdesc:ad8dcf2f922a1e6d65632d37edd9df978"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable. <br /></td></tr>
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<tr class="separator:ad8dcf2f922a1e6d65632d37edd9df978"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e012e85301736293192173070e022e3"><td class="memItemLeft" align="right" valign="top"><a id="a5e012e85301736293192173070e022e3"></a>
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__IO <a class="el" href="unionCAN__TXBCIE__Type.html">CAN_TXBCIE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a5e012e85301736293192173070e022e3">TXBCIE</a></td></tr>
|
|
<tr class="memdesc:a5e012e85301736293192173070e022e3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable. <br /></td></tr>
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<tr class="separator:a5e012e85301736293192173070e022e3"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a336e1a0506972bfb0afada177ec43d84"><td class="memItemLeft" align="right" valign="top"><a id="a336e1a0506972bfb0afada177ec43d84"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x8]</td></tr>
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<tr class="separator:a336e1a0506972bfb0afada177ec43d84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7b86272f96877c6531e705c6c1b6ba62"><td class="memItemLeft" align="right" valign="top"><a id="a7b86272f96877c6531e705c6c1b6ba62"></a>
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__IO <a class="el" href="unionCAN__TXEFC__Type.html">CAN_TXEFC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a7b86272f96877c6531e705c6c1b6ba62">TXEFC</a></td></tr>
|
|
<tr class="memdesc:a7b86272f96877c6531e705c6c1b6ba62"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration. <br /></td></tr>
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<tr class="separator:a7b86272f96877c6531e705c6c1b6ba62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65478edd8194626fd52819f67835cba5"><td class="memItemLeft" align="right" valign="top"><a id="a65478edd8194626fd52819f67835cba5"></a>
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__I <a class="el" href="unionCAN__TXEFS__Type.html">CAN_TXEFS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#a65478edd8194626fd52819f67835cba5">TXEFS</a></td></tr>
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<tr class="memdesc:a65478edd8194626fd52819f67835cba5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF4 (R/ 32) Tx Event FIFO Status. <br /></td></tr>
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<tr class="separator:a65478edd8194626fd52819f67835cba5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa94297369fb07bb5f168805407473c83"><td class="memItemLeft" align="right" valign="top"><a id="aa94297369fb07bb5f168805407473c83"></a>
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__IO <a class="el" href="unionCAN__TXEFA__Type.html">CAN_TXEFA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCan.html#aa94297369fb07bb5f168805407473c83">TXEFA</a></td></tr>
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<tr class="memdesc:aa94297369fb07bb5f168805407473c83"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge. <br /></td></tr>
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<tr class="separator:aa94297369fb07bb5f168805407473c83"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>CAN APB hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="can_8h_source.html#l03034">3034</a> of file <a class="el" href="can_8h_source.html">can.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="can_8h_source.html">can.h</a></li>
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</ul>
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