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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">port.h File Reference</div> </div>
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<p>Instance description for PORT.
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<a href="#details">More...</a></p>
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<p><a href="instance_2port_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a97266c43309c6d9ae5e9b0b7fade9b88"><td class="memItemLeft" align="right" valign="top"><a id="a97266c43309c6d9ae5e9b0b7fade9b88"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a97266c43309c6d9ae5e9b0b7fade9b88">REG_PORT_DIR0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008000UL)</td></tr>
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<tr class="memdesc:a97266c43309c6d9ae5e9b0b7fade9b88"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction 0 <br /></td></tr>
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<tr class="separator:a97266c43309c6d9ae5e9b0b7fade9b88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a202e7577e003ee206321199cc1425730"><td class="memItemLeft" align="right" valign="top"><a id="a202e7577e003ee206321199cc1425730"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a202e7577e003ee206321199cc1425730">REG_PORT_DIRCLR0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008004UL)</td></tr>
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<tr class="memdesc:a202e7577e003ee206321199cc1425730"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Clear 0 <br /></td></tr>
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<tr class="separator:a202e7577e003ee206321199cc1425730"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adfceb6d4e4c262cf212b9be2109e989f"><td class="memItemLeft" align="right" valign="top"><a id="adfceb6d4e4c262cf212b9be2109e989f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#adfceb6d4e4c262cf212b9be2109e989f">REG_PORT_DIRSET0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008008UL)</td></tr>
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<tr class="memdesc:adfceb6d4e4c262cf212b9be2109e989f"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Set 0 <br /></td></tr>
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<tr class="separator:adfceb6d4e4c262cf212b9be2109e989f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44d946752b1e9c699bd69918081579a4"><td class="memItemLeft" align="right" valign="top"><a id="a44d946752b1e9c699bd69918081579a4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a44d946752b1e9c699bd69918081579a4">REG_PORT_DIRTGL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100800CUL)</td></tr>
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<tr class="memdesc:a44d946752b1e9c699bd69918081579a4"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Toggle 0 <br /></td></tr>
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<tr class="separator:a44d946752b1e9c699bd69918081579a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac0e9c345de1c1ea20a4634012545a4de"><td class="memItemLeft" align="right" valign="top"><a id="ac0e9c345de1c1ea20a4634012545a4de"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ac0e9c345de1c1ea20a4634012545a4de">REG_PORT_OUT0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008010UL)</td></tr>
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<tr class="memdesc:ac0e9c345de1c1ea20a4634012545a4de"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value 0 <br /></td></tr>
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<tr class="separator:ac0e9c345de1c1ea20a4634012545a4de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad7a6aa55482c6e92ed66a6deeca0b0b5"><td class="memItemLeft" align="right" valign="top"><a id="ad7a6aa55482c6e92ed66a6deeca0b0b5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ad7a6aa55482c6e92ed66a6deeca0b0b5">REG_PORT_OUTCLR0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008014UL)</td></tr>
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<tr class="memdesc:ad7a6aa55482c6e92ed66a6deeca0b0b5"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Clear 0 <br /></td></tr>
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<tr class="separator:ad7a6aa55482c6e92ed66a6deeca0b0b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3481abedeb8460f687c1a19ec8433dd9"><td class="memItemLeft" align="right" valign="top"><a id="a3481abedeb8460f687c1a19ec8433dd9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a3481abedeb8460f687c1a19ec8433dd9">REG_PORT_OUTSET0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008018UL)</td></tr>
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<tr class="memdesc:a3481abedeb8460f687c1a19ec8433dd9"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Set 0 <br /></td></tr>
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<tr class="separator:a3481abedeb8460f687c1a19ec8433dd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a078c4860bbcb38bdc972ae229eeea08e"><td class="memItemLeft" align="right" valign="top"><a id="a078c4860bbcb38bdc972ae229eeea08e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a078c4860bbcb38bdc972ae229eeea08e">REG_PORT_OUTTGL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100801CUL)</td></tr>
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<tr class="memdesc:a078c4860bbcb38bdc972ae229eeea08e"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Toggle 0 <br /></td></tr>
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<tr class="separator:a078c4860bbcb38bdc972ae229eeea08e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a80079360b9d522773b1793da944d3f10"><td class="memItemLeft" align="right" valign="top"><a id="a80079360b9d522773b1793da944d3f10"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a80079360b9d522773b1793da944d3f10">REG_PORT_IN0</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41008020UL)</td></tr>
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<tr class="memdesc:a80079360b9d522773b1793da944d3f10"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Input Value 0 <br /></td></tr>
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<tr class="separator:a80079360b9d522773b1793da944d3f10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af2078f225a38de014a88804d31e7c032"><td class="memItemLeft" align="right" valign="top"><a id="af2078f225a38de014a88804d31e7c032"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#af2078f225a38de014a88804d31e7c032">REG_PORT_CTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008024UL)</td></tr>
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<tr class="memdesc:af2078f225a38de014a88804d31e7c032"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Control 0 <br /></td></tr>
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<tr class="separator:af2078f225a38de014a88804d31e7c032"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91ac37967534f1755cdf49b6bb3bc559"><td class="memItemLeft" align="right" valign="top"><a id="a91ac37967534f1755cdf49b6bb3bc559"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a91ac37967534f1755cdf49b6bb3bc559">REG_PORT_WRCONFIG0</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x41008028UL)</td></tr>
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<tr class="memdesc:a91ac37967534f1755cdf49b6bb3bc559"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Write Configuration 0 <br /></td></tr>
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<tr class="separator:a91ac37967534f1755cdf49b6bb3bc559"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac947060c7edb8c76015d52236a4ad62"><td class="memItemLeft" align="right" valign="top"><a id="aac947060c7edb8c76015d52236a4ad62"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#aac947060c7edb8c76015d52236a4ad62">REG_PORT_EVCTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100802CUL)</td></tr>
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<tr class="memdesc:aac947060c7edb8c76015d52236a4ad62"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Event Input Control 0 <br /></td></tr>
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<tr class="separator:aac947060c7edb8c76015d52236a4ad62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb037cc9cda118676dff8ad7505ddc2f"><td class="memItemLeft" align="right" valign="top"><a id="aeb037cc9cda118676dff8ad7505ddc2f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#aeb037cc9cda118676dff8ad7505ddc2f">REG_PORT_PMUX0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41008030UL)</td></tr>
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<tr class="memdesc:aeb037cc9cda118676dff8ad7505ddc2f"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Peripheral Multiplexing 0 <br /></td></tr>
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<tr class="separator:aeb037cc9cda118676dff8ad7505ddc2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e31b23171a494bff836994fa537f731"><td class="memItemLeft" align="right" valign="top"><a id="a2e31b23171a494bff836994fa537f731"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a2e31b23171a494bff836994fa537f731">REG_PORT_PINCFG0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41008040UL)</td></tr>
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<tr class="memdesc:a2e31b23171a494bff836994fa537f731"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Pin Configuration 0 <br /></td></tr>
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<tr class="separator:a2e31b23171a494bff836994fa537f731"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8dc6913719cf8cf84d5b902bb08b3e5"><td class="memItemLeft" align="right" valign="top"><a id="ac8dc6913719cf8cf84d5b902bb08b3e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ac8dc6913719cf8cf84d5b902bb08b3e5">REG_PORT_DIR1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008080UL)</td></tr>
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<tr class="memdesc:ac8dc6913719cf8cf84d5b902bb08b3e5"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction 1 <br /></td></tr>
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<tr class="separator:ac8dc6913719cf8cf84d5b902bb08b3e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05a281f12c37a0d891edb87e4e3f44f0"><td class="memItemLeft" align="right" valign="top"><a id="a05a281f12c37a0d891edb87e4e3f44f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a05a281f12c37a0d891edb87e4e3f44f0">REG_PORT_DIRCLR1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008084UL)</td></tr>
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<tr class="memdesc:a05a281f12c37a0d891edb87e4e3f44f0"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Clear 1 <br /></td></tr>
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<tr class="separator:a05a281f12c37a0d891edb87e4e3f44f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad08b54a1cadc6153671bd02995e7fdf9"><td class="memItemLeft" align="right" valign="top"><a id="ad08b54a1cadc6153671bd02995e7fdf9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ad08b54a1cadc6153671bd02995e7fdf9">REG_PORT_DIRSET1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008088UL)</td></tr>
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<tr class="memdesc:ad08b54a1cadc6153671bd02995e7fdf9"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Set 1 <br /></td></tr>
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<tr class="separator:ad08b54a1cadc6153671bd02995e7fdf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f243c3e1324bf63fe615463fd7da9ec"><td class="memItemLeft" align="right" valign="top"><a id="a3f243c3e1324bf63fe615463fd7da9ec"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a3f243c3e1324bf63fe615463fd7da9ec">REG_PORT_DIRTGL1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100808CUL)</td></tr>
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<tr class="memdesc:a3f243c3e1324bf63fe615463fd7da9ec"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Toggle 1 <br /></td></tr>
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<tr class="separator:a3f243c3e1324bf63fe615463fd7da9ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a675f28e419b3dad129f7d2866a37e957"><td class="memItemLeft" align="right" valign="top"><a id="a675f28e419b3dad129f7d2866a37e957"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a675f28e419b3dad129f7d2866a37e957">REG_PORT_OUT1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008090UL)</td></tr>
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<tr class="memdesc:a675f28e419b3dad129f7d2866a37e957"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value 1 <br /></td></tr>
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<tr class="separator:a675f28e419b3dad129f7d2866a37e957"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa231b8a484b2b2e25e024529ab0bdaa4"><td class="memItemLeft" align="right" valign="top"><a id="aa231b8a484b2b2e25e024529ab0bdaa4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#aa231b8a484b2b2e25e024529ab0bdaa4">REG_PORT_OUTCLR1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008094UL)</td></tr>
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<tr class="memdesc:aa231b8a484b2b2e25e024529ab0bdaa4"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Clear 1 <br /></td></tr>
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<tr class="separator:aa231b8a484b2b2e25e024529ab0bdaa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:accd4c6ca59c7375653168f8cd3f7695e"><td class="memItemLeft" align="right" valign="top"><a id="accd4c6ca59c7375653168f8cd3f7695e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#accd4c6ca59c7375653168f8cd3f7695e">REG_PORT_OUTSET1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008098UL)</td></tr>
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<tr class="memdesc:accd4c6ca59c7375653168f8cd3f7695e"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Set 1 <br /></td></tr>
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<tr class="separator:accd4c6ca59c7375653168f8cd3f7695e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6ef8a41ab86b47ac05ed1de8cc0442f1"><td class="memItemLeft" align="right" valign="top"><a id="a6ef8a41ab86b47ac05ed1de8cc0442f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a6ef8a41ab86b47ac05ed1de8cc0442f1">REG_PORT_OUTTGL1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100809CUL)</td></tr>
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<tr class="memdesc:a6ef8a41ab86b47ac05ed1de8cc0442f1"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Toggle 1 <br /></td></tr>
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<tr class="separator:a6ef8a41ab86b47ac05ed1de8cc0442f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a94288e15fe3ce4c8b1a968396de063ae"><td class="memItemLeft" align="right" valign="top"><a id="a94288e15fe3ce4c8b1a968396de063ae"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a94288e15fe3ce4c8b1a968396de063ae">REG_PORT_IN1</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x410080A0UL)</td></tr>
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<tr class="memdesc:a94288e15fe3ce4c8b1a968396de063ae"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Input Value 1 <br /></td></tr>
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<tr class="separator:a94288e15fe3ce4c8b1a968396de063ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ada81fa07af25afdc8437a28f6835784a"><td class="memItemLeft" align="right" valign="top"><a id="ada81fa07af25afdc8437a28f6835784a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ada81fa07af25afdc8437a28f6835784a">REG_PORT_CTRL1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x410080A4UL)</td></tr>
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<tr class="memdesc:ada81fa07af25afdc8437a28f6835784a"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Control 1 <br /></td></tr>
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<tr class="separator:ada81fa07af25afdc8437a28f6835784a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adf1cf6e3d72650defd52025c13333f75"><td class="memItemLeft" align="right" valign="top"><a id="adf1cf6e3d72650defd52025c13333f75"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#adf1cf6e3d72650defd52025c13333f75">REG_PORT_WRCONFIG1</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x410080A8UL)</td></tr>
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<tr class="memdesc:adf1cf6e3d72650defd52025c13333f75"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Write Configuration 1 <br /></td></tr>
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<tr class="separator:adf1cf6e3d72650defd52025c13333f75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac9e245291d5e9b4742b898acd2a48c51"><td class="memItemLeft" align="right" valign="top"><a id="ac9e245291d5e9b4742b898acd2a48c51"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ac9e245291d5e9b4742b898acd2a48c51">REG_PORT_EVCTRL1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x410080ACUL)</td></tr>
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<tr class="memdesc:ac9e245291d5e9b4742b898acd2a48c51"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Event Input Control 1 <br /></td></tr>
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<tr class="separator:ac9e245291d5e9b4742b898acd2a48c51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7045d8c7fbb9ac73235016d1f4c8e4f4"><td class="memItemLeft" align="right" valign="top"><a id="a7045d8c7fbb9ac73235016d1f4c8e4f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a7045d8c7fbb9ac73235016d1f4c8e4f4">REG_PORT_PMUX1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x410080B0UL)</td></tr>
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<tr class="memdesc:a7045d8c7fbb9ac73235016d1f4c8e4f4"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Peripheral Multiplexing 1 <br /></td></tr>
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<tr class="separator:a7045d8c7fbb9ac73235016d1f4c8e4f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a66e44ef756e8a9b0af90efe44ba34987"><td class="memItemLeft" align="right" valign="top"><a id="a66e44ef756e8a9b0af90efe44ba34987"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a66e44ef756e8a9b0af90efe44ba34987">REG_PORT_PINCFG1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x410080C0UL)</td></tr>
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<tr class="memdesc:a66e44ef756e8a9b0af90efe44ba34987"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Pin Configuration 1 <br /></td></tr>
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<tr class="separator:a66e44ef756e8a9b0af90efe44ba34987"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a872afd5fcbef3b6ee9ee6fb44add7146"><td class="memItemLeft" align="right" valign="top"><a id="a872afd5fcbef3b6ee9ee6fb44add7146"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a872afd5fcbef3b6ee9ee6fb44add7146">REG_PORT_DIR2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008100UL)</td></tr>
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<tr class="memdesc:a872afd5fcbef3b6ee9ee6fb44add7146"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction 2 <br /></td></tr>
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<tr class="separator:a872afd5fcbef3b6ee9ee6fb44add7146"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad38fc174d5931ccec83836e2612de56c"><td class="memItemLeft" align="right" valign="top"><a id="ad38fc174d5931ccec83836e2612de56c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ad38fc174d5931ccec83836e2612de56c">REG_PORT_DIRCLR2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008104UL)</td></tr>
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<tr class="memdesc:ad38fc174d5931ccec83836e2612de56c"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Clear 2 <br /></td></tr>
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<tr class="separator:ad38fc174d5931ccec83836e2612de56c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adce4f38c02a8477a5cb2f9c33f0b13d5"><td class="memItemLeft" align="right" valign="top"><a id="adce4f38c02a8477a5cb2f9c33f0b13d5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#adce4f38c02a8477a5cb2f9c33f0b13d5">REG_PORT_DIRSET2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008108UL)</td></tr>
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<tr class="memdesc:adce4f38c02a8477a5cb2f9c33f0b13d5"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Set 2 <br /></td></tr>
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<tr class="separator:adce4f38c02a8477a5cb2f9c33f0b13d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6ff43e4151c08f13eb157f2e66a40245"><td class="memItemLeft" align="right" valign="top"><a id="a6ff43e4151c08f13eb157f2e66a40245"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a6ff43e4151c08f13eb157f2e66a40245">REG_PORT_DIRTGL2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100810CUL)</td></tr>
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<tr class="memdesc:a6ff43e4151c08f13eb157f2e66a40245"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Toggle 2 <br /></td></tr>
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<tr class="separator:a6ff43e4151c08f13eb157f2e66a40245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a507d998c5cc641f434475cbcae20f5d0"><td class="memItemLeft" align="right" valign="top"><a id="a507d998c5cc641f434475cbcae20f5d0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a507d998c5cc641f434475cbcae20f5d0">REG_PORT_OUT2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008110UL)</td></tr>
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<tr class="memdesc:a507d998c5cc641f434475cbcae20f5d0"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value 2 <br /></td></tr>
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<tr class="separator:a507d998c5cc641f434475cbcae20f5d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4dbb89796636fd5c6dfb34c06cbb49b7"><td class="memItemLeft" align="right" valign="top"><a id="a4dbb89796636fd5c6dfb34c06cbb49b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a4dbb89796636fd5c6dfb34c06cbb49b7">REG_PORT_OUTCLR2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008114UL)</td></tr>
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<tr class="memdesc:a4dbb89796636fd5c6dfb34c06cbb49b7"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Clear 2 <br /></td></tr>
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<tr class="separator:a4dbb89796636fd5c6dfb34c06cbb49b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c956e8d7634fb454c1a84ea67634b88"><td class="memItemLeft" align="right" valign="top"><a id="a2c956e8d7634fb454c1a84ea67634b88"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a2c956e8d7634fb454c1a84ea67634b88">REG_PORT_OUTSET2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008118UL)</td></tr>
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<tr class="memdesc:a2c956e8d7634fb454c1a84ea67634b88"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Set 2 <br /></td></tr>
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<tr class="separator:a2c956e8d7634fb454c1a84ea67634b88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba863da2144fcdc3b7d8e123f4092277"><td class="memItemLeft" align="right" valign="top"><a id="aba863da2144fcdc3b7d8e123f4092277"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#aba863da2144fcdc3b7d8e123f4092277">REG_PORT_OUTTGL2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100811CUL)</td></tr>
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<tr class="memdesc:aba863da2144fcdc3b7d8e123f4092277"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Toggle 2 <br /></td></tr>
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<tr class="separator:aba863da2144fcdc3b7d8e123f4092277"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a76da99db4e2d836ad27f8803a0252ffc"><td class="memItemLeft" align="right" valign="top"><a id="a76da99db4e2d836ad27f8803a0252ffc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a76da99db4e2d836ad27f8803a0252ffc">REG_PORT_IN2</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41008120UL)</td></tr>
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<tr class="memdesc:a76da99db4e2d836ad27f8803a0252ffc"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Input Value 2 <br /></td></tr>
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<tr class="separator:a76da99db4e2d836ad27f8803a0252ffc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa36d2fd0669cc9c6dc7999c6f67f0ea2"><td class="memItemLeft" align="right" valign="top"><a id="aa36d2fd0669cc9c6dc7999c6f67f0ea2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#aa36d2fd0669cc9c6dc7999c6f67f0ea2">REG_PORT_CTRL2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008124UL)</td></tr>
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<tr class="memdesc:aa36d2fd0669cc9c6dc7999c6f67f0ea2"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Control 2 <br /></td></tr>
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<tr class="separator:aa36d2fd0669cc9c6dc7999c6f67f0ea2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e146dee7a6dd42fa8a1e991fd949474"><td class="memItemLeft" align="right" valign="top"><a id="a8e146dee7a6dd42fa8a1e991fd949474"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a8e146dee7a6dd42fa8a1e991fd949474">REG_PORT_WRCONFIG2</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x41008128UL)</td></tr>
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<tr class="memdesc:a8e146dee7a6dd42fa8a1e991fd949474"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Write Configuration 2 <br /></td></tr>
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<tr class="separator:a8e146dee7a6dd42fa8a1e991fd949474"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af89f6c4f192391bee2733e726ff25b63"><td class="memItemLeft" align="right" valign="top"><a id="af89f6c4f192391bee2733e726ff25b63"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#af89f6c4f192391bee2733e726ff25b63">REG_PORT_EVCTRL2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100812CUL)</td></tr>
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<tr class="memdesc:af89f6c4f192391bee2733e726ff25b63"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Event Input Control 2 <br /></td></tr>
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<tr class="separator:af89f6c4f192391bee2733e726ff25b63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a861b7f546ae0bb7f02905f5a30cd1c67"><td class="memItemLeft" align="right" valign="top"><a id="a861b7f546ae0bb7f02905f5a30cd1c67"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a861b7f546ae0bb7f02905f5a30cd1c67">REG_PORT_PMUX2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41008130UL)</td></tr>
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<tr class="memdesc:a861b7f546ae0bb7f02905f5a30cd1c67"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Peripheral Multiplexing 2 <br /></td></tr>
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<tr class="separator:a861b7f546ae0bb7f02905f5a30cd1c67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac17d95425b4880233144f4a9fda3f12b"><td class="memItemLeft" align="right" valign="top"><a id="ac17d95425b4880233144f4a9fda3f12b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#ac17d95425b4880233144f4a9fda3f12b">REG_PORT_PINCFG2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41008140UL)</td></tr>
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<tr class="memdesc:ac17d95425b4880233144f4a9fda3f12b"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Pin Configuration 2 <br /></td></tr>
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<tr class="separator:ac17d95425b4880233144f4a9fda3f12b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb974144b9fcaadfaf05ba87bb68e089"><td class="memItemLeft" align="right" valign="top"><a id="adb974144b9fcaadfaf05ba87bb68e089"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#adb974144b9fcaadfaf05ba87bb68e089">REG_PORT_DIR3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008180UL)</td></tr>
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<tr class="memdesc:adb974144b9fcaadfaf05ba87bb68e089"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction 3 <br /></td></tr>
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<tr class="separator:adb974144b9fcaadfaf05ba87bb68e089"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb37489aebca03ae1447cc096efa49d4"><td class="memItemLeft" align="right" valign="top"><a id="afb37489aebca03ae1447cc096efa49d4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#afb37489aebca03ae1447cc096efa49d4">REG_PORT_DIRCLR3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008184UL)</td></tr>
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<tr class="memdesc:afb37489aebca03ae1447cc096efa49d4"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Clear 3 <br /></td></tr>
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<tr class="separator:afb37489aebca03ae1447cc096efa49d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95c61d5508d06ed87eaf8e705e22d7d7"><td class="memItemLeft" align="right" valign="top"><a id="a95c61d5508d06ed87eaf8e705e22d7d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a95c61d5508d06ed87eaf8e705e22d7d7">REG_PORT_DIRSET3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008188UL)</td></tr>
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<tr class="memdesc:a95c61d5508d06ed87eaf8e705e22d7d7"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Set 3 <br /></td></tr>
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<tr class="separator:a95c61d5508d06ed87eaf8e705e22d7d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a982edfcece99f6e44ce29b7689a61d9e"><td class="memItemLeft" align="right" valign="top"><a id="a982edfcece99f6e44ce29b7689a61d9e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a982edfcece99f6e44ce29b7689a61d9e">REG_PORT_DIRTGL3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100818CUL)</td></tr>
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<tr class="memdesc:a982edfcece99f6e44ce29b7689a61d9e"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Direction Toggle 3 <br /></td></tr>
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<tr class="separator:a982edfcece99f6e44ce29b7689a61d9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7098f84e744325310acee6d70fc22ee3"><td class="memItemLeft" align="right" valign="top"><a id="a7098f84e744325310acee6d70fc22ee3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a7098f84e744325310acee6d70fc22ee3">REG_PORT_OUT3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008190UL)</td></tr>
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<tr class="memdesc:a7098f84e744325310acee6d70fc22ee3"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value 3 <br /></td></tr>
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<tr class="separator:a7098f84e744325310acee6d70fc22ee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a527c434ecfc889b9f7d68129675d769b"><td class="memItemLeft" align="right" valign="top"><a id="a527c434ecfc889b9f7d68129675d769b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a527c434ecfc889b9f7d68129675d769b">REG_PORT_OUTCLR3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008194UL)</td></tr>
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<tr class="memdesc:a527c434ecfc889b9f7d68129675d769b"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Clear 3 <br /></td></tr>
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<tr class="separator:a527c434ecfc889b9f7d68129675d769b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee2f7f8e3c5c5c89c69c8201625e0c8f"><td class="memItemLeft" align="right" valign="top"><a id="aee2f7f8e3c5c5c89c69c8201625e0c8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#aee2f7f8e3c5c5c89c69c8201625e0c8f">REG_PORT_OUTSET3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41008198UL)</td></tr>
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<tr class="memdesc:aee2f7f8e3c5c5c89c69c8201625e0c8f"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Set 3 <br /></td></tr>
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<tr class="separator:aee2f7f8e3c5c5c89c69c8201625e0c8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3530acbf836432a098d1447637055da4"><td class="memItemLeft" align="right" valign="top"><a id="a3530acbf836432a098d1447637055da4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a3530acbf836432a098d1447637055da4">REG_PORT_OUTTGL3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100819CUL)</td></tr>
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<tr class="memdesc:a3530acbf836432a098d1447637055da4"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Output Value Toggle 3 <br /></td></tr>
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<tr class="separator:a3530acbf836432a098d1447637055da4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4b3e245beaa6ebec94956e5d0b7fb417"><td class="memItemLeft" align="right" valign="top"><a id="a4b3e245beaa6ebec94956e5d0b7fb417"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a4b3e245beaa6ebec94956e5d0b7fb417">REG_PORT_IN3</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x410081A0UL)</td></tr>
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<tr class="memdesc:a4b3e245beaa6ebec94956e5d0b7fb417"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Data Input Value 3 <br /></td></tr>
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<tr class="separator:a4b3e245beaa6ebec94956e5d0b7fb417"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad460286154e843c5df4fab20ecb9c80"><td class="memItemLeft" align="right" valign="top"><a id="aad460286154e843c5df4fab20ecb9c80"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#aad460286154e843c5df4fab20ecb9c80">REG_PORT_CTRL3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x410081A4UL)</td></tr>
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<tr class="memdesc:aad460286154e843c5df4fab20ecb9c80"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Control 3 <br /></td></tr>
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<tr class="separator:aad460286154e843c5df4fab20ecb9c80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7175d2d84e153a5f5549772e59a19fd2"><td class="memItemLeft" align="right" valign="top"><a id="a7175d2d84e153a5f5549772e59a19fd2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a7175d2d84e153a5f5549772e59a19fd2">REG_PORT_WRCONFIG3</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x410081A8UL)</td></tr>
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<tr class="memdesc:a7175d2d84e153a5f5549772e59a19fd2"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Write Configuration 3 <br /></td></tr>
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<tr class="separator:a7175d2d84e153a5f5549772e59a19fd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5646355ad13c594ac708cf2b5ca47e5b"><td class="memItemLeft" align="right" valign="top"><a id="a5646355ad13c594ac708cf2b5ca47e5b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a5646355ad13c594ac708cf2b5ca47e5b">REG_PORT_EVCTRL3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x410081ACUL)</td></tr>
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<tr class="memdesc:a5646355ad13c594ac708cf2b5ca47e5b"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Event Input Control 3 <br /></td></tr>
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<tr class="separator:a5646355ad13c594ac708cf2b5ca47e5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a37e0d2dbf82c71a19abf8f91285523ef"><td class="memItemLeft" align="right" valign="top"><a id="a37e0d2dbf82c71a19abf8f91285523ef"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a37e0d2dbf82c71a19abf8f91285523ef">REG_PORT_PMUX3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x410081B0UL)</td></tr>
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<tr class="memdesc:a37e0d2dbf82c71a19abf8f91285523ef"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Peripheral Multiplexing 3 <br /></td></tr>
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<tr class="separator:a37e0d2dbf82c71a19abf8f91285523ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a08074a30f4db9891561655ac0d57012c"><td class="memItemLeft" align="right" valign="top"><a id="a08074a30f4db9891561655ac0d57012c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2port_8h.html#a08074a30f4db9891561655ac0d57012c">REG_PORT_PINCFG3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x410081C0UL)</td></tr>
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<tr class="memdesc:a08074a30f4db9891561655ac0d57012c"><td class="mdescLeft"> </td><td class="mdescRight">(PORT) Pin Configuration 3 <br /></td></tr>
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<tr class="separator:a08074a30f4db9891561655ac0d57012c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a108355009766d90bac37c294fad39ca5"><td class="memItemLeft" align="right" valign="top"><a id="a108355009766d90bac37c294fad39ca5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_BITS</b>   118</td></tr>
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<tr class="separator:a108355009766d90bac37c294fad39ca5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af35308b5676631ef93a605aadc6b8fa3"><td class="memItemLeft" align="right" valign="top"><a id="af35308b5676631ef93a605aadc6b8fa3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_DIR_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:af35308b5676631ef93a605aadc6b8fa3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed3571ae30bfd475f338a8e0405f44bf"><td class="memItemLeft" align="right" valign="top"><a id="aed3571ae30bfd475f338a8e0405f44bf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_DIR_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:aed3571ae30bfd475f338a8e0405f44bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a9b97ea98e9ff54a57e515b471446bc"><td class="memItemLeft" align="right" valign="top"><a id="a0a9b97ea98e9ff54a57e515b471446bc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_DRVSTR</b>   1</td></tr>
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<tr class="separator:a0a9b97ea98e9ff54a57e515b471446bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0de17a59016df06f9eb2f30f81f9a1d2"><td class="memItemLeft" align="right" valign="top"><a id="a0de17a59016df06f9eb2f30f81f9a1d2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_DRVSTR_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a0de17a59016df06f9eb2f30f81f9a1d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29743b20fe94f722e725c573ad5291ee"><td class="memItemLeft" align="right" valign="top"><a id="a29743b20fe94f722e725c573ad5291ee"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_DRVSTR_IMPLEMENTED</b>   { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:a29743b20fe94f722e725c573ad5291ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5af913fc10c2af2a00eb1e9e8d663e93"><td class="memItemLeft" align="right" valign="top"><a id="a5af913fc10c2af2a00eb1e9e8d663e93"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_EVENT_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:a5af913fc10c2af2a00eb1e9e8d663e93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa3ed1ff1cb6ff30d094138b40b501fee"><td class="memItemLeft" align="right" valign="top"><a id="aa3ed1ff1cb6ff30d094138b40b501fee"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_EV_NUM</b>   4</td></tr>
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<tr class="separator:aa3ed1ff1cb6ff30d094138b40b501fee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abd4af8f89bda0b310c1126bd4b852932"><td class="memItemLeft" align="right" valign="top"><a id="abd4af8f89bda0b310c1126bd4b852932"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_INEN_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:abd4af8f89bda0b310c1126bd4b852932"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01514846baea78c2bf128ac4e52920d9"><td class="memItemLeft" align="right" valign="top"><a id="a01514846baea78c2bf128ac4e52920d9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_INEN_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:a01514846baea78c2bf128ac4e52920d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af6f92c9535b0a11b9f68ad164d9b65b1"><td class="memItemLeft" align="right" valign="top"><a id="af6f92c9535b0a11b9f68ad164d9b65b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_ODRAIN</b>   0</td></tr>
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<tr class="separator:af6f92c9535b0a11b9f68ad164d9b65b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1bad589458245b39eb99941949141dca"><td class="memItemLeft" align="right" valign="top"><a id="a1bad589458245b39eb99941949141dca"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_ODRAIN_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a1bad589458245b39eb99941949141dca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c1a628312fae8b4b986c34bc9dbd1a4"><td class="memItemLeft" align="right" valign="top"><a id="a5c1a628312fae8b4b986c34bc9dbd1a4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_ODRAIN_IMPLEMENTED</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a5c1a628312fae8b4b986c34bc9dbd1a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acc57f650f9f7b0df5922cb8173fc2dc0"><td class="memItemLeft" align="right" valign="top"><a id="acc57f650f9f7b0df5922cb8173fc2dc0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_OUT_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:acc57f650f9f7b0df5922cb8173fc2dc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6fc15edfdf94c8abed0afaaff8dc7240"><td class="memItemLeft" align="right" valign="top"><a id="a6fc15edfdf94c8abed0afaaff8dc7240"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_OUT_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:a6fc15edfdf94c8abed0afaaff8dc7240"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6260d5ab94402da0ee3ff84ec12fb776"><td class="memItemLeft" align="right" valign="top"><a id="a6260d5ab94402da0ee3ff84ec12fb776"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PIN_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:a6260d5ab94402da0ee3ff84ec12fb776"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3249c95a7ea25926722286d8d9662b18"><td class="memItemLeft" align="right" valign="top"><a id="a3249c95a7ea25926722286d8d9662b18"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT0_DEFAULT_VAL</b>   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a3249c95a7ea25926722286d8d9662b18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67c615949f64d8133db323a81ce36a64"><td class="memItemLeft" align="right" valign="top"><a id="a67c615949f64d8133db323a81ce36a64"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT0_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }</td></tr>
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<tr class="separator:a67c615949f64d8133db323a81ce36a64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad44e50d9c838ae9fb1653194bdac46ba"><td class="memItemLeft" align="right" valign="top"><a id="ad44e50d9c838ae9fb1653194bdac46ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT1_DEFAULT_VAL</b>   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:ad44e50d9c838ae9fb1653194bdac46ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c07ddf5efcaaec18059806ffba9d645"><td class="memItemLeft" align="right" valign="top"><a id="a4c07ddf5efcaaec18059806ffba9d645"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT1_IMPLEMENTED</b>   { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }</td></tr>
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<tr class="separator:a4c07ddf5efcaaec18059806ffba9d645"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28183bf8a1f48c2ee9830c3984f41b91"><td class="memItemLeft" align="right" valign="top"><a id="a28183bf8a1f48c2ee9830c3984f41b91"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT2_DEFAULT_VAL</b>   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a28183bf8a1f48c2ee9830c3984f41b91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6fca565e25fee996160a96bed502f7f8"><td class="memItemLeft" align="right" valign="top"><a id="a6fca565e25fee996160a96bed502f7f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT2_IMPLEMENTED</b>   { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }</td></tr>
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<tr class="separator:a6fca565e25fee996160a96bed502f7f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f7c5d6003a98b0322a273ae35c4cf57"><td class="memItemLeft" align="right" valign="top"><a id="a1f7c5d6003a98b0322a273ae35c4cf57"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT3_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a1f7c5d6003a98b0322a273ae35c4cf57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad47d79c51875355cabbe91b790be1ced"><td class="memItemLeft" align="right" valign="top"><a id="ad47d79c51875355cabbe91b790be1ced"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXBIT3_IMPLEMENTED</b>   { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }</td></tr>
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<tr class="separator:ad47d79c51875355cabbe91b790be1ced"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7ca878682ce9bcf7224ad35fbb3e207"><td class="memItemLeft" align="right" valign="top"><a id="af7ca878682ce9bcf7224ad35fbb3e207"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXEN_DEFAULT_VAL</b>   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:af7ca878682ce9bcf7224ad35fbb3e207"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a03807024b771aab5517f294c03428289"><td class="memItemLeft" align="right" valign="top"><a id="a03807024b771aab5517f294c03428289"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PMUXEN_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:a03807024b771aab5517f294c03428289"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a800cc0eee881aa316f1128d5de0d76ac"><td class="memItemLeft" align="right" valign="top"><a id="a800cc0eee881aa316f1128d5de0d76ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PPP_IMPLEMENTED</b>   { 0x00000001 }</td></tr>
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<tr class="separator:a800cc0eee881aa316f1128d5de0d76ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a151ac8ec2dbf4c508720499d59c29c3f"><td class="memItemLeft" align="right" valign="top"><a id="a151ac8ec2dbf4c508720499d59c29c3f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PULLEN_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a151ac8ec2dbf4c508720499d59c29c3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a847bb6c2eb088bd0ced3f6cc48f0ffd2"><td class="memItemLeft" align="right" valign="top"><a id="a847bb6c2eb088bd0ced3f6cc48f0ffd2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PULLEN_IMPLEMENTED</b>   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</td></tr>
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<tr class="separator:a847bb6c2eb088bd0ced3f6cc48f0ffd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa6127560cb5e14032802d7d9d5f7dfdf"><td class="memItemLeft" align="right" valign="top"><a id="aa6127560cb5e14032802d7d9d5f7dfdf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_SLEWLIM</b>   0</td></tr>
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<tr class="separator:aa6127560cb5e14032802d7d9d5f7dfdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6fbe4c8f1489188aaeaf5d1c86c2d3a4"><td class="memItemLeft" align="right" valign="top"><a id="a6fbe4c8f1489188aaeaf5d1c86c2d3a4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_SLEWLIM_DEFAULT_VAL</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:a6fbe4c8f1489188aaeaf5d1c86c2d3a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab345cb20e5b1b20e1926142fbe81ba85"><td class="memItemLeft" align="right" valign="top"><a id="ab345cb20e5b1b20e1926142fbe81ba85"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_SLEWLIM_IMPLEMENTED</b>   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</td></tr>
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<tr class="separator:ab345cb20e5b1b20e1926142fbe81ba85"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for PORT. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2port_8h_source.html">port.h</a>.</p>
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