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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">nvmctrl.h</div> </div>
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<a href="instance_2nvmctrl_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_NVMCTRL_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_NVMCTRL_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for NVMCTRL peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_NVMCTRL_CTRLA (0x41004000) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_NVMCTRL_CTRLB (0x41004004) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_NVMCTRL_PARAM (0x41004008) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_NVMCTRL_INTENCLR (0x4100400C) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_NVMCTRL_INTENSET (0x4100400E) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_NVMCTRL_INTFLAG (0x41004010) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_NVMCTRL_STATUS (0x41004012) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_NVMCTRL_ADDR (0x41004014) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_NVMCTRL_RUNLOCK (0x41004018) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_NVMCTRL_PBLDATA0 (0x4100401C) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_NVMCTRL_PBLDATA1 (0x41004020) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_NVMCTRL_ECCERR (0x41004024) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_NVMCTRL_DBGCTRL (0x41004028) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_NVMCTRL_SEECFG (0x4100402A) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_NVMCTRL_SEESTAT (0x4100402C) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#acc618e21a0eb1ab2ffa30b4cfe4959b2"> 51</a></span> <span class="preprocessor">#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a3b5ee6fc085db292ab663404984f188b"> 52</a></span> <span class="preprocessor">#define REG_NVMCTRL_CTRLB (*(WoReg16*)0x41004004UL) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#acb8bca389483cfb6fe2b55808f309679"> 53</a></span> <span class="preprocessor">#define REG_NVMCTRL_PARAM (*(RoReg *)0x41004008UL) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#aa5c3423c4f0873ba42ba07701eeddcc3"> 54</a></span> <span class="preprocessor">#define REG_NVMCTRL_INTENCLR (*(RwReg16*)0x4100400CUL) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a10dae9ef3de98a81b07f25c3d966742d"> 55</a></span> <span class="preprocessor">#define REG_NVMCTRL_INTENSET (*(RwReg16*)0x4100400EUL) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#aefe5fb67fdd36dd1074f4b7f7baa4301"> 56</a></span> <span class="preprocessor">#define REG_NVMCTRL_INTFLAG (*(RwReg16*)0x41004010UL) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a2f1bef4d068f3d9fe9b2668db41eec7a"> 57</a></span> <span class="preprocessor">#define REG_NVMCTRL_STATUS (*(RoReg16*)0x41004012UL) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a5e95aa19ff2d77918b1b29bb5fb7e83e"> 58</a></span> <span class="preprocessor">#define REG_NVMCTRL_ADDR (*(RwReg *)0x41004014UL) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a9d0f5d37f3bd30480c37de538f8faff5"> 59</a></span> <span class="preprocessor">#define REG_NVMCTRL_RUNLOCK (*(RoReg *)0x41004018UL) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#aa2b37013eaceec7fe5e069e661a1d135"> 60</a></span> <span class="preprocessor">#define REG_NVMCTRL_PBLDATA0 (*(RoReg *)0x4100401CUL) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a3ebda2c1f15ec7775b7c1c42cf00840f"> 61</a></span> <span class="preprocessor">#define REG_NVMCTRL_PBLDATA1 (*(RoReg *)0x41004020UL) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#ae3167a45dc850da39a82c775be1f2987"> 62</a></span> <span class="preprocessor">#define REG_NVMCTRL_ECCERR (*(RoReg *)0x41004024UL) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a94b8559ddc5da94450f23a76f3a04117"> 63</a></span> <span class="preprocessor">#define REG_NVMCTRL_DBGCTRL (*(RwReg8 *)0x41004028UL) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#a8161e55906c971605a3d1b9fb6c1cdf6"> 64</a></span> <span class="preprocessor">#define REG_NVMCTRL_SEECFG (*(RwReg8 *)0x4100402AUL) </span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="instance_2nvmctrl_8h.html#ad24afe0e8d778a96a75df7c462ce8eb6"> 65</a></span> <span class="preprocessor">#define REG_NVMCTRL_SEESTAT (*(RoReg *)0x4100402CUL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"> 66</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"> 67</span>  </div>
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<div class="line"><a name="l00068"></a><span class="lineno"> 68</span> <span class="comment">/* ========== Instance parameters for NVMCTRL peripheral ========== */</span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"> 69</span> <span class="preprocessor">#define NVMCTRL_BLOCK_SIZE 8192 // Size Of Block (Bytes, Smallest Granularity for Erase Operation)</span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"> 70</span> <span class="preprocessor">#define NVMCTRL_CLK_AHB_ID 6 // Index of AHB Clock in PM.AHBMASK register</span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"> 71</span> <span class="preprocessor">#define NVMCTRL_CLK_AHB_ID_CACHE 23 // Index of AHB Clock in PM.AHBMASK register for NVMCTRL CACHE lines</span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"> 72</span> <span class="preprocessor">#define NVMCTRL_CLK_AHB_ID_SMEEPROM 22 // Index of AHB Clock in PM.AHBMASK register for SMEE submodule</span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"> 73</span> <span class="preprocessor">#define NVMCTRL_PAGE_SIZE 512 // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array)</span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"> 74</span>  </div>
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<div class="line"><a name="l00075"></a><span class="lineno"> 75</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_NVMCTRL_INSTANCE_ */</span><span class="preprocessor"></span></div>
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