doc/html/instance_2nvmctrl_8h_source.html

#ifndef _SAME54_NVMCTRL_INSTANCE_

#define _SAME54_NVMCTRL_INSTANCE_


/* ========== Register definition for NVMCTRL peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_NVMCTRL_CTRLA          (0x41004000)

#define REG_NVMCTRL_CTRLB          (0x41004004)

#define REG_NVMCTRL_PARAM          (0x41004008)

#define REG_NVMCTRL_INTENCLR       (0x4100400C)

#define REG_NVMCTRL_INTENSET       (0x4100400E)

#define REG_NVMCTRL_INTFLAG        (0x41004010)

#define REG_NVMCTRL_STATUS         (0x41004012)

#define REG_NVMCTRL_ADDR           (0x41004014)

#define REG_NVMCTRL_RUNLOCK        (0x41004018)

#define REG_NVMCTRL_PBLDATA0       (0x4100401C)

#define REG_NVMCTRL_PBLDATA1       (0x41004020)

#define REG_NVMCTRL_ECCERR         (0x41004024)

#define REG_NVMCTRL_DBGCTRL        (0x41004028)

#define REG_NVMCTRL_SEECFG         (0x4100402A)

#define REG_NVMCTRL_SEESTAT        (0x4100402C)

#else

#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000UL)

#define REG_NVMCTRL_CTRLB          (*(WoReg16*)0x41004004UL)

#define REG_NVMCTRL_PARAM          (*(RoReg  *)0x41004008UL)

#define REG_NVMCTRL_INTENCLR       (*(RwReg16*)0x4100400CUL)

#define REG_NVMCTRL_INTENSET       (*(RwReg16*)0x4100400EUL)

#define REG_NVMCTRL_INTFLAG        (*(RwReg16*)0x41004010UL)

#define REG_NVMCTRL_STATUS         (*(RoReg16*)0x41004012UL)

#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x41004014UL)

#define REG_NVMCTRL_RUNLOCK        (*(RoReg  *)0x41004018UL)

#define REG_NVMCTRL_PBLDATA0       (*(RoReg  *)0x4100401CUL)

#define REG_NVMCTRL_PBLDATA1       (*(RoReg  *)0x41004020UL)

#define REG_NVMCTRL_ECCERR         (*(RoReg  *)0x41004024UL)

#define REG_NVMCTRL_DBGCTRL        (*(RwReg8 *)0x41004028UL)

#define REG_NVMCTRL_SEECFG         (*(RwReg8 *)0x4100402AUL)

#define REG_NVMCTRL_SEESTAT        (*(RoReg  *)0x4100402CUL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for NVMCTRL peripheral ========== */

#define NVMCTRL_BLOCK_SIZE          8192     // Size Of Block (Bytes, Smallest Granularity for Erase Operation)

#define NVMCTRL_CLK_AHB_ID          6        // Index of AHB Clock in PM.AHBMASK register

#define NVMCTRL_CLK_AHB_ID_CACHE    23       // Index of AHB Clock in PM.AHBMASK register for NVMCTRL CACHE lines

#define NVMCTRL_CLK_AHB_ID_SMEEPROM 22       // Index of AHB Clock in PM.AHBMASK register for SMEE submodule

#define NVMCTRL_PAGE_SIZE           512      // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array)


#endif /* _SAME54_NVMCTRL_INSTANCE_ */