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299 lines
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">can1.h File Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>Instance description for CAN1.
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<a href="#details">More...</a></p>
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<p><a href="can1_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a59ee2251dbaeffbdf8ccf8799c92220c"><td class="memItemLeft" align="right" valign="top"><a id="a59ee2251dbaeffbdf8ccf8799c92220c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a59ee2251dbaeffbdf8ccf8799c92220c">REG_CAN1_CREL</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000400UL)</td></tr>
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<tr class="memdesc:a59ee2251dbaeffbdf8ccf8799c92220c"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Core Release <br /></td></tr>
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<tr class="separator:a59ee2251dbaeffbdf8ccf8799c92220c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae634cf07fb4e342f2a4ca4c08d6f50cf"><td class="memItemLeft" align="right" valign="top"><a id="ae634cf07fb4e342f2a4ca4c08d6f50cf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ae634cf07fb4e342f2a4ca4c08d6f50cf">REG_CAN1_ENDN</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000404UL)</td></tr>
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<tr class="memdesc:ae634cf07fb4e342f2a4ca4c08d6f50cf"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Endian <br /></td></tr>
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<tr class="separator:ae634cf07fb4e342f2a4ca4c08d6f50cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ad7df01e2356786472b1a7e9c463c9d"><td class="memItemLeft" align="right" valign="top"><a id="a5ad7df01e2356786472b1a7e9c463c9d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a5ad7df01e2356786472b1a7e9c463c9d">REG_CAN1_MRCFG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000408UL)</td></tr>
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<tr class="memdesc:a5ad7df01e2356786472b1a7e9c463c9d"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Message RAM Configuration <br /></td></tr>
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<tr class="separator:a5ad7df01e2356786472b1a7e9c463c9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abba79d61995499a274f20d5b5f4b7aba"><td class="memItemLeft" align="right" valign="top"><a id="abba79d61995499a274f20d5b5f4b7aba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#abba79d61995499a274f20d5b5f4b7aba">REG_CAN1_DBTP</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200040CUL)</td></tr>
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<tr class="memdesc:abba79d61995499a274f20d5b5f4b7aba"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Fast Bit Timing and Prescaler <br /></td></tr>
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<tr class="separator:abba79d61995499a274f20d5b5f4b7aba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a470abb8ee63aa5041957e73718b760ca"><td class="memItemLeft" align="right" valign="top"><a id="a470abb8ee63aa5041957e73718b760ca"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a470abb8ee63aa5041957e73718b760ca">REG_CAN1_TEST</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000410UL)</td></tr>
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<tr class="memdesc:a470abb8ee63aa5041957e73718b760ca"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Test <br /></td></tr>
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<tr class="separator:a470abb8ee63aa5041957e73718b760ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac153897aacd488e7789e7cccc0746245"><td class="memItemLeft" align="right" valign="top"><a id="ac153897aacd488e7789e7cccc0746245"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ac153897aacd488e7789e7cccc0746245">REG_CAN1_RWD</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000414UL)</td></tr>
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<tr class="memdesc:ac153897aacd488e7789e7cccc0746245"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) RAM Watchdog <br /></td></tr>
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<tr class="separator:ac153897aacd488e7789e7cccc0746245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4d209956fcbd2bc5474d40b60543664"><td class="memItemLeft" align="right" valign="top"><a id="ab4d209956fcbd2bc5474d40b60543664"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ab4d209956fcbd2bc5474d40b60543664">REG_CAN1_CCCR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000418UL)</td></tr>
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<tr class="memdesc:ab4d209956fcbd2bc5474d40b60543664"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) CC Control <br /></td></tr>
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<tr class="separator:ab4d209956fcbd2bc5474d40b60543664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4caa2592c5c2bb2772ee2a6b54fdda46"><td class="memItemLeft" align="right" valign="top"><a id="a4caa2592c5c2bb2772ee2a6b54fdda46"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a4caa2592c5c2bb2772ee2a6b54fdda46">REG_CAN1_NBTP</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200041CUL)</td></tr>
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<tr class="memdesc:a4caa2592c5c2bb2772ee2a6b54fdda46"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Nominal Bit Timing and Prescaler <br /></td></tr>
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<tr class="separator:a4caa2592c5c2bb2772ee2a6b54fdda46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a309188ead4dfb0b9fff7a8df2ca386ba"><td class="memItemLeft" align="right" valign="top"><a id="a309188ead4dfb0b9fff7a8df2ca386ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a309188ead4dfb0b9fff7a8df2ca386ba">REG_CAN1_TSCC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000420UL)</td></tr>
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<tr class="memdesc:a309188ead4dfb0b9fff7a8df2ca386ba"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Timestamp Counter Configuration <br /></td></tr>
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<tr class="separator:a309188ead4dfb0b9fff7a8df2ca386ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec2b57598deb21aac5278f737a5de49b"><td class="memItemLeft" align="right" valign="top"><a id="aec2b57598deb21aac5278f737a5de49b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#aec2b57598deb21aac5278f737a5de49b">REG_CAN1_TSCV</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000424UL)</td></tr>
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<tr class="memdesc:aec2b57598deb21aac5278f737a5de49b"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Timestamp Counter Value <br /></td></tr>
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<tr class="separator:aec2b57598deb21aac5278f737a5de49b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2b5eb175d1812f94eefe18ff7f5414ec"><td class="memItemLeft" align="right" valign="top"><a id="a2b5eb175d1812f94eefe18ff7f5414ec"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a2b5eb175d1812f94eefe18ff7f5414ec">REG_CAN1_TOCC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000428UL)</td></tr>
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<tr class="memdesc:a2b5eb175d1812f94eefe18ff7f5414ec"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Timeout Counter Configuration <br /></td></tr>
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<tr class="separator:a2b5eb175d1812f94eefe18ff7f5414ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4319ad0f3c98cfb1a016d04b55c2c3ba"><td class="memItemLeft" align="right" valign="top"><a id="a4319ad0f3c98cfb1a016d04b55c2c3ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a4319ad0f3c98cfb1a016d04b55c2c3ba">REG_CAN1_TOCV</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200042CUL)</td></tr>
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<tr class="memdesc:a4319ad0f3c98cfb1a016d04b55c2c3ba"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Timeout Counter Value <br /></td></tr>
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<tr class="separator:a4319ad0f3c98cfb1a016d04b55c2c3ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d89c28482aa9c664e93099bbb2ff3a5"><td class="memItemLeft" align="right" valign="top"><a id="a4d89c28482aa9c664e93099bbb2ff3a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a4d89c28482aa9c664e93099bbb2ff3a5">REG_CAN1_ECR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000440UL)</td></tr>
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<tr class="memdesc:a4d89c28482aa9c664e93099bbb2ff3a5"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Error Counter <br /></td></tr>
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<tr class="separator:a4d89c28482aa9c664e93099bbb2ff3a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa6b875959828d94ad909b34d2b845091"><td class="memItemLeft" align="right" valign="top"><a id="aa6b875959828d94ad909b34d2b845091"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#aa6b875959828d94ad909b34d2b845091">REG_CAN1_PSR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000444UL)</td></tr>
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<tr class="memdesc:aa6b875959828d94ad909b34d2b845091"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Protocol Status <br /></td></tr>
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<tr class="separator:aa6b875959828d94ad909b34d2b845091"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a40136d905788b45f4aea683831dbd04e"><td class="memItemLeft" align="right" valign="top"><a id="a40136d905788b45f4aea683831dbd04e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a40136d905788b45f4aea683831dbd04e">REG_CAN1_TDCR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000448UL)</td></tr>
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<tr class="memdesc:a40136d905788b45f4aea683831dbd04e"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Extended ID Filter Configuration <br /></td></tr>
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<tr class="separator:a40136d905788b45f4aea683831dbd04e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb39471220816a31e454ab41838a2355"><td class="memItemLeft" align="right" valign="top"><a id="aeb39471220816a31e454ab41838a2355"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#aeb39471220816a31e454ab41838a2355">REG_CAN1_IR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000450UL)</td></tr>
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<tr class="memdesc:aeb39471220816a31e454ab41838a2355"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Interrupt <br /></td></tr>
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<tr class="separator:aeb39471220816a31e454ab41838a2355"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acab7b4c88a26260c0f6bbcdaa41bcc07"><td class="memItemLeft" align="right" valign="top"><a id="acab7b4c88a26260c0f6bbcdaa41bcc07"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#acab7b4c88a26260c0f6bbcdaa41bcc07">REG_CAN1_IE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000454UL)</td></tr>
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<tr class="memdesc:acab7b4c88a26260c0f6bbcdaa41bcc07"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Interrupt Enable <br /></td></tr>
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<tr class="separator:acab7b4c88a26260c0f6bbcdaa41bcc07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34983ab7904733fe8e2d09d5b0259c90"><td class="memItemLeft" align="right" valign="top"><a id="a34983ab7904733fe8e2d09d5b0259c90"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a34983ab7904733fe8e2d09d5b0259c90">REG_CAN1_ILS</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000458UL)</td></tr>
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<tr class="memdesc:a34983ab7904733fe8e2d09d5b0259c90"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Interrupt Line Select <br /></td></tr>
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<tr class="separator:a34983ab7904733fe8e2d09d5b0259c90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad9fe025c66cf37b817dae5376cf4dfc9"><td class="memItemLeft" align="right" valign="top"><a id="ad9fe025c66cf37b817dae5376cf4dfc9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ad9fe025c66cf37b817dae5376cf4dfc9">REG_CAN1_ILE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200045CUL)</td></tr>
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<tr class="memdesc:ad9fe025c66cf37b817dae5376cf4dfc9"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Interrupt Line Enable <br /></td></tr>
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<tr class="separator:ad9fe025c66cf37b817dae5376cf4dfc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d7a34ff4a872a2684ba5ce7d2b297ac"><td class="memItemLeft" align="right" valign="top"><a id="a0d7a34ff4a872a2684ba5ce7d2b297ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a0d7a34ff4a872a2684ba5ce7d2b297ac">REG_CAN1_GFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000480UL)</td></tr>
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<tr class="memdesc:a0d7a34ff4a872a2684ba5ce7d2b297ac"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Global Filter Configuration <br /></td></tr>
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<tr class="separator:a0d7a34ff4a872a2684ba5ce7d2b297ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01e287dd78a8add38c298c579a89d9f1"><td class="memItemLeft" align="right" valign="top"><a id="a01e287dd78a8add38c298c579a89d9f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a01e287dd78a8add38c298c579a89d9f1">REG_CAN1_SIDFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000484UL)</td></tr>
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<tr class="memdesc:a01e287dd78a8add38c298c579a89d9f1"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Standard ID Filter Configuration <br /></td></tr>
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<tr class="separator:a01e287dd78a8add38c298c579a89d9f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a476a694551a7934c348f5ec6bddcc427"><td class="memItemLeft" align="right" valign="top"><a id="a476a694551a7934c348f5ec6bddcc427"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a476a694551a7934c348f5ec6bddcc427">REG_CAN1_XIDFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000488UL)</td></tr>
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<tr class="memdesc:a476a694551a7934c348f5ec6bddcc427"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Extended ID Filter Configuration <br /></td></tr>
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<tr class="separator:a476a694551a7934c348f5ec6bddcc427"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a790adffed271c32377330e14544e9e33"><td class="memItemLeft" align="right" valign="top"><a id="a790adffed271c32377330e14544e9e33"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a790adffed271c32377330e14544e9e33">REG_CAN1_XIDAM</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000490UL)</td></tr>
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<tr class="memdesc:a790adffed271c32377330e14544e9e33"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Extended ID AND Mask <br /></td></tr>
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<tr class="separator:a790adffed271c32377330e14544e9e33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6369b6cdfae8e0ee574e38ecc3e785d7"><td class="memItemLeft" align="right" valign="top"><a id="a6369b6cdfae8e0ee574e38ecc3e785d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a6369b6cdfae8e0ee574e38ecc3e785d7">REG_CAN1_HPMS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000494UL)</td></tr>
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<tr class="memdesc:a6369b6cdfae8e0ee574e38ecc3e785d7"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) High Priority Message Status <br /></td></tr>
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<tr class="separator:a6369b6cdfae8e0ee574e38ecc3e785d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90895aa051339198129f754b6dcc79f0"><td class="memItemLeft" align="right" valign="top"><a id="a90895aa051339198129f754b6dcc79f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a90895aa051339198129f754b6dcc79f0">REG_CAN1_NDAT1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000498UL)</td></tr>
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<tr class="memdesc:a90895aa051339198129f754b6dcc79f0"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) New Data 1 <br /></td></tr>
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<tr class="separator:a90895aa051339198129f754b6dcc79f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aefc9660202b318fb52a2907142ba5822"><td class="memItemLeft" align="right" valign="top"><a id="aefc9660202b318fb52a2907142ba5822"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#aefc9660202b318fb52a2907142ba5822">REG_CAN1_NDAT2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200049CUL)</td></tr>
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<tr class="memdesc:aefc9660202b318fb52a2907142ba5822"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) New Data 2 <br /></td></tr>
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<tr class="separator:aefc9660202b318fb52a2907142ba5822"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acda403a045674f6fb09c1407dbc886e6"><td class="memItemLeft" align="right" valign="top"><a id="acda403a045674f6fb09c1407dbc886e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#acda403a045674f6fb09c1407dbc886e6">REG_CAN1_RXF0C</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004A0UL)</td></tr>
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<tr class="memdesc:acda403a045674f6fb09c1407dbc886e6"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx FIFO 0 Configuration <br /></td></tr>
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<tr class="separator:acda403a045674f6fb09c1407dbc886e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0e9e0550498e2a871aec0456cc4660b"><td class="memItemLeft" align="right" valign="top"><a id="ab0e9e0550498e2a871aec0456cc4660b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ab0e9e0550498e2a871aec0456cc4660b">REG_CAN1_RXF0S</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420004A4UL)</td></tr>
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<tr class="memdesc:ab0e9e0550498e2a871aec0456cc4660b"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx FIFO 0 Status <br /></td></tr>
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<tr class="separator:ab0e9e0550498e2a871aec0456cc4660b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41c962c900a460d6d0d35673c394ffff"><td class="memItemLeft" align="right" valign="top"><a id="a41c962c900a460d6d0d35673c394ffff"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a41c962c900a460d6d0d35673c394ffff">REG_CAN1_RXF0A</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004A8UL)</td></tr>
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<tr class="memdesc:a41c962c900a460d6d0d35673c394ffff"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx FIFO 0 Acknowledge <br /></td></tr>
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<tr class="separator:a41c962c900a460d6d0d35673c394ffff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41a571045833355aaa13e174c1fffad8"><td class="memItemLeft" align="right" valign="top"><a id="a41a571045833355aaa13e174c1fffad8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a41a571045833355aaa13e174c1fffad8">REG_CAN1_RXBC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004ACUL)</td></tr>
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<tr class="memdesc:a41a571045833355aaa13e174c1fffad8"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx Buffer Configuration <br /></td></tr>
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<tr class="separator:a41a571045833355aaa13e174c1fffad8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a37e41c6c5954dabfa9e8ff1b19307a86"><td class="memItemLeft" align="right" valign="top"><a id="a37e41c6c5954dabfa9e8ff1b19307a86"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a37e41c6c5954dabfa9e8ff1b19307a86">REG_CAN1_RXF1C</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004B0UL)</td></tr>
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<tr class="memdesc:a37e41c6c5954dabfa9e8ff1b19307a86"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx FIFO 1 Configuration <br /></td></tr>
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<tr class="separator:a37e41c6c5954dabfa9e8ff1b19307a86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af5d09f06c9c8c12b8a8b8db3c9554cff"><td class="memItemLeft" align="right" valign="top"><a id="af5d09f06c9c8c12b8a8b8db3c9554cff"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#af5d09f06c9c8c12b8a8b8db3c9554cff">REG_CAN1_RXF1S</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420004B4UL)</td></tr>
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<tr class="memdesc:af5d09f06c9c8c12b8a8b8db3c9554cff"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx FIFO 1 Status <br /></td></tr>
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<tr class="separator:af5d09f06c9c8c12b8a8b8db3c9554cff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30424e3f79fe3084a8a8b2ca6fd0f993"><td class="memItemLeft" align="right" valign="top"><a id="a30424e3f79fe3084a8a8b2ca6fd0f993"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a30424e3f79fe3084a8a8b2ca6fd0f993">REG_CAN1_RXF1A</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004B8UL)</td></tr>
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<tr class="memdesc:a30424e3f79fe3084a8a8b2ca6fd0f993"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx FIFO 1 Acknowledge <br /></td></tr>
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<tr class="separator:a30424e3f79fe3084a8a8b2ca6fd0f993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afd6c12c59967b60b7ab3d3cb20ecc81f"><td class="memItemLeft" align="right" valign="top"><a id="afd6c12c59967b60b7ab3d3cb20ecc81f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#afd6c12c59967b60b7ab3d3cb20ecc81f">REG_CAN1_RXESC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004BCUL)</td></tr>
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<tr class="memdesc:afd6c12c59967b60b7ab3d3cb20ecc81f"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Rx Buffer / FIFO Element Size Configuration <br /></td></tr>
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<tr class="separator:afd6c12c59967b60b7ab3d3cb20ecc81f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab791821f96c43a4e65105f8279d201eb"><td class="memItemLeft" align="right" valign="top"><a id="ab791821f96c43a4e65105f8279d201eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ab791821f96c43a4e65105f8279d201eb">REG_CAN1_TXBC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004C0UL)</td></tr>
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<tr class="memdesc:ab791821f96c43a4e65105f8279d201eb"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Configuration <br /></td></tr>
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<tr class="separator:ab791821f96c43a4e65105f8279d201eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a292fbf2fe86d962c9330a9498de6110f"><td class="memItemLeft" align="right" valign="top"><a id="a292fbf2fe86d962c9330a9498de6110f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a292fbf2fe86d962c9330a9498de6110f">REG_CAN1_TXFQS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420004C4UL)</td></tr>
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<tr class="memdesc:a292fbf2fe86d962c9330a9498de6110f"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx FIFO / Queue Status <br /></td></tr>
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<tr class="separator:a292fbf2fe86d962c9330a9498de6110f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae6f535f610581cf84eff90443c96bacf"><td class="memItemLeft" align="right" valign="top"><a id="ae6f535f610581cf84eff90443c96bacf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ae6f535f610581cf84eff90443c96bacf">REG_CAN1_TXESC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004C8UL)</td></tr>
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<tr class="memdesc:ae6f535f610581cf84eff90443c96bacf"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Element Size Configuration <br /></td></tr>
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<tr class="separator:ae6f535f610581cf84eff90443c96bacf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a80f61743d27d067724dad94e7b2df9a5"><td class="memItemLeft" align="right" valign="top"><a id="a80f61743d27d067724dad94e7b2df9a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a80f61743d27d067724dad94e7b2df9a5">REG_CAN1_TXBRP</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420004CCUL)</td></tr>
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<tr class="memdesc:a80f61743d27d067724dad94e7b2df9a5"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Request Pending <br /></td></tr>
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<tr class="separator:a80f61743d27d067724dad94e7b2df9a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0219b4b0027a5a01969abd60c93fb322"><td class="memItemLeft" align="right" valign="top"><a id="a0219b4b0027a5a01969abd60c93fb322"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a0219b4b0027a5a01969abd60c93fb322">REG_CAN1_TXBAR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004D0UL)</td></tr>
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<tr class="memdesc:a0219b4b0027a5a01969abd60c93fb322"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Add Request <br /></td></tr>
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<tr class="separator:a0219b4b0027a5a01969abd60c93fb322"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8ff5e7aeb1d9b15a0bcca054cf152c89"><td class="memItemLeft" align="right" valign="top"><a id="a8ff5e7aeb1d9b15a0bcca054cf152c89"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a8ff5e7aeb1d9b15a0bcca054cf152c89">REG_CAN1_TXBCR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004D4UL)</td></tr>
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<tr class="memdesc:a8ff5e7aeb1d9b15a0bcca054cf152c89"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Cancellation Request <br /></td></tr>
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<tr class="separator:a8ff5e7aeb1d9b15a0bcca054cf152c89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab2ccd3ca7df88be7034ad2f7da497f1f"><td class="memItemLeft" align="right" valign="top"><a id="ab2ccd3ca7df88be7034ad2f7da497f1f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ab2ccd3ca7df88be7034ad2f7da497f1f">REG_CAN1_TXBTO</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420004D8UL)</td></tr>
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<tr class="memdesc:ab2ccd3ca7df88be7034ad2f7da497f1f"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Transmission Occurred <br /></td></tr>
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<tr class="separator:ab2ccd3ca7df88be7034ad2f7da497f1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa2237b89e8c6ba8d92d5daae0d0cc7ba"><td class="memItemLeft" align="right" valign="top"><a id="aa2237b89e8c6ba8d92d5daae0d0cc7ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#aa2237b89e8c6ba8d92d5daae0d0cc7ba">REG_CAN1_TXBCF</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420004DCUL)</td></tr>
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<tr class="memdesc:aa2237b89e8c6ba8d92d5daae0d0cc7ba"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Cancellation Finished <br /></td></tr>
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<tr class="separator:aa2237b89e8c6ba8d92d5daae0d0cc7ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a53fb66a9bdf3de41bdd78f256896dd7f"><td class="memItemLeft" align="right" valign="top"><a id="a53fb66a9bdf3de41bdd78f256896dd7f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a53fb66a9bdf3de41bdd78f256896dd7f">REG_CAN1_TXBTIE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004E0UL)</td></tr>
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<tr class="memdesc:a53fb66a9bdf3de41bdd78f256896dd7f"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Transmission Interrupt Enable <br /></td></tr>
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<tr class="separator:a53fb66a9bdf3de41bdd78f256896dd7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1cbc9ed54637e8494420e7e40c4a2e4"><td class="memItemLeft" align="right" valign="top"><a id="aa1cbc9ed54637e8494420e7e40c4a2e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#aa1cbc9ed54637e8494420e7e40c4a2e4">REG_CAN1_TXBCIE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004E4UL)</td></tr>
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<tr class="memdesc:aa1cbc9ed54637e8494420e7e40c4a2e4"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Buffer Cancellation Finished Interrupt Enable <br /></td></tr>
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<tr class="separator:aa1cbc9ed54637e8494420e7e40c4a2e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad61247c3ad6da3063ef9a8310ce0753"><td class="memItemLeft" align="right" valign="top"><a id="aad61247c3ad6da3063ef9a8310ce0753"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#aad61247c3ad6da3063ef9a8310ce0753">REG_CAN1_TXEFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004F0UL)</td></tr>
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<tr class="memdesc:aad61247c3ad6da3063ef9a8310ce0753"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Event FIFO Configuration <br /></td></tr>
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<tr class="separator:aad61247c3ad6da3063ef9a8310ce0753"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad9db6f7f90147931fbe228ddb4942371"><td class="memItemLeft" align="right" valign="top"><a id="ad9db6f7f90147931fbe228ddb4942371"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#ad9db6f7f90147931fbe228ddb4942371">REG_CAN1_TXEFS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420004F4UL)</td></tr>
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<tr class="memdesc:ad9db6f7f90147931fbe228ddb4942371"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Event FIFO Status <br /></td></tr>
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<tr class="separator:ad9db6f7f90147931fbe228ddb4942371"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a014f9b55f4c435ef0878513f5d1bbef1"><td class="memItemLeft" align="right" valign="top"><a id="a014f9b55f4c435ef0878513f5d1bbef1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can1_8h.html#a014f9b55f4c435ef0878513f5d1bbef1">REG_CAN1_TXEFA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420004F8UL)</td></tr>
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<tr class="memdesc:a014f9b55f4c435ef0878513f5d1bbef1"><td class="mdescLeft"> </td><td class="mdescRight">(CAN1) Tx Event FIFO Acknowledge <br /></td></tr>
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<tr class="separator:a014f9b55f4c435ef0878513f5d1bbef1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af22a9dc7a21f551217f97be80077a044"><td class="memItemLeft" align="right" valign="top"><a id="af22a9dc7a21f551217f97be80077a044"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN1_CLK_AHB_ID</b>   18</td></tr>
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<tr class="separator:af22a9dc7a21f551217f97be80077a044"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad832f94b93bb04dcaba2f00eeb102fb5"><td class="memItemLeft" align="right" valign="top"><a id="ad832f94b93bb04dcaba2f00eeb102fb5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN1_DMAC_ID_DEBUG</b>   21</td></tr>
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<tr class="separator:ad832f94b93bb04dcaba2f00eeb102fb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af2b96c319beefeb0ec92e749226f56cd"><td class="memItemLeft" align="right" valign="top"><a id="af2b96c319beefeb0ec92e749226f56cd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN1_GCLK_ID</b>   28</td></tr>
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<tr class="separator:af2b96c319beefeb0ec92e749226f56cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac7ca7776d8f19bed028d3c7732021ea8"><td class="memItemLeft" align="right" valign="top"><a id="ac7ca7776d8f19bed028d3c7732021ea8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN1_MSG_RAM_ADDR</b>   0x20000000</td></tr>
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<tr class="separator:ac7ca7776d8f19bed028d3c7732021ea8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81db872aebe7a63f68cfa46aea4f7016"><td class="memItemLeft" align="right" valign="top"><a id="a81db872aebe7a63f68cfa46aea4f7016"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN1_QOS_RESET_VAL</b>   1</td></tr>
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<tr class="separator:a81db872aebe7a63f68cfa46aea4f7016"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for CAN1. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="can1_8h_source.html">can1.h</a>.</p>
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