doc/html/component_2supc_8h_source.html

#ifndef _SAME54_SUPC_COMPONENT_

#define _SAME54_SUPC_COMPONENT_


/* ========================================================================== */

/* ========================================================================== */


#define SUPC_U2407

#define REV_SUPC                    0x110


/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BOD33RDY:1;

    uint32_t BOD33DET:1;

    uint32_t B33SRDY:1;

    uint32_t :5;

    uint32_t VREGRDY:1;

    uint32_t :1;

    uint32_t VCORERDY:1;

    uint32_t :21;

  } bit;

  uint32_t reg;

} SUPC_INTENCLR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_INTENCLR_OFFSET        0x00

#define SUPC_INTENCLR_RESETVALUE    _U_(0x00000000)

#define SUPC_INTENCLR_BOD33RDY_Pos  0

#define SUPC_INTENCLR_BOD33RDY      (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos)

#define SUPC_INTENCLR_BOD33DET_Pos  1

#define SUPC_INTENCLR_BOD33DET      (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)

#define SUPC_INTENCLR_B33SRDY_Pos   2

#define SUPC_INTENCLR_B33SRDY       (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)

#define SUPC_INTENCLR_VREGRDY_Pos   8

#define SUPC_INTENCLR_VREGRDY       (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)

#define SUPC_INTENCLR_VCORERDY_Pos  10

#define SUPC_INTENCLR_VCORERDY      (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)

#define SUPC_INTENCLR_MASK          _U_(0x00000507)

/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BOD33RDY:1;

    uint32_t BOD33DET:1;

    uint32_t B33SRDY:1;

    uint32_t :5;

    uint32_t VREGRDY:1;

    uint32_t :1;

    uint32_t VCORERDY:1;

    uint32_t :21;

  } bit;

  uint32_t reg;

} SUPC_INTENSET_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_INTENSET_OFFSET        0x04

#define SUPC_INTENSET_RESETVALUE    _U_(0x00000000)

#define SUPC_INTENSET_BOD33RDY_Pos  0

#define SUPC_INTENSET_BOD33RDY      (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos)

#define SUPC_INTENSET_BOD33DET_Pos  1

#define SUPC_INTENSET_BOD33DET      (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)

#define SUPC_INTENSET_B33SRDY_Pos   2

#define SUPC_INTENSET_B33SRDY       (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)

#define SUPC_INTENSET_VREGRDY_Pos   8

#define SUPC_INTENSET_VREGRDY       (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)

#define SUPC_INTENSET_VCORERDY_Pos  10

#define SUPC_INTENSET_VCORERDY      (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)

#define SUPC_INTENSET_MASK          _U_(0x00000507)

/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union { // __I to avoid read-modify-write on write-to-clear register

  struct {

    __I uint32_t BOD33RDY:1;

    __I uint32_t BOD33DET:1;

    __I uint32_t B33SRDY:1;

    __I uint32_t :5;

    __I uint32_t VREGRDY:1;

    __I uint32_t :1;

    __I uint32_t VCORERDY:1;

    __I uint32_t :21;

  } bit;

  uint32_t reg;

} SUPC_INTFLAG_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_INTFLAG_OFFSET         0x08

#define SUPC_INTFLAG_RESETVALUE     _U_(0x00000000)

#define SUPC_INTFLAG_BOD33RDY_Pos   0

#define SUPC_INTFLAG_BOD33RDY       (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos)

#define SUPC_INTFLAG_BOD33DET_Pos   1

#define SUPC_INTFLAG_BOD33DET       (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)

#define SUPC_INTFLAG_B33SRDY_Pos    2

#define SUPC_INTFLAG_B33SRDY        (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)

#define SUPC_INTFLAG_VREGRDY_Pos    8

#define SUPC_INTFLAG_VREGRDY        (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)

#define SUPC_INTFLAG_VCORERDY_Pos   10

#define SUPC_INTFLAG_VCORERDY       (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)

#define SUPC_INTFLAG_MASK           _U_(0x00000507)

/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/  32) Power and Clocks Status -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BOD33RDY:1;

    uint32_t BOD33DET:1;

    uint32_t B33SRDY:1;

    uint32_t :5;

    uint32_t VREGRDY:1;

    uint32_t :1;

    uint32_t VCORERDY:1;

    uint32_t :21;

  } bit;

  uint32_t reg;

} SUPC_STATUS_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_STATUS_OFFSET          0x0C

#define SUPC_STATUS_RESETVALUE      _U_(0x00000000)

#define SUPC_STATUS_BOD33RDY_Pos    0

#define SUPC_STATUS_BOD33RDY        (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos)

#define SUPC_STATUS_BOD33DET_Pos    1

#define SUPC_STATUS_BOD33DET        (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)

#define SUPC_STATUS_B33SRDY_Pos     2

#define SUPC_STATUS_B33SRDY         (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)

#define SUPC_STATUS_VREGRDY_Pos     8

#define SUPC_STATUS_VREGRDY         (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)

#define SUPC_STATUS_VCORERDY_Pos    10

#define SUPC_STATUS_VCORERDY        (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)

#define SUPC_STATUS_MASK            _U_(0x00000507)

/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t :1;

    uint32_t ENABLE:1;

    uint32_t ACTION:2;

    uint32_t STDBYCFG:1;

    uint32_t RUNSTDBY:1;

    uint32_t RUNHIB:1;

    uint32_t RUNBKUP:1;

    uint32_t HYST:4;

    uint32_t PSEL:3;

    uint32_t :1;

    uint32_t LEVEL:8;

    uint32_t VBATLEVEL:8;

  } bit;

  uint32_t reg;

} SUPC_BOD33_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_BOD33_OFFSET           0x10

#define SUPC_BOD33_RESETVALUE       _U_(0x00000000)

#define SUPC_BOD33_ENABLE_Pos       1

#define SUPC_BOD33_ENABLE           (_U_(0x1) << SUPC_BOD33_ENABLE_Pos)

#define SUPC_BOD33_ACTION_Pos       2

#define SUPC_BOD33_ACTION_Msk       (_U_(0x3) << SUPC_BOD33_ACTION_Pos)

#define SUPC_BOD33_ACTION(value)    (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))

#define   SUPC_BOD33_ACTION_NONE_Val      _U_(0x0)

#define   SUPC_BOD33_ACTION_RESET_Val     _U_(0x1)

#define   SUPC_BOD33_ACTION_INT_Val       _U_(0x2)

#define   SUPC_BOD33_ACTION_BKUP_Val      _U_(0x3)

#define SUPC_BOD33_ACTION_NONE      (SUPC_BOD33_ACTION_NONE_Val    << SUPC_BOD33_ACTION_Pos)

#define SUPC_BOD33_ACTION_RESET     (SUPC_BOD33_ACTION_RESET_Val   << SUPC_BOD33_ACTION_Pos)

#define SUPC_BOD33_ACTION_INT       (SUPC_BOD33_ACTION_INT_Val     << SUPC_BOD33_ACTION_Pos)

#define SUPC_BOD33_ACTION_BKUP      (SUPC_BOD33_ACTION_BKUP_Val    << SUPC_BOD33_ACTION_Pos)

#define SUPC_BOD33_STDBYCFG_Pos     4

#define SUPC_BOD33_STDBYCFG         (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos)

#define SUPC_BOD33_RUNSTDBY_Pos     5

#define SUPC_BOD33_RUNSTDBY         (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos)

#define SUPC_BOD33_RUNHIB_Pos       6

#define SUPC_BOD33_RUNHIB           (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos)

#define SUPC_BOD33_RUNBKUP_Pos      7

#define SUPC_BOD33_RUNBKUP          (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos)

#define SUPC_BOD33_HYST_Pos         8

#define SUPC_BOD33_HYST_Msk         (_U_(0xF) << SUPC_BOD33_HYST_Pos)

#define SUPC_BOD33_HYST(value)      (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))

#define SUPC_BOD33_PSEL_Pos         12

#define SUPC_BOD33_PSEL_Msk         (_U_(0x7) << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL(value)      (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))

#define   SUPC_BOD33_PSEL_NODIV_Val       _U_(0x0)

#define   SUPC_BOD33_PSEL_DIV4_Val        _U_(0x1)

#define   SUPC_BOD33_PSEL_DIV8_Val        _U_(0x2)

#define   SUPC_BOD33_PSEL_DIV16_Val       _U_(0x3)

#define   SUPC_BOD33_PSEL_DIV32_Val       _U_(0x4)

#define   SUPC_BOD33_PSEL_DIV64_Val       _U_(0x5)

#define   SUPC_BOD33_PSEL_DIV128_Val      _U_(0x6)

#define   SUPC_BOD33_PSEL_DIV256_Val      _U_(0x7)

#define SUPC_BOD33_PSEL_NODIV       (SUPC_BOD33_PSEL_NODIV_Val     << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL_DIV4        (SUPC_BOD33_PSEL_DIV4_Val      << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL_DIV8        (SUPC_BOD33_PSEL_DIV8_Val      << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL_DIV16       (SUPC_BOD33_PSEL_DIV16_Val     << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL_DIV32       (SUPC_BOD33_PSEL_DIV32_Val     << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL_DIV64       (SUPC_BOD33_PSEL_DIV64_Val     << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL_DIV128      (SUPC_BOD33_PSEL_DIV128_Val    << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_PSEL_DIV256      (SUPC_BOD33_PSEL_DIV256_Val    << SUPC_BOD33_PSEL_Pos)

#define SUPC_BOD33_LEVEL_Pos        16

#define SUPC_BOD33_LEVEL_Msk        (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos)

#define SUPC_BOD33_LEVEL(value)     (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))

#define SUPC_BOD33_VBATLEVEL_Pos    24

#define SUPC_BOD33_VBATLEVEL_Msk    (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos)

#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))

#define SUPC_BOD33_MASK             _U_(0xFFFF7FFE)

/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t :1;

    uint32_t ENABLE:1;

    uint32_t SEL:1;

    uint32_t :4;

    uint32_t RUNBKUP:1;

    uint32_t :8;

    uint32_t VSEN:1;

    uint32_t :7;

    uint32_t VSPER:3;

    uint32_t :5;

  } bit;

  uint32_t reg;

} SUPC_VREG_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_VREG_OFFSET            0x18

#define SUPC_VREG_RESETVALUE        _U_(0x00000002)

#define SUPC_VREG_ENABLE_Pos        1

#define SUPC_VREG_ENABLE            (_U_(0x1) << SUPC_VREG_ENABLE_Pos)

#define SUPC_VREG_SEL_Pos           2

#define SUPC_VREG_SEL               (_U_(0x1) << SUPC_VREG_SEL_Pos)

#define   SUPC_VREG_SEL_LDO_Val           _U_(0x0)

#define   SUPC_VREG_SEL_BUCK_Val          _U_(0x1)

#define SUPC_VREG_SEL_LDO           (SUPC_VREG_SEL_LDO_Val         << SUPC_VREG_SEL_Pos)

#define SUPC_VREG_SEL_BUCK          (SUPC_VREG_SEL_BUCK_Val        << SUPC_VREG_SEL_Pos)

#define SUPC_VREG_RUNBKUP_Pos       7

#define SUPC_VREG_RUNBKUP           (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos)

#define SUPC_VREG_VSEN_Pos          16

#define SUPC_VREG_VSEN              (_U_(0x1) << SUPC_VREG_VSEN_Pos)

#define SUPC_VREG_VSPER_Pos         24

#define SUPC_VREG_VSPER_Msk         (_U_(0x7) << SUPC_VREG_VSPER_Pos)

#define SUPC_VREG_VSPER(value)      (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))

#define SUPC_VREG_MASK              _U_(0x07010086)

/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t :1;

    uint32_t TSEN:1;

    uint32_t VREFOE:1;

    uint32_t TSSEL:1;

    uint32_t :2;

    uint32_t RUNSTDBY:1;

    uint32_t ONDEMAND:1;

    uint32_t :8;

    uint32_t SEL:4;

    uint32_t :12;

  } bit;

  uint32_t reg;

} SUPC_VREF_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_VREF_OFFSET            0x1C

#define SUPC_VREF_RESETVALUE        _U_(0x00000000)

#define SUPC_VREF_TSEN_Pos          1

#define SUPC_VREF_TSEN              (_U_(0x1) << SUPC_VREF_TSEN_Pos)

#define SUPC_VREF_VREFOE_Pos        2

#define SUPC_VREF_VREFOE            (_U_(0x1) << SUPC_VREF_VREFOE_Pos)

#define SUPC_VREF_TSSEL_Pos         3

#define SUPC_VREF_TSSEL             (_U_(0x1) << SUPC_VREF_TSSEL_Pos)

#define SUPC_VREF_RUNSTDBY_Pos      6

#define SUPC_VREF_RUNSTDBY          (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)

#define SUPC_VREF_ONDEMAND_Pos      7

#define SUPC_VREF_ONDEMAND          (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)

#define SUPC_VREF_SEL_Pos           16

#define SUPC_VREF_SEL_Msk           (_U_(0xF) << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL(value)        (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))

#define   SUPC_VREF_SEL_1V0_Val           _U_(0x0)

#define   SUPC_VREF_SEL_1V1_Val           _U_(0x1)

#define   SUPC_VREF_SEL_1V2_Val           _U_(0x2)

#define   SUPC_VREF_SEL_1V25_Val          _U_(0x3)

#define   SUPC_VREF_SEL_2V0_Val           _U_(0x4)

#define   SUPC_VREF_SEL_2V2_Val           _U_(0x5)

#define   SUPC_VREF_SEL_2V4_Val           _U_(0x6)

#define   SUPC_VREF_SEL_2V5_Val           _U_(0x7)

#define SUPC_VREF_SEL_1V0           (SUPC_VREF_SEL_1V0_Val         << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL_1V1           (SUPC_VREF_SEL_1V1_Val         << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL_1V2           (SUPC_VREF_SEL_1V2_Val         << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL_1V25          (SUPC_VREF_SEL_1V25_Val        << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL_2V0           (SUPC_VREF_SEL_2V0_Val         << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL_2V2           (SUPC_VREF_SEL_2V2_Val         << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL_2V4           (SUPC_VREF_SEL_2V4_Val         << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_SEL_2V5           (SUPC_VREF_SEL_2V5_Val         << SUPC_VREF_SEL_Pos)

#define SUPC_VREF_MASK              _U_(0x000F00CE)

/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t CONF:1;

    uint32_t :1;

    uint32_t WAKEEN:1;

    uint32_t :29;

  } bit;

  uint32_t reg;

} SUPC_BBPS_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_BBPS_OFFSET            0x20

#define SUPC_BBPS_RESETVALUE        _U_(0x00000000)

#define SUPC_BBPS_CONF_Pos          0

#define SUPC_BBPS_CONF              (_U_(0x1) << SUPC_BBPS_CONF_Pos)

#define   SUPC_BBPS_CONF_BOD33_Val        _U_(0x0)

#define   SUPC_BBPS_CONF_FORCED_Val       _U_(0x1)

#define SUPC_BBPS_CONF_BOD33        (SUPC_BBPS_CONF_BOD33_Val      << SUPC_BBPS_CONF_Pos)

#define SUPC_BBPS_CONF_FORCED       (SUPC_BBPS_CONF_FORCED_Val     << SUPC_BBPS_CONF_Pos)

#define SUPC_BBPS_WAKEEN_Pos        2

#define SUPC_BBPS_WAKEEN            (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos)

#define SUPC_BBPS_MASK              _U_(0x00000005)

/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t EN:2;

    uint32_t :6;

    uint32_t CLR:2;

    uint32_t :6;

    uint32_t SET:2;

    uint32_t :6;

    uint32_t RTCTGL:2;

    uint32_t :6;

  } bit;

  uint32_t reg;

} SUPC_BKOUT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_BKOUT_OFFSET           0x24

#define SUPC_BKOUT_RESETVALUE       _U_(0x00000000)

#define SUPC_BKOUT_EN_Pos           0

#define SUPC_BKOUT_EN_Msk           (_U_(0x3) << SUPC_BKOUT_EN_Pos)

#define SUPC_BKOUT_EN(value)        (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))

#define SUPC_BKOUT_CLR_Pos          8

#define SUPC_BKOUT_CLR_Msk          (_U_(0x3) << SUPC_BKOUT_CLR_Pos)

#define SUPC_BKOUT_CLR(value)       (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))

#define SUPC_BKOUT_SET_Pos          16

#define SUPC_BKOUT_SET_Msk          (_U_(0x3) << SUPC_BKOUT_SET_Pos)

#define SUPC_BKOUT_SET(value)       (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))

#define SUPC_BKOUT_RTCTGL_Pos       24

#define SUPC_BKOUT_RTCTGL_Msk       (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos)

#define SUPC_BKOUT_RTCTGL(value)    (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))

#define SUPC_BKOUT_MASK             _U_(0x03030303)

/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/  32) Backup Input Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BKIN:8;

    uint32_t :24;

  } bit;

  uint32_t reg;

} SUPC_BKIN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define SUPC_BKIN_OFFSET            0x28

#define SUPC_BKIN_RESETVALUE        _U_(0x00000000)

#define SUPC_BKIN_BKIN_Pos          0

#define SUPC_BKIN_BKIN_Msk          (_U_(0xFF) << SUPC_BKIN_BKIN_Pos)

#define SUPC_BKIN_BKIN(value)       (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))

#define SUPC_BKIN_MASK              _U_(0x000000FF)

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO SUPC_INTENCLR_Type        INTENCLR;

  __IO SUPC_INTENSET_Type        INTENSET;

  __IO SUPC_INTFLAG_Type         INTFLAG;

  __I  SUPC_STATUS_Type          STATUS;

  __IO SUPC_BOD33_Type           BOD33;

       RoReg8                    Reserved1[0x4];

  __IO SUPC_VREG_Type            VREG;

  __IO SUPC_VREF_Type            VREF;

  __IO SUPC_BBPS_Type            BBPS;

  __IO SUPC_BKOUT_Type           BKOUT;

  __I  SUPC_BKIN_Type            BKIN;

} Supc;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#endif /* _SAME54_SUPC_COMPONENT_ */