doc/html/component_2rtc_8h_source.html

#ifndef _SAME54_RTC_COMPONENT_

#define _SAME54_RTC_COMPONENT_


/* ========================================================================== */

/* ========================================================================== */


#define RTC_U2250

#define REV_RTC                     0x210


/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t SWRST:1;

    uint16_t ENABLE:1;

    uint16_t MODE:2;

    uint16_t :3;

    uint16_t MATCHCLR:1;

    uint16_t PRESCALER:4;

    uint16_t :1;

    uint16_t BKTRST:1;

    uint16_t GPTRST:1;

    uint16_t COUNTSYNC:1;

  } bit;

  uint16_t reg;

} RTC_MODE0_CTRLA_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_CTRLA_OFFSET      0x00

#define RTC_MODE0_CTRLA_RESETVALUE  _U_(0x0000)

#define RTC_MODE0_CTRLA_SWRST_Pos   0

#define RTC_MODE0_CTRLA_SWRST       (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)

#define RTC_MODE0_CTRLA_ENABLE_Pos  1

#define RTC_MODE0_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)

#define RTC_MODE0_CTRLA_MODE_Pos    2

#define RTC_MODE0_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)

#define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))

#define   RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0)

#define   RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1)

#define   RTC_MODE0_CTRLA_MODE_CLOCK_Val  _U_(0x2)

#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)

#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)

#define RTC_MODE0_CTRLA_MODE_CLOCK  (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)

#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7

#define RTC_MODE0_CTRLA_MATCHCLR    (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_Pos 8

#define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))

#define   RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA)

#define   RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)

#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define RTC_MODE0_CTRLA_BKTRST_Pos  13

#define RTC_MODE0_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)

#define RTC_MODE0_CTRLA_GPTRST_Pos  14

#define RTC_MODE0_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)

#define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15

#define RTC_MODE0_CTRLA_COUNTSYNC   (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)

#define RTC_MODE0_CTRLA_MASK        _U_(0xEF8F)

/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t SWRST:1;

    uint16_t ENABLE:1;

    uint16_t MODE:2;

    uint16_t :4;

    uint16_t PRESCALER:4;

    uint16_t :1;

    uint16_t BKTRST:1;

    uint16_t GPTRST:1;

    uint16_t COUNTSYNC:1;

  } bit;

  uint16_t reg;

} RTC_MODE1_CTRLA_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_CTRLA_OFFSET      0x00

#define RTC_MODE1_CTRLA_RESETVALUE  _U_(0x0000)

#define RTC_MODE1_CTRLA_SWRST_Pos   0

#define RTC_MODE1_CTRLA_SWRST       (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)

#define RTC_MODE1_CTRLA_ENABLE_Pos  1

#define RTC_MODE1_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)

#define RTC_MODE1_CTRLA_MODE_Pos    2

#define RTC_MODE1_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)

#define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))

#define   RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0)

#define   RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1)

#define   RTC_MODE1_CTRLA_MODE_CLOCK_Val  _U_(0x2)

#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)

#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)

#define RTC_MODE1_CTRLA_MODE_CLOCK  (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_Pos 8

#define RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))

#define   RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA)

#define   RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)

#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define RTC_MODE1_CTRLA_BKTRST_Pos  13

#define RTC_MODE1_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)

#define RTC_MODE1_CTRLA_GPTRST_Pos  14

#define RTC_MODE1_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)

#define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15

#define RTC_MODE1_CTRLA_COUNTSYNC   (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)

#define RTC_MODE1_CTRLA_MASK        _U_(0xEF0F)

/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t SWRST:1;

    uint16_t ENABLE:1;

    uint16_t MODE:2;

    uint16_t :2;

    uint16_t CLKREP:1;

    uint16_t MATCHCLR:1;

    uint16_t PRESCALER:4;

    uint16_t :1;

    uint16_t BKTRST:1;

    uint16_t GPTRST:1;

    uint16_t CLOCKSYNC:1;

  } bit;

  uint16_t reg;

} RTC_MODE2_CTRLA_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_CTRLA_OFFSET      0x00

#define RTC_MODE2_CTRLA_RESETVALUE  _U_(0x0000)

#define RTC_MODE2_CTRLA_SWRST_Pos   0

#define RTC_MODE2_CTRLA_SWRST       (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)

#define RTC_MODE2_CTRLA_ENABLE_Pos  1

#define RTC_MODE2_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)

#define RTC_MODE2_CTRLA_MODE_Pos    2

#define RTC_MODE2_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)

#define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))

#define   RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0)

#define   RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1)

#define   RTC_MODE2_CTRLA_MODE_CLOCK_Val  _U_(0x2)

#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)

#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)

#define RTC_MODE2_CTRLA_MODE_CLOCK  (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)

#define RTC_MODE2_CTRLA_CLKREP_Pos  6

#define RTC_MODE2_CTRLA_CLKREP      (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)

#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7

#define RTC_MODE2_CTRLA_MATCHCLR    (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_Pos 8

#define RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))

#define   RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA)

#define   RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)

#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define RTC_MODE2_CTRLA_BKTRST_Pos  13

#define RTC_MODE2_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)

#define RTC_MODE2_CTRLA_GPTRST_Pos  14

#define RTC_MODE2_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)

#define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15

#define RTC_MODE2_CTRLA_CLOCKSYNC   (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)

#define RTC_MODE2_CTRLA_MASK        _U_(0xEFCF)

/* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 MODE0 Control B -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t GP0EN:1;

    uint16_t GP2EN:1;

    uint16_t :2;

    uint16_t DEBMAJ:1;

    uint16_t DEBASYNC:1;

    uint16_t RTCOUT:1;

    uint16_t DMAEN:1;

    uint16_t DEBF:3;

    uint16_t :1;

    uint16_t ACTF:3;

    uint16_t :1;

  } bit;

  uint16_t reg;

} RTC_MODE0_CTRLB_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_CTRLB_OFFSET      0x02

#define RTC_MODE0_CTRLB_RESETVALUE  _U_(0x0000)

#define RTC_MODE0_CTRLB_GP0EN_Pos   0

#define RTC_MODE0_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)

#define RTC_MODE0_CTRLB_GP2EN_Pos   1

#define RTC_MODE0_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)

#define RTC_MODE0_CTRLB_DEBMAJ_Pos  4

#define RTC_MODE0_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)

#define RTC_MODE0_CTRLB_DEBASYNC_Pos 5

#define RTC_MODE0_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)

#define RTC_MODE0_CTRLB_RTCOUT_Pos  6

#define RTC_MODE0_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)

#define RTC_MODE0_CTRLB_DMAEN_Pos   7

#define RTC_MODE0_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)

#define RTC_MODE0_CTRLB_DEBF_Pos    8

#define RTC_MODE0_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))

#define   RTC_MODE0_CTRLB_DEBF_DIV2_Val   _U_(0x0)

#define   RTC_MODE0_CTRLB_DEBF_DIV4_Val   _U_(0x1)

#define   RTC_MODE0_CTRLB_DEBF_DIV8_Val   _U_(0x2)

#define   RTC_MODE0_CTRLB_DEBF_DIV16_Val  _U_(0x3)

#define   RTC_MODE0_CTRLB_DEBF_DIV32_Val  _U_(0x4)

#define   RTC_MODE0_CTRLB_DEBF_DIV64_Val  _U_(0x5)

#define   RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6)

#define   RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7)

#define RTC_MODE0_CTRLB_DEBF_DIV2   (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF_DIV4   (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF_DIV8   (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF_DIV16  (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF_DIV32  (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF_DIV64  (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define RTC_MODE0_CTRLB_ACTF_Pos    12

#define RTC_MODE0_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))

#define   RTC_MODE0_CTRLB_ACTF_DIV2_Val   _U_(0x0)

#define   RTC_MODE0_CTRLB_ACTF_DIV4_Val   _U_(0x1)

#define   RTC_MODE0_CTRLB_ACTF_DIV8_Val   _U_(0x2)

#define   RTC_MODE0_CTRLB_ACTF_DIV16_Val  _U_(0x3)

#define   RTC_MODE0_CTRLB_ACTF_DIV32_Val  _U_(0x4)

#define   RTC_MODE0_CTRLB_ACTF_DIV64_Val  _U_(0x5)

#define   RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6)

#define   RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7)

#define RTC_MODE0_CTRLB_ACTF_DIV2   (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF_DIV4   (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF_DIV8   (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF_DIV16  (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF_DIV32  (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF_DIV64  (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define RTC_MODE0_CTRLB_MASK        _U_(0x77F3)

/* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 MODE1 Control B -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t GP0EN:1;

    uint16_t GP2EN:1;

    uint16_t :2;

    uint16_t DEBMAJ:1;

    uint16_t DEBASYNC:1;

    uint16_t RTCOUT:1;

    uint16_t DMAEN:1;

    uint16_t DEBF:3;

    uint16_t :1;

    uint16_t ACTF:3;

    uint16_t :1;

  } bit;

  uint16_t reg;

} RTC_MODE1_CTRLB_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_CTRLB_OFFSET      0x02

#define RTC_MODE1_CTRLB_RESETVALUE  _U_(0x0000)

#define RTC_MODE1_CTRLB_GP0EN_Pos   0

#define RTC_MODE1_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)

#define RTC_MODE1_CTRLB_GP2EN_Pos   1

#define RTC_MODE1_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)

#define RTC_MODE1_CTRLB_DEBMAJ_Pos  4

#define RTC_MODE1_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)

#define RTC_MODE1_CTRLB_DEBASYNC_Pos 5

#define RTC_MODE1_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)

#define RTC_MODE1_CTRLB_RTCOUT_Pos  6

#define RTC_MODE1_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)

#define RTC_MODE1_CTRLB_DMAEN_Pos   7

#define RTC_MODE1_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)

#define RTC_MODE1_CTRLB_DEBF_Pos    8

#define RTC_MODE1_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))

#define   RTC_MODE1_CTRLB_DEBF_DIV2_Val   _U_(0x0)

#define   RTC_MODE1_CTRLB_DEBF_DIV4_Val   _U_(0x1)

#define   RTC_MODE1_CTRLB_DEBF_DIV8_Val   _U_(0x2)

#define   RTC_MODE1_CTRLB_DEBF_DIV16_Val  _U_(0x3)

#define   RTC_MODE1_CTRLB_DEBF_DIV32_Val  _U_(0x4)

#define   RTC_MODE1_CTRLB_DEBF_DIV64_Val  _U_(0x5)

#define   RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6)

#define   RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7)

#define RTC_MODE1_CTRLB_DEBF_DIV2   (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF_DIV4   (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF_DIV8   (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF_DIV16  (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF_DIV32  (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF_DIV64  (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define RTC_MODE1_CTRLB_ACTF_Pos    12

#define RTC_MODE1_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))

#define   RTC_MODE1_CTRLB_ACTF_DIV2_Val   _U_(0x0)

#define   RTC_MODE1_CTRLB_ACTF_DIV4_Val   _U_(0x1)

#define   RTC_MODE1_CTRLB_ACTF_DIV8_Val   _U_(0x2)

#define   RTC_MODE1_CTRLB_ACTF_DIV16_Val  _U_(0x3)

#define   RTC_MODE1_CTRLB_ACTF_DIV32_Val  _U_(0x4)

#define   RTC_MODE1_CTRLB_ACTF_DIV64_Val  _U_(0x5)

#define   RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6)

#define   RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7)

#define RTC_MODE1_CTRLB_ACTF_DIV2   (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF_DIV4   (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF_DIV8   (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF_DIV16  (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF_DIV32  (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF_DIV64  (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define RTC_MODE1_CTRLB_MASK        _U_(0x77F3)

/* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 MODE2 Control B -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t GP0EN:1;

    uint16_t GP2EN:1;

    uint16_t :2;

    uint16_t DEBMAJ:1;

    uint16_t DEBASYNC:1;

    uint16_t RTCOUT:1;

    uint16_t DMAEN:1;

    uint16_t DEBF:3;

    uint16_t :1;

    uint16_t ACTF:3;

    uint16_t :1;

  } bit;

  uint16_t reg;

} RTC_MODE2_CTRLB_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_CTRLB_OFFSET      0x02

#define RTC_MODE2_CTRLB_RESETVALUE  _U_(0x0000)

#define RTC_MODE2_CTRLB_GP0EN_Pos   0

#define RTC_MODE2_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)

#define RTC_MODE2_CTRLB_GP2EN_Pos   1

#define RTC_MODE2_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)

#define RTC_MODE2_CTRLB_DEBMAJ_Pos  4

#define RTC_MODE2_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)

#define RTC_MODE2_CTRLB_DEBASYNC_Pos 5

#define RTC_MODE2_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)

#define RTC_MODE2_CTRLB_RTCOUT_Pos  6

#define RTC_MODE2_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)

#define RTC_MODE2_CTRLB_DMAEN_Pos   7

#define RTC_MODE2_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)

#define RTC_MODE2_CTRLB_DEBF_Pos    8

#define RTC_MODE2_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))

#define   RTC_MODE2_CTRLB_DEBF_DIV2_Val   _U_(0x0)

#define   RTC_MODE2_CTRLB_DEBF_DIV4_Val   _U_(0x1)

#define   RTC_MODE2_CTRLB_DEBF_DIV8_Val   _U_(0x2)

#define   RTC_MODE2_CTRLB_DEBF_DIV16_Val  _U_(0x3)

#define   RTC_MODE2_CTRLB_DEBF_DIV32_Val  _U_(0x4)

#define   RTC_MODE2_CTRLB_DEBF_DIV64_Val  _U_(0x5)

#define   RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6)

#define   RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7)

#define RTC_MODE2_CTRLB_DEBF_DIV2   (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF_DIV4   (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF_DIV8   (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF_DIV16  (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF_DIV32  (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF_DIV64  (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define RTC_MODE2_CTRLB_ACTF_Pos    12

#define RTC_MODE2_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))

#define   RTC_MODE2_CTRLB_ACTF_DIV2_Val   _U_(0x0)

#define   RTC_MODE2_CTRLB_ACTF_DIV4_Val   _U_(0x1)

#define   RTC_MODE2_CTRLB_ACTF_DIV8_Val   _U_(0x2)

#define   RTC_MODE2_CTRLB_ACTF_DIV16_Val  _U_(0x3)

#define   RTC_MODE2_CTRLB_ACTF_DIV32_Val  _U_(0x4)

#define   RTC_MODE2_CTRLB_ACTF_DIV64_Val  _U_(0x5)

#define   RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6)

#define   RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7)

#define RTC_MODE2_CTRLB_ACTF_DIV2   (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF_DIV4   (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF_DIV8   (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF_DIV16  (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF_DIV32  (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF_DIV64  (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define RTC_MODE2_CTRLB_MASK        _U_(0x77F3)

/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t PEREO0:1;

    uint32_t PEREO1:1;

    uint32_t PEREO2:1;

    uint32_t PEREO3:1;

    uint32_t PEREO4:1;

    uint32_t PEREO5:1;

    uint32_t PEREO6:1;

    uint32_t PEREO7:1;

    uint32_t CMPEO0:1;

    uint32_t CMPEO1:1;

    uint32_t :4;

    uint32_t TAMPEREO:1;

    uint32_t OVFEO:1;

    uint32_t TAMPEVEI:1;

    uint32_t :15;

  } bit;

  struct {

    uint32_t PEREO:8;

    uint32_t CMPEO:2;

    uint32_t :22;

  } vec;

  uint32_t reg;

} RTC_MODE0_EVCTRL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_EVCTRL_OFFSET     0x04

#define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000)

#define RTC_MODE0_EVCTRL_PEREO0_Pos 0

#define RTC_MODE0_EVCTRL_PEREO0     (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)

#define RTC_MODE0_EVCTRL_PEREO1_Pos 1

#define RTC_MODE0_EVCTRL_PEREO1     (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)

#define RTC_MODE0_EVCTRL_PEREO2_Pos 2

#define RTC_MODE0_EVCTRL_PEREO2     (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)

#define RTC_MODE0_EVCTRL_PEREO3_Pos 3

#define RTC_MODE0_EVCTRL_PEREO3     (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)

#define RTC_MODE0_EVCTRL_PEREO4_Pos 4

#define RTC_MODE0_EVCTRL_PEREO4     (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)

#define RTC_MODE0_EVCTRL_PEREO5_Pos 5

#define RTC_MODE0_EVCTRL_PEREO5     (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)

#define RTC_MODE0_EVCTRL_PEREO6_Pos 6

#define RTC_MODE0_EVCTRL_PEREO6     (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)

#define RTC_MODE0_EVCTRL_PEREO7_Pos 7

#define RTC_MODE0_EVCTRL_PEREO7     (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)

#define RTC_MODE0_EVCTRL_PEREO_Pos  0

#define RTC_MODE0_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)

#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))

#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8

#define RTC_MODE0_EVCTRL_CMPEO0     (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)

#define RTC_MODE0_EVCTRL_CMPEO1_Pos 9

#define RTC_MODE0_EVCTRL_CMPEO1     (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)

#define RTC_MODE0_EVCTRL_CMPEO_Pos  8

#define RTC_MODE0_EVCTRL_CMPEO_Msk  (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)

#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))

#define RTC_MODE0_EVCTRL_TAMPEREO_Pos 14

#define RTC_MODE0_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)

#define RTC_MODE0_EVCTRL_OVFEO_Pos  15

#define RTC_MODE0_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)

#define RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16

#define RTC_MODE0_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)

#define RTC_MODE0_EVCTRL_MASK       _U_(0x0001C3FF)

/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t PEREO0:1;

    uint32_t PEREO1:1;

    uint32_t PEREO2:1;

    uint32_t PEREO3:1;

    uint32_t PEREO4:1;

    uint32_t PEREO5:1;

    uint32_t PEREO6:1;

    uint32_t PEREO7:1;

    uint32_t CMPEO0:1;

    uint32_t CMPEO1:1;

    uint32_t CMPEO2:1;

    uint32_t CMPEO3:1;

    uint32_t :2;

    uint32_t TAMPEREO:1;

    uint32_t OVFEO:1;

    uint32_t TAMPEVEI:1;

    uint32_t :15;

  } bit;

  struct {

    uint32_t PEREO:8;

    uint32_t CMPEO:4;

    uint32_t :20;

  } vec;

  uint32_t reg;

} RTC_MODE1_EVCTRL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_EVCTRL_OFFSET     0x04

#define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000)

#define RTC_MODE1_EVCTRL_PEREO0_Pos 0

#define RTC_MODE1_EVCTRL_PEREO0     (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)

#define RTC_MODE1_EVCTRL_PEREO1_Pos 1

#define RTC_MODE1_EVCTRL_PEREO1     (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)

#define RTC_MODE1_EVCTRL_PEREO2_Pos 2

#define RTC_MODE1_EVCTRL_PEREO2     (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)

#define RTC_MODE1_EVCTRL_PEREO3_Pos 3

#define RTC_MODE1_EVCTRL_PEREO3     (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)

#define RTC_MODE1_EVCTRL_PEREO4_Pos 4

#define RTC_MODE1_EVCTRL_PEREO4     (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)

#define RTC_MODE1_EVCTRL_PEREO5_Pos 5

#define RTC_MODE1_EVCTRL_PEREO5     (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)

#define RTC_MODE1_EVCTRL_PEREO6_Pos 6

#define RTC_MODE1_EVCTRL_PEREO6     (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)

#define RTC_MODE1_EVCTRL_PEREO7_Pos 7

#define RTC_MODE1_EVCTRL_PEREO7     (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)

#define RTC_MODE1_EVCTRL_PEREO_Pos  0

#define RTC_MODE1_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)

#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))

#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8

#define RTC_MODE1_EVCTRL_CMPEO0     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)

#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9

#define RTC_MODE1_EVCTRL_CMPEO1     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)

#define RTC_MODE1_EVCTRL_CMPEO2_Pos 10

#define RTC_MODE1_EVCTRL_CMPEO2     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)

#define RTC_MODE1_EVCTRL_CMPEO3_Pos 11

#define RTC_MODE1_EVCTRL_CMPEO3     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)

#define RTC_MODE1_EVCTRL_CMPEO_Pos  8

#define RTC_MODE1_EVCTRL_CMPEO_Msk  (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)

#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))

#define RTC_MODE1_EVCTRL_TAMPEREO_Pos 14

#define RTC_MODE1_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)

#define RTC_MODE1_EVCTRL_OVFEO_Pos  15

#define RTC_MODE1_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)

#define RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16

#define RTC_MODE1_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)

#define RTC_MODE1_EVCTRL_MASK       _U_(0x0001CFFF)

/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t PEREO0:1;

    uint32_t PEREO1:1;

    uint32_t PEREO2:1;

    uint32_t PEREO3:1;

    uint32_t PEREO4:1;

    uint32_t PEREO5:1;

    uint32_t PEREO6:1;

    uint32_t PEREO7:1;

    uint32_t ALARMEO0:1;

    uint32_t ALARMEO1:1;

    uint32_t :4;

    uint32_t TAMPEREO:1;

    uint32_t OVFEO:1;

    uint32_t TAMPEVEI:1;

    uint32_t :15;

  } bit;

  struct {

    uint32_t PEREO:8;

    uint32_t ALARMEO:2;

    uint32_t :22;

  } vec;

  uint32_t reg;

} RTC_MODE2_EVCTRL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_EVCTRL_OFFSET     0x04

#define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000)

#define RTC_MODE2_EVCTRL_PEREO0_Pos 0

#define RTC_MODE2_EVCTRL_PEREO0     (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)

#define RTC_MODE2_EVCTRL_PEREO1_Pos 1

#define RTC_MODE2_EVCTRL_PEREO1     (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)

#define RTC_MODE2_EVCTRL_PEREO2_Pos 2

#define RTC_MODE2_EVCTRL_PEREO2     (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)

#define RTC_MODE2_EVCTRL_PEREO3_Pos 3

#define RTC_MODE2_EVCTRL_PEREO3     (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)

#define RTC_MODE2_EVCTRL_PEREO4_Pos 4

#define RTC_MODE2_EVCTRL_PEREO4     (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)

#define RTC_MODE2_EVCTRL_PEREO5_Pos 5

#define RTC_MODE2_EVCTRL_PEREO5     (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)

#define RTC_MODE2_EVCTRL_PEREO6_Pos 6

#define RTC_MODE2_EVCTRL_PEREO6     (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)

#define RTC_MODE2_EVCTRL_PEREO7_Pos 7

#define RTC_MODE2_EVCTRL_PEREO7     (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)

#define RTC_MODE2_EVCTRL_PEREO_Pos  0

#define RTC_MODE2_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)

#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))

#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8

#define RTC_MODE2_EVCTRL_ALARMEO0   (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)

#define RTC_MODE2_EVCTRL_ALARMEO1_Pos 9

#define RTC_MODE2_EVCTRL_ALARMEO1   (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)

#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8

#define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)

#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))

#define RTC_MODE2_EVCTRL_TAMPEREO_Pos 14

#define RTC_MODE2_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)

#define RTC_MODE2_EVCTRL_OVFEO_Pos  15

#define RTC_MODE2_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)

#define RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16

#define RTC_MODE2_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)

#define RTC_MODE2_EVCTRL_MASK       _U_(0x0001C3FF)

/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t PER0:1;

    uint16_t PER1:1;

    uint16_t PER2:1;

    uint16_t PER3:1;

    uint16_t PER4:1;

    uint16_t PER5:1;

    uint16_t PER6:1;

    uint16_t PER7:1;

    uint16_t CMP0:1;

    uint16_t CMP1:1;

    uint16_t :4;

    uint16_t TAMPER:1;

    uint16_t OVF:1;

  } bit;

  struct {

    uint16_t PER:8;

    uint16_t CMP:2;

    uint16_t :6;

  } vec;

  uint16_t reg;

} RTC_MODE0_INTENCLR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_INTENCLR_OFFSET   0x08

#define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000)

#define RTC_MODE0_INTENCLR_PER0_Pos 0

#define RTC_MODE0_INTENCLR_PER0     (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)

#define RTC_MODE0_INTENCLR_PER1_Pos 1

#define RTC_MODE0_INTENCLR_PER1     (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)

#define RTC_MODE0_INTENCLR_PER2_Pos 2

#define RTC_MODE0_INTENCLR_PER2     (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)

#define RTC_MODE0_INTENCLR_PER3_Pos 3

#define RTC_MODE0_INTENCLR_PER3     (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)

#define RTC_MODE0_INTENCLR_PER4_Pos 4

#define RTC_MODE0_INTENCLR_PER4     (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)

#define RTC_MODE0_INTENCLR_PER5_Pos 5

#define RTC_MODE0_INTENCLR_PER5     (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)

#define RTC_MODE0_INTENCLR_PER6_Pos 6

#define RTC_MODE0_INTENCLR_PER6     (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)

#define RTC_MODE0_INTENCLR_PER7_Pos 7

#define RTC_MODE0_INTENCLR_PER7     (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)

#define RTC_MODE0_INTENCLR_PER_Pos  0

#define RTC_MODE0_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)

#define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))

#define RTC_MODE0_INTENCLR_CMP0_Pos 8

#define RTC_MODE0_INTENCLR_CMP0     (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)

#define RTC_MODE0_INTENCLR_CMP1_Pos 9

#define RTC_MODE0_INTENCLR_CMP1     (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)

#define RTC_MODE0_INTENCLR_CMP_Pos  8

#define RTC_MODE0_INTENCLR_CMP_Msk  (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)

#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))

#define RTC_MODE0_INTENCLR_TAMPER_Pos 14

#define RTC_MODE0_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)

#define RTC_MODE0_INTENCLR_OVF_Pos  15

#define RTC_MODE0_INTENCLR_OVF      (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)

#define RTC_MODE0_INTENCLR_MASK     _U_(0xC3FF)

/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t PER0:1;

    uint16_t PER1:1;

    uint16_t PER2:1;

    uint16_t PER3:1;

    uint16_t PER4:1;

    uint16_t PER5:1;

    uint16_t PER6:1;

    uint16_t PER7:1;

    uint16_t CMP0:1;

    uint16_t CMP1:1;

    uint16_t CMP2:1;

    uint16_t CMP3:1;

    uint16_t :2;

    uint16_t TAMPER:1;

    uint16_t OVF:1;

  } bit;

  struct {

    uint16_t PER:8;

    uint16_t CMP:4;

    uint16_t :4;

  } vec;

  uint16_t reg;

} RTC_MODE1_INTENCLR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_INTENCLR_OFFSET   0x08

#define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000)

#define RTC_MODE1_INTENCLR_PER0_Pos 0

#define RTC_MODE1_INTENCLR_PER0     (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)

#define RTC_MODE1_INTENCLR_PER1_Pos 1

#define RTC_MODE1_INTENCLR_PER1     (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)

#define RTC_MODE1_INTENCLR_PER2_Pos 2

#define RTC_MODE1_INTENCLR_PER2     (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)

#define RTC_MODE1_INTENCLR_PER3_Pos 3

#define RTC_MODE1_INTENCLR_PER3     (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)

#define RTC_MODE1_INTENCLR_PER4_Pos 4

#define RTC_MODE1_INTENCLR_PER4     (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)

#define RTC_MODE1_INTENCLR_PER5_Pos 5

#define RTC_MODE1_INTENCLR_PER5     (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)

#define RTC_MODE1_INTENCLR_PER6_Pos 6

#define RTC_MODE1_INTENCLR_PER6     (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)

#define RTC_MODE1_INTENCLR_PER7_Pos 7

#define RTC_MODE1_INTENCLR_PER7     (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)

#define RTC_MODE1_INTENCLR_PER_Pos  0

#define RTC_MODE1_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)

#define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))

#define RTC_MODE1_INTENCLR_CMP0_Pos 8

#define RTC_MODE1_INTENCLR_CMP0     (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)

#define RTC_MODE1_INTENCLR_CMP1_Pos 9

#define RTC_MODE1_INTENCLR_CMP1     (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)

#define RTC_MODE1_INTENCLR_CMP2_Pos 10

#define RTC_MODE1_INTENCLR_CMP2     (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)

#define RTC_MODE1_INTENCLR_CMP3_Pos 11

#define RTC_MODE1_INTENCLR_CMP3     (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)

#define RTC_MODE1_INTENCLR_CMP_Pos  8

#define RTC_MODE1_INTENCLR_CMP_Msk  (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)

#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))

#define RTC_MODE1_INTENCLR_TAMPER_Pos 14

#define RTC_MODE1_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)

#define RTC_MODE1_INTENCLR_OVF_Pos  15

#define RTC_MODE1_INTENCLR_OVF      (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)

#define RTC_MODE1_INTENCLR_MASK     _U_(0xCFFF)

/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t PER0:1;

    uint16_t PER1:1;

    uint16_t PER2:1;

    uint16_t PER3:1;

    uint16_t PER4:1;

    uint16_t PER5:1;

    uint16_t PER6:1;

    uint16_t PER7:1;

    uint16_t ALARM0:1;

    uint16_t ALARM1:1;

    uint16_t :4;

    uint16_t TAMPER:1;

    uint16_t OVF:1;

  } bit;

  struct {

    uint16_t PER:8;

    uint16_t ALARM:2;

    uint16_t :6;

  } vec;

  uint16_t reg;

} RTC_MODE2_INTENCLR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_INTENCLR_OFFSET   0x08

#define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000)

#define RTC_MODE2_INTENCLR_PER0_Pos 0

#define RTC_MODE2_INTENCLR_PER0     (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)

#define RTC_MODE2_INTENCLR_PER1_Pos 1

#define RTC_MODE2_INTENCLR_PER1     (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)

#define RTC_MODE2_INTENCLR_PER2_Pos 2

#define RTC_MODE2_INTENCLR_PER2     (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)

#define RTC_MODE2_INTENCLR_PER3_Pos 3

#define RTC_MODE2_INTENCLR_PER3     (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)

#define RTC_MODE2_INTENCLR_PER4_Pos 4

#define RTC_MODE2_INTENCLR_PER4     (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)

#define RTC_MODE2_INTENCLR_PER5_Pos 5

#define RTC_MODE2_INTENCLR_PER5     (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)

#define RTC_MODE2_INTENCLR_PER6_Pos 6

#define RTC_MODE2_INTENCLR_PER6     (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)

#define RTC_MODE2_INTENCLR_PER7_Pos 7

#define RTC_MODE2_INTENCLR_PER7     (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)

#define RTC_MODE2_INTENCLR_PER_Pos  0

#define RTC_MODE2_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)

#define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))

#define RTC_MODE2_INTENCLR_ALARM0_Pos 8

#define RTC_MODE2_INTENCLR_ALARM0   (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)

#define RTC_MODE2_INTENCLR_ALARM1_Pos 9

#define RTC_MODE2_INTENCLR_ALARM1   (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)

#define RTC_MODE2_INTENCLR_ALARM_Pos 8

#define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)

#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))

#define RTC_MODE2_INTENCLR_TAMPER_Pos 14

#define RTC_MODE2_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)

#define RTC_MODE2_INTENCLR_OVF_Pos  15

#define RTC_MODE2_INTENCLR_OVF      (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)

#define RTC_MODE2_INTENCLR_MASK     _U_(0xC3FF)

/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t PER0:1;

    uint16_t PER1:1;

    uint16_t PER2:1;

    uint16_t PER3:1;

    uint16_t PER4:1;

    uint16_t PER5:1;

    uint16_t PER6:1;

    uint16_t PER7:1;

    uint16_t CMP0:1;

    uint16_t CMP1:1;

    uint16_t :4;

    uint16_t TAMPER:1;

    uint16_t OVF:1;

  } bit;

  struct {

    uint16_t PER:8;

    uint16_t CMP:2;

    uint16_t :6;

  } vec;

  uint16_t reg;

} RTC_MODE0_INTENSET_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_INTENSET_OFFSET   0x0A

#define RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000)

#define RTC_MODE0_INTENSET_PER0_Pos 0

#define RTC_MODE0_INTENSET_PER0     (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)

#define RTC_MODE0_INTENSET_PER1_Pos 1

#define RTC_MODE0_INTENSET_PER1     (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)

#define RTC_MODE0_INTENSET_PER2_Pos 2

#define RTC_MODE0_INTENSET_PER2     (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)

#define RTC_MODE0_INTENSET_PER3_Pos 3

#define RTC_MODE0_INTENSET_PER3     (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)

#define RTC_MODE0_INTENSET_PER4_Pos 4

#define RTC_MODE0_INTENSET_PER4     (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)

#define RTC_MODE0_INTENSET_PER5_Pos 5

#define RTC_MODE0_INTENSET_PER5     (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)

#define RTC_MODE0_INTENSET_PER6_Pos 6

#define RTC_MODE0_INTENSET_PER6     (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)

#define RTC_MODE0_INTENSET_PER7_Pos 7

#define RTC_MODE0_INTENSET_PER7     (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)

#define RTC_MODE0_INTENSET_PER_Pos  0

#define RTC_MODE0_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)

#define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))

#define RTC_MODE0_INTENSET_CMP0_Pos 8

#define RTC_MODE0_INTENSET_CMP0     (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)

#define RTC_MODE0_INTENSET_CMP1_Pos 9

#define RTC_MODE0_INTENSET_CMP1     (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)

#define RTC_MODE0_INTENSET_CMP_Pos  8

#define RTC_MODE0_INTENSET_CMP_Msk  (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)

#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))

#define RTC_MODE0_INTENSET_TAMPER_Pos 14

#define RTC_MODE0_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)

#define RTC_MODE0_INTENSET_OVF_Pos  15

#define RTC_MODE0_INTENSET_OVF      (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)

#define RTC_MODE0_INTENSET_MASK     _U_(0xC3FF)

/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t PER0:1;

    uint16_t PER1:1;

    uint16_t PER2:1;

    uint16_t PER3:1;

    uint16_t PER4:1;

    uint16_t PER5:1;

    uint16_t PER6:1;

    uint16_t PER7:1;

    uint16_t CMP0:1;

    uint16_t CMP1:1;

    uint16_t CMP2:1;

    uint16_t CMP3:1;

    uint16_t :2;

    uint16_t TAMPER:1;

    uint16_t OVF:1;

  } bit;

  struct {

    uint16_t PER:8;

    uint16_t CMP:4;

    uint16_t :4;

  } vec;

  uint16_t reg;

} RTC_MODE1_INTENSET_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_INTENSET_OFFSET   0x0A

#define RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000)

#define RTC_MODE1_INTENSET_PER0_Pos 0

#define RTC_MODE1_INTENSET_PER0     (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)

#define RTC_MODE1_INTENSET_PER1_Pos 1

#define RTC_MODE1_INTENSET_PER1     (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)

#define RTC_MODE1_INTENSET_PER2_Pos 2

#define RTC_MODE1_INTENSET_PER2     (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)

#define RTC_MODE1_INTENSET_PER3_Pos 3

#define RTC_MODE1_INTENSET_PER3     (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)

#define RTC_MODE1_INTENSET_PER4_Pos 4

#define RTC_MODE1_INTENSET_PER4     (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)

#define RTC_MODE1_INTENSET_PER5_Pos 5

#define RTC_MODE1_INTENSET_PER5     (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)

#define RTC_MODE1_INTENSET_PER6_Pos 6

#define RTC_MODE1_INTENSET_PER6     (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)

#define RTC_MODE1_INTENSET_PER7_Pos 7

#define RTC_MODE1_INTENSET_PER7     (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)

#define RTC_MODE1_INTENSET_PER_Pos  0

#define RTC_MODE1_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)

#define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))

#define RTC_MODE1_INTENSET_CMP0_Pos 8

#define RTC_MODE1_INTENSET_CMP0     (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)

#define RTC_MODE1_INTENSET_CMP1_Pos 9

#define RTC_MODE1_INTENSET_CMP1     (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)

#define RTC_MODE1_INTENSET_CMP2_Pos 10

#define RTC_MODE1_INTENSET_CMP2     (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)

#define RTC_MODE1_INTENSET_CMP3_Pos 11

#define RTC_MODE1_INTENSET_CMP3     (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)

#define RTC_MODE1_INTENSET_CMP_Pos  8

#define RTC_MODE1_INTENSET_CMP_Msk  (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)

#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))

#define RTC_MODE1_INTENSET_TAMPER_Pos 14

#define RTC_MODE1_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)

#define RTC_MODE1_INTENSET_OVF_Pos  15

#define RTC_MODE1_INTENSET_OVF      (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)

#define RTC_MODE1_INTENSET_MASK     _U_(0xCFFF)

/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t PER0:1;

    uint16_t PER1:1;

    uint16_t PER2:1;

    uint16_t PER3:1;

    uint16_t PER4:1;

    uint16_t PER5:1;

    uint16_t PER6:1;

    uint16_t PER7:1;

    uint16_t ALARM0:1;

    uint16_t ALARM1:1;

    uint16_t :4;

    uint16_t TAMPER:1;

    uint16_t OVF:1;

  } bit;

  struct {

    uint16_t PER:8;

    uint16_t ALARM:2;

    uint16_t :6;

  } vec;

  uint16_t reg;

} RTC_MODE2_INTENSET_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_INTENSET_OFFSET   0x0A

#define RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000)

#define RTC_MODE2_INTENSET_PER0_Pos 0

#define RTC_MODE2_INTENSET_PER0     (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)

#define RTC_MODE2_INTENSET_PER1_Pos 1

#define RTC_MODE2_INTENSET_PER1     (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)

#define RTC_MODE2_INTENSET_PER2_Pos 2

#define RTC_MODE2_INTENSET_PER2     (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)

#define RTC_MODE2_INTENSET_PER3_Pos 3

#define RTC_MODE2_INTENSET_PER3     (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)

#define RTC_MODE2_INTENSET_PER4_Pos 4

#define RTC_MODE2_INTENSET_PER4     (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)

#define RTC_MODE2_INTENSET_PER5_Pos 5

#define RTC_MODE2_INTENSET_PER5     (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)

#define RTC_MODE2_INTENSET_PER6_Pos 6

#define RTC_MODE2_INTENSET_PER6     (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)

#define RTC_MODE2_INTENSET_PER7_Pos 7

#define RTC_MODE2_INTENSET_PER7     (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)

#define RTC_MODE2_INTENSET_PER_Pos  0

#define RTC_MODE2_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)

#define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))

#define RTC_MODE2_INTENSET_ALARM0_Pos 8

#define RTC_MODE2_INTENSET_ALARM0   (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)

#define RTC_MODE2_INTENSET_ALARM1_Pos 9

#define RTC_MODE2_INTENSET_ALARM1   (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)

#define RTC_MODE2_INTENSET_ALARM_Pos 8

#define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)

#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))

#define RTC_MODE2_INTENSET_TAMPER_Pos 14

#define RTC_MODE2_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)

#define RTC_MODE2_INTENSET_OVF_Pos  15

#define RTC_MODE2_INTENSET_OVF      (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)

#define RTC_MODE2_INTENSET_MASK     _U_(0xC3FF)

/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union { // __I to avoid read-modify-write on write-to-clear register

  struct {

    __I uint16_t PER0:1;

    __I uint16_t PER1:1;

    __I uint16_t PER2:1;

    __I uint16_t PER3:1;

    __I uint16_t PER4:1;

    __I uint16_t PER5:1;

    __I uint16_t PER6:1;

    __I uint16_t PER7:1;

    __I uint16_t CMP0:1;

    __I uint16_t CMP1:1;

    __I uint16_t :4;

    __I uint16_t TAMPER:1;

    __I uint16_t OVF:1;

  } bit;

  struct {

    __I uint16_t PER:8;

    __I uint16_t CMP:2;

    __I uint16_t :6;

  } vec;

  uint16_t reg;

} RTC_MODE0_INTFLAG_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_INTFLAG_OFFSET    0x0C

#define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000)

#define RTC_MODE0_INTFLAG_PER0_Pos  0

#define RTC_MODE0_INTFLAG_PER0      (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)

#define RTC_MODE0_INTFLAG_PER1_Pos  1

#define RTC_MODE0_INTFLAG_PER1      (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)

#define RTC_MODE0_INTFLAG_PER2_Pos  2

#define RTC_MODE0_INTFLAG_PER2      (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)

#define RTC_MODE0_INTFLAG_PER3_Pos  3

#define RTC_MODE0_INTFLAG_PER3      (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)

#define RTC_MODE0_INTFLAG_PER4_Pos  4

#define RTC_MODE0_INTFLAG_PER4      (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)

#define RTC_MODE0_INTFLAG_PER5_Pos  5

#define RTC_MODE0_INTFLAG_PER5      (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)

#define RTC_MODE0_INTFLAG_PER6_Pos  6

#define RTC_MODE0_INTFLAG_PER6      (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)

#define RTC_MODE0_INTFLAG_PER7_Pos  7

#define RTC_MODE0_INTFLAG_PER7      (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)

#define RTC_MODE0_INTFLAG_PER_Pos   0

#define RTC_MODE0_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)

#define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))

#define RTC_MODE0_INTFLAG_CMP0_Pos  8

#define RTC_MODE0_INTFLAG_CMP0      (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)

#define RTC_MODE0_INTFLAG_CMP1_Pos  9

#define RTC_MODE0_INTFLAG_CMP1      (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)

#define RTC_MODE0_INTFLAG_CMP_Pos   8

#define RTC_MODE0_INTFLAG_CMP_Msk   (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)

#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))

#define RTC_MODE0_INTFLAG_TAMPER_Pos 14

#define RTC_MODE0_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)

#define RTC_MODE0_INTFLAG_OVF_Pos   15

#define RTC_MODE0_INTFLAG_OVF       (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)

#define RTC_MODE0_INTFLAG_MASK      _U_(0xC3FF)

/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union { // __I to avoid read-modify-write on write-to-clear register

  struct {

    __I uint16_t PER0:1;

    __I uint16_t PER1:1;

    __I uint16_t PER2:1;

    __I uint16_t PER3:1;

    __I uint16_t PER4:1;

    __I uint16_t PER5:1;

    __I uint16_t PER6:1;

    __I uint16_t PER7:1;

    __I uint16_t CMP0:1;

    __I uint16_t CMP1:1;

    __I uint16_t CMP2:1;

    __I uint16_t CMP3:1;

    __I uint16_t :2;

    __I uint16_t TAMPER:1;

    __I uint16_t OVF:1;

  } bit;

  struct {

    __I uint16_t PER:8;

    __I uint16_t CMP:4;

    __I uint16_t :4;

  } vec;

  uint16_t reg;

} RTC_MODE1_INTFLAG_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_INTFLAG_OFFSET    0x0C

#define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000)

#define RTC_MODE1_INTFLAG_PER0_Pos  0

#define RTC_MODE1_INTFLAG_PER0      (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)

#define RTC_MODE1_INTFLAG_PER1_Pos  1

#define RTC_MODE1_INTFLAG_PER1      (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)

#define RTC_MODE1_INTFLAG_PER2_Pos  2

#define RTC_MODE1_INTFLAG_PER2      (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)

#define RTC_MODE1_INTFLAG_PER3_Pos  3

#define RTC_MODE1_INTFLAG_PER3      (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)

#define RTC_MODE1_INTFLAG_PER4_Pos  4

#define RTC_MODE1_INTFLAG_PER4      (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)

#define RTC_MODE1_INTFLAG_PER5_Pos  5

#define RTC_MODE1_INTFLAG_PER5      (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)

#define RTC_MODE1_INTFLAG_PER6_Pos  6

#define RTC_MODE1_INTFLAG_PER6      (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)

#define RTC_MODE1_INTFLAG_PER7_Pos  7

#define RTC_MODE1_INTFLAG_PER7      (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)

#define RTC_MODE1_INTFLAG_PER_Pos   0

#define RTC_MODE1_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)

#define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))

#define RTC_MODE1_INTFLAG_CMP0_Pos  8

#define RTC_MODE1_INTFLAG_CMP0      (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)

#define RTC_MODE1_INTFLAG_CMP1_Pos  9

#define RTC_MODE1_INTFLAG_CMP1      (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)

#define RTC_MODE1_INTFLAG_CMP2_Pos  10

#define RTC_MODE1_INTFLAG_CMP2      (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)

#define RTC_MODE1_INTFLAG_CMP3_Pos  11

#define RTC_MODE1_INTFLAG_CMP3      (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)

#define RTC_MODE1_INTFLAG_CMP_Pos   8

#define RTC_MODE1_INTFLAG_CMP_Msk   (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)

#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))

#define RTC_MODE1_INTFLAG_TAMPER_Pos 14

#define RTC_MODE1_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)

#define RTC_MODE1_INTFLAG_OVF_Pos   15

#define RTC_MODE1_INTFLAG_OVF       (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)

#define RTC_MODE1_INTFLAG_MASK      _U_(0xCFFF)

/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union { // __I to avoid read-modify-write on write-to-clear register

  struct {

    __I uint16_t PER0:1;

    __I uint16_t PER1:1;

    __I uint16_t PER2:1;

    __I uint16_t PER3:1;

    __I uint16_t PER4:1;

    __I uint16_t PER5:1;

    __I uint16_t PER6:1;

    __I uint16_t PER7:1;

    __I uint16_t ALARM0:1;

    __I uint16_t ALARM1:1;

    __I uint16_t :4;

    __I uint16_t TAMPER:1;

    __I uint16_t OVF:1;

  } bit;

  struct {

    __I uint16_t PER:8;

    __I uint16_t ALARM:2;

    __I uint16_t :6;

  } vec;

  uint16_t reg;

} RTC_MODE2_INTFLAG_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_INTFLAG_OFFSET    0x0C

#define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000)

#define RTC_MODE2_INTFLAG_PER0_Pos  0

#define RTC_MODE2_INTFLAG_PER0      (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)

#define RTC_MODE2_INTFLAG_PER1_Pos  1

#define RTC_MODE2_INTFLAG_PER1      (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)

#define RTC_MODE2_INTFLAG_PER2_Pos  2

#define RTC_MODE2_INTFLAG_PER2      (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)

#define RTC_MODE2_INTFLAG_PER3_Pos  3

#define RTC_MODE2_INTFLAG_PER3      (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)

#define RTC_MODE2_INTFLAG_PER4_Pos  4

#define RTC_MODE2_INTFLAG_PER4      (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)

#define RTC_MODE2_INTFLAG_PER5_Pos  5

#define RTC_MODE2_INTFLAG_PER5      (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)

#define RTC_MODE2_INTFLAG_PER6_Pos  6

#define RTC_MODE2_INTFLAG_PER6      (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)

#define RTC_MODE2_INTFLAG_PER7_Pos  7

#define RTC_MODE2_INTFLAG_PER7      (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)

#define RTC_MODE2_INTFLAG_PER_Pos   0

#define RTC_MODE2_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)

#define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))

#define RTC_MODE2_INTFLAG_ALARM0_Pos 8

#define RTC_MODE2_INTFLAG_ALARM0    (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)

#define RTC_MODE2_INTFLAG_ALARM1_Pos 9

#define RTC_MODE2_INTFLAG_ALARM1    (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)

#define RTC_MODE2_INTFLAG_ALARM_Pos 8

#define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)

#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))

#define RTC_MODE2_INTFLAG_TAMPER_Pos 14

#define RTC_MODE2_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)

#define RTC_MODE2_INTFLAG_OVF_Pos   15

#define RTC_MODE2_INTFLAG_OVF       (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)

#define RTC_MODE2_INTFLAG_MASK      _U_(0xC3FF)

/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W  8) Debug Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint8_t  DBGRUN:1;

    uint8_t  :7;

  } bit;

  uint8_t reg;

} RTC_DBGCTRL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_DBGCTRL_OFFSET          0x0E

#define RTC_DBGCTRL_RESETVALUE      _U_(0x00)

#define RTC_DBGCTRL_DBGRUN_Pos      0

#define RTC_DBGCTRL_DBGRUN          (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)

#define RTC_DBGCTRL_MASK            _U_(0x01)

/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE0 MODE0 Synchronization Busy Status -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SWRST:1;

    uint32_t ENABLE:1;

    uint32_t FREQCORR:1;

    uint32_t COUNT:1;

    uint32_t :1;

    uint32_t COMP0:1;

    uint32_t COMP1:1;

    uint32_t :8;

    uint32_t COUNTSYNC:1;

    uint32_t GP0:1;

    uint32_t GP1:1;

    uint32_t GP2:1;

    uint32_t GP3:1;

    uint32_t :12;

  } bit;

  struct {

    uint32_t :5;

    uint32_t COMP:2;

    uint32_t :9;

    uint32_t GP:4;

    uint32_t :12;

  } vec;

  uint32_t reg;

} RTC_MODE0_SYNCBUSY_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_SYNCBUSY_OFFSET   0x10

#define RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000)

#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0

#define RTC_MODE0_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)

#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1

#define RTC_MODE0_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)

#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2

#define RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)

#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3

#define RTC_MODE0_SYNCBUSY_COUNT    (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)

#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5

#define RTC_MODE0_SYNCBUSY_COMP0    (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)

#define RTC_MODE0_SYNCBUSY_COMP1_Pos 6

#define RTC_MODE0_SYNCBUSY_COMP1    (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)

#define RTC_MODE0_SYNCBUSY_COMP_Pos 5

#define RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)

#define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))

#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15

#define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)

#define RTC_MODE0_SYNCBUSY_GP0_Pos  16

#define RTC_MODE0_SYNCBUSY_GP0      (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)

#define RTC_MODE0_SYNCBUSY_GP1_Pos  17

#define RTC_MODE0_SYNCBUSY_GP1      (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)

#define RTC_MODE0_SYNCBUSY_GP2_Pos  18

#define RTC_MODE0_SYNCBUSY_GP2      (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)

#define RTC_MODE0_SYNCBUSY_GP3_Pos  19

#define RTC_MODE0_SYNCBUSY_GP3      (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)

#define RTC_MODE0_SYNCBUSY_GP_Pos   16

#define RTC_MODE0_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)

#define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))

#define RTC_MODE0_SYNCBUSY_MASK     _U_(0x000F806F)

/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE1 MODE1 Synchronization Busy Status -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SWRST:1;

    uint32_t ENABLE:1;

    uint32_t FREQCORR:1;

    uint32_t COUNT:1;

    uint32_t PER:1;

    uint32_t COMP0:1;

    uint32_t COMP1:1;

    uint32_t COMP2:1;

    uint32_t COMP3:1;

    uint32_t :6;

    uint32_t COUNTSYNC:1;

    uint32_t GP0:1;

    uint32_t GP1:1;

    uint32_t GP2:1;

    uint32_t GP3:1;

    uint32_t :12;

  } bit;

  struct {

    uint32_t :5;

    uint32_t COMP:4;

    uint32_t :7;

    uint32_t GP:4;

    uint32_t :12;

  } vec;

  uint32_t reg;

} RTC_MODE1_SYNCBUSY_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_SYNCBUSY_OFFSET   0x10

#define RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000)

#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0

#define RTC_MODE1_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)

#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1

#define RTC_MODE1_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)

#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2

#define RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)

#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3

#define RTC_MODE1_SYNCBUSY_COUNT    (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)

#define RTC_MODE1_SYNCBUSY_PER_Pos  4

#define RTC_MODE1_SYNCBUSY_PER      (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)

#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5

#define RTC_MODE1_SYNCBUSY_COMP0    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)

#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6

#define RTC_MODE1_SYNCBUSY_COMP1    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)

#define RTC_MODE1_SYNCBUSY_COMP2_Pos 7

#define RTC_MODE1_SYNCBUSY_COMP2    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)

#define RTC_MODE1_SYNCBUSY_COMP3_Pos 8

#define RTC_MODE1_SYNCBUSY_COMP3    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)

#define RTC_MODE1_SYNCBUSY_COMP_Pos 5

#define RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)

#define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))

#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15

#define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)

#define RTC_MODE1_SYNCBUSY_GP0_Pos  16

#define RTC_MODE1_SYNCBUSY_GP0      (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)

#define RTC_MODE1_SYNCBUSY_GP1_Pos  17

#define RTC_MODE1_SYNCBUSY_GP1      (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)

#define RTC_MODE1_SYNCBUSY_GP2_Pos  18

#define RTC_MODE1_SYNCBUSY_GP2      (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)

#define RTC_MODE1_SYNCBUSY_GP3_Pos  19

#define RTC_MODE1_SYNCBUSY_GP3      (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)

#define RTC_MODE1_SYNCBUSY_GP_Pos   16

#define RTC_MODE1_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)

#define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))

#define RTC_MODE1_SYNCBUSY_MASK     _U_(0x000F81FF)

/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE2 MODE2 Synchronization Busy Status -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SWRST:1;

    uint32_t ENABLE:1;

    uint32_t FREQCORR:1;

    uint32_t CLOCK:1;

    uint32_t :1;

    uint32_t ALARM0:1;

    uint32_t ALARM1:1;

    uint32_t :4;

    uint32_t MASK0:1;

    uint32_t MASK1:1;

    uint32_t :2;

    uint32_t CLOCKSYNC:1;

    uint32_t GP0:1;

    uint32_t GP1:1;

    uint32_t GP2:1;

    uint32_t GP3:1;

    uint32_t :12;

  } bit;

  struct {

    uint32_t :5;

    uint32_t ALARM:2;

    uint32_t :4;

    uint32_t MASK:2;

    uint32_t :3;

    uint32_t GP:4;

    uint32_t :12;

  } vec;

  uint32_t reg;

} RTC_MODE2_SYNCBUSY_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_SYNCBUSY_OFFSET   0x10

#define RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000)

#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0

#define RTC_MODE2_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)

#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1

#define RTC_MODE2_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)

#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2

#define RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)

#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3

#define RTC_MODE2_SYNCBUSY_CLOCK    (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)

#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5

#define RTC_MODE2_SYNCBUSY_ALARM0   (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)

#define RTC_MODE2_SYNCBUSY_ALARM1_Pos 6

#define RTC_MODE2_SYNCBUSY_ALARM1   (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)

#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5

#define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)

#define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))

#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11

#define RTC_MODE2_SYNCBUSY_MASK0    (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)

#define RTC_MODE2_SYNCBUSY_MASK1_Pos 12

#define RTC_MODE2_SYNCBUSY_MASK1    (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)

#define RTC_MODE2_SYNCBUSY_MASK_Pos 11

#define RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)

#define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))

#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15

#define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)

#define RTC_MODE2_SYNCBUSY_GP0_Pos  16

#define RTC_MODE2_SYNCBUSY_GP0      (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)

#define RTC_MODE2_SYNCBUSY_GP1_Pos  17

#define RTC_MODE2_SYNCBUSY_GP1      (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)

#define RTC_MODE2_SYNCBUSY_GP2_Pos  18

#define RTC_MODE2_SYNCBUSY_GP2      (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)

#define RTC_MODE2_SYNCBUSY_GP3_Pos  19

#define RTC_MODE2_SYNCBUSY_GP3      (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)

#define RTC_MODE2_SYNCBUSY_GP_Pos   16

#define RTC_MODE2_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)

#define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))

#define RTC_MODE2_SYNCBUSY_MASK_    _U_(0x000F986F)

/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W  8) Frequency Correction -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint8_t  VALUE:7;

    uint8_t  SIGN:1;

  } bit;

  uint8_t reg;

} RTC_FREQCORR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_FREQCORR_OFFSET         0x14

#define RTC_FREQCORR_RESETVALUE     _U_(0x00)

#define RTC_FREQCORR_VALUE_Pos      0

#define RTC_FREQCORR_VALUE_Msk      (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)

#define RTC_FREQCORR_VALUE(value)   (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))

#define RTC_FREQCORR_SIGN_Pos       7

#define RTC_FREQCORR_SIGN           (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)

#define RTC_FREQCORR_MASK           _U_(0xFF)

/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t COUNT:32;

  } bit;

  uint32_t reg;

} RTC_MODE0_COUNT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_COUNT_OFFSET      0x18

#define RTC_MODE0_COUNT_RESETVALUE  _U_(0x00000000)

#define RTC_MODE0_COUNT_COUNT_Pos   0

#define RTC_MODE0_COUNT_COUNT_Msk   (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)

#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))

#define RTC_MODE0_COUNT_MASK        _U_(0xFFFFFFFF)

/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t COUNT:16;

  } bit;

  uint16_t reg;

} RTC_MODE1_COUNT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_COUNT_OFFSET      0x18

#define RTC_MODE1_COUNT_RESETVALUE  _U_(0x0000)

#define RTC_MODE1_COUNT_COUNT_Pos   0

#define RTC_MODE1_COUNT_COUNT_Msk   (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)

#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))

#define RTC_MODE1_COUNT_MASK        _U_(0xFFFF)

/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SECOND:6;

    uint32_t MINUTE:6;

    uint32_t HOUR:5;

    uint32_t DAY:5;

    uint32_t MONTH:4;

    uint32_t YEAR:6;

  } bit;

  uint32_t reg;

} RTC_MODE2_CLOCK_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_CLOCK_OFFSET      0x18

#define RTC_MODE2_CLOCK_RESETVALUE  _U_(0x00000000)

#define RTC_MODE2_CLOCK_SECOND_Pos  0

#define RTC_MODE2_CLOCK_SECOND_Msk  (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)

#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))

#define RTC_MODE2_CLOCK_MINUTE_Pos  6

#define RTC_MODE2_CLOCK_MINUTE_Msk  (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)

#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))

#define RTC_MODE2_CLOCK_HOUR_Pos    12

#define RTC_MODE2_CLOCK_HOUR_Msk    (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)

#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))

#define   RTC_MODE2_CLOCK_HOUR_AM_Val     _U_(0x0)

#define   RTC_MODE2_CLOCK_HOUR_PM_Val     _U_(0x10)

#define RTC_MODE2_CLOCK_HOUR_AM     (RTC_MODE2_CLOCK_HOUR_AM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)

#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)

#define RTC_MODE2_CLOCK_DAY_Pos     17

#define RTC_MODE2_CLOCK_DAY_Msk     (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)

#define RTC_MODE2_CLOCK_DAY(value)  (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))

#define RTC_MODE2_CLOCK_MONTH_Pos   22

#define RTC_MODE2_CLOCK_MONTH_Msk   (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)

#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))

#define RTC_MODE2_CLOCK_YEAR_Pos    26

#define RTC_MODE2_CLOCK_YEAR_Msk    (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)

#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))

#define RTC_MODE2_CLOCK_MASK        _U_(0xFFFFFFFF)

/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t PER:16;

  } bit;

  uint16_t reg;

} RTC_MODE1_PER_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_PER_OFFSET        0x1C

#define RTC_MODE1_PER_RESETVALUE    _U_(0x0000)

#define RTC_MODE1_PER_PER_Pos       0

#define RTC_MODE1_PER_PER_Msk       (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)

#define RTC_MODE1_PER_PER(value)    (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))

#define RTC_MODE1_PER_MASK          _U_(0xFFFF)

/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t COMP:32;

  } bit;

  uint32_t reg;

} RTC_MODE0_COMP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_COMP_OFFSET       0x20

#define RTC_MODE0_COMP_RESETVALUE   _U_(0x00000000)

#define RTC_MODE0_COMP_COMP_Pos     0

#define RTC_MODE0_COMP_COMP_Msk     (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)

#define RTC_MODE0_COMP_COMP(value)  (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))

#define RTC_MODE0_COMP_MASK         _U_(0xFFFFFFFF)

/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint16_t COMP:16;

  } bit;

  uint16_t reg;

} RTC_MODE1_COMP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_COMP_OFFSET       0x20

#define RTC_MODE1_COMP_RESETVALUE   _U_(0x0000)

#define RTC_MODE1_COMP_COMP_Pos     0

#define RTC_MODE1_COMP_COMP_Msk     (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)

#define RTC_MODE1_COMP_COMP(value)  (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))

#define RTC_MODE1_COMP_MASK         _U_(0xFFFF)

/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SECOND:6;

    uint32_t MINUTE:6;

    uint32_t HOUR:5;

    uint32_t DAY:5;

    uint32_t MONTH:4;

    uint32_t YEAR:6;

  } bit;

  uint32_t reg;

} RTC_MODE2_ALARM_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_ALARM_OFFSET      0x20

#define RTC_MODE2_ALARM_RESETVALUE  _U_(0x00000000)

#define RTC_MODE2_ALARM_SECOND_Pos  0

#define RTC_MODE2_ALARM_SECOND_Msk  (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)

#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))

#define RTC_MODE2_ALARM_MINUTE_Pos  6

#define RTC_MODE2_ALARM_MINUTE_Msk  (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)

#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))

#define RTC_MODE2_ALARM_HOUR_Pos    12

#define RTC_MODE2_ALARM_HOUR_Msk    (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)

#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))

#define   RTC_MODE2_ALARM_HOUR_AM_Val     _U_(0x0)

#define   RTC_MODE2_ALARM_HOUR_PM_Val     _U_(0x10)

#define RTC_MODE2_ALARM_HOUR_AM     (RTC_MODE2_ALARM_HOUR_AM_Val   << RTC_MODE2_ALARM_HOUR_Pos)

#define RTC_MODE2_ALARM_HOUR_PM     (RTC_MODE2_ALARM_HOUR_PM_Val   << RTC_MODE2_ALARM_HOUR_Pos)

#define RTC_MODE2_ALARM_DAY_Pos     17

#define RTC_MODE2_ALARM_DAY_Msk     (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)

#define RTC_MODE2_ALARM_DAY(value)  (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))

#define RTC_MODE2_ALARM_MONTH_Pos   22

#define RTC_MODE2_ALARM_MONTH_Msk   (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)

#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))

#define RTC_MODE2_ALARM_YEAR_Pos    26

#define RTC_MODE2_ALARM_YEAR_Msk    (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)

#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))

#define RTC_MODE2_ALARM_MASK        _U_(0xFFFFFFFF)

/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint8_t  SEL:3;

    uint8_t  :5;

  } bit;

  uint8_t reg;

} RTC_MODE2_MASK_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_MASK_OFFSET       0x24

#define RTC_MODE2_MASK_RESETVALUE   _U_(0x00)

#define RTC_MODE2_MASK_SEL_Pos      0

#define RTC_MODE2_MASK_SEL_Msk      (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_SEL(value)   (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))

#define   RTC_MODE2_MASK_SEL_OFF_Val      _U_(0x0)

#define   RTC_MODE2_MASK_SEL_SS_Val       _U_(0x1)

#define   RTC_MODE2_MASK_SEL_MMSS_Val     _U_(0x2)

#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   _U_(0x3)

#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4)

#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5)

#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6)

#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define RTC_MODE2_MASK_MASK         _U_(0x07)

/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t GP:32;

  } bit;

  uint32_t reg;

} RTC_GP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_GP_OFFSET               0x40

#define RTC_GP_RESETVALUE           _U_(0x00000000)

#define RTC_GP_GP_Pos               0

#define RTC_GP_GP_Msk               (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)

#define RTC_GP_GP(value)            (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))

#define RTC_GP_MASK                 _U_(0xFFFFFFFF)

/* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t IN0ACT:2;

    uint32_t IN1ACT:2;

    uint32_t IN2ACT:2;

    uint32_t IN3ACT:2;

    uint32_t IN4ACT:2;

    uint32_t :6;

    uint32_t TAMLVL0:1;

    uint32_t TAMLVL1:1;

    uint32_t TAMLVL2:1;

    uint32_t TAMLVL3:1;

    uint32_t TAMLVL4:1;

    uint32_t :3;

    uint32_t DEBNC0:1;

    uint32_t DEBNC1:1;

    uint32_t DEBNC2:1;

    uint32_t DEBNC3:1;

    uint32_t DEBNC4:1;

    uint32_t :3;

  } bit;

  struct {

    uint32_t :16;

    uint32_t TAMLVL:5;

    uint32_t :3;

    uint32_t DEBNC:5;

    uint32_t :3;

  } vec;

  uint32_t reg;

} RTC_TAMPCTRL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_TAMPCTRL_OFFSET         0x60

#define RTC_TAMPCTRL_RESETVALUE     _U_(0x00000000)

#define RTC_TAMPCTRL_IN0ACT_Pos     0

#define RTC_TAMPCTRL_IN0ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)

#define RTC_TAMPCTRL_IN0ACT(value)  (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))

#define   RTC_TAMPCTRL_IN0ACT_OFF_Val     _U_(0x0)

#define   RTC_TAMPCTRL_IN0ACT_WAKE_Val    _U_(0x1)

#define   RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2)

#define   RTC_TAMPCTRL_IN0ACT_ACTL_Val    _U_(0x3)

#define RTC_TAMPCTRL_IN0ACT_OFF     (RTC_TAMPCTRL_IN0ACT_OFF_Val   << RTC_TAMPCTRL_IN0ACT_Pos)

#define RTC_TAMPCTRL_IN0ACT_WAKE    (RTC_TAMPCTRL_IN0ACT_WAKE_Val  << RTC_TAMPCTRL_IN0ACT_Pos)

#define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)

#define RTC_TAMPCTRL_IN0ACT_ACTL    (RTC_TAMPCTRL_IN0ACT_ACTL_Val  << RTC_TAMPCTRL_IN0ACT_Pos)

#define RTC_TAMPCTRL_IN1ACT_Pos     2

#define RTC_TAMPCTRL_IN1ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)

#define RTC_TAMPCTRL_IN1ACT(value)  (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))

#define   RTC_TAMPCTRL_IN1ACT_OFF_Val     _U_(0x0)

#define   RTC_TAMPCTRL_IN1ACT_WAKE_Val    _U_(0x1)

#define   RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2)

#define   RTC_TAMPCTRL_IN1ACT_ACTL_Val    _U_(0x3)

#define RTC_TAMPCTRL_IN1ACT_OFF     (RTC_TAMPCTRL_IN1ACT_OFF_Val   << RTC_TAMPCTRL_IN1ACT_Pos)

#define RTC_TAMPCTRL_IN1ACT_WAKE    (RTC_TAMPCTRL_IN1ACT_WAKE_Val  << RTC_TAMPCTRL_IN1ACT_Pos)

#define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)

#define RTC_TAMPCTRL_IN1ACT_ACTL    (RTC_TAMPCTRL_IN1ACT_ACTL_Val  << RTC_TAMPCTRL_IN1ACT_Pos)

#define RTC_TAMPCTRL_IN2ACT_Pos     4

#define RTC_TAMPCTRL_IN2ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)

#define RTC_TAMPCTRL_IN2ACT(value)  (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))

#define   RTC_TAMPCTRL_IN2ACT_OFF_Val     _U_(0x0)

#define   RTC_TAMPCTRL_IN2ACT_WAKE_Val    _U_(0x1)

#define   RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2)

#define   RTC_TAMPCTRL_IN2ACT_ACTL_Val    _U_(0x3)

#define RTC_TAMPCTRL_IN2ACT_OFF     (RTC_TAMPCTRL_IN2ACT_OFF_Val   << RTC_TAMPCTRL_IN2ACT_Pos)

#define RTC_TAMPCTRL_IN2ACT_WAKE    (RTC_TAMPCTRL_IN2ACT_WAKE_Val  << RTC_TAMPCTRL_IN2ACT_Pos)

#define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)

#define RTC_TAMPCTRL_IN2ACT_ACTL    (RTC_TAMPCTRL_IN2ACT_ACTL_Val  << RTC_TAMPCTRL_IN2ACT_Pos)

#define RTC_TAMPCTRL_IN3ACT_Pos     6

#define RTC_TAMPCTRL_IN3ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)

#define RTC_TAMPCTRL_IN3ACT(value)  (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))

#define   RTC_TAMPCTRL_IN3ACT_OFF_Val     _U_(0x0)

#define   RTC_TAMPCTRL_IN3ACT_WAKE_Val    _U_(0x1)

#define   RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2)

#define   RTC_TAMPCTRL_IN3ACT_ACTL_Val    _U_(0x3)

#define RTC_TAMPCTRL_IN3ACT_OFF     (RTC_TAMPCTRL_IN3ACT_OFF_Val   << RTC_TAMPCTRL_IN3ACT_Pos)

#define RTC_TAMPCTRL_IN3ACT_WAKE    (RTC_TAMPCTRL_IN3ACT_WAKE_Val  << RTC_TAMPCTRL_IN3ACT_Pos)

#define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)

#define RTC_TAMPCTRL_IN3ACT_ACTL    (RTC_TAMPCTRL_IN3ACT_ACTL_Val  << RTC_TAMPCTRL_IN3ACT_Pos)

#define RTC_TAMPCTRL_IN4ACT_Pos     8

#define RTC_TAMPCTRL_IN4ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)

#define RTC_TAMPCTRL_IN4ACT(value)  (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))

#define   RTC_TAMPCTRL_IN4ACT_OFF_Val     _U_(0x0)

#define   RTC_TAMPCTRL_IN4ACT_WAKE_Val    _U_(0x1)

#define   RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2)

#define   RTC_TAMPCTRL_IN4ACT_ACTL_Val    _U_(0x3)

#define RTC_TAMPCTRL_IN4ACT_OFF     (RTC_TAMPCTRL_IN4ACT_OFF_Val   << RTC_TAMPCTRL_IN4ACT_Pos)

#define RTC_TAMPCTRL_IN4ACT_WAKE    (RTC_TAMPCTRL_IN4ACT_WAKE_Val  << RTC_TAMPCTRL_IN4ACT_Pos)

#define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)

#define RTC_TAMPCTRL_IN4ACT_ACTL    (RTC_TAMPCTRL_IN4ACT_ACTL_Val  << RTC_TAMPCTRL_IN4ACT_Pos)

#define RTC_TAMPCTRL_TAMLVL0_Pos    16

#define RTC_TAMPCTRL_TAMLVL0        (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)

#define RTC_TAMPCTRL_TAMLVL1_Pos    17

#define RTC_TAMPCTRL_TAMLVL1        (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)

#define RTC_TAMPCTRL_TAMLVL2_Pos    18

#define RTC_TAMPCTRL_TAMLVL2        (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)

#define RTC_TAMPCTRL_TAMLVL3_Pos    19

#define RTC_TAMPCTRL_TAMLVL3        (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)

#define RTC_TAMPCTRL_TAMLVL4_Pos    20

#define RTC_TAMPCTRL_TAMLVL4        (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)

#define RTC_TAMPCTRL_TAMLVL_Pos     16

#define RTC_TAMPCTRL_TAMLVL_Msk     (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)

#define RTC_TAMPCTRL_TAMLVL(value)  (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))

#define RTC_TAMPCTRL_DEBNC0_Pos     24

#define RTC_TAMPCTRL_DEBNC0         (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)

#define RTC_TAMPCTRL_DEBNC1_Pos     25

#define RTC_TAMPCTRL_DEBNC1         (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)

#define RTC_TAMPCTRL_DEBNC2_Pos     26

#define RTC_TAMPCTRL_DEBNC2         (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)

#define RTC_TAMPCTRL_DEBNC3_Pos     27

#define RTC_TAMPCTRL_DEBNC3         (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)

#define RTC_TAMPCTRL_DEBNC4_Pos     28

#define RTC_TAMPCTRL_DEBNC4         (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)

#define RTC_TAMPCTRL_DEBNC_Pos      24

#define RTC_TAMPCTRL_DEBNC_Msk      (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)

#define RTC_TAMPCTRL_DEBNC(value)   (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))

#define RTC_TAMPCTRL_MASK           _U_(0x1F1F03FF)

/* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE0 MODE0 Timestamp -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t COUNT:32;

  } bit;

  uint32_t reg;

} RTC_MODE0_TIMESTAMP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE0_TIMESTAMP_OFFSET  0x64

#define RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000)

#define RTC_MODE0_TIMESTAMP_COUNT_Pos 0

#define RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)

#define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))

#define RTC_MODE0_TIMESTAMP_MASK    _U_(0xFFFFFFFF)

/* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE1 MODE1 Timestamp -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t COUNT:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} RTC_MODE1_TIMESTAMP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE1_TIMESTAMP_OFFSET  0x64

#define RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000)

#define RTC_MODE1_TIMESTAMP_COUNT_Pos 0

#define RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)

#define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))

#define RTC_MODE1_TIMESTAMP_MASK    _U_(0x0000FFFF)

/* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE2 MODE2 Timestamp -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SECOND:6;

    uint32_t MINUTE:6;

    uint32_t HOUR:5;

    uint32_t DAY:5;

    uint32_t MONTH:4;

    uint32_t YEAR:6;

  } bit;

  uint32_t reg;

} RTC_MODE2_TIMESTAMP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_MODE2_TIMESTAMP_OFFSET  0x64

#define RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000)

#define RTC_MODE2_TIMESTAMP_SECOND_Pos 0

#define RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)

#define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))

#define RTC_MODE2_TIMESTAMP_MINUTE_Pos 6

#define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)

#define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))

#define RTC_MODE2_TIMESTAMP_HOUR_Pos 12

#define RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)

#define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))

#define   RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0)

#define   RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10)

#define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)

#define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)

#define RTC_MODE2_TIMESTAMP_DAY_Pos 17

#define RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)

#define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))

#define RTC_MODE2_TIMESTAMP_MONTH_Pos 22

#define RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)

#define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))

#define RTC_MODE2_TIMESTAMP_YEAR_Pos 26

#define RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)

#define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))

#define RTC_MODE2_TIMESTAMP_MASK    _U_(0xFFFFFFFF)

/* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TAMPID0:1;

    uint32_t TAMPID1:1;

    uint32_t TAMPID2:1;

    uint32_t TAMPID3:1;

    uint32_t TAMPID4:1;

    uint32_t :26;

    uint32_t TAMPEVT:1;

  } bit;

  struct {

    uint32_t TAMPID:5;

    uint32_t :27;

  } vec;

  uint32_t reg;

} RTC_TAMPID_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_TAMPID_OFFSET           0x68

#define RTC_TAMPID_RESETVALUE       _U_(0x00000000)

#define RTC_TAMPID_TAMPID0_Pos      0

#define RTC_TAMPID_TAMPID0          (_U_(1) << RTC_TAMPID_TAMPID0_Pos)

#define RTC_TAMPID_TAMPID1_Pos      1

#define RTC_TAMPID_TAMPID1          (_U_(1) << RTC_TAMPID_TAMPID1_Pos)

#define RTC_TAMPID_TAMPID2_Pos      2

#define RTC_TAMPID_TAMPID2          (_U_(1) << RTC_TAMPID_TAMPID2_Pos)

#define RTC_TAMPID_TAMPID3_Pos      3

#define RTC_TAMPID_TAMPID3          (_U_(1) << RTC_TAMPID_TAMPID3_Pos)

#define RTC_TAMPID_TAMPID4_Pos      4

#define RTC_TAMPID_TAMPID4          (_U_(1) << RTC_TAMPID_TAMPID4_Pos)

#define RTC_TAMPID_TAMPID_Pos       0

#define RTC_TAMPID_TAMPID_Msk       (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)

#define RTC_TAMPID_TAMPID(value)    (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))

#define RTC_TAMPID_TAMPEVT_Pos      31

#define RTC_TAMPID_TAMPEVT          (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)

#define RTC_TAMPID_MASK             _U_(0x8000001F)

/* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BKUP:32;

  } bit;

  uint32_t reg;

} RTC_BKUP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define RTC_BKUP_OFFSET             0x80

#define RTC_BKUP_RESETVALUE         _U_(0x00000000)

#define RTC_BKUP_BKUP_Pos           0

#define RTC_BKUP_BKUP_Msk           (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)

#define RTC_BKUP_BKUP(value)        (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))

#define RTC_BKUP_MASK               _U_(0xFFFFFFFF)

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO RTC_MODE2_ALARM_Type      ALARM;

  __IO RTC_MODE2_MASK_Type       MASK;

       RoReg8                    Reserved1[0x3];

} RtcMode2Alarm;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct { /* 32-bit Counter with Single 32-bit Compare */

  __IO RTC_MODE0_CTRLA_Type      CTRLA;

  __IO RTC_MODE0_CTRLB_Type      CTRLB;

  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;

  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;

  __IO RTC_MODE0_INTENSET_Type   INTENSET;

  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;

  __IO RTC_DBGCTRL_Type          DBGCTRL;

       RoReg8                    Reserved1[0x1];

  __I  RTC_MODE0_SYNCBUSY_Type   SYNCBUSY;

  __IO RTC_FREQCORR_Type         FREQCORR;

       RoReg8                    Reserved2[0x3];

  __IO RTC_MODE0_COUNT_Type      COUNT;

       RoReg8                    Reserved3[0x4];

  __IO RTC_MODE0_COMP_Type       COMP[2];

       RoReg8                    Reserved4[0x18];

  __IO RTC_GP_Type               GP[4];

       RoReg8                    Reserved5[0x10];

  __IO RTC_TAMPCTRL_Type         TAMPCTRL;

  __I  RTC_MODE0_TIMESTAMP_Type  TIMESTAMP;

  __IO RTC_TAMPID_Type           TAMPID;

       RoReg8                    Reserved6[0x14];

  __IO RTC_BKUP_Type             BKUP[8];

} RtcMode0;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct { /* 16-bit Counter with Two 16-bit Compares */

  __IO RTC_MODE1_CTRLA_Type      CTRLA;

  __IO RTC_MODE1_CTRLB_Type      CTRLB;

  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;

  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;

  __IO RTC_MODE1_INTENSET_Type   INTENSET;

  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;

  __IO RTC_DBGCTRL_Type          DBGCTRL;

       RoReg8                    Reserved1[0x1];

  __I  RTC_MODE1_SYNCBUSY_Type   SYNCBUSY;

  __IO RTC_FREQCORR_Type         FREQCORR;

       RoReg8                    Reserved2[0x3];

  __IO RTC_MODE1_COUNT_Type      COUNT;

       RoReg8                    Reserved3[0x2];

  __IO RTC_MODE1_PER_Type        PER;

       RoReg8                    Reserved4[0x2];

  __IO RTC_MODE1_COMP_Type       COMP[4];

       RoReg8                    Reserved5[0x18];

  __IO RTC_GP_Type               GP[4];

       RoReg8                    Reserved6[0x10];

  __IO RTC_TAMPCTRL_Type         TAMPCTRL;

  __I  RTC_MODE1_TIMESTAMP_Type  TIMESTAMP;

  __IO RTC_TAMPID_Type           TAMPID;

       RoReg8                    Reserved7[0x14];

  __IO RTC_BKUP_Type             BKUP[8];

} RtcMode1;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct { /* Clock/Calendar with Alarm */

  __IO RTC_MODE2_CTRLA_Type      CTRLA;

  __IO RTC_MODE2_CTRLB_Type      CTRLB;

  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;

  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;

  __IO RTC_MODE2_INTENSET_Type   INTENSET;

  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;

  __IO RTC_DBGCTRL_Type          DBGCTRL;

       RoReg8                    Reserved1[0x1];

  __I  RTC_MODE2_SYNCBUSY_Type   SYNCBUSY;

  __IO RTC_FREQCORR_Type         FREQCORR;

       RoReg8                    Reserved2[0x3];

  __IO RTC_MODE2_CLOCK_Type      CLOCK;

       RoReg8                    Reserved3[0x4];

       RtcMode2Alarm             Mode2Alarm[2];

       RoReg8                    Reserved4[0x10];

  __IO RTC_GP_Type               GP[4];

       RoReg8                    Reserved5[0x10];

  __IO RTC_TAMPCTRL_Type         TAMPCTRL;

  __I  RTC_MODE2_TIMESTAMP_Type  TIMESTAMP;

  __IO RTC_TAMPID_Type           TAMPID;

       RoReg8                    Reserved6[0x14];

  __IO RTC_BKUP_Type             BKUP[8];

} RtcMode2;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

       RtcMode0                  MODE0;

       RtcMode1                  MODE1;

       RtcMode2                  MODE2;

} Rtc;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#endif /* _SAME54_RTC_COMPONENT_ */