Component description for DAC. More...

Data Structures
union	DAC_CTRLA_Type

union	DAC_CTRLB_Type

union	DAC_EVCTRL_Type

union	DAC_INTENCLR_Type

union	DAC_INTENSET_Type

union	DAC_INTFLAG_Type

union	DAC_STATUS_Type

union	DAC_SYNCBUSY_Type

union	DAC_DACCTRL_Type

union	DAC_DATA_Type

union	DAC_DATABUF_Type

union	DAC_DBGCTRL_Type

union	DAC_RESULT_Type

struct	Dac
	DAC hardware registers. More...

Macros
#define	DAC_U2502

#define	REV_DAC 0x100

#define	DAC_CTRLA_OFFSET 0x00
	(DAC_CTRLA offset) Control A

#define	DAC_CTRLA_RESETVALUE _U_(0x00)
	(DAC_CTRLA reset_value) Control A

#define	DAC_CTRLA_SWRST_Pos 0
	(DAC_CTRLA) Software Reset

#define	DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)

#define	DAC_CTRLA_ENABLE_Pos 1
	(DAC_CTRLA) Enable DAC Controller

#define	DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)

#define	DAC_CTRLA_MASK _U_(0x03)
	(DAC_CTRLA) MASK Register

#define	DAC_CTRLB_OFFSET 0x01
	(DAC_CTRLB offset) Control B

#define	DAC_CTRLB_RESETVALUE _U_(0x02)
	(DAC_CTRLB reset_value) Control B

#define	DAC_CTRLB_DIFF_Pos 0
	(DAC_CTRLB) Differential mode enable

#define	DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)

#define	DAC_CTRLB_REFSEL_Pos 1
	(DAC_CTRLB) Reference Selection for DAC0/1

#define	DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)

#define	DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))

#define	DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0)
	(DAC_CTRLB) External reference unbuffered

#define	DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1)
	(DAC_CTRLB) Analog supply

#define	DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2)
	(DAC_CTRLB) External reference buffered

#define	DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3)
	(DAC_CTRLB) Internal bandgap reference

#define	DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)

#define	DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)

#define	DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)

#define	DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)

#define	DAC_CTRLB_MASK _U_(0x07)
	(DAC_CTRLB) MASK Register

#define	DAC_EVCTRL_OFFSET 0x02
	(DAC_EVCTRL offset) Event Control

#define	DAC_EVCTRL_RESETVALUE _U_(0x00)
	(DAC_EVCTRL reset_value) Event Control

#define	DAC_EVCTRL_STARTEI0_Pos 0
	(DAC_EVCTRL) Start Conversion Event Input DAC 0

#define	DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)

#define	DAC_EVCTRL_STARTEI1_Pos 1
	(DAC_EVCTRL) Start Conversion Event Input DAC 1

#define	DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)

#define	DAC_EVCTRL_STARTEI_Pos 0
	(DAC_EVCTRL) Start Conversion Event Input DAC x

#define	DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)

#define	DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))

#define	DAC_EVCTRL_EMPTYEO0_Pos 2
	(DAC_EVCTRL) Data Buffer Empty Event Output DAC 0

#define	DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)

#define	DAC_EVCTRL_EMPTYEO1_Pos 3
	(DAC_EVCTRL) Data Buffer Empty Event Output DAC 1

#define	DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)

#define	DAC_EVCTRL_EMPTYEO_Pos 2
	(DAC_EVCTRL) Data Buffer Empty Event Output DAC x

#define	DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)

#define	DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))

#define	DAC_EVCTRL_INVEI0_Pos 4
	(DAC_EVCTRL) Enable Invertion of DAC 0 input event

#define	DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)

#define	DAC_EVCTRL_INVEI1_Pos 5
	(DAC_EVCTRL) Enable Invertion of DAC 1 input event

#define	DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)

#define	DAC_EVCTRL_INVEI_Pos 4
	(DAC_EVCTRL) Enable Invertion of DAC x input event

#define	DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)

#define	DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))

#define	DAC_EVCTRL_RESRDYEO0_Pos 6
	(DAC_EVCTRL) Result Ready Event Output 0

#define	DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)

#define	DAC_EVCTRL_RESRDYEO1_Pos 7
	(DAC_EVCTRL) Result Ready Event Output 1

#define	DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)

#define	DAC_EVCTRL_RESRDYEO_Pos 6
	(DAC_EVCTRL) Result Ready Event Output x

#define	DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)

#define	DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))

#define	DAC_EVCTRL_MASK _U_(0xFF)
	(DAC_EVCTRL) MASK Register

#define	DAC_INTENCLR_OFFSET 0x04
	(DAC_INTENCLR offset) Interrupt Enable Clear

#define	DAC_INTENCLR_RESETVALUE _U_(0x00)
	(DAC_INTENCLR reset_value) Interrupt Enable Clear

#define	DAC_INTENCLR_UNDERRUN0_Pos 0
	(DAC_INTENCLR) Underrun 0 Interrupt Enable

#define	DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)

#define	DAC_INTENCLR_UNDERRUN1_Pos 1
	(DAC_INTENCLR) Underrun 1 Interrupt Enable

#define	DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)

#define	DAC_INTENCLR_UNDERRUN_Pos 0
	(DAC_INTENCLR) Underrun x Interrupt Enable

#define	DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)

#define	DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))

#define	DAC_INTENCLR_EMPTY0_Pos 2
	(DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable

#define	DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)

#define	DAC_INTENCLR_EMPTY1_Pos 3
	(DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable

#define	DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)

#define	DAC_INTENCLR_EMPTY_Pos 2
	(DAC_INTENCLR) Data Buffer x Empty Interrupt Enable

#define	DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)

#define	DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))

#define	DAC_INTENCLR_RESRDY0_Pos 4
	(DAC_INTENCLR) Result 0 Ready Interrupt Enable

#define	DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)

#define	DAC_INTENCLR_RESRDY1_Pos 5
	(DAC_INTENCLR) Result 1 Ready Interrupt Enable

#define	DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)

#define	DAC_INTENCLR_RESRDY_Pos 4
	(DAC_INTENCLR) Result x Ready Interrupt Enable

#define	DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)

#define	DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))

#define	DAC_INTENCLR_OVERRUN0_Pos 6
	(DAC_INTENCLR) Overrun 0 Interrupt Enable

#define	DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)

#define	DAC_INTENCLR_OVERRUN1_Pos 7
	(DAC_INTENCLR) Overrun 1 Interrupt Enable

#define	DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)

#define	DAC_INTENCLR_OVERRUN_Pos 6
	(DAC_INTENCLR) Overrun x Interrupt Enable

#define	DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)

#define	DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))

#define	DAC_INTENCLR_MASK _U_(0xFF)
	(DAC_INTENCLR) MASK Register

#define	DAC_INTENSET_OFFSET 0x05
	(DAC_INTENSET offset) Interrupt Enable Set

#define	DAC_INTENSET_RESETVALUE _U_(0x00)
	(DAC_INTENSET reset_value) Interrupt Enable Set

#define	DAC_INTENSET_UNDERRUN0_Pos 0
	(DAC_INTENSET) Underrun 0 Interrupt Enable

#define	DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)

#define	DAC_INTENSET_UNDERRUN1_Pos 1
	(DAC_INTENSET) Underrun 1 Interrupt Enable

#define	DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)

#define	DAC_INTENSET_UNDERRUN_Pos 0
	(DAC_INTENSET) Underrun x Interrupt Enable

#define	DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)

#define	DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))

#define	DAC_INTENSET_EMPTY0_Pos 2
	(DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable

#define	DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)

#define	DAC_INTENSET_EMPTY1_Pos 3
	(DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable

#define	DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)

#define	DAC_INTENSET_EMPTY_Pos 2
	(DAC_INTENSET) Data Buffer x Empty Interrupt Enable

#define	DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)

#define	DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))

#define	DAC_INTENSET_RESRDY0_Pos 4
	(DAC_INTENSET) Result 0 Ready Interrupt Enable

#define	DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)

#define	DAC_INTENSET_RESRDY1_Pos 5
	(DAC_INTENSET) Result 1 Ready Interrupt Enable

#define	DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)

#define	DAC_INTENSET_RESRDY_Pos 4
	(DAC_INTENSET) Result x Ready Interrupt Enable

#define	DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)

#define	DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))

#define	DAC_INTENSET_OVERRUN0_Pos 6
	(DAC_INTENSET) Overrun 0 Interrupt Enable

#define	DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)

#define	DAC_INTENSET_OVERRUN1_Pos 7
	(DAC_INTENSET) Overrun 1 Interrupt Enable

#define	DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)

#define	DAC_INTENSET_OVERRUN_Pos 6
	(DAC_INTENSET) Overrun x Interrupt Enable

#define	DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)

#define	DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))

#define	DAC_INTENSET_MASK _U_(0xFF)
	(DAC_INTENSET) MASK Register

#define	DAC_INTFLAG_OFFSET 0x06
	(DAC_INTFLAG offset) Interrupt Flag Status and Clear

#define	DAC_INTFLAG_RESETVALUE _U_(0x00)
	(DAC_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	DAC_INTFLAG_UNDERRUN0_Pos 0
	(DAC_INTFLAG) Result 0 Underrun

#define	DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)

#define	DAC_INTFLAG_UNDERRUN1_Pos 1
	(DAC_INTFLAG) Result 1 Underrun

#define	DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)

#define	DAC_INTFLAG_UNDERRUN_Pos 0
	(DAC_INTFLAG) Result x Underrun

#define	DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)

#define	DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))

#define	DAC_INTFLAG_EMPTY0_Pos 2
	(DAC_INTFLAG) Data Buffer 0 Empty

#define	DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)

#define	DAC_INTFLAG_EMPTY1_Pos 3
	(DAC_INTFLAG) Data Buffer 1 Empty

#define	DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)

#define	DAC_INTFLAG_EMPTY_Pos 2
	(DAC_INTFLAG) Data Buffer x Empty

#define	DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)

#define	DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))

#define	DAC_INTFLAG_RESRDY0_Pos 4
	(DAC_INTFLAG) Result 0 Ready

#define	DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)

#define	DAC_INTFLAG_RESRDY1_Pos 5
	(DAC_INTFLAG) Result 1 Ready

#define	DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)

#define	DAC_INTFLAG_RESRDY_Pos 4
	(DAC_INTFLAG) Result x Ready

#define	DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)

#define	DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))

#define	DAC_INTFLAG_OVERRUN0_Pos 6
	(DAC_INTFLAG) Result 0 Overrun

#define	DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)

#define	DAC_INTFLAG_OVERRUN1_Pos 7
	(DAC_INTFLAG) Result 1 Overrun

#define	DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)

#define	DAC_INTFLAG_OVERRUN_Pos 6
	(DAC_INTFLAG) Result x Overrun

#define	DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)

#define	DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))

#define	DAC_INTFLAG_MASK _U_(0xFF)
	(DAC_INTFLAG) MASK Register

#define	DAC_STATUS_OFFSET 0x07
	(DAC_STATUS offset) Status

#define	DAC_STATUS_RESETVALUE _U_(0x00)
	(DAC_STATUS reset_value) Status

#define	DAC_STATUS_READY0_Pos 0
	(DAC_STATUS) DAC 0 Startup Ready

#define	DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)

#define	DAC_STATUS_READY1_Pos 1
	(DAC_STATUS) DAC 1 Startup Ready

#define	DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)

#define	DAC_STATUS_READY_Pos 0
	(DAC_STATUS) DAC x Startup Ready

#define	DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)

#define	DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))

#define	DAC_STATUS_EOC0_Pos 2
	(DAC_STATUS) DAC 0 End of Conversion

#define	DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)

#define	DAC_STATUS_EOC1_Pos 3
	(DAC_STATUS) DAC 1 End of Conversion

#define	DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)

#define	DAC_STATUS_EOC_Pos 2
	(DAC_STATUS) DAC x End of Conversion

#define	DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)

#define	DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))

#define	DAC_STATUS_MASK _U_(0x0F)
	(DAC_STATUS) MASK Register

#define	DAC_SYNCBUSY_OFFSET 0x08
	(DAC_SYNCBUSY offset) Synchronization Busy

#define	DAC_SYNCBUSY_RESETVALUE _U_(0x00000000)
	(DAC_SYNCBUSY reset_value) Synchronization Busy

#define	DAC_SYNCBUSY_SWRST_Pos 0
	(DAC_SYNCBUSY) Software Reset

#define	DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)

#define	DAC_SYNCBUSY_ENABLE_Pos 1
	(DAC_SYNCBUSY) DAC Enable Status

#define	DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)

#define	DAC_SYNCBUSY_DATA0_Pos 2
	(DAC_SYNCBUSY) Data DAC 0

#define	DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)

#define	DAC_SYNCBUSY_DATA1_Pos 3
	(DAC_SYNCBUSY) Data DAC 1

#define	DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)

#define	DAC_SYNCBUSY_DATA_Pos 2
	(DAC_SYNCBUSY) Data DAC x

#define	DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)

#define	DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))

#define	DAC_SYNCBUSY_DATABUF0_Pos 4
	(DAC_SYNCBUSY) Data Buffer DAC 0

#define	DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)

#define	DAC_SYNCBUSY_DATABUF1_Pos 5
	(DAC_SYNCBUSY) Data Buffer DAC 1

#define	DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)

#define	DAC_SYNCBUSY_DATABUF_Pos 4
	(DAC_SYNCBUSY) Data Buffer DAC x

#define	DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)

#define	DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))

#define	DAC_SYNCBUSY_MASK _U_(0x0000003F)
	(DAC_SYNCBUSY) MASK Register

#define	DAC_DACCTRL_OFFSET 0x0C
	(DAC_DACCTRL offset) DAC n Control

#define	DAC_DACCTRL_RESETVALUE _U_(0x0000)
	(DAC_DACCTRL reset_value) DAC n Control

#define	DAC_DACCTRL_LEFTADJ_Pos 0
	(DAC_DACCTRL) Left Adjusted Data

#define	DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)

#define	DAC_DACCTRL_ENABLE_Pos 1
	(DAC_DACCTRL) Enable DAC0

#define	DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)

#define	DAC_DACCTRL_CCTRL_Pos 2
	(DAC_DACCTRL) Current Control

#define	DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)

#define	DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))

#define	DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0)
	(DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS)

#define	DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1)
	(DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS)

#define	DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2)
	(DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS)

#define	DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)

#define	DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)

#define	DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)

#define	DAC_DACCTRL_FEXT_Pos 5
	(DAC_DACCTRL) Standalone Filter

#define	DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)

#define	DAC_DACCTRL_RUNSTDBY_Pos 6
	(DAC_DACCTRL) Run in Standby

#define	DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)

#define	DAC_DACCTRL_DITHER_Pos 7
	(DAC_DACCTRL) Dithering Mode

#define	DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)

#define	DAC_DACCTRL_REFRESH_Pos 8
	(DAC_DACCTRL) Refresh period

#define	DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)

#define	DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))

#define	DAC_DACCTRL_OSR_Pos 13
	(DAC_DACCTRL) Sampling Rate

#define	DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)

#define	DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))

#define	DAC_DACCTRL_MASK _U_(0xEFEF)
	(DAC_DACCTRL) MASK Register

#define	DAC_DATA_OFFSET 0x10
	(DAC_DATA offset) DAC n Data

#define	DAC_DATA_RESETVALUE _U_(0x0000)
	(DAC_DATA reset_value) DAC n Data

#define	DAC_DATA_DATA_Pos 0
	(DAC_DATA) DAC0 Data

#define	DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)

#define	DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))

#define	DAC_DATA_MASK _U_(0xFFFF)
	(DAC_DATA) MASK Register

#define	DAC_DATABUF_OFFSET 0x14
	(DAC_DATABUF offset) DAC n Data Buffer

#define	DAC_DATABUF_RESETVALUE _U_(0x0000)
	(DAC_DATABUF reset_value) DAC n Data Buffer

#define	DAC_DATABUF_DATABUF_Pos 0
	(DAC_DATABUF) DAC0 Data Buffer

#define	DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)

#define	DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))

#define	DAC_DATABUF_MASK _U_(0xFFFF)
	(DAC_DATABUF) MASK Register

#define	DAC_DBGCTRL_OFFSET 0x18
	(DAC_DBGCTRL offset) Debug Control

#define	DAC_DBGCTRL_RESETVALUE _U_(0x00)
	(DAC_DBGCTRL reset_value) Debug Control

#define	DAC_DBGCTRL_DBGRUN_Pos 0
	(DAC_DBGCTRL) Debug Run

#define	DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)

#define	DAC_DBGCTRL_MASK _U_(0x01)
	(DAC_DBGCTRL) MASK Register

#define	DAC_RESULT_OFFSET 0x1C
	(DAC_RESULT offset) Filter Result

#define	DAC_RESULT_RESETVALUE _U_(0x0000)
	(DAC_RESULT reset_value) Filter Result

#define	DAC_RESULT_RESULT_Pos 0
	(DAC_RESULT) Filter Result

#define	DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)

#define	DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))

#define	DAC_RESULT_MASK _U_(0xFFFF)
	(DAC_RESULT) MASK Register

Detailed Description

Component description for DAC.

\asf_license_start

Definition in file dac.h.

Data Structures

Macros

Detailed Description