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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Dac Struct Reference</div> </div>
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<p>DAC hardware registers.
<a href="structDac.html#details">More...</a></p>
<p><code>#include <<a class="el" href="component_2dac_8h_source.html">dac.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ae64d3013c578889b3bc5bc9f0cfda66e"><td class="memItemLeft" align="right" valign="top"><a id="ae64d3013c578889b3bc5bc9f0cfda66e"></a>
__IO <a class="el" href="unionDAC__CTRLA__Type.html">DAC_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#ae64d3013c578889b3bc5bc9f0cfda66e">CTRLA</a></td></tr>
<tr class="memdesc:ae64d3013c578889b3bc5bc9f0cfda66e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 8) Control A. <br /></td></tr>
<tr class="separator:ae64d3013c578889b3bc5bc9f0cfda66e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a36fa8a7f785454c1af6d1bd41caa8e7a"><td class="memItemLeft" align="right" valign="top"><a id="a36fa8a7f785454c1af6d1bd41caa8e7a"></a>
__IO <a class="el" href="unionDAC__CTRLB__Type.html">DAC_CTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a36fa8a7f785454c1af6d1bd41caa8e7a">CTRLB</a></td></tr>
<tr class="memdesc:a36fa8a7f785454c1af6d1bd41caa8e7a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01 (R/W 8) Control B. <br /></td></tr>
<tr class="separator:a36fa8a7f785454c1af6d1bd41caa8e7a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae32cabe063f42303d39b109034781a8c"><td class="memItemLeft" align="right" valign="top"><a id="ae32cabe063f42303d39b109034781a8c"></a>
__IO <a class="el" href="unionDAC__EVCTRL__Type.html">DAC_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#ae32cabe063f42303d39b109034781a8c">EVCTRL</a></td></tr>
<tr class="memdesc:ae32cabe063f42303d39b109034781a8c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02 (R/W 8) Event Control. <br /></td></tr>
<tr class="separator:ae32cabe063f42303d39b109034781a8c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad855dcabdcbeadc273ffdd02356aeca6"><td class="memItemLeft" align="right" valign="top"><a id="ad855dcabdcbeadc273ffdd02356aeca6"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x1]</td></tr>
<tr class="separator:ad855dcabdcbeadc273ffdd02356aeca6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a02bfbb17949d48af6df846837a977723"><td class="memItemLeft" align="right" valign="top"><a id="a02bfbb17949d48af6df846837a977723"></a>
__IO <a class="el" href="unionDAC__INTENCLR__Type.html">DAC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a02bfbb17949d48af6df846837a977723">INTENCLR</a></td></tr>
<tr class="memdesc:a02bfbb17949d48af6df846837a977723"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Interrupt Enable Clear. <br /></td></tr>
<tr class="separator:a02bfbb17949d48af6df846837a977723"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6a92c98c095897a17be5869798d408f5"><td class="memItemLeft" align="right" valign="top"><a id="a6a92c98c095897a17be5869798d408f5"></a>
__IO <a class="el" href="unionDAC__INTENSET__Type.html">DAC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a6a92c98c095897a17be5869798d408f5">INTENSET</a></td></tr>
<tr class="memdesc:a6a92c98c095897a17be5869798d408f5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05 (R/W 8) Interrupt Enable Set. <br /></td></tr>
<tr class="separator:a6a92c98c095897a17be5869798d408f5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aeafbfa143f0c3c637251a76946396ea9"><td class="memItemLeft" align="right" valign="top"><a id="aeafbfa143f0c3c637251a76946396ea9"></a>
__IO <a class="el" href="unionDAC__INTFLAG__Type.html">DAC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#aeafbfa143f0c3c637251a76946396ea9">INTFLAG</a></td></tr>
<tr class="memdesc:aeafbfa143f0c3c637251a76946396ea9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear. <br /></td></tr>
<tr class="separator:aeafbfa143f0c3c637251a76946396ea9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0d0a06cbd41a340403915871fe2c2188"><td class="memItemLeft" align="right" valign="top"><a id="a0d0a06cbd41a340403915871fe2c2188"></a>
__I <a class="el" href="unionDAC__STATUS__Type.html">DAC_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a0d0a06cbd41a340403915871fe2c2188">STATUS</a></td></tr>
<tr class="memdesc:a0d0a06cbd41a340403915871fe2c2188"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x07 (R/ 8) Status. <br /></td></tr>
<tr class="separator:a0d0a06cbd41a340403915871fe2c2188"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a313da4a56adf63066a0ba2e42248ae17"><td class="memItemLeft" align="right" valign="top"><a id="a313da4a56adf63066a0ba2e42248ae17"></a>
__I <a class="el" href="unionDAC__SYNCBUSY__Type.html">DAC_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a313da4a56adf63066a0ba2e42248ae17">SYNCBUSY</a></td></tr>
<tr class="memdesc:a313da4a56adf63066a0ba2e42248ae17"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/ 32) Synchronization Busy. <br /></td></tr>
<tr class="separator:a313da4a56adf63066a0ba2e42248ae17"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4dd6fe47e9f0503ade8cef7d154c9490"><td class="memItemLeft" align="right" valign="top"><a id="a4dd6fe47e9f0503ade8cef7d154c9490"></a>
__IO <a class="el" href="unionDAC__DACCTRL__Type.html">DAC_DACCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a4dd6fe47e9f0503ade8cef7d154c9490">DACCTRL</a> [2]</td></tr>
<tr class="memdesc:a4dd6fe47e9f0503ade8cef7d154c9490"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 16) DAC n Control. <br /></td></tr>
<tr class="separator:a4dd6fe47e9f0503ade8cef7d154c9490"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a35c02595c7c67921e41a0d6d78cfe39e"><td class="memItemLeft" align="right" valign="top"><a id="a35c02595c7c67921e41a0d6d78cfe39e"></a>
__O <a class="el" href="unionDAC__DATA__Type.html">DAC_DATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a35c02595c7c67921e41a0d6d78cfe39e">DATA</a> [2]</td></tr>
<tr class="memdesc:a35c02595c7c67921e41a0d6d78cfe39e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 ( /W 16) DAC n Data. <br /></td></tr>
<tr class="separator:a35c02595c7c67921e41a0d6d78cfe39e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a89b7cbc57ffaf876555e80d25a4b1d72"><td class="memItemLeft" align="right" valign="top"><a id="a89b7cbc57ffaf876555e80d25a4b1d72"></a>
__O <a class="el" href="unionDAC__DATABUF__Type.html">DAC_DATABUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a89b7cbc57ffaf876555e80d25a4b1d72">DATABUF</a> [2]</td></tr>
<tr class="memdesc:a89b7cbc57ffaf876555e80d25a4b1d72"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 ( /W 16) DAC n Data Buffer. <br /></td></tr>
<tr class="separator:a89b7cbc57ffaf876555e80d25a4b1d72"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a41d3f7de223368a4dd5d60ed5370947a"><td class="memItemLeft" align="right" valign="top"><a id="a41d3f7de223368a4dd5d60ed5370947a"></a>
__IO <a class="el" href="unionDAC__DBGCTRL__Type.html">DAC_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#a41d3f7de223368a4dd5d60ed5370947a">DBGCTRL</a></td></tr>
<tr class="memdesc:a41d3f7de223368a4dd5d60ed5370947a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 8) Debug Control. <br /></td></tr>
<tr class="separator:a41d3f7de223368a4dd5d60ed5370947a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab662bf02f45b1cd8c57a5dc23bbc78eb"><td class="memItemLeft" align="right" valign="top"><a id="ab662bf02f45b1cd8c57a5dc23bbc78eb"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x3]</td></tr>
<tr class="separator:ab662bf02f45b1cd8c57a5dc23bbc78eb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad8fa64e973fb5bcd3907233e39aac97f"><td class="memItemLeft" align="right" valign="top"><a id="ad8fa64e973fb5bcd3907233e39aac97f"></a>
__I <a class="el" href="unionDAC__RESULT__Type.html">DAC_RESULT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDac.html#ad8fa64e973fb5bcd3907233e39aac97f">RESULT</a> [2]</td></tr>
<tr class="memdesc:ad8fa64e973fb5bcd3907233e39aac97f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/ 16) Filter Result. <br /></td></tr>
<tr class="separator:ad8fa64e973fb5bcd3907233e39aac97f"><td class="memSeparator" colspan="2"> </td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>DAC hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2dac_8h_source.html#l00523">523</a> of file <a class="el" href="component_2dac_8h_source.html">dac.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2dac_8h_source.html">dac.h</a></li>
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