SAME54P20A Test Project
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Header file for SAME54N20A. More...
#include <stdint.h>
#include <core_cm4.h>
#include "system_same54.h"
#include "component/ac.h"
#include "component/adc.h"
#include "component/aes.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/cmcc.h"
#include "component/dac.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/gmac.h"
#include "component/hmatrixb.h"
#include "component/icm.h"
#include "component/i2s.h"
#include "component/mclk.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pcc.h"
#include "component/pdec.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/qspi.h"
#include "component/ramecc.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdhc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/trng.h"
#include "component/usb.h"
#include "component/wdt.h"
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/aes.h"
#include "instance/can0.h"
#include "instance/can1.h"
#include "instance/ccl.h"
#include "instance/cmcc.h"
#include "instance/dac.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/gmac.h"
#include "instance/hmatrix.h"
#include "instance/icm.h"
#include "instance/i2s.h"
#include "instance/mclk.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pcc.h"
#include "instance/pdec.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/pukcc.h"
#include "instance/qspi.h"
#include "instance/ramecc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdhc0.h"
#include "instance/sdhc1.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/sercom4.h"
#include "instance/sercom5.h"
#include "instance/sercom6.h"
#include "instance/sercom7.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tc5.h"
#include "instance/tc6.h"
#include "instance/tc7.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tcc3.h"
#include "instance/tcc4.h"
#include "instance/trng.h"
#include "instance/usb.h"
#include "instance/wdt.h"
#include "pio/same54n20a.h"
Go to the source code of this file.
Data Structures | |
struct | _DeviceVectors |
Macros | |
#define | _U_(x) x ## U |
#define | _L_(x) x ## L |
#define | _UL_(x) x ## UL |
#define | __CM4_REV 1 |
#define | __DEBUG_LVL 3 |
#define | __FPU_PRESENT 1 |
#define | __MPU_PRESENT 1 |
#define | __NVIC_PRIO_BITS 3 |
#define | __TRACE_LVL 2 |
#define | __VTOR_PRESENT 1 |
#define | __Vendor_SysTickConfig 0 |
#define | ID_PAC 0 |
Peripheral Access Controller (PAC) | |
#define | ID_PM 1 |
Power Manager (PM) | |
#define | ID_MCLK 2 |
Main Clock (MCLK) | |
#define | ID_RSTC 3 |
Reset Controller (RSTC) | |
#define | ID_OSCCTRL 4 |
Oscillators Control (OSCCTRL) | |
#define | ID_OSC32KCTRL 5 |
32kHz Oscillators Control (OSC32KCTRL) | |
#define | ID_SUPC 6 |
Supply Controller (SUPC) | |
#define | ID_GCLK 7 |
Generic Clock Generator (GCLK) | |
#define | ID_WDT 8 |
Watchdog Timer (WDT) | |
#define | ID_RTC 9 |
Real-Time Counter (RTC) | |
#define | ID_EIC 10 |
External Interrupt Controller (EIC) | |
#define | ID_FREQM 11 |
Frequency Meter (FREQM) | |
#define | ID_SERCOM0 12 |
Serial Communication Interface 0 (SERCOM0) | |
#define | ID_SERCOM1 13 |
Serial Communication Interface 1 (SERCOM1) | |
#define | ID_TC0 14 |
Basic Timer Counter 0 (TC0) | |
#define | ID_TC1 15 |
Basic Timer Counter 1 (TC1) | |
#define | ID_USB 32 |
Universal Serial Bus (USB) | |
#define | ID_DSU 33 |
Device Service Unit (DSU) | |
#define | ID_NVMCTRL 34 |
Non-Volatile Memory Controller (NVMCTRL) | |
#define | ID_CMCC 35 |
Cortex M Cache Controller (CMCC) | |
#define | ID_PORT 36 |
Port Module (PORT) | |
#define | ID_DMAC 37 |
Direct Memory Access Controller (DMAC) | |
#define | ID_HMATRIX 38 |
HSB Matrix (HMATRIX) | |
#define | ID_EVSYS 39 |
Event System Interface (EVSYS) | |
#define | ID_SERCOM2 41 |
Serial Communication Interface 2 (SERCOM2) | |
#define | ID_SERCOM3 42 |
Serial Communication Interface 3 (SERCOM3) | |
#define | ID_TCC0 43 |
Timer Counter Control 0 (TCC0) | |
#define | ID_TCC1 44 |
Timer Counter Control 1 (TCC1) | |
#define | ID_TC2 45 |
Basic Timer Counter 2 (TC2) | |
#define | ID_TC3 46 |
Basic Timer Counter 3 (TC3) | |
#define | ID_RAMECC 48 |
RAM ECC (RAMECC) | |
#define | ID_CAN0 64 |
Control Area Network 0 (CAN0) | |
#define | ID_CAN1 65 |
Control Area Network 1 (CAN1) | |
#define | ID_GMAC 66 |
Ethernet MAC (GMAC) | |
#define | ID_TCC2 67 |
Timer Counter Control 2 (TCC2) | |
#define | ID_TCC3 68 |
Timer Counter Control 3 (TCC3) | |
#define | ID_TC4 69 |
Basic Timer Counter 4 (TC4) | |
#define | ID_TC5 70 |
Basic Timer Counter 5 (TC5) | |
#define | ID_PDEC 71 |
Quadrature Decodeur (PDEC) | |
#define | ID_AC 72 |
Analog Comparators (AC) | |
#define | ID_AES 73 |
Advanced Encryption Standard (AES) | |
#define | ID_TRNG 74 |
True Random Generator (TRNG) | |
#define | ID_ICM 75 |
Integrity Check Monitor (ICM) | |
#define | ID_PUKCC 76 |
PUblic-Key Cryptography Controller (PUKCC) | |
#define | ID_QSPI 77 |
Quad SPI interface (QSPI) | |
#define | ID_CCL 78 |
Configurable Custom Logic (CCL) | |
#define | ID_SERCOM4 96 |
Serial Communication Interface 4 (SERCOM4) | |
#define | ID_SERCOM5 97 |
Serial Communication Interface 5 (SERCOM5) | |
#define | ID_SERCOM6 98 |
Serial Communication Interface 6 (SERCOM6) | |
#define | ID_SERCOM7 99 |
Serial Communication Interface 7 (SERCOM7) | |
#define | ID_TCC4 100 |
Timer Counter Control 4 (TCC4) | |
#define | ID_TC6 101 |
Basic Timer Counter 6 (TC6) | |
#define | ID_TC7 102 |
Basic Timer Counter 7 (TC7) | |
#define | ID_ADC0 103 |
Analog Digital Converter 0 (ADC0) | |
#define | ID_ADC1 104 |
Analog Digital Converter 1 (ADC1) | |
#define | ID_DAC 105 |
Digital-to-Analog Converter (DAC) | |
#define | ID_I2S 106 |
Inter-IC Sound Interface (I2S) | |
#define | ID_PCC 107 |
Parallel Capture Controller (PCC) | |
#define | ID_SDHC0 128 |
SD/MMC Host Controller (SDHC0) | |
#define | ID_SDHC1 129 |
SD/MMC Host Controller (SDHC1) | |
#define | ID_PERIPH_COUNT 130 |
Max number of peripheral IDs. | |
#define | AC ((Ac *)0x42002000UL) |
(AC) APB Base Address | |
#define | AC_INST_NUM 1 |
(AC) Number of instances | |
#define | AC_INSTS { AC } |
(AC) Instances List | |
#define | ADC0 ((Adc *)0x43001C00UL) |
(ADC0) APB Base Address | |
#define | ADC1 ((Adc *)0x43002000UL) |
(ADC1) APB Base Address | |
#define | ADC_INST_NUM 2 |
(ADC) Number of instances | |
#define | ADC_INSTS { ADC0, ADC1 } |
(ADC) Instances List | |
#define | AES ((Aes *)0x42002400UL) |
(AES) APB Base Address | |
#define | AES_INST_NUM 1 |
(AES) Number of instances | |
#define | AES_INSTS { AES } |
(AES) Instances List | |
#define | CAN0 ((Can *)0x42000000UL) |
(CAN0) APB Base Address | |
#define | CAN1 ((Can *)0x42000400UL) |
(CAN1) APB Base Address | |
#define | CAN_INST_NUM 2 |
(CAN) Number of instances | |
#define | CAN_INSTS { CAN0, CAN1 } |
(CAN) Instances List | |
#define | CCL ((Ccl *)0x42003800UL) |
(CCL) APB Base Address | |
#define | CCL_INST_NUM 1 |
(CCL) Number of instances | |
#define | CCL_INSTS { CCL } |
(CCL) Instances List | |
#define | CMCC ((Cmcc *)0x41006000UL) |
(CMCC) APB Base Address | |
#define | CMCC_AHB (0x03000000UL) |
(CMCC) AHB Base Address | |
#define | CMCC_INST_NUM 1 |
(CMCC) Number of instances | |
#define | CMCC_INSTS { CMCC } |
(CMCC) Instances List | |
#define | DAC ((Dac *)0x43002400UL) |
(DAC) APB Base Address | |
#define | DAC_INST_NUM 1 |
(DAC) Number of instances | |
#define | DAC_INSTS { DAC } |
(DAC) Instances List | |
#define | DMAC ((Dmac *)0x4100A000UL) |
(DMAC) APB Base Address | |
#define | DMAC_INST_NUM 1 |
(DMAC) Number of instances | |
#define | DMAC_INSTS { DMAC } |
(DMAC) Instances List | |
#define | DSU ((Dsu *)0x41002000UL) |
(DSU) APB Base Address | |
#define | DSU_INST_NUM 1 |
(DSU) Number of instances | |
#define | DSU_INSTS { DSU } |
(DSU) Instances List | |
#define | EIC ((Eic *)0x40002800UL) |
(EIC) APB Base Address | |
#define | EIC_INST_NUM 1 |
(EIC) Number of instances | |
#define | EIC_INSTS { EIC } |
(EIC) Instances List | |
#define | EVSYS ((Evsys *)0x4100E000UL) |
(EVSYS) APB Base Address | |
#define | EVSYS_INST_NUM 1 |
(EVSYS) Number of instances | |
#define | EVSYS_INSTS { EVSYS } |
(EVSYS) Instances List | |
#define | FREQM ((Freqm *)0x40002C00UL) |
(FREQM) APB Base Address | |
#define | FREQM_INST_NUM 1 |
(FREQM) Number of instances | |
#define | FREQM_INSTS { FREQM } |
(FREQM) Instances List | |
#define | GCLK ((Gclk *)0x40001C00UL) |
(GCLK) APB Base Address | |
#define | GCLK_INST_NUM 1 |
(GCLK) Number of instances | |
#define | GCLK_INSTS { GCLK } |
(GCLK) Instances List | |
#define | GMAC ((Gmac *)0x42000800UL) |
(GMAC) APB Base Address | |
#define | GMAC_INST_NUM 1 |
(GMAC) Number of instances | |
#define | GMAC_INSTS { GMAC } |
(GMAC) Instances List | |
#define | HMATRIX ((Hmatrixb *)0x4100C000UL) |
(HMATRIX) APB Base Address | |
#define | HMATRIXB_INST_NUM 1 |
(HMATRIXB) Number of instances | |
#define | HMATRIXB_INSTS { HMATRIX } |
(HMATRIXB) Instances List | |
#define | ICM ((Icm *)0x42002C00UL) |
(ICM) APB Base Address | |
#define | ICM_INST_NUM 1 |
(ICM) Number of instances | |
#define | ICM_INSTS { ICM } |
(ICM) Instances List | |
#define | I2S ((I2s *)0x43002800UL) |
(I2S) APB Base Address | |
#define | I2S_INST_NUM 1 |
(I2S) Number of instances | |
#define | I2S_INSTS { I2S } |
(I2S) Instances List | |
#define | MCLK ((Mclk *)0x40000800UL) |
(MCLK) APB Base Address | |
#define | MCLK_INST_NUM 1 |
(MCLK) Number of instances | |
#define | MCLK_INSTS { MCLK } |
(MCLK) Instances List | |
#define | NVMCTRL ((Nvmctrl *)0x41004000UL) |
(NVMCTRL) APB Base Address | |
#define | NVMCTRL_SW0 (0x00800080UL) |
(NVMCTRL) SW0 Base Address | |
#define | NVMCTRL_TEMP_LOG (0x00800100UL) |
(NVMCTRL) TEMP_LOG Base Address | |
#define | NVMCTRL_USER (0x00804000UL) |
(NVMCTRL) USER Base Address | |
#define | NVMCTRL_INST_NUM 1 |
(NVMCTRL) Number of instances | |
#define | NVMCTRL_INSTS { NVMCTRL } |
(NVMCTRL) Instances List | |
#define | OSCCTRL ((Oscctrl *)0x40001000UL) |
(OSCCTRL) APB Base Address | |
#define | OSCCTRL_INST_NUM 1 |
(OSCCTRL) Number of instances | |
#define | OSCCTRL_INSTS { OSCCTRL } |
(OSCCTRL) Instances List | |
#define | OSC32KCTRL ((Osc32kctrl *)0x40001400UL) |
(OSC32KCTRL) APB Base Address | |
#define | OSC32KCTRL_INST_NUM 1 |
(OSC32KCTRL) Number of instances | |
#define | OSC32KCTRL_INSTS { OSC32KCTRL } |
(OSC32KCTRL) Instances List | |
#define | PAC ((Pac *)0x40000000UL) |
(PAC) APB Base Address | |
#define | PAC_INST_NUM 1 |
(PAC) Number of instances | |
#define | PAC_INSTS { PAC } |
(PAC) Instances List | |
#define | PCC ((Pcc *)0x43002C00UL) |
(PCC) APB Base Address | |
#define | PCC_INST_NUM 1 |
(PCC) Number of instances | |
#define | PCC_INSTS { PCC } |
(PCC) Instances List | |
#define | PDEC ((Pdec *)0x42001C00UL) |
(PDEC) APB Base Address | |
#define | PDEC_INST_NUM 1 |
(PDEC) Number of instances | |
#define | PDEC_INSTS { PDEC } |
(PDEC) Instances List | |
#define | PM ((Pm *)0x40000400UL) |
(PM) APB Base Address | |
#define | PM_INST_NUM 1 |
(PM) Number of instances | |
#define | PM_INSTS { PM } |
(PM) Instances List | |
#define | PORT ((Port *)0x41008000UL) |
(PORT) APB Base Address | |
#define | PORT_INST_NUM 1 |
(PORT) Number of instances | |
#define | PORT_INSTS { PORT } |
(PORT) Instances List | |
#define | PUKCC ((void *)0x42003000UL) |
(PUKCC) APB Base Address | |
#define | PUKCC_AHB ((void *)0x02000000UL) |
(PUKCC) AHB Base Address | |
#define | PUKCC_INST_NUM 1 |
(PUKCC) Number of instances | |
#define | PUKCC_INSTS { PUKCC } |
(PUKCC) Instances List | |
#define | QSPI ((Qspi *)0x42003400UL) |
(QSPI) APB Base Address | |
#define | QSPI_AHB (0x04000000UL) |
(QSPI) AHB Base Address | |
#define | QSPI_INST_NUM 1 |
(QSPI) Number of instances | |
#define | QSPI_INSTS { QSPI } |
(QSPI) Instances List | |
#define | RAMECC ((Ramecc *)0x41020000UL) |
(RAMECC) APB Base Address | |
#define | RAMECC_INST_NUM 1 |
(RAMECC) Number of instances | |
#define | RAMECC_INSTS { RAMECC } |
(RAMECC) Instances List | |
#define | RSTC ((Rstc *)0x40000C00UL) |
(RSTC) APB Base Address | |
#define | RSTC_INST_NUM 1 |
(RSTC) Number of instances | |
#define | RSTC_INSTS { RSTC } |
(RSTC) Instances List | |
#define | RTC ((Rtc *)0x40002400UL) |
(RTC) APB Base Address | |
#define | RTC_INST_NUM 1 |
(RTC) Number of instances | |
#define | RTC_INSTS { RTC } |
(RTC) Instances List | |
#define | SDHC0 ((Sdhc *)0x45000000UL) |
(SDHC0) AHB Base Address | |
#define | SDHC1 ((Sdhc *)0x46000000UL) |
(SDHC1) AHB Base Address | |
#define | SDHC_INST_NUM 2 |
(SDHC) Number of instances | |
#define | SDHC_INSTS { SDHC0, SDHC1 } |
(SDHC) Instances List | |
#define | SERCOM0 ((Sercom *)0x40003000UL) |
(SERCOM0) APB Base Address | |
#define | SERCOM1 ((Sercom *)0x40003400UL) |
(SERCOM1) APB Base Address | |
#define | SERCOM2 ((Sercom *)0x41012000UL) |
(SERCOM2) APB Base Address | |
#define | SERCOM3 ((Sercom *)0x41014000UL) |
(SERCOM3) APB Base Address | |
#define | SERCOM4 ((Sercom *)0x43000000UL) |
(SERCOM4) APB Base Address | |
#define | SERCOM5 ((Sercom *)0x43000400UL) |
(SERCOM5) APB Base Address | |
#define | SERCOM6 ((Sercom *)0x43000800UL) |
(SERCOM6) APB Base Address | |
#define | SERCOM7 ((Sercom *)0x43000C00UL) |
(SERCOM7) APB Base Address | |
#define | SERCOM_INST_NUM 8 |
(SERCOM) Number of instances | |
#define | SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } |
(SERCOM) Instances List | |
#define | SUPC ((Supc *)0x40001800UL) |
(SUPC) APB Base Address | |
#define | SUPC_INST_NUM 1 |
(SUPC) Number of instances | |
#define | SUPC_INSTS { SUPC } |
(SUPC) Instances List | |
#define | TC0 ((Tc *)0x40003800UL) |
(TC0) APB Base Address | |
#define | TC1 ((Tc *)0x40003C00UL) |
(TC1) APB Base Address | |
#define | TC2 ((Tc *)0x4101A000UL) |
(TC2) APB Base Address | |
#define | TC3 ((Tc *)0x4101C000UL) |
(TC3) APB Base Address | |
#define | TC4 ((Tc *)0x42001400UL) |
(TC4) APB Base Address | |
#define | TC5 ((Tc *)0x42001800UL) |
(TC5) APB Base Address | |
#define | TC6 ((Tc *)0x43001400UL) |
(TC6) APB Base Address | |
#define | TC7 ((Tc *)0x43001800UL) |
(TC7) APB Base Address | |
#define | TC_INST_NUM 8 |
(TC) Number of instances | |
#define | TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } |
(TC) Instances List | |
#define | TCC0 ((Tcc *)0x41016000UL) |
(TCC0) APB Base Address | |
#define | TCC1 ((Tcc *)0x41018000UL) |
(TCC1) APB Base Address | |
#define | TCC2 ((Tcc *)0x42000C00UL) |
(TCC2) APB Base Address | |
#define | TCC3 ((Tcc *)0x42001000UL) |
(TCC3) APB Base Address | |
#define | TCC4 ((Tcc *)0x43001000UL) |
(TCC4) APB Base Address | |
#define | TCC_INST_NUM 5 |
(TCC) Number of instances | |
#define | TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } |
(TCC) Instances List | |
#define | TRNG ((Trng *)0x42002800UL) |
(TRNG) APB Base Address | |
#define | TRNG_INST_NUM 1 |
(TRNG) Number of instances | |
#define | TRNG_INSTS { TRNG } |
(TRNG) Instances List | |
#define | USB ((Usb *)0x41000000UL) |
(USB) APB Base Address | |
#define | USB_INST_NUM 1 |
(USB) Number of instances | |
#define | USB_INSTS { USB } |
(USB) Instances List | |
#define | WDT ((Wdt *)0x40002000UL) |
(WDT) APB Base Address | |
#define | WDT_INST_NUM 1 |
(WDT) Number of instances | |
#define | WDT_INSTS { WDT } |
(WDT) Instances List | |
#define | HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ |
#define | FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ |
#define | FLASH_PAGE_SIZE 512 |
#define | FLASH_NB_OF_PAGES 2048 |
#define | FLASH_USER_PAGE_SIZE 512 |
#define | BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ |
#define | QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ |
#define | FLASH_ADDR _UL_(0x00000000) |
#define | CMCC_DATARAM_ADDR _UL_(0x03000000) |
#define | CMCC_DATARAM_SIZE _UL_(0x00001000) |
#define | CMCC_TAGRAM_ADDR _UL_(0x03001000) |
#define | CMCC_TAGRAM_SIZE _UL_(0x00000400) |
#define | CMCC_VALIDRAM_ADDR _UL_(0x03002000) |
#define | CMCC_VALIDRAM_SIZE _UL_(0x00000040) |
#define | HSRAM_ADDR _UL_(0x20000000) |
#define | HSRAM_ETB_ADDR _UL_(0x20000000) |
#define | HSRAM_ETB_SIZE _UL_(0x00008000) |
#define | HSRAM_RET1_ADDR _UL_(0x20000000) |
#define | HSRAM_RET1_SIZE _UL_(0x00008000) |
#define | HPB0_ADDR _UL_(0x40000000) |
#define | HPB1_ADDR _UL_(0x41000000) |
#define | HPB2_ADDR _UL_(0x42000000) |
#define | HPB3_ADDR _UL_(0x43000000) |
#define | SEEPROM_ADDR _UL_(0x44000000) |
#define | BKUPRAM_ADDR _UL_(0x47000000) |
#define | PPB_ADDR _UL_(0xE0000000) |
#define | DSU_DID_RESETVALUE _UL_(0x61840302) |
#define | ADC0_TOUCH_LINES_NUM 32 |
#define | PORT_GROUPS 3 |
Typedefs | |
typedef volatile const uint32_t | RoReg |
typedef volatile const uint16_t | RoReg16 |
typedef volatile const uint8_t | RoReg8 |
typedef volatile uint32_t | WoReg |
typedef volatile uint16_t | WoReg16 |
typedef volatile uint8_t | WoReg8 |
typedef volatile uint32_t | RwReg |
typedef volatile uint16_t | RwReg16 |
typedef volatile uint8_t | RwReg8 |
typedef enum IRQn | IRQn_Type |
typedef struct _DeviceVectors | DeviceVectors |
Functions | |
void | Reset_Handler (void) |
This is the code that gets called on processor reset. To initialize the device, and call the main() routine. | |
void | NonMaskableInt_Handler (void) |
void | HardFault_Handler (void) |
void | MemManagement_Handler (void) |
void | BusFault_Handler (void) |
void | UsageFault_Handler (void) |
void | SVCall_Handler (void) |
void | DebugMonitor_Handler (void) |
void | PendSV_Handler (void) |
void | SysTick_Handler (void) |
void | PM_Handler (void) |
void | MCLK_Handler (void) |
void | OSCCTRL_0_Handler (void) |
void | OSCCTRL_1_Handler (void) |
void | OSCCTRL_2_Handler (void) |
void | OSCCTRL_3_Handler (void) |
void | OSCCTRL_4_Handler (void) |
void | OSC32KCTRL_Handler (void) |
void | SUPC_0_Handler (void) |
void | SUPC_1_Handler (void) |
void | WDT_Handler (void) |
void | RTC_Handler (void) |
void | EIC_0_Handler (void) |
void | EIC_1_Handler (void) |
void | EIC_2_Handler (void) |
void | EIC_3_Handler (void) |
void | EIC_4_Handler (void) |
void | EIC_5_Handler (void) |
void | EIC_6_Handler (void) |
void | EIC_7_Handler (void) |
void | EIC_8_Handler (void) |
void | EIC_9_Handler (void) |
void | EIC_10_Handler (void) |
void | EIC_11_Handler (void) |
void | EIC_12_Handler (void) |
void | EIC_13_Handler (void) |
void | EIC_14_Handler (void) |
void | EIC_15_Handler (void) |
void | FREQM_Handler (void) |
void | NVMCTRL_0_Handler (void) |
void | NVMCTRL_1_Handler (void) |
void | DMAC_0_Handler (void) |
void | DMAC_1_Handler (void) |
void | DMAC_2_Handler (void) |
void | DMAC_3_Handler (void) |
void | DMAC_4_Handler (void) |
void | EVSYS_0_Handler (void) |
void | EVSYS_1_Handler (void) |
void | EVSYS_2_Handler (void) |
void | EVSYS_3_Handler (void) |
void | EVSYS_4_Handler (void) |
void | PAC_Handler (void) |
void | RAMECC_Handler (void) |
void | SERCOM0_0_Handler (void) |
void | SERCOM0_1_Handler (void) |
void | SERCOM0_2_Handler (void) |
void | SERCOM0_3_Handler (void) |
void | SERCOM1_0_Handler (void) |
void | SERCOM1_1_Handler (void) |
void | SERCOM1_2_Handler (void) |
void | SERCOM1_3_Handler (void) |
void | SERCOM2_0_Handler (void) |
void | SERCOM2_1_Handler (void) |
void | SERCOM2_2_Handler (void) |
void | SERCOM2_3_Handler (void) |
void | SERCOM3_0_Handler (void) |
void | SERCOM3_1_Handler (void) |
void | SERCOM3_2_Handler (void) |
void | SERCOM3_3_Handler (void) |
void | SERCOM4_0_Handler (void) |
void | SERCOM4_1_Handler (void) |
void | SERCOM4_2_Handler (void) |
void | SERCOM4_3_Handler (void) |
void | SERCOM5_0_Handler (void) |
void | SERCOM5_1_Handler (void) |
void | SERCOM5_2_Handler (void) |
void | SERCOM5_3_Handler (void) |
void | SERCOM6_0_Handler (void) |
void | SERCOM6_1_Handler (void) |
void | SERCOM6_2_Handler (void) |
void | SERCOM6_3_Handler (void) |
void | SERCOM7_0_Handler (void) |
void | SERCOM7_1_Handler (void) |
void | SERCOM7_2_Handler (void) |
void | SERCOM7_3_Handler (void) |
void | CAN0_Handler (void) |
void | CAN1_Handler (void) |
void | USB_0_Handler (void) |
void | USB_1_Handler (void) |
void | USB_2_Handler (void) |
void | USB_3_Handler (void) |
void | GMAC_Handler (void) |
void | TCC0_0_Handler (void) |
void | TCC0_1_Handler (void) |
void | TCC0_2_Handler (void) |
void | TCC0_3_Handler (void) |
void | TCC0_4_Handler (void) |
void | TCC0_5_Handler (void) |
void | TCC0_6_Handler (void) |
void | TCC1_0_Handler (void) |
void | TCC1_1_Handler (void) |
void | TCC1_2_Handler (void) |
void | TCC1_3_Handler (void) |
void | TCC1_4_Handler (void) |
void | TCC2_0_Handler (void) |
void | TCC2_1_Handler (void) |
void | TCC2_2_Handler (void) |
void | TCC2_3_Handler (void) |
void | TCC3_0_Handler (void) |
void | TCC3_1_Handler (void) |
void | TCC3_2_Handler (void) |
void | TCC4_0_Handler (void) |
void | TCC4_1_Handler (void) |
void | TCC4_2_Handler (void) |
void | TC0_Handler (void) |
void | TC1_Handler (void) |
void | TC2_Handler (void) |
void | TC3_Handler (void) |
void | TC4_Handler (void) |
void | TC5_Handler (void) |
void | TC6_Handler (void) |
void | TC7_Handler (void) |
void | PDEC_0_Handler (void) |
void | PDEC_1_Handler (void) |
void | PDEC_2_Handler (void) |
void | ADC0_0_Handler (void) |
void | ADC0_1_Handler (void) |
void | ADC1_0_Handler (void) |
void | ADC1_1_Handler (void) |
void | AC_Handler (void) |
void | DAC_0_Handler (void) |
void | DAC_1_Handler (void) |
void | DAC_2_Handler (void) |
void | DAC_3_Handler (void) |
void | DAC_4_Handler (void) |
void | I2S_Handler (void) |
void | PCC_Handler (void) |
void | AES_Handler (void) |
void | TRNG_Handler (void) |
void | ICM_Handler (void) |
void | PUKCC_Handler (void) |
void | QSPI_Handler (void) |
void | SDHC0_Handler (void) |
void | SDHC1_Handler (void) |
Header file for SAME54N20A.
Copyright (c) 2019 Microchip Technology Inc.
\asf_license_start
Definition in file same54n20a.h.
#define __CM4_REV 1 |
Core revision r0p1
Definition at line 556 of file same54n20a.h.
#define __DEBUG_LVL 3 |
Full debug plus DWT data matching
Definition at line 557 of file same54n20a.h.
#define __FPU_PRESENT 1 |
FPU present or not
Definition at line 558 of file same54n20a.h.
#define __MPU_PRESENT 1 |
MPU present or not
Definition at line 559 of file same54n20a.h.
#define __NVIC_PRIO_BITS 3 |
Number of bits used for Priority Levels
Definition at line 560 of file same54n20a.h.
#define __TRACE_LVL 2 |
Full trace: ITM, DWT triggers and counters, ETM
Definition at line 561 of file same54n20a.h.
#define __Vendor_SysTickConfig 0 |
Set to 1 if different SysTick Config is used
Definition at line 563 of file same54n20a.h.
#define __VTOR_PRESENT 1 |
VTOR present or not
Definition at line 562 of file same54n20a.h.
#define _L_ | ( | x | ) | x ## L |
C code: Long integer literal constant value
Definition at line 75 of file same54n20a.h.
#define _U_ | ( | x | ) | x ## U |
C code: Unsigned integer literal constant value
Definition at line 74 of file same54n20a.h.
#define _UL_ | ( | x | ) | x ## UL |
C code: Unsigned Long integer literal constant value
Definition at line 76 of file same54n20a.h.
#define BKUPRAM_ADDR _UL_(0x47000000) |
BKUPRAM base address
Definition at line 1067 of file same54n20a.h.
#define CMCC_DATARAM_ADDR _UL_(0x03000000) |
CMCC_DATARAM base address
Definition at line 1051 of file same54n20a.h.
#define CMCC_DATARAM_SIZE _UL_(0x00001000) |
CMCC_DATARAM size
Definition at line 1052 of file same54n20a.h.
#define CMCC_TAGRAM_ADDR _UL_(0x03001000) |
CMCC_TAGRAM base address
Definition at line 1053 of file same54n20a.h.
#define CMCC_TAGRAM_SIZE _UL_(0x00000400) |
CMCC_TAGRAM size
Definition at line 1054 of file same54n20a.h.
#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) |
CMCC_VALIDRAM base address
Definition at line 1055 of file same54n20a.h.
#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) |
CMCC_VALIDRAM size
Definition at line 1056 of file same54n20a.h.
#define FLASH_ADDR _UL_(0x00000000) |
FLASH base address
Definition at line 1050 of file same54n20a.h.
#define HPB0_ADDR _UL_(0x40000000) |
HPB0 base address
Definition at line 1062 of file same54n20a.h.
#define HPB1_ADDR _UL_(0x41000000) |
HPB1 base address
Definition at line 1063 of file same54n20a.h.
#define HPB2_ADDR _UL_(0x42000000) |
HPB2 base address
Definition at line 1064 of file same54n20a.h.
#define HPB3_ADDR _UL_(0x43000000) |
HPB3 base address
Definition at line 1065 of file same54n20a.h.
#define HSRAM_ADDR _UL_(0x20000000) |
HSRAM base address
Definition at line 1057 of file same54n20a.h.
#define HSRAM_ETB_ADDR _UL_(0x20000000) |
HSRAM_ETB base address
Definition at line 1058 of file same54n20a.h.
#define HSRAM_ETB_SIZE _UL_(0x00008000) |
HSRAM_ETB size
Definition at line 1059 of file same54n20a.h.
#define HSRAM_RET1_ADDR _UL_(0x20000000) |
HSRAM_RET1 base address
Definition at line 1060 of file same54n20a.h.
#define HSRAM_RET1_SIZE _UL_(0x00008000) |
HSRAM_RET1 size
Definition at line 1061 of file same54n20a.h.
#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ |
MEMORY MAPPING DEFINITIONS FOR SAME54N20A
Definition at line 1042 of file same54n20a.h.
#define PPB_ADDR _UL_(0xE0000000) |
PPB base address
Definition at line 1068 of file same54n20a.h.
#define SEEPROM_ADDR _UL_(0x44000000) |
SEEPROM base address
Definition at line 1066 of file same54n20a.h.
typedef volatile const uint32_t RoReg |
Read only 32-bit register (volatile const unsigned int)
Definition at line 51 of file same54n20a.h.
typedef volatile const uint16_t RoReg16 |
Read only 16-bit register (volatile const unsigned int)
Definition at line 52 of file same54n20a.h.
typedef volatile const uint8_t RoReg8 |
Read only 8-bit register (volatile const unsigned int)
Definition at line 53 of file same54n20a.h.
typedef volatile uint32_t RwReg |
Read-Write 32-bit register (volatile unsigned int)
Definition at line 62 of file same54n20a.h.
typedef volatile uint16_t RwReg16 |
Read-Write 16-bit register (volatile unsigned int)
Definition at line 63 of file same54n20a.h.
typedef volatile uint8_t RwReg8 |
Read-Write 8-bit register (volatile unsigned int)
Definition at line 64 of file same54n20a.h.
typedef volatile uint32_t WoReg |
Write only 32-bit register (volatile unsigned int)
Definition at line 59 of file same54n20a.h.
typedef volatile uint16_t WoReg16 |
Write only 16-bit register (volatile unsigned int)
Definition at line 60 of file same54n20a.h.
typedef volatile uint8_t WoReg8 |
Write only 8-bit register (volatile unsigned int)
Definition at line 61 of file same54n20a.h.
enum IRQn |
Interrupt Number Definition
Definition at line 91 of file same54n20a.h.