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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tc4.h</div> </div>
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<a href="tc4_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TC4_INSTANCE_</span></div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TC4_INSTANCE_</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TC4 peripheral ========== */</span></div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TC4_CTRLA (0x42001400) </span></div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TC4_CTRLBCLR (0x42001404) </span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TC4_CTRLBSET (0x42001405) </span></div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TC4_EVCTRL (0x42001406) </span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TC4_INTENCLR (0x42001408) </span></div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TC4_INTENSET (0x42001409) </span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TC4_INTFLAG (0x4200140A) </span></div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TC4_STATUS (0x4200140B) </span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TC4_WAVE (0x4200140C) </span></div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TC4_DRVCTRL (0x4200140D) </span></div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TC4_DBGCTRL (0x4200140F) </span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TC4_SYNCBUSY (0x42001410) </span></div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TC4_COUNT16_COUNT (0x42001414) </span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TC4_COUNT16_CC0 (0x4200141C) </span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TC4_COUNT16_CC1 (0x4200141E) </span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TC4_COUNT16_CCBUF0 (0x42001430) </span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TC4_COUNT16_CCBUF1 (0x42001432) </span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TC4_COUNT32_COUNT (0x42001414) </span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TC4_COUNT32_CC0 (0x4200141C) </span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TC4_COUNT32_CC1 (0x42001420) </span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TC4_COUNT32_CCBUF0 (0x42001430) </span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TC4_COUNT32_CCBUF1 (0x42001434) </span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TC4_COUNT8_COUNT (0x42001414) </span></div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TC4_COUNT8_PER (0x4200141B) </span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TC4_COUNT8_CC0 (0x4200141C) </span></div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TC4_COUNT8_CC1 (0x4200141D) </span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TC4_COUNT8_PERBUF (0x4200142F) </span></div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TC4_COUNT8_CCBUF0 (0x42001430) </span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_TC4_COUNT8_CCBUF1 (0x42001431) </span></div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tc4_8h.html#aeb2ed74f8a2ebe4ce05c145f57b5a45a"> 65</a></span> <span class="preprocessor">#define REG_TC4_CTRLA (*(RwReg *)0x42001400UL) </span></div>
<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tc4_8h.html#a09057ff1fc6bbdf2ef3463d73f155659"> 66</a></span> <span class="preprocessor">#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42001404UL) </span></div>
<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tc4_8h.html#abb2bf637ab6784861bbccd5f5301136a"> 67</a></span> <span class="preprocessor">#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42001405UL) </span></div>
<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tc4_8h.html#a61fb8f2937cc13a511227fe2fa7afc99"> 68</a></span> <span class="preprocessor">#define REG_TC4_EVCTRL (*(RwReg16*)0x42001406UL) </span></div>
<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tc4_8h.html#a48ee902839144b17e521d7cbd6f850b5"> 69</a></span> <span class="preprocessor">#define REG_TC4_INTENCLR (*(RwReg8 *)0x42001408UL) </span></div>
<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tc4_8h.html#a194d2f57c7415ad7fb9591667d428bca"> 70</a></span> <span class="preprocessor">#define REG_TC4_INTENSET (*(RwReg8 *)0x42001409UL) </span></div>
<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tc4_8h.html#ade0fcb831a1eb8cebd9982961a0a06c6"> 71</a></span> <span class="preprocessor">#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200140AUL) </span></div>
<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tc4_8h.html#aabd96a26edc3a37b6ec5b93cf068f810"> 72</a></span> <span class="preprocessor">#define REG_TC4_STATUS (*(RwReg8 *)0x4200140BUL) </span></div>
<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tc4_8h.html#abc148dd802df4502ab0d7ec77b6b970e"> 73</a></span> <span class="preprocessor">#define REG_TC4_WAVE (*(RwReg8 *)0x4200140CUL) </span></div>
<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tc4_8h.html#ab9745a4efbc77c898d56d3922a93f7a7"> 74</a></span> <span class="preprocessor">#define REG_TC4_DRVCTRL (*(RwReg8 *)0x4200140DUL) </span></div>
<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tc4_8h.html#af4e1a0e36abf3f084dd9269a57519325"> 75</a></span> <span class="preprocessor">#define REG_TC4_DBGCTRL (*(RwReg8 *)0x4200140FUL) </span></div>
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tc4_8h.html#ad95357bd0d86c520d5845c033c8fe37b"> 76</a></span> <span class="preprocessor">#define REG_TC4_SYNCBUSY (*(RoReg *)0x42001410UL) </span></div>
<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tc4_8h.html#a2dc7994edac0cb1f7991b510eb0fd04e"> 77</a></span> <span class="preprocessor">#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42001414UL) </span></div>
<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tc4_8h.html#a2ed6cd8e548b63e9eed3bcf826b5a550"> 78</a></span> <span class="preprocessor">#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x4200141CUL) </span></div>
<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tc4_8h.html#aa8dd0b4c944b9c9ea0a4cee755144e26"> 79</a></span> <span class="preprocessor">#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200141EUL) </span></div>
<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tc4_8h.html#a1985f7cd0bb7c34dca89c0602b4bb0bd"> 80</a></span> <span class="preprocessor">#define REG_TC4_COUNT16_CCBUF0 (*(RwReg16*)0x42001430UL) </span></div>
<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tc4_8h.html#a2b8f9bf6835e8741f4492d4e39a21358"> 81</a></span> <span class="preprocessor">#define REG_TC4_COUNT16_CCBUF1 (*(RwReg16*)0x42001432UL) </span></div>
<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tc4_8h.html#a25777ad4f95b66dadc5d8b99649b8f60"> 82</a></span> <span class="preprocessor">#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42001414UL) </span></div>
<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tc4_8h.html#aed64c81c373cf527bd068cafa06a4f5f"> 83</a></span> <span class="preprocessor">#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x4200141CUL) </span></div>
<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tc4_8h.html#a0150fbd9f5ba7242037e98e887fe5441"> 84</a></span> <span class="preprocessor">#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x42001420UL) </span></div>
<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tc4_8h.html#a060dec0a51361463b21672b0af84a32d"> 85</a></span> <span class="preprocessor">#define REG_TC4_COUNT32_CCBUF0 (*(RwReg *)0x42001430UL) </span></div>
<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tc4_8h.html#a9cf5f326df25a89a0d1e916fde40fd1b"> 86</a></span> <span class="preprocessor">#define REG_TC4_COUNT32_CCBUF1 (*(RwReg *)0x42001434UL) </span></div>
<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tc4_8h.html#af96d6e554d369671d066be6614b1155e"> 87</a></span> <span class="preprocessor">#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42001414UL) </span></div>
<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tc4_8h.html#ac6a241b3fe2247fa35aa7cfa0be6e07e"> 88</a></span> <span class="preprocessor">#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x4200141BUL) </span></div>
<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tc4_8h.html#acd41910eb23c87470aedd2fb435c8a8d"> 89</a></span> <span class="preprocessor">#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x4200141CUL) </span></div>
<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tc4_8h.html#a149083f8edf0aaa3860ed31af76b3197"> 90</a></span> <span class="preprocessor">#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x4200141DUL) </span></div>
<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tc4_8h.html#a7321db0a6e0bf3d82abe56920bee1f13"> 91</a></span> <span class="preprocessor">#define REG_TC4_COUNT8_PERBUF (*(RwReg8 *)0x4200142FUL) </span></div>
<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="tc4_8h.html#a5261bb99664ccdb1b49b409f57bc705c"> 92</a></span> <span class="preprocessor">#define REG_TC4_COUNT8_CCBUF0 (*(RwReg8 *)0x42001430UL) </span></div>
<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="tc4_8h.html#a2f42ff2005fd67630a27660b9883d58f"> 93</a></span> <span class="preprocessor">#define REG_TC4_COUNT8_CCBUF1 (*(RwReg8 *)0x42001431UL) </span></div>
<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>  </div>
<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="comment">/* ========== Instance parameters for TC4 peripheral ========== */</span></div>
<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TC4_CC_NUM 2 </span></div>
<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define TC4_DMAC_ID_MC_0 57</span></div>
<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define TC4_DMAC_ID_MC_1 58</span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define TC4_DMAC_ID_MC_LSB 57</span></div>
<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define TC4_DMAC_ID_MC_MSB 58</span></div>
<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define TC4_DMAC_ID_MC_SIZE 2</span></div>
<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TC4_DMAC_ID_OVF 56 // Indexes of DMA Overflow trigger</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TC4_EXT 0 // Coding of implemented extended features (keep 0 value)</span></div>
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TC4_GCLK_ID 30 // Index of Generic Clock</span></div>
<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TC4_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave</span></div>
<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TC4_OW_NUM 2 // Number of Output Waveforms</span></div>
<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>  </div>
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TC4_INSTANCE_ */</span><span class="preprocessor"></span></div>
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