sdhc1.h File Reference

Instance description for SDHC1. More...

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Macros
#define	REG_SDHC1_SSAR   (*(RwReg *)0x46000000UL)
	(SDHC1) SDMA System Address / Argument 2
#define	REG_SDHC1_BSR   (*(RwReg16*)0x46000004UL)
	(SDHC1) Block Size
#define	REG_SDHC1_BCR   (*(RwReg16*)0x46000006UL)
	(SDHC1) Block Count
#define	REG_SDHC1_ARG1R   (*(RwReg *)0x46000008UL)
	(SDHC1) Argument 1
#define	REG_SDHC1_TMR   (*(RwReg16*)0x4600000CUL)
	(SDHC1) Transfer Mode
#define	REG_SDHC1_CR   (*(RwReg16*)0x4600000EUL)
	(SDHC1) Command
#define	REG_SDHC1_RR0   (*(RoReg *)0x46000010UL)
	(SDHC1) Response 0
#define	REG_SDHC1_RR1   (*(RoReg *)0x46000014UL)
	(SDHC1) Response 1
#define	REG_SDHC1_RR2   (*(RoReg *)0x46000018UL)
	(SDHC1) Response 2
#define	REG_SDHC1_RR3   (*(RoReg *)0x4600001CUL)
	(SDHC1) Response 3
#define	REG_SDHC1_BDPR   (*(RwReg *)0x46000020UL)
	(SDHC1) Buffer Data Port
#define	REG_SDHC1_PSR   (*(RoReg *)0x46000024UL)
	(SDHC1) Present State
#define	REG_SDHC1_HC1R   (*(RwReg8 *)0x46000028UL)
	(SDHC1) Host Control 1
#define	REG_SDHC1_PCR   (*(RwReg8 *)0x46000029UL)
	(SDHC1) Power Control
#define	REG_SDHC1_BGCR   (*(RwReg8 *)0x4600002AUL)
	(SDHC1) Block Gap Control
#define	REG_SDHC1_WCR   (*(RwReg8 *)0x4600002BUL)
	(SDHC1) Wakeup Control
#define	REG_SDHC1_CCR   (*(RwReg16*)0x4600002CUL)
	(SDHC1) Clock Control
#define	REG_SDHC1_TCR   (*(RwReg8 *)0x4600002EUL)
	(SDHC1) Timeout Control
#define	REG_SDHC1_SRR   (*(RwReg8 *)0x4600002FUL)
	(SDHC1) Software Reset
#define	REG_SDHC1_NISTR   (*(RwReg16*)0x46000030UL)
	(SDHC1) Normal Interrupt Status
#define	REG_SDHC1_EISTR   (*(RwReg16*)0x46000032UL)
	(SDHC1) Error Interrupt Status
#define	REG_SDHC1_NISTER   (*(RwReg16*)0x46000034UL)
	(SDHC1) Normal Interrupt Status Enable
#define	REG_SDHC1_EISTER   (*(RwReg16*)0x46000036UL)
	(SDHC1) Error Interrupt Status Enable
#define	REG_SDHC1_NISIER   (*(RwReg16*)0x46000038UL)
	(SDHC1) Normal Interrupt Signal Enable
#define	REG_SDHC1_EISIER   (*(RwReg16*)0x4600003AUL)
	(SDHC1) Error Interrupt Signal Enable
#define	REG_SDHC1_ACESR   (*(RoReg16*)0x4600003CUL)
	(SDHC1) Auto CMD Error Status
#define	REG_SDHC1_HC2R   (*(RwReg16*)0x4600003EUL)
	(SDHC1) Host Control 2
#define	REG_SDHC1_CA0R   (*(RoReg *)0x46000040UL)
	(SDHC1) Capabilities 0
#define	REG_SDHC1_CA1R   (*(RoReg *)0x46000044UL)
	(SDHC1) Capabilities 1
#define	REG_SDHC1_MCCAR   (*(RoReg *)0x46000048UL)
	(SDHC1) Maximum Current Capabilities
#define	REG_SDHC1_FERACES   (*(WoReg16*)0x46000050UL)
	(SDHC1) Force Event for Auto CMD Error Status
#define	REG_SDHC1_FEREIS   (*(WoReg16*)0x46000052UL)
	(SDHC1) Force Event for Error Interrupt Status
#define	REG_SDHC1_AESR   (*(RoReg8 *)0x46000054UL)
	(SDHC1) ADMA Error Status
#define	REG_SDHC1_ASAR0   (*(RwReg *)0x46000058UL)
	(SDHC1) ADMA System Address 0
#define	REG_SDHC1_PVR0   (*(RwReg16*)0x46000060UL)
	(SDHC1) Preset Value 0
#define	REG_SDHC1_PVR1   (*(RwReg16*)0x46000062UL)
	(SDHC1) Preset Value 1
#define	REG_SDHC1_PVR2   (*(RwReg16*)0x46000064UL)
	(SDHC1) Preset Value 2
#define	REG_SDHC1_PVR3   (*(RwReg16*)0x46000066UL)
	(SDHC1) Preset Value 3
#define	REG_SDHC1_PVR4   (*(RwReg16*)0x46000068UL)
	(SDHC1) Preset Value 4
#define	REG_SDHC1_PVR5   (*(RwReg16*)0x4600006AUL)
	(SDHC1) Preset Value 5
#define	REG_SDHC1_PVR6   (*(RwReg16*)0x4600006CUL)
	(SDHC1) Preset Value 6
#define	REG_SDHC1_PVR7   (*(RwReg16*)0x4600006EUL)
	(SDHC1) Preset Value 7
#define	REG_SDHC1_SISR   (*(RoReg16*)0x460000FCUL)
	(SDHC1) Slot Interrupt Status
#define	REG_SDHC1_HCVR   (*(RoReg16*)0x460000FEUL)
	(SDHC1) Host Controller Version
#define	REG_SDHC1_MC1R   (*(RwReg8 *)0x46000204UL)
	(SDHC1) MMC Control 1
#define	REG_SDHC1_MC2R   (*(WoReg8 *)0x46000205UL)
	(SDHC1) MMC Control 2
#define	REG_SDHC1_ACR   (*(RwReg *)0x46000208UL)
	(SDHC1) AHB Control
#define	REG_SDHC1_CC2R   (*(RwReg *)0x4600020CUL)
	(SDHC1) Clock Control 2
#define	REG_SDHC1_CACR   (*(RwReg *)0x46000230UL)
	(SDHC1) Capabilities Control
#define	REG_SDHC1_DBGR   (*(RwReg8 *)0x46000234UL)
	(SDHC1) Debug
#define	SDHC1_CARD_DATA_SIZE   4
#define	SDHC1_CLK_AHB_ID   16
#define	SDHC1_GCLK_ID   46
#define	SDHC1_GCLK_ID_SLOW   3
#define	SDHC1_NB_OF_DEVICES   1
#define	SDHC1_NB_REG_PVR   8
#define	SDHC1_NB_REG_RR   4

Detailed Description

Instance description for SDHC1.

Copyright (c) 2019 Microchip Technology Inc.

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Definition in file sdhc1.h.