doc/html/sdhc1_8h_source.html

#ifndef _SAME54_SDHC1_INSTANCE_

#define _SAME54_SDHC1_INSTANCE_


/* ========== Register definition for SDHC1 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_SDHC1_SSAR             (0x46000000)

#define REG_SDHC1_BSR              (0x46000004)

#define REG_SDHC1_BCR              (0x46000006)

#define REG_SDHC1_ARG1R            (0x46000008)

#define REG_SDHC1_TMR              (0x4600000C)

#define REG_SDHC1_CR               (0x4600000E)

#define REG_SDHC1_RR0              (0x46000010)

#define REG_SDHC1_RR1              (0x46000014)

#define REG_SDHC1_RR2              (0x46000018)

#define REG_SDHC1_RR3              (0x4600001C)

#define REG_SDHC1_BDPR             (0x46000020)

#define REG_SDHC1_PSR              (0x46000024)

#define REG_SDHC1_HC1R             (0x46000028)

#define REG_SDHC1_PCR              (0x46000029)

#define REG_SDHC1_BGCR             (0x4600002A)

#define REG_SDHC1_WCR              (0x4600002B)

#define REG_SDHC1_CCR              (0x4600002C)

#define REG_SDHC1_TCR              (0x4600002E)

#define REG_SDHC1_SRR              (0x4600002F)

#define REG_SDHC1_NISTR            (0x46000030)

#define REG_SDHC1_EISTR            (0x46000032)

#define REG_SDHC1_NISTER           (0x46000034)

#define REG_SDHC1_EISTER           (0x46000036)

#define REG_SDHC1_NISIER           (0x46000038)

#define REG_SDHC1_EISIER           (0x4600003A)

#define REG_SDHC1_ACESR            (0x4600003C)

#define REG_SDHC1_HC2R             (0x4600003E)

#define REG_SDHC1_CA0R             (0x46000040)

#define REG_SDHC1_CA1R             (0x46000044)

#define REG_SDHC1_MCCAR            (0x46000048)

#define REG_SDHC1_FERACES          (0x46000050)

#define REG_SDHC1_FEREIS           (0x46000052)

#define REG_SDHC1_AESR             (0x46000054)

#define REG_SDHC1_ASAR0            (0x46000058)

#define REG_SDHC1_PVR0             (0x46000060)

#define REG_SDHC1_PVR1             (0x46000062)

#define REG_SDHC1_PVR2             (0x46000064)

#define REG_SDHC1_PVR3             (0x46000066)

#define REG_SDHC1_PVR4             (0x46000068)

#define REG_SDHC1_PVR5             (0x4600006A)

#define REG_SDHC1_PVR6             (0x4600006C)

#define REG_SDHC1_PVR7             (0x4600006E)

#define REG_SDHC1_SISR             (0x460000FC)

#define REG_SDHC1_HCVR             (0x460000FE)

#define REG_SDHC1_MC1R             (0x46000204)

#define REG_SDHC1_MC2R             (0x46000205)

#define REG_SDHC1_ACR              (0x46000208)

#define REG_SDHC1_CC2R             (0x4600020C)

#define REG_SDHC1_CACR             (0x46000230)

#define REG_SDHC1_DBGR             (0x46000234)

#else

#define REG_SDHC1_SSAR             (*(RwReg  *)0x46000000UL)

#define REG_SDHC1_BSR              (*(RwReg16*)0x46000004UL)

#define REG_SDHC1_BCR              (*(RwReg16*)0x46000006UL)

#define REG_SDHC1_ARG1R            (*(RwReg  *)0x46000008UL)

#define REG_SDHC1_TMR              (*(RwReg16*)0x4600000CUL)

#define REG_SDHC1_CR               (*(RwReg16*)0x4600000EUL)

#define REG_SDHC1_RR0              (*(RoReg  *)0x46000010UL)

#define REG_SDHC1_RR1              (*(RoReg  *)0x46000014UL)

#define REG_SDHC1_RR2              (*(RoReg  *)0x46000018UL)

#define REG_SDHC1_RR3              (*(RoReg  *)0x4600001CUL)

#define REG_SDHC1_BDPR             (*(RwReg  *)0x46000020UL)

#define REG_SDHC1_PSR              (*(RoReg  *)0x46000024UL)

#define REG_SDHC1_HC1R             (*(RwReg8 *)0x46000028UL)

#define REG_SDHC1_PCR              (*(RwReg8 *)0x46000029UL)

#define REG_SDHC1_BGCR             (*(RwReg8 *)0x4600002AUL)

#define REG_SDHC1_WCR              (*(RwReg8 *)0x4600002BUL)

#define REG_SDHC1_CCR              (*(RwReg16*)0x4600002CUL)

#define REG_SDHC1_TCR              (*(RwReg8 *)0x4600002EUL)

#define REG_SDHC1_SRR              (*(RwReg8 *)0x4600002FUL)

#define REG_SDHC1_NISTR            (*(RwReg16*)0x46000030UL)

#define REG_SDHC1_EISTR            (*(RwReg16*)0x46000032UL)

#define REG_SDHC1_NISTER           (*(RwReg16*)0x46000034UL)

#define REG_SDHC1_EISTER           (*(RwReg16*)0x46000036UL)

#define REG_SDHC1_NISIER           (*(RwReg16*)0x46000038UL)

#define REG_SDHC1_EISIER           (*(RwReg16*)0x4600003AUL)

#define REG_SDHC1_ACESR            (*(RoReg16*)0x4600003CUL)

#define REG_SDHC1_HC2R             (*(RwReg16*)0x4600003EUL)

#define REG_SDHC1_CA0R             (*(RoReg  *)0x46000040UL)

#define REG_SDHC1_CA1R             (*(RoReg  *)0x46000044UL)

#define REG_SDHC1_MCCAR            (*(RoReg  *)0x46000048UL)

#define REG_SDHC1_FERACES          (*(WoReg16*)0x46000050UL)

#define REG_SDHC1_FEREIS           (*(WoReg16*)0x46000052UL)

#define REG_SDHC1_AESR             (*(RoReg8 *)0x46000054UL)

#define REG_SDHC1_ASAR0            (*(RwReg  *)0x46000058UL)

#define REG_SDHC1_PVR0             (*(RwReg16*)0x46000060UL)

#define REG_SDHC1_PVR1             (*(RwReg16*)0x46000062UL)

#define REG_SDHC1_PVR2             (*(RwReg16*)0x46000064UL)

#define REG_SDHC1_PVR3             (*(RwReg16*)0x46000066UL)

#define REG_SDHC1_PVR4             (*(RwReg16*)0x46000068UL)

#define REG_SDHC1_PVR5             (*(RwReg16*)0x4600006AUL)

#define REG_SDHC1_PVR6             (*(RwReg16*)0x4600006CUL)

#define REG_SDHC1_PVR7             (*(RwReg16*)0x4600006EUL)

#define REG_SDHC1_SISR             (*(RoReg16*)0x460000FCUL)

#define REG_SDHC1_HCVR             (*(RoReg16*)0x460000FEUL)

#define REG_SDHC1_MC1R             (*(RwReg8 *)0x46000204UL)

#define REG_SDHC1_MC2R             (*(WoReg8 *)0x46000205UL)

#define REG_SDHC1_ACR              (*(RwReg  *)0x46000208UL)

#define REG_SDHC1_CC2R             (*(RwReg  *)0x4600020CUL)

#define REG_SDHC1_CACR             (*(RwReg  *)0x46000230UL)

#define REG_SDHC1_DBGR             (*(RwReg8 *)0x46000234UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for SDHC1 peripheral ========== */

#define SDHC1_CARD_DATA_SIZE        4

#define SDHC1_CLK_AHB_ID            16

#define SDHC1_GCLK_ID               46

#define SDHC1_GCLK_ID_SLOW          3

#define SDHC1_NB_OF_DEVICES         1

#define SDHC1_NB_REG_PVR            8

#define SDHC1_NB_REG_RR             4


#endif /* _SAME54_SDHC1_INSTANCE_ */