Component description for AES. More...

Data Structures
union	AES_CTRLA_Type

union	AES_CTRLB_Type

union	AES_INTENCLR_Type

union	AES_INTENSET_Type

union	AES_INTFLAG_Type

union	AES_DATABUFPTR_Type

union	AES_DBGCTRL_Type

union	AES_KEYWORD_Type

union	AES_INDATA_Type

union	AES_INTVECTV_Type

union	AES_HASHKEY_Type

union	AES_GHASH_Type

union	AES_CIPLEN_Type

union	AES_RANDSEED_Type

struct	Aes
	AES hardware registers. More...

Macros
#define	AES_U2238

#define	REV_AES 0x220

#define	AES_CTRLA_OFFSET 0x00
	(AES_CTRLA offset) Control A

#define	AES_CTRLA_RESETVALUE _U_(0x00000000)
	(AES_CTRLA reset_value) Control A

#define	AES_CTRLA_SWRST_Pos 0
	(AES_CTRLA) Software Reset

#define	AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)

#define	AES_CTRLA_ENABLE_Pos 1
	(AES_CTRLA) Enable

#define	AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)

#define	AES_CTRLA_AESMODE_Pos 2
	(AES_CTRLA) AES Modes of operation

#define	AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))

#define	AES_CTRLA_AESMODE_ECB_Val _U_(0x0)
	(AES_CTRLA) Electronic code book mode

#define	AES_CTRLA_AESMODE_CBC_Val _U_(0x1)
	(AES_CTRLA) Cipher block chaining mode

#define	AES_CTRLA_AESMODE_OFB_Val _U_(0x2)
	(AES_CTRLA) Output feedback mode

#define	AES_CTRLA_AESMODE_CFB_Val _U_(0x3)
	(AES_CTRLA) Cipher feedback mode

#define	AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4)
	(AES_CTRLA) Counter mode

#define	AES_CTRLA_AESMODE_CCM_Val _U_(0x5)
	(AES_CTRLA) CCM mode

#define	AES_CTRLA_AESMODE_GCM_Val _U_(0x6)
	(AES_CTRLA) Galois counter mode

#define	AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)

#define	AES_CTRLA_CFBS_Pos 5
	(AES_CTRLA) Cipher Feedback Block Size

#define	AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)

#define	AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))

#define	AES_CTRLA_CFBS_128BIT_Val _U_(0x0)
	(AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode

#define	AES_CTRLA_CFBS_64BIT_Val _U_(0x1)
	(AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode

#define	AES_CTRLA_CFBS_32BIT_Val _U_(0x2)
	(AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode

#define	AES_CTRLA_CFBS_16BIT_Val _U_(0x3)
	(AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode

#define	AES_CTRLA_CFBS_8BIT_Val _U_(0x4)
	(AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode

#define	AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)

#define	AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)

#define	AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)

#define	AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)

#define	AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)

#define	AES_CTRLA_KEYSIZE_Pos 8
	(AES_CTRLA) Encryption Key Size

#define	AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)

#define	AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))

#define	AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0)
	(AES_CTRLA) 128-bit Key for Encryption / Decryption

#define	AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1)
	(AES_CTRLA) 192-bit Key for Encryption / Decryption

#define	AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2)
	(AES_CTRLA) 256-bit Key for Encryption / Decryption

#define	AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)

#define	AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)

#define	AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)

#define	AES_CTRLA_CIPHER_Pos 10
	(AES_CTRLA) Cipher Mode

#define	AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)

#define	AES_CTRLA_CIPHER_DEC_Val _U_(0x0)
	(AES_CTRLA) Decryption

#define	AES_CTRLA_CIPHER_ENC_Val _U_(0x1)
	(AES_CTRLA) Encryption

#define	AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)

#define	AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)

#define	AES_CTRLA_STARTMODE_Pos 11
	(AES_CTRLA) Start Mode Select

#define	AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)

#define	AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0)
	(AES_CTRLA) Start Encryption / Decryption in Manual mode

#define	AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1)
	(AES_CTRLA) Start Encryption / Decryption in Auto mode

#define	AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)

#define	AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)

#define	AES_CTRLA_LOD_Pos 12
	(AES_CTRLA) Last Output Data Mode

#define	AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)

#define	AES_CTRLA_LOD_NONE_Val _U_(0x0)
	(AES_CTRLA) No effect

#define	AES_CTRLA_LOD_LAST_Val _U_(0x1)
	(AES_CTRLA) Start encryption in Last Output Data mode

#define	AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)

#define	AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)

#define	AES_CTRLA_KEYGEN_Pos 13
	(AES_CTRLA) Last Key Generation

#define	AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)

#define	AES_CTRLA_KEYGEN_NONE_Val _U_(0x0)
	(AES_CTRLA) No effect

#define	AES_CTRLA_KEYGEN_LAST_Val _U_(0x1)
	(AES_CTRLA) Start Computation of the last NK words of the expanded key

#define	AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)

#define	AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)

#define	AES_CTRLA_XORKEY_Pos 14
	(AES_CTRLA) XOR Key Operation

#define	AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)

#define	AES_CTRLA_XORKEY_NONE_Val _U_(0x0)
	(AES_CTRLA) No effect

#define	AES_CTRLA_XORKEY_XOR_Val _U_(0x1)
	(AES_CTRLA) The user keyword gets XORed with the previous keyword register content.

#define	AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)

#define	AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)

#define	AES_CTRLA_CTYPE_Pos 16
	(AES_CTRLA) Counter Measure Type

#define	AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)

#define	AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))

#define	AES_CTRLA_MASK _U_(0x000F7FFF)
	(AES_CTRLA) MASK Register

#define	AES_CTRLB_OFFSET 0x04
	(AES_CTRLB offset) Control B

#define	AES_CTRLB_RESETVALUE _U_(0x00)
	(AES_CTRLB reset_value) Control B

#define	AES_CTRLB_START_Pos 0
	(AES_CTRLB) Start Encryption/Decryption

#define	AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)

#define	AES_CTRLB_NEWMSG_Pos 1
	(AES_CTRLB) New message

#define	AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)

#define	AES_CTRLB_EOM_Pos 2
	(AES_CTRLB) End of message

#define	AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)

#define	AES_CTRLB_GFMUL_Pos 3
	(AES_CTRLB) GF Multiplication

#define	AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)

#define	AES_CTRLB_MASK _U_(0x0F)
	(AES_CTRLB) MASK Register

#define	AES_INTENCLR_OFFSET 0x05
	(AES_INTENCLR offset) Interrupt Enable Clear

#define	AES_INTENCLR_RESETVALUE _U_(0x00)
	(AES_INTENCLR reset_value) Interrupt Enable Clear

#define	AES_INTENCLR_ENCCMP_Pos 0
	(AES_INTENCLR) Encryption Complete Interrupt Enable

#define	AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)

#define	AES_INTENCLR_GFMCMP_Pos 1
	(AES_INTENCLR) GF Multiplication Complete Interrupt Enable

#define	AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)

#define	AES_INTENCLR_MASK _U_(0x03)
	(AES_INTENCLR) MASK Register

#define	AES_INTENSET_OFFSET 0x06
	(AES_INTENSET offset) Interrupt Enable Set

#define	AES_INTENSET_RESETVALUE _U_(0x00)
	(AES_INTENSET reset_value) Interrupt Enable Set

#define	AES_INTENSET_ENCCMP_Pos 0
	(AES_INTENSET) Encryption Complete Interrupt Enable

#define	AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)

#define	AES_INTENSET_GFMCMP_Pos 1
	(AES_INTENSET) GF Multiplication Complete Interrupt Enable

#define	AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)

#define	AES_INTENSET_MASK _U_(0x03)
	(AES_INTENSET) MASK Register

#define	AES_INTFLAG_OFFSET 0x07
	(AES_INTFLAG offset) Interrupt Flag Status

#define	AES_INTFLAG_RESETVALUE _U_(0x00)
	(AES_INTFLAG reset_value) Interrupt Flag Status

#define	AES_INTFLAG_ENCCMP_Pos 0
	(AES_INTFLAG) Encryption Complete

#define	AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)

#define	AES_INTFLAG_GFMCMP_Pos 1
	(AES_INTFLAG) GF Multiplication Complete

#define	AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)

#define	AES_INTFLAG_MASK _U_(0x03)
	(AES_INTFLAG) MASK Register

#define	AES_DATABUFPTR_OFFSET 0x08
	(AES_DATABUFPTR offset) Data buffer pointer

#define	AES_DATABUFPTR_RESETVALUE _U_(0x00)
	(AES_DATABUFPTR reset_value) Data buffer pointer

#define	AES_DATABUFPTR_INDATAPTR_Pos 0
	(AES_DATABUFPTR) Input Data Pointer

#define	AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)

#define	AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))

#define	AES_DATABUFPTR_MASK _U_(0x03)
	(AES_DATABUFPTR) MASK Register

#define	AES_DBGCTRL_OFFSET 0x09
	(AES_DBGCTRL offset) Debug control

#define	AES_DBGCTRL_RESETVALUE _U_(0x00)
	(AES_DBGCTRL reset_value) Debug control

#define	AES_DBGCTRL_DBGRUN_Pos 0
	(AES_DBGCTRL) Debug Run

#define	AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)

#define	AES_DBGCTRL_MASK _U_(0x01)
	(AES_DBGCTRL) MASK Register

#define	AES_KEYWORD_OFFSET 0x0C
	(AES_KEYWORD offset) Keyword n

#define	AES_KEYWORD_RESETVALUE _U_(0x00000000)
	(AES_KEYWORD reset_value) Keyword n

#define	AES_KEYWORD_MASK _U_(0xFFFFFFFF)
	(AES_KEYWORD) MASK Register

#define	AES_INDATA_OFFSET 0x38
	(AES_INDATA offset) Indata

#define	AES_INDATA_RESETVALUE _U_(0x00000000)
	(AES_INDATA reset_value) Indata

#define	AES_INDATA_MASK _U_(0xFFFFFFFF)
	(AES_INDATA) MASK Register

#define	AES_INTVECTV_OFFSET 0x3C
	(AES_INTVECTV offset) Initialisation Vector n

#define	AES_INTVECTV_RESETVALUE _U_(0x00000000)
	(AES_INTVECTV reset_value) Initialisation Vector n

#define	AES_INTVECTV_MASK _U_(0xFFFFFFFF)
	(AES_INTVECTV) MASK Register

#define	AES_HASHKEY_OFFSET 0x5C
	(AES_HASHKEY offset) Hash key n

#define	AES_HASHKEY_RESETVALUE _U_(0x00000000)
	(AES_HASHKEY reset_value) Hash key n

#define	AES_HASHKEY_MASK _U_(0xFFFFFFFF)
	(AES_HASHKEY) MASK Register

#define	AES_GHASH_OFFSET 0x6C
	(AES_GHASH offset) Galois Hash n

#define	AES_GHASH_RESETVALUE _U_(0x00000000)
	(AES_GHASH reset_value) Galois Hash n

#define	AES_GHASH_MASK _U_(0xFFFFFFFF)
	(AES_GHASH) MASK Register

#define	AES_CIPLEN_OFFSET 0x80
	(AES_CIPLEN offset) Cipher Length

#define	AES_CIPLEN_RESETVALUE _U_(0x00000000)
	(AES_CIPLEN reset_value) Cipher Length

#define	AES_CIPLEN_MASK _U_(0xFFFFFFFF)
	(AES_CIPLEN) MASK Register

#define	AES_RANDSEED_OFFSET 0x84
	(AES_RANDSEED offset) Random Seed

#define	AES_RANDSEED_RESETVALUE _U_(0x00000000)
	(AES_RANDSEED reset_value) Random Seed

#define	AES_RANDSEED_MASK _U_(0xFFFFFFFF)
	(AES_RANDSEED) MASK Register

Detailed Description

Component description for AES.

\asf_license_start

Definition in file aes.h.

Data Structures

Macros

Detailed Description