|
SAME54P20A Test Project
|
SDHC hardware registers. More...
#include <sdhc.h>
Data Fields | |
| __IO SDHC_SSAR_Type | SSAR |
| Offset: 0x000 (R/W 32) SDMA System Address / Argument 2. | |
| __IO SDHC_BSR_Type | BSR |
| Offset: 0x004 (R/W 16) Block Size. | |
| __IO SDHC_BCR_Type | BCR |
| Offset: 0x006 (R/W 16) Block Count. | |
| __IO SDHC_ARG1R_Type | ARG1R |
| Offset: 0x008 (R/W 32) Argument 1. | |
| __IO SDHC_TMR_Type | TMR |
| Offset: 0x00C (R/W 16) Transfer Mode. | |
| __IO SDHC_CR_Type | CR |
| Offset: 0x00E (R/W 16) Command. | |
| __I SDHC_RR_Type | RR [4] |
| Offset: 0x010 (R/ 32) Response. | |
| __IO SDHC_BDPR_Type | BDPR |
| Offset: 0x020 (R/W 32) Buffer Data Port. | |
| __I SDHC_PSR_Type | PSR |
| Offset: 0x024 (R/ 32) Present State. | |
| __IO SDHC_HC1R_Type | HC1R |
| Offset: 0x028 (R/W 8) Host Control 1. | |
| __IO SDHC_PCR_Type | PCR |
| Offset: 0x029 (R/W 8) Power Control. | |
| __IO SDHC_BGCR_Type | BGCR |
| Offset: 0x02A (R/W 8) Block Gap Control. | |
| __IO SDHC_WCR_Type | WCR |
| Offset: 0x02B (R/W 8) Wakeup Control. | |
| __IO SDHC_CCR_Type | CCR |
| Offset: 0x02C (R/W 16) Clock Control. | |
| __IO SDHC_TCR_Type | TCR |
| Offset: 0x02E (R/W 8) Timeout Control. | |
| __IO SDHC_SRR_Type | SRR |
| Offset: 0x02F (R/W 8) Software Reset. | |
| __IO SDHC_NISTR_Type | NISTR |
| Offset: 0x030 (R/W 16) Normal Interrupt Status. | |
| __IO SDHC_EISTR_Type | EISTR |
| Offset: 0x032 (R/W 16) Error Interrupt Status. | |
| __IO SDHC_NISTER_Type | NISTER |
| Offset: 0x034 (R/W 16) Normal Interrupt Status Enable. | |
| __IO SDHC_EISTER_Type | EISTER |
| Offset: 0x036 (R/W 16) Error Interrupt Status Enable. | |
| __IO SDHC_NISIER_Type | NISIER |
| Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable. | |
| __IO SDHC_EISIER_Type | EISIER |
| Offset: 0x03A (R/W 16) Error Interrupt Signal Enable. | |
| __I SDHC_ACESR_Type | ACESR |
| Offset: 0x03C (R/ 16) Auto CMD Error Status. | |
| __IO SDHC_HC2R_Type | HC2R |
| Offset: 0x03E (R/W 16) Host Control 2. | |
| __I SDHC_CA0R_Type | CA0R |
| Offset: 0x040 (R/ 32) Capabilities 0. | |
| __I SDHC_CA1R_Type | CA1R |
| Offset: 0x044 (R/ 32) Capabilities 1. | |
| __I SDHC_MCCAR_Type | MCCAR |
| Offset: 0x048 (R/ 32) Maximum Current Capabilities. | |
| RoReg8 | Reserved1 [0x4] |
| __O SDHC_FERACES_Type | FERACES |
| Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status. | |
| __O SDHC_FEREIS_Type | FEREIS |
| Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status. | |
| __I SDHC_AESR_Type | AESR |
| Offset: 0x054 (R/ 8) ADMA Error Status. | |
| RoReg8 | Reserved2 [0x3] |
| __IO SDHC_ASAR_Type | ASAR [1] |
| Offset: 0x058 (R/W 32) ADMA System Address n. | |
| RoReg8 | Reserved3 [0x4] |
| __IO SDHC_PVR_Type | PVR [8] |
| Offset: 0x060 (R/W 16) Preset Value n. | |
| RoReg8 | Reserved4 [0x8C] |
| __I SDHC_SISR_Type | SISR |
| Offset: 0x0FC (R/ 16) Slot Interrupt Status. | |
| __I SDHC_HCVR_Type | HCVR |
| Offset: 0x0FE (R/ 16) Host Controller Version. | |
| RoReg8 | Reserved5 [0x104] |
| __IO SDHC_MC1R_Type | MC1R |
| Offset: 0x204 (R/W 8) MMC Control 1. | |
| __O SDHC_MC2R_Type | MC2R |
| Offset: 0x205 ( /W 8) MMC Control 2. | |
| RoReg8 | Reserved6 [0x2] |
| __IO SDHC_ACR_Type | ACR |
| Offset: 0x208 (R/W 32) AHB Control. | |
| __IO SDHC_CC2R_Type | CC2R |
| Offset: 0x20C (R/W 32) Clock Control 2. | |
| RoReg8 | Reserved7 [0x20] |
| __IO SDHC_CACR_Type | CACR |
| Offset: 0x230 (R/W 32) Capabilities Control. | |
| __IO SDHC_DBGR_Type | DBGR |
| Offset: 0x234 (R/W 8) Debug. | |
1.8.20