sdhc.h

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#ifndef _SAME54_SDHC_COMPONENT_
#define _SAME54_SDHC_COMPONENT_
 
/* ========================================================================== */
/* ========================================================================== */
 
#define SDHC_U2011
#define REV_SDHC                    0x183
 
/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct { // CMD23 mode
    uint32_t ARG2:32;          
  } CMD23;                     
  struct {
    uint32_t ADDR:32;          
  } bit;                       
  uint32_t reg;                
} SDHC_SSAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_SSAR_OFFSET            0x000        
#define SDHC_SSAR_RESETVALUE        _U_(0x00000000) 
// CMD23 mode
#define SDHC_SSAR_CMD23_ARG2_Pos    0            
#define SDHC_SSAR_CMD23_ARG2_Msk    (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)
#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos))
#define SDHC_SSAR_CMD23_MASK        _U_(0xFFFFFFFF) 
#define SDHC_SSAR_ADDR_Pos          0            
#define SDHC_SSAR_ADDR_Msk          (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)
#define SDHC_SSAR_ADDR(value)       (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos))
#define SDHC_SSAR_MASK              _U_(0xFFFFFFFF) 
/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t BLOCKSIZE:10;     
    uint16_t :2;               
    uint16_t BOUNDARY:3;       
    uint16_t :1;               
  } bit;                       
  uint16_t reg;                
} SDHC_BSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_BSR_OFFSET             0x004        
#define SDHC_BSR_RESETVALUE         _U_(0x0000)  
#define SDHC_BSR_BLOCKSIZE_Pos      0            
#define SDHC_BSR_BLOCKSIZE_Msk      (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)
#define SDHC_BSR_BLOCKSIZE(value)   (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos))
#define SDHC_BSR_BOUNDARY_Pos       12           
#define SDHC_BSR_BOUNDARY_Msk       (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY(value)    (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos))
#define   SDHC_BSR_BOUNDARY_4K_Val        _U_(0x0)   
#define   SDHC_BSR_BOUNDARY_8K_Val        _U_(0x1)   
#define   SDHC_BSR_BOUNDARY_16K_Val       _U_(0x2)   
#define   SDHC_BSR_BOUNDARY_32K_Val       _U_(0x3)   
#define   SDHC_BSR_BOUNDARY_64K_Val       _U_(0x4)   
#define   SDHC_BSR_BOUNDARY_128K_Val      _U_(0x5)   
#define   SDHC_BSR_BOUNDARY_256K_Val      _U_(0x6)   
#define   SDHC_BSR_BOUNDARY_512K_Val      _U_(0x7)   
#define SDHC_BSR_BOUNDARY_4K        (SDHC_BSR_BOUNDARY_4K_Val      << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY_8K        (SDHC_BSR_BOUNDARY_8K_Val      << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY_16K       (SDHC_BSR_BOUNDARY_16K_Val     << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY_32K       (SDHC_BSR_BOUNDARY_32K_Val     << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY_64K       (SDHC_BSR_BOUNDARY_64K_Val     << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY_128K      (SDHC_BSR_BOUNDARY_128K_Val    << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY_256K      (SDHC_BSR_BOUNDARY_256K_Val    << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_BOUNDARY_512K      (SDHC_BSR_BOUNDARY_512K_Val    << SDHC_BSR_BOUNDARY_Pos)
#define SDHC_BSR_MASK               _U_(0x73FF)  
/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t BCNT:16;          
  } bit;                       
  uint16_t reg;                
} SDHC_BCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_BCR_OFFSET             0x006        
#define SDHC_BCR_RESETVALUE         _U_(0x0000)  
#define SDHC_BCR_BCNT_Pos           0            
#define SDHC_BCR_BCNT_Msk           (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos)
#define SDHC_BCR_BCNT(value)        (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos))
#define SDHC_BCR_MASK               _U_(0xFFFF)  
/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t ARG:32;           
  } bit;                       
  uint32_t reg;                
} SDHC_ARG1R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_ARG1R_OFFSET           0x008        
#define SDHC_ARG1R_RESETVALUE       _U_(0x00000000) 
#define SDHC_ARG1R_ARG_Pos          0            
#define SDHC_ARG1R_ARG_Msk          (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos)
#define SDHC_ARG1R_ARG(value)       (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos))
#define SDHC_ARG1R_MASK             _U_(0xFFFFFFFF) 
/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t DMAEN:1;          
    uint16_t BCEN:1;           
    uint16_t ACMDEN:2;         
    uint16_t DTDSEL:1;         
    uint16_t MSBSEL:1;         
    uint16_t :10;              
  } bit;                       
  uint16_t reg;                
} SDHC_TMR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_TMR_OFFSET             0x00C        
#define SDHC_TMR_RESETVALUE         _U_(0x0000)  
#define SDHC_TMR_DMAEN_Pos          0            
#define SDHC_TMR_DMAEN              (_U_(0x1) << SDHC_TMR_DMAEN_Pos)
#define   SDHC_TMR_DMAEN_DISABLE_Val      _U_(0x0)   
#define   SDHC_TMR_DMAEN_ENABLE_Val       _U_(0x1)   
#define SDHC_TMR_DMAEN_DISABLE      (SDHC_TMR_DMAEN_DISABLE_Val    << SDHC_TMR_DMAEN_Pos)
#define SDHC_TMR_DMAEN_ENABLE       (SDHC_TMR_DMAEN_ENABLE_Val     << SDHC_TMR_DMAEN_Pos)
#define SDHC_TMR_BCEN_Pos           1            
#define SDHC_TMR_BCEN               (_U_(0x1) << SDHC_TMR_BCEN_Pos)
#define   SDHC_TMR_BCEN_DISABLE_Val       _U_(0x0)   
#define   SDHC_TMR_BCEN_ENABLE_Val        _U_(0x1)   
#define SDHC_TMR_BCEN_DISABLE       (SDHC_TMR_BCEN_DISABLE_Val     << SDHC_TMR_BCEN_Pos)
#define SDHC_TMR_BCEN_ENABLE        (SDHC_TMR_BCEN_ENABLE_Val      << SDHC_TMR_BCEN_Pos)
#define SDHC_TMR_ACMDEN_Pos         2            
#define SDHC_TMR_ACMDEN_Msk         (_U_(0x3) << SDHC_TMR_ACMDEN_Pos)
#define SDHC_TMR_ACMDEN(value)      (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos))
#define   SDHC_TMR_ACMDEN_DISABLED_Val    _U_(0x0)   
#define   SDHC_TMR_ACMDEN_CMD12_Val       _U_(0x1)   
#define   SDHC_TMR_ACMDEN_CMD23_Val       _U_(0x2)   
#define   SDHC_TMR_ACMDEN_3_Val           _U_(0x3)   
#define SDHC_TMR_ACMDEN_DISABLED    (SDHC_TMR_ACMDEN_DISABLED_Val  << SDHC_TMR_ACMDEN_Pos)
#define SDHC_TMR_ACMDEN_CMD12       (SDHC_TMR_ACMDEN_CMD12_Val     << SDHC_TMR_ACMDEN_Pos)
#define SDHC_TMR_ACMDEN_CMD23       (SDHC_TMR_ACMDEN_CMD23_Val     << SDHC_TMR_ACMDEN_Pos)
#define SDHC_TMR_ACMDEN_3           (SDHC_TMR_ACMDEN_3_Val         << SDHC_TMR_ACMDEN_Pos)
#define SDHC_TMR_DTDSEL_Pos         4            
#define SDHC_TMR_DTDSEL             (_U_(0x1) << SDHC_TMR_DTDSEL_Pos)
#define   SDHC_TMR_DTDSEL_WRITE_Val       _U_(0x0)   
#define   SDHC_TMR_DTDSEL_READ_Val        _U_(0x1)   
#define SDHC_TMR_DTDSEL_WRITE       (SDHC_TMR_DTDSEL_WRITE_Val     << SDHC_TMR_DTDSEL_Pos)
#define SDHC_TMR_DTDSEL_READ        (SDHC_TMR_DTDSEL_READ_Val      << SDHC_TMR_DTDSEL_Pos)
#define SDHC_TMR_MSBSEL_Pos         5            
#define SDHC_TMR_MSBSEL             (_U_(0x1) << SDHC_TMR_MSBSEL_Pos)
#define   SDHC_TMR_MSBSEL_SINGLE_Val      _U_(0x0)   
#define   SDHC_TMR_MSBSEL_MULTIPLE_Val    _U_(0x1)   
#define SDHC_TMR_MSBSEL_SINGLE      (SDHC_TMR_MSBSEL_SINGLE_Val    << SDHC_TMR_MSBSEL_Pos)
#define SDHC_TMR_MSBSEL_MULTIPLE    (SDHC_TMR_MSBSEL_MULTIPLE_Val  << SDHC_TMR_MSBSEL_Pos)
#define SDHC_TMR_MASK               _U_(0x003F)  
/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t RESPTYP:2;        
    uint16_t :1;               
    uint16_t CMDCCEN:1;        
    uint16_t CMDICEN:1;        
    uint16_t DPSEL:1;          
    uint16_t CMDTYP:2;         
    uint16_t CMDIDX:6;         
    uint16_t :2;               
  } bit;                       
  uint16_t reg;                
} SDHC_CR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_CR_OFFSET              0x00E        
#define SDHC_CR_RESETVALUE          _U_(0x0000)  
#define SDHC_CR_RESPTYP_Pos         0            
#define SDHC_CR_RESPTYP_Msk         (_U_(0x3) << SDHC_CR_RESPTYP_Pos)
#define SDHC_CR_RESPTYP(value)      (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos))
#define   SDHC_CR_RESPTYP_NONE_Val        _U_(0x0)   
#define   SDHC_CR_RESPTYP_136_BIT_Val     _U_(0x1)   
#define   SDHC_CR_RESPTYP_48_BIT_Val      _U_(0x2)   
#define   SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3)   
#define SDHC_CR_RESPTYP_NONE        (SDHC_CR_RESPTYP_NONE_Val      << SDHC_CR_RESPTYP_Pos)
#define SDHC_CR_RESPTYP_136_BIT     (SDHC_CR_RESPTYP_136_BIT_Val   << SDHC_CR_RESPTYP_Pos)
#define SDHC_CR_RESPTYP_48_BIT      (SDHC_CR_RESPTYP_48_BIT_Val    << SDHC_CR_RESPTYP_Pos)
#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos)
#define SDHC_CR_CMDCCEN_Pos         3            
#define SDHC_CR_CMDCCEN             (_U_(0x1) << SDHC_CR_CMDCCEN_Pos)
#define   SDHC_CR_CMDCCEN_DISABLE_Val     _U_(0x0)   
#define   SDHC_CR_CMDCCEN_ENABLE_Val      _U_(0x1)   
#define SDHC_CR_CMDCCEN_DISABLE     (SDHC_CR_CMDCCEN_DISABLE_Val   << SDHC_CR_CMDCCEN_Pos)
#define SDHC_CR_CMDCCEN_ENABLE      (SDHC_CR_CMDCCEN_ENABLE_Val    << SDHC_CR_CMDCCEN_Pos)
#define SDHC_CR_CMDICEN_Pos         4            
#define SDHC_CR_CMDICEN             (_U_(0x1) << SDHC_CR_CMDICEN_Pos)
#define   SDHC_CR_CMDICEN_DISABLE_Val     _U_(0x0)   
#define   SDHC_CR_CMDICEN_ENABLE_Val      _U_(0x1)   
#define SDHC_CR_CMDICEN_DISABLE     (SDHC_CR_CMDICEN_DISABLE_Val   << SDHC_CR_CMDICEN_Pos)
#define SDHC_CR_CMDICEN_ENABLE      (SDHC_CR_CMDICEN_ENABLE_Val    << SDHC_CR_CMDICEN_Pos)
#define SDHC_CR_DPSEL_Pos           5            
#define SDHC_CR_DPSEL               (_U_(0x1) << SDHC_CR_DPSEL_Pos)
#define   SDHC_CR_DPSEL_NO_DATA_Val       _U_(0x0)   
#define   SDHC_CR_DPSEL_DATA_Val          _U_(0x1)   
#define SDHC_CR_DPSEL_NO_DATA       (SDHC_CR_DPSEL_NO_DATA_Val     << SDHC_CR_DPSEL_Pos)
#define SDHC_CR_DPSEL_DATA          (SDHC_CR_DPSEL_DATA_Val        << SDHC_CR_DPSEL_Pos)
#define SDHC_CR_CMDTYP_Pos          6            
#define SDHC_CR_CMDTYP_Msk          (_U_(0x3) << SDHC_CR_CMDTYP_Pos)
#define SDHC_CR_CMDTYP(value)       (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos))
#define   SDHC_CR_CMDTYP_NORMAL_Val       _U_(0x0)   
#define   SDHC_CR_CMDTYP_SUSPEND_Val      _U_(0x1)   
#define   SDHC_CR_CMDTYP_RESUME_Val       _U_(0x2)   
#define   SDHC_CR_CMDTYP_ABORT_Val        _U_(0x3)   
#define SDHC_CR_CMDTYP_NORMAL       (SDHC_CR_CMDTYP_NORMAL_Val     << SDHC_CR_CMDTYP_Pos)
#define SDHC_CR_CMDTYP_SUSPEND      (SDHC_CR_CMDTYP_SUSPEND_Val    << SDHC_CR_CMDTYP_Pos)
#define SDHC_CR_CMDTYP_RESUME       (SDHC_CR_CMDTYP_RESUME_Val     << SDHC_CR_CMDTYP_Pos)
#define SDHC_CR_CMDTYP_ABORT        (SDHC_CR_CMDTYP_ABORT_Val      << SDHC_CR_CMDTYP_Pos)
#define SDHC_CR_CMDIDX_Pos          8            
#define SDHC_CR_CMDIDX_Msk          (_U_(0x3F) << SDHC_CR_CMDIDX_Pos)
#define SDHC_CR_CMDIDX(value)       (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos))
#define SDHC_CR_MASK                _U_(0x3FFB)  
/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/  32) Response -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t CMDRESP:32;       
  } bit;                       
  uint32_t reg;                
} SDHC_RR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_RR_OFFSET              0x010        
#define SDHC_RR_RESETVALUE          _U_(0x00000000) 
#define SDHC_RR_CMDRESP_Pos         0            
#define SDHC_RR_CMDRESP_Msk         (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos)
#define SDHC_RR_CMDRESP(value)      (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos))
#define SDHC_RR_MASK                _U_(0xFFFFFFFF) 
/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t BUFDATA:32;       
  } bit;                       
  uint32_t reg;                
} SDHC_BDPR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_BDPR_OFFSET            0x020        
#define SDHC_BDPR_RESETVALUE        _U_(0x00000000) 
#define SDHC_BDPR_BUFDATA_Pos       0            
#define SDHC_BDPR_BUFDATA_Msk       (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos)
#define SDHC_BDPR_BUFDATA(value)    (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos))
#define SDHC_BDPR_MASK              _U_(0xFFFFFFFF) 
/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/  32) Present State -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t CMDINHC:1;        
    uint32_t CMDINHD:1;        
    uint32_t DLACT:1;          
    uint32_t RTREQ:1;          
    uint32_t :4;               
    uint32_t WTACT:1;          
    uint32_t RTACT:1;          
    uint32_t BUFWREN:1;        
    uint32_t BUFRDEN:1;        
    uint32_t :4;               
    uint32_t CARDINS:1;        
    uint32_t CARDSS:1;         
    uint32_t CARDDPL:1;        
    uint32_t WRPPL:1;          
    uint32_t DATLL:4;          
    uint32_t CMDLL:1;          
    uint32_t :7;               
  } bit;                       
  uint32_t reg;                
} SDHC_PSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_PSR_OFFSET             0x024        
#define SDHC_PSR_RESETVALUE         _U_(0x00F80000) 
#define SDHC_PSR_CMDINHC_Pos        0            
#define SDHC_PSR_CMDINHC            (_U_(0x1) << SDHC_PSR_CMDINHC_Pos)
#define   SDHC_PSR_CMDINHC_CAN_Val        _U_(0x0)   
#define   SDHC_PSR_CMDINHC_CANNOT_Val     _U_(0x1)   
#define SDHC_PSR_CMDINHC_CAN        (SDHC_PSR_CMDINHC_CAN_Val      << SDHC_PSR_CMDINHC_Pos)
#define SDHC_PSR_CMDINHC_CANNOT     (SDHC_PSR_CMDINHC_CANNOT_Val   << SDHC_PSR_CMDINHC_Pos)
#define SDHC_PSR_CMDINHD_Pos        1            
#define SDHC_PSR_CMDINHD            (_U_(0x1) << SDHC_PSR_CMDINHD_Pos)
#define   SDHC_PSR_CMDINHD_CAN_Val        _U_(0x0)   
#define   SDHC_PSR_CMDINHD_CANNOT_Val     _U_(0x1)   
#define SDHC_PSR_CMDINHD_CAN        (SDHC_PSR_CMDINHD_CAN_Val      << SDHC_PSR_CMDINHD_Pos)
#define SDHC_PSR_CMDINHD_CANNOT     (SDHC_PSR_CMDINHD_CANNOT_Val   << SDHC_PSR_CMDINHD_Pos)
#define SDHC_PSR_DLACT_Pos          2            
#define SDHC_PSR_DLACT              (_U_(0x1) << SDHC_PSR_DLACT_Pos)
#define   SDHC_PSR_DLACT_INACTIVE_Val     _U_(0x0)   
#define   SDHC_PSR_DLACT_ACTIVE_Val       _U_(0x1)   
#define SDHC_PSR_DLACT_INACTIVE     (SDHC_PSR_DLACT_INACTIVE_Val   << SDHC_PSR_DLACT_Pos)
#define SDHC_PSR_DLACT_ACTIVE       (SDHC_PSR_DLACT_ACTIVE_Val     << SDHC_PSR_DLACT_Pos)
#define SDHC_PSR_RTREQ_Pos          3            
#define SDHC_PSR_RTREQ              (_U_(0x1) << SDHC_PSR_RTREQ_Pos)
#define   SDHC_PSR_RTREQ_OK_Val           _U_(0x0)   
#define   SDHC_PSR_RTREQ_REQUIRED_Val     _U_(0x1)   
#define SDHC_PSR_RTREQ_OK           (SDHC_PSR_RTREQ_OK_Val         << SDHC_PSR_RTREQ_Pos)
#define SDHC_PSR_RTREQ_REQUIRED     (SDHC_PSR_RTREQ_REQUIRED_Val   << SDHC_PSR_RTREQ_Pos)
#define SDHC_PSR_WTACT_Pos          8            
#define SDHC_PSR_WTACT              (_U_(0x1) << SDHC_PSR_WTACT_Pos)
#define   SDHC_PSR_WTACT_NO_Val           _U_(0x0)   
#define   SDHC_PSR_WTACT_YES_Val          _U_(0x1)   
#define SDHC_PSR_WTACT_NO           (SDHC_PSR_WTACT_NO_Val         << SDHC_PSR_WTACT_Pos)
#define SDHC_PSR_WTACT_YES          (SDHC_PSR_WTACT_YES_Val        << SDHC_PSR_WTACT_Pos)
#define SDHC_PSR_RTACT_Pos          9            
#define SDHC_PSR_RTACT              (_U_(0x1) << SDHC_PSR_RTACT_Pos)
#define   SDHC_PSR_RTACT_NO_Val           _U_(0x0)   
#define   SDHC_PSR_RTACT_YES_Val          _U_(0x1)   
#define SDHC_PSR_RTACT_NO           (SDHC_PSR_RTACT_NO_Val         << SDHC_PSR_RTACT_Pos)
#define SDHC_PSR_RTACT_YES          (SDHC_PSR_RTACT_YES_Val        << SDHC_PSR_RTACT_Pos)
#define SDHC_PSR_BUFWREN_Pos        10           
#define SDHC_PSR_BUFWREN            (_U_(0x1) << SDHC_PSR_BUFWREN_Pos)
#define   SDHC_PSR_BUFWREN_DISABLE_Val    _U_(0x0)   
#define   SDHC_PSR_BUFWREN_ENABLE_Val     _U_(0x1)   
#define SDHC_PSR_BUFWREN_DISABLE    (SDHC_PSR_BUFWREN_DISABLE_Val  << SDHC_PSR_BUFWREN_Pos)
#define SDHC_PSR_BUFWREN_ENABLE     (SDHC_PSR_BUFWREN_ENABLE_Val   << SDHC_PSR_BUFWREN_Pos)
#define SDHC_PSR_BUFRDEN_Pos        11           
#define SDHC_PSR_BUFRDEN            (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos)
#define   SDHC_PSR_BUFRDEN_DISABLE_Val    _U_(0x0)   
#define   SDHC_PSR_BUFRDEN_ENABLE_Val     _U_(0x1)   
#define SDHC_PSR_BUFRDEN_DISABLE    (SDHC_PSR_BUFRDEN_DISABLE_Val  << SDHC_PSR_BUFRDEN_Pos)
#define SDHC_PSR_BUFRDEN_ENABLE     (SDHC_PSR_BUFRDEN_ENABLE_Val   << SDHC_PSR_BUFRDEN_Pos)
#define SDHC_PSR_CARDINS_Pos        16           
#define SDHC_PSR_CARDINS            (_U_(0x1) << SDHC_PSR_CARDINS_Pos)
#define   SDHC_PSR_CARDINS_NO_Val         _U_(0x0)   
#define   SDHC_PSR_CARDINS_YES_Val        _U_(0x1)   
#define SDHC_PSR_CARDINS_NO         (SDHC_PSR_CARDINS_NO_Val       << SDHC_PSR_CARDINS_Pos)
#define SDHC_PSR_CARDINS_YES        (SDHC_PSR_CARDINS_YES_Val      << SDHC_PSR_CARDINS_Pos)
#define SDHC_PSR_CARDSS_Pos         17           
#define SDHC_PSR_CARDSS             (_U_(0x1) << SDHC_PSR_CARDSS_Pos)
#define   SDHC_PSR_CARDSS_NO_Val          _U_(0x0)   
#define   SDHC_PSR_CARDSS_YES_Val         _U_(0x1)   
#define SDHC_PSR_CARDSS_NO          (SDHC_PSR_CARDSS_NO_Val        << SDHC_PSR_CARDSS_Pos)
#define SDHC_PSR_CARDSS_YES         (SDHC_PSR_CARDSS_YES_Val       << SDHC_PSR_CARDSS_Pos)
#define SDHC_PSR_CARDDPL_Pos        18           
#define SDHC_PSR_CARDDPL            (_U_(0x1) << SDHC_PSR_CARDDPL_Pos)
#define   SDHC_PSR_CARDDPL_NO_Val         _U_(0x0)   
#define   SDHC_PSR_CARDDPL_YES_Val        _U_(0x1)   
#define SDHC_PSR_CARDDPL_NO         (SDHC_PSR_CARDDPL_NO_Val       << SDHC_PSR_CARDDPL_Pos)
#define SDHC_PSR_CARDDPL_YES        (SDHC_PSR_CARDDPL_YES_Val      << SDHC_PSR_CARDDPL_Pos)
#define SDHC_PSR_WRPPL_Pos          19           
#define SDHC_PSR_WRPPL              (_U_(0x1) << SDHC_PSR_WRPPL_Pos)
#define   SDHC_PSR_WRPPL_PROTECTED_Val    _U_(0x0)   
#define   SDHC_PSR_WRPPL_ENABLED_Val      _U_(0x1)   
#define SDHC_PSR_WRPPL_PROTECTED    (SDHC_PSR_WRPPL_PROTECTED_Val  << SDHC_PSR_WRPPL_Pos)
#define SDHC_PSR_WRPPL_ENABLED      (SDHC_PSR_WRPPL_ENABLED_Val    << SDHC_PSR_WRPPL_Pos)
#define SDHC_PSR_DATLL_Pos          20           
#define SDHC_PSR_DATLL_Msk          (_U_(0xF) << SDHC_PSR_DATLL_Pos)
#define SDHC_PSR_DATLL(value)       (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos))
#define SDHC_PSR_CMDLL_Pos          24           
#define SDHC_PSR_CMDLL              (_U_(0x1) << SDHC_PSR_CMDLL_Pos)
#define SDHC_PSR_MASK               _U_(0x01FF0F0F) 
/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W  8) Host Control 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  LEDCTRL:1;        
    uint8_t  DW:1;             
    uint8_t  HSEN:1;           
    uint8_t  DMASEL:2;         
    uint8_t  :1;               
    uint8_t  CARDDTL:1;        
    uint8_t  CARDDSEL:1;       
  } bit;                       
  struct { // EMMC mode
    uint8_t  :1;               
    uint8_t  DW:1;             
    uint8_t  HSEN:1;           
    uint8_t  DMASEL:2;         
    uint8_t  :3;               
  } EMMC;                      
  uint8_t reg;                 
} SDHC_HC1R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_HC1R_OFFSET            0x028        
#define SDHC_HC1R_RESETVALUE        _U_(0xE00)   
#define SDHC_HC1R_LEDCTRL_Pos       0            
#define SDHC_HC1R_LEDCTRL           (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos)
#define   SDHC_HC1R_LEDCTRL_OFF_Val       _U_(0x0)   
#define   SDHC_HC1R_LEDCTRL_ON_Val        _U_(0x1)   
#define SDHC_HC1R_LEDCTRL_OFF       (SDHC_HC1R_LEDCTRL_OFF_Val     << SDHC_HC1R_LEDCTRL_Pos)
#define SDHC_HC1R_LEDCTRL_ON        (SDHC_HC1R_LEDCTRL_ON_Val      << SDHC_HC1R_LEDCTRL_Pos)
#define SDHC_HC1R_DW_Pos            1            
#define SDHC_HC1R_DW                (_U_(0x1) << SDHC_HC1R_DW_Pos)
#define   SDHC_HC1R_DW_1BIT_Val           _U_(0x0)   
#define   SDHC_HC1R_DW_4BIT_Val           _U_(0x1)   
#define SDHC_HC1R_DW_1BIT           (SDHC_HC1R_DW_1BIT_Val         << SDHC_HC1R_DW_Pos)
#define SDHC_HC1R_DW_4BIT           (SDHC_HC1R_DW_4BIT_Val         << SDHC_HC1R_DW_Pos)
#define SDHC_HC1R_HSEN_Pos          2            
#define SDHC_HC1R_HSEN              (_U_(0x1) << SDHC_HC1R_HSEN_Pos)
#define   SDHC_HC1R_HSEN_NORMAL_Val       _U_(0x0)   
#define   SDHC_HC1R_HSEN_HIGH_Val         _U_(0x1)   
#define SDHC_HC1R_HSEN_NORMAL       (SDHC_HC1R_HSEN_NORMAL_Val     << SDHC_HC1R_HSEN_Pos)
#define SDHC_HC1R_HSEN_HIGH         (SDHC_HC1R_HSEN_HIGH_Val       << SDHC_HC1R_HSEN_Pos)
#define SDHC_HC1R_DMASEL_Pos        3            
#define SDHC_HC1R_DMASEL_Msk        (_U_(0x3) << SDHC_HC1R_DMASEL_Pos)
#define SDHC_HC1R_DMASEL(value)     (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos))
#define   SDHC_HC1R_DMASEL_SDMA_Val       _U_(0x0)   
#define   SDHC_HC1R_DMASEL_1_Val          _U_(0x1)   
#define   SDHC_HC1R_DMASEL_32BIT_Val      _U_(0x2)   
#define SDHC_HC1R_DMASEL_SDMA       (SDHC_HC1R_DMASEL_SDMA_Val     << SDHC_HC1R_DMASEL_Pos)
#define SDHC_HC1R_DMASEL_1          (SDHC_HC1R_DMASEL_1_Val        << SDHC_HC1R_DMASEL_Pos)
#define SDHC_HC1R_DMASEL_32BIT      (SDHC_HC1R_DMASEL_32BIT_Val    << SDHC_HC1R_DMASEL_Pos)
#define SDHC_HC1R_CARDDTL_Pos       6            
#define SDHC_HC1R_CARDDTL           (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos)
#define   SDHC_HC1R_CARDDTL_NO_Val        _U_(0x0)   
#define   SDHC_HC1R_CARDDTL_YES_Val       _U_(0x1)   
#define SDHC_HC1R_CARDDTL_NO        (SDHC_HC1R_CARDDTL_NO_Val      << SDHC_HC1R_CARDDTL_Pos)
#define SDHC_HC1R_CARDDTL_YES       (SDHC_HC1R_CARDDTL_YES_Val     << SDHC_HC1R_CARDDTL_Pos)
#define SDHC_HC1R_CARDDSEL_Pos      7            
#define SDHC_HC1R_CARDDSEL          (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos)
#define   SDHC_HC1R_CARDDSEL_NORMAL_Val   _U_(0x0)   
#define   SDHC_HC1R_CARDDSEL_TEST_Val     _U_(0x1)   
#define SDHC_HC1R_CARDDSEL_NORMAL   (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos)
#define SDHC_HC1R_CARDDSEL_TEST     (SDHC_HC1R_CARDDSEL_TEST_Val   << SDHC_HC1R_CARDDSEL_Pos)
#define SDHC_HC1R_MASK              _U_(0xDF)    
// EMMC mode
#define SDHC_HC1R_EMMC_DW_Pos       1            
#define SDHC_HC1R_EMMC_DW           (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos)
#define   SDHC_HC1R_EMMC_DW_1BIT_Val      _U_(0x0)   
#define   SDHC_HC1R_EMMC_DW_4BIT_Val      _U_(0x1)   
#define SDHC_HC1R_EMMC_DW_1BIT      (SDHC_HC1R_EMMC_DW_1BIT_Val    << SDHC_HC1R_EMMC_DW_Pos)
#define SDHC_HC1R_EMMC_DW_4BIT      (SDHC_HC1R_EMMC_DW_4BIT_Val    << SDHC_HC1R_EMMC_DW_Pos)
#define SDHC_HC1R_EMMC_HSEN_Pos     2            
#define SDHC_HC1R_EMMC_HSEN         (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos)
#define   SDHC_HC1R_EMMC_HSEN_NORMAL_Val  _U_(0x0)   
#define   SDHC_HC1R_EMMC_HSEN_HIGH_Val    _U_(0x1)   
#define SDHC_HC1R_EMMC_HSEN_NORMAL  (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos)
#define SDHC_HC1R_EMMC_HSEN_HIGH    (SDHC_HC1R_EMMC_HSEN_HIGH_Val  << SDHC_HC1R_EMMC_HSEN_Pos)
#define SDHC_HC1R_EMMC_DMASEL_Pos   3            
#define SDHC_HC1R_EMMC_DMASEL_Msk   (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos)
#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos))
#define   SDHC_HC1R_EMMC_DMASEL_SDMA_Val  _U_(0x0)   
#define   SDHC_HC1R_EMMC_DMASEL_1_Val     _U_(0x1)   
#define   SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2)   
#define SDHC_HC1R_EMMC_DMASEL_SDMA  (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
#define SDHC_HC1R_EMMC_DMASEL_1     (SDHC_HC1R_EMMC_DMASEL_1_Val   << SDHC_HC1R_EMMC_DMASEL_Pos)
#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
#define SDHC_HC1R_EMMC_MASK         _U_(0x1E)    
/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W  8) Power Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  SDBPWR:1;         
    uint8_t  SDBVSEL:3;        
    uint8_t  :4;               
  } bit;                       
  uint8_t reg;                 
} SDHC_PCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_PCR_OFFSET             0x029        
#define SDHC_PCR_RESETVALUE         _U_(0x0E)    
#define SDHC_PCR_SDBPWR_Pos         0            
#define SDHC_PCR_SDBPWR             (_U_(0x1) << SDHC_PCR_SDBPWR_Pos)
#define   SDHC_PCR_SDBPWR_OFF_Val         _U_(0x0)   
#define   SDHC_PCR_SDBPWR_ON_Val          _U_(0x1)   
#define SDHC_PCR_SDBPWR_OFF         (SDHC_PCR_SDBPWR_OFF_Val       << SDHC_PCR_SDBPWR_Pos)
#define SDHC_PCR_SDBPWR_ON          (SDHC_PCR_SDBPWR_ON_Val        << SDHC_PCR_SDBPWR_Pos)
#define SDHC_PCR_SDBVSEL_Pos        1            
#define SDHC_PCR_SDBVSEL_Msk        (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos)
#define SDHC_PCR_SDBVSEL(value)     (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos))
#define   SDHC_PCR_SDBVSEL_1V8_Val        _U_(0x5)   
#define   SDHC_PCR_SDBVSEL_3V0_Val        _U_(0x6)   
#define   SDHC_PCR_SDBVSEL_3V3_Val        _U_(0x7)   
#define SDHC_PCR_SDBVSEL_1V8        (SDHC_PCR_SDBVSEL_1V8_Val      << SDHC_PCR_SDBVSEL_Pos)
#define SDHC_PCR_SDBVSEL_3V0        (SDHC_PCR_SDBVSEL_3V0_Val      << SDHC_PCR_SDBVSEL_Pos)
#define SDHC_PCR_SDBVSEL_3V3        (SDHC_PCR_SDBVSEL_3V3_Val      << SDHC_PCR_SDBVSEL_Pos)
#define SDHC_PCR_MASK               _U_(0x0F)    
/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W  8) Block Gap Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  STPBGR:1;         
    uint8_t  CONTR:1;          
    uint8_t  RWCTRL:1;         
    uint8_t  INTBG:1;          
    uint8_t  :4;               
  } bit;                       
  struct { // EMMC mode
    uint8_t  STPBGR:1;         
    uint8_t  CONTR:1;          
    uint8_t  :6;               
  } EMMC;                      
  uint8_t reg;                 
} SDHC_BGCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_BGCR_OFFSET            0x02A        
#define SDHC_BGCR_RESETVALUE        _U_(0x00)    
#define SDHC_BGCR_STPBGR_Pos        0            
#define SDHC_BGCR_STPBGR            (_U_(0x1) << SDHC_BGCR_STPBGR_Pos)
#define   SDHC_BGCR_STPBGR_TRANSFER_Val   _U_(0x0)   
#define   SDHC_BGCR_STPBGR_STOP_Val       _U_(0x1)   
#define SDHC_BGCR_STPBGR_TRANSFER   (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos)
#define SDHC_BGCR_STPBGR_STOP       (SDHC_BGCR_STPBGR_STOP_Val     << SDHC_BGCR_STPBGR_Pos)
#define SDHC_BGCR_CONTR_Pos         1            
#define SDHC_BGCR_CONTR             (_U_(0x1) << SDHC_BGCR_CONTR_Pos)
#define   SDHC_BGCR_CONTR_GO_ON_Val       _U_(0x0)   
#define   SDHC_BGCR_CONTR_RESTART_Val     _U_(0x1)   
#define SDHC_BGCR_CONTR_GO_ON       (SDHC_BGCR_CONTR_GO_ON_Val     << SDHC_BGCR_CONTR_Pos)
#define SDHC_BGCR_CONTR_RESTART     (SDHC_BGCR_CONTR_RESTART_Val   << SDHC_BGCR_CONTR_Pos)
#define SDHC_BGCR_RWCTRL_Pos        2            
#define SDHC_BGCR_RWCTRL            (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos)
#define   SDHC_BGCR_RWCTRL_DISABLE_Val    _U_(0x0)   
#define   SDHC_BGCR_RWCTRL_ENABLE_Val     _U_(0x1)   
#define SDHC_BGCR_RWCTRL_DISABLE    (SDHC_BGCR_RWCTRL_DISABLE_Val  << SDHC_BGCR_RWCTRL_Pos)
#define SDHC_BGCR_RWCTRL_ENABLE     (SDHC_BGCR_RWCTRL_ENABLE_Val   << SDHC_BGCR_RWCTRL_Pos)
#define SDHC_BGCR_INTBG_Pos         3            
#define SDHC_BGCR_INTBG             (_U_(0x1) << SDHC_BGCR_INTBG_Pos)
#define   SDHC_BGCR_INTBG_DISABLED_Val    _U_(0x0)   
#define   SDHC_BGCR_INTBG_ENABLED_Val     _U_(0x1)   
#define SDHC_BGCR_INTBG_DISABLED    (SDHC_BGCR_INTBG_DISABLED_Val  << SDHC_BGCR_INTBG_Pos)
#define SDHC_BGCR_INTBG_ENABLED     (SDHC_BGCR_INTBG_ENABLED_Val   << SDHC_BGCR_INTBG_Pos)
#define SDHC_BGCR_MASK              _U_(0x0F)    
// EMMC mode
#define SDHC_BGCR_EMMC_STPBGR_Pos   0            
#define SDHC_BGCR_EMMC_STPBGR       (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos)
#define   SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0)   
#define   SDHC_BGCR_EMMC_STPBGR_STOP_Val  _U_(0x1)   
#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
#define SDHC_BGCR_EMMC_STPBGR_STOP  (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
#define SDHC_BGCR_EMMC_CONTR_Pos    1            
#define SDHC_BGCR_EMMC_CONTR        (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos)
#define   SDHC_BGCR_EMMC_CONTR_GO_ON_Val  _U_(0x0)   
#define   SDHC_BGCR_EMMC_CONTR_RESTART_Val _U_(0x1)   
#define SDHC_BGCR_EMMC_CONTR_GO_ON  (SDHC_BGCR_EMMC_CONTR_GO_ON_Val << SDHC_BGCR_EMMC_CONTR_Pos)
#define SDHC_BGCR_EMMC_CONTR_RESTART (SDHC_BGCR_EMMC_CONTR_RESTART_Val << SDHC_BGCR_EMMC_CONTR_Pos)
#define SDHC_BGCR_EMMC_MASK         _U_(0x03)    
/* -------- SDHC_WCR : (SDHC Offset: 0x02B) (R/W  8) Wakeup Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  WKENCINT:1;       
    uint8_t  WKENCINS:1;       
    uint8_t  WKENCREM:1;       
    uint8_t  :5;               
  } bit;                       
  uint8_t reg;                 
} SDHC_WCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_WCR_OFFSET             0x02B        
#define SDHC_WCR_RESETVALUE         _U_(0x00)    
#define SDHC_WCR_WKENCINT_Pos       0            
#define SDHC_WCR_WKENCINT           (_U_(0x1) << SDHC_WCR_WKENCINT_Pos)
#define   SDHC_WCR_WKENCINT_DISABLE_Val   _U_(0x0)   
#define   SDHC_WCR_WKENCINT_ENABLE_Val    _U_(0x1)   
#define SDHC_WCR_WKENCINT_DISABLE   (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos)
#define SDHC_WCR_WKENCINT_ENABLE    (SDHC_WCR_WKENCINT_ENABLE_Val  << SDHC_WCR_WKENCINT_Pos)
#define SDHC_WCR_WKENCINS_Pos       1            
#define SDHC_WCR_WKENCINS           (_U_(0x1) << SDHC_WCR_WKENCINS_Pos)
#define   SDHC_WCR_WKENCINS_DISABLE_Val   _U_(0x0)   
#define   SDHC_WCR_WKENCINS_ENABLE_Val    _U_(0x1)   
#define SDHC_WCR_WKENCINS_DISABLE   (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos)
#define SDHC_WCR_WKENCINS_ENABLE    (SDHC_WCR_WKENCINS_ENABLE_Val  << SDHC_WCR_WKENCINS_Pos)
#define SDHC_WCR_WKENCREM_Pos       2            
#define SDHC_WCR_WKENCREM           (_U_(0x1) << SDHC_WCR_WKENCREM_Pos)
#define   SDHC_WCR_WKENCREM_DISABLE_Val   _U_(0x0)   
#define   SDHC_WCR_WKENCREM_ENABLE_Val    _U_(0x1)   
#define SDHC_WCR_WKENCREM_DISABLE   (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos)
#define SDHC_WCR_WKENCREM_ENABLE    (SDHC_WCR_WKENCREM_ENABLE_Val  << SDHC_WCR_WKENCREM_Pos)
#define SDHC_WCR_MASK               _U_(0x07)    
/* -------- SDHC_CCR : (SDHC Offset: 0x02C) (R/W 16) Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t INTCLKEN:1;       
    uint16_t INTCLKS:1;        
    uint16_t SDCLKEN:1;        
    uint16_t :2;               
    uint16_t CLKGSEL:1;        
    uint16_t USDCLKFSEL:2;     
    uint16_t SDCLKFSEL:8;      
  } bit;                       
  uint16_t reg;                
} SDHC_CCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_CCR_OFFSET             0x02C        
#define SDHC_CCR_RESETVALUE         _U_(0x0000)  
#define SDHC_CCR_INTCLKEN_Pos       0            
#define SDHC_CCR_INTCLKEN           (_U_(0x1) << SDHC_CCR_INTCLKEN_Pos)
#define   SDHC_CCR_INTCLKEN_OFF_Val       _U_(0x0)   
#define   SDHC_CCR_INTCLKEN_ON_Val        _U_(0x1)   
#define SDHC_CCR_INTCLKEN_OFF       (SDHC_CCR_INTCLKEN_OFF_Val     << SDHC_CCR_INTCLKEN_Pos)
#define SDHC_CCR_INTCLKEN_ON        (SDHC_CCR_INTCLKEN_ON_Val      << SDHC_CCR_INTCLKEN_Pos)
#define SDHC_CCR_INTCLKS_Pos        1            
#define SDHC_CCR_INTCLKS            (_U_(0x1) << SDHC_CCR_INTCLKS_Pos)
#define   SDHC_CCR_INTCLKS_NOT_READY_Val  _U_(0x0)   
#define   SDHC_CCR_INTCLKS_READY_Val      _U_(0x1)   
#define SDHC_CCR_INTCLKS_NOT_READY  (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos)
#define SDHC_CCR_INTCLKS_READY      (SDHC_CCR_INTCLKS_READY_Val    << SDHC_CCR_INTCLKS_Pos)
#define SDHC_CCR_SDCLKEN_Pos        2            
#define SDHC_CCR_SDCLKEN            (_U_(0x1) << SDHC_CCR_SDCLKEN_Pos)
#define   SDHC_CCR_SDCLKEN_DISABLE_Val    _U_(0x0)   
#define   SDHC_CCR_SDCLKEN_ENABLE_Val     _U_(0x1)   
#define SDHC_CCR_SDCLKEN_DISABLE    (SDHC_CCR_SDCLKEN_DISABLE_Val  << SDHC_CCR_SDCLKEN_Pos)
#define SDHC_CCR_SDCLKEN_ENABLE     (SDHC_CCR_SDCLKEN_ENABLE_Val   << SDHC_CCR_SDCLKEN_Pos)
#define SDHC_CCR_CLKGSEL_Pos        5            
#define SDHC_CCR_CLKGSEL            (_U_(0x1) << SDHC_CCR_CLKGSEL_Pos)
#define   SDHC_CCR_CLKGSEL_DIV_Val        _U_(0x0)   
#define   SDHC_CCR_CLKGSEL_PROG_Val       _U_(0x1)   
#define SDHC_CCR_CLKGSEL_DIV        (SDHC_CCR_CLKGSEL_DIV_Val      << SDHC_CCR_CLKGSEL_Pos)
#define SDHC_CCR_CLKGSEL_PROG       (SDHC_CCR_CLKGSEL_PROG_Val     << SDHC_CCR_CLKGSEL_Pos)
#define SDHC_CCR_USDCLKFSEL_Pos     6            
#define SDHC_CCR_USDCLKFSEL_Msk     (_U_(0x3) << SDHC_CCR_USDCLKFSEL_Pos)
#define SDHC_CCR_USDCLKFSEL(value)  (SDHC_CCR_USDCLKFSEL_Msk & ((value) << SDHC_CCR_USDCLKFSEL_Pos))
#define SDHC_CCR_SDCLKFSEL_Pos      8            
#define SDHC_CCR_SDCLKFSEL_Msk      (_U_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos)
#define SDHC_CCR_SDCLKFSEL(value)   (SDHC_CCR_SDCLKFSEL_Msk & ((value) << SDHC_CCR_SDCLKFSEL_Pos))
#define SDHC_CCR_MASK               _U_(0xFFE7)  
/* -------- SDHC_TCR : (SDHC Offset: 0x02E) (R/W  8) Timeout Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  DTCVAL:4;         
    uint8_t  :4;               
  } bit;                       
  uint8_t reg;                 
} SDHC_TCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_TCR_OFFSET             0x02E        
#define SDHC_TCR_RESETVALUE         _U_(0x00)    
#define SDHC_TCR_DTCVAL_Pos         0            
#define SDHC_TCR_DTCVAL_Msk         (_U_(0xF) << SDHC_TCR_DTCVAL_Pos)
#define SDHC_TCR_DTCVAL(value)      (SDHC_TCR_DTCVAL_Msk & ((value) << SDHC_TCR_DTCVAL_Pos))
#define SDHC_TCR_MASK               _U_(0x0F)    
/* -------- SDHC_SRR : (SDHC Offset: 0x02F) (R/W  8) Software Reset -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  SWRSTALL:1;       
    uint8_t  SWRSTCMD:1;       
    uint8_t  SWRSTDAT:1;       
    uint8_t  :5;               
  } bit;                       
  uint8_t reg;                 
} SDHC_SRR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_SRR_OFFSET             0x02F        
#define SDHC_SRR_RESETVALUE         _U_(0x00)    
#define SDHC_SRR_SWRSTALL_Pos       0            
#define SDHC_SRR_SWRSTALL           (_U_(0x1) << SDHC_SRR_SWRSTALL_Pos)
#define   SDHC_SRR_SWRSTALL_WORK_Val      _U_(0x0)   
#define   SDHC_SRR_SWRSTALL_RESET_Val     _U_(0x1)   
#define SDHC_SRR_SWRSTALL_WORK      (SDHC_SRR_SWRSTALL_WORK_Val    << SDHC_SRR_SWRSTALL_Pos)
#define SDHC_SRR_SWRSTALL_RESET     (SDHC_SRR_SWRSTALL_RESET_Val   << SDHC_SRR_SWRSTALL_Pos)
#define SDHC_SRR_SWRSTCMD_Pos       1            
#define SDHC_SRR_SWRSTCMD           (_U_(0x1) << SDHC_SRR_SWRSTCMD_Pos)
#define   SDHC_SRR_SWRSTCMD_WORK_Val      _U_(0x0)   
#define   SDHC_SRR_SWRSTCMD_RESET_Val     _U_(0x1)   
#define SDHC_SRR_SWRSTCMD_WORK      (SDHC_SRR_SWRSTCMD_WORK_Val    << SDHC_SRR_SWRSTCMD_Pos)
#define SDHC_SRR_SWRSTCMD_RESET     (SDHC_SRR_SWRSTCMD_RESET_Val   << SDHC_SRR_SWRSTCMD_Pos)
#define SDHC_SRR_SWRSTDAT_Pos       2            
#define SDHC_SRR_SWRSTDAT           (_U_(0x1) << SDHC_SRR_SWRSTDAT_Pos)
#define   SDHC_SRR_SWRSTDAT_WORK_Val      _U_(0x0)   
#define   SDHC_SRR_SWRSTDAT_RESET_Val     _U_(0x1)   
#define SDHC_SRR_SWRSTDAT_WORK      (SDHC_SRR_SWRSTDAT_WORK_Val    << SDHC_SRR_SWRSTDAT_Pos)
#define SDHC_SRR_SWRSTDAT_RESET     (SDHC_SRR_SWRSTDAT_RESET_Val   << SDHC_SRR_SWRSTDAT_Pos)
#define SDHC_SRR_MASK               _U_(0x07)    
/* -------- SDHC_NISTR : (SDHC Offset: 0x030) (R/W 16) Normal Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CMDC:1;           
    uint16_t TRFC:1;           
    uint16_t BLKGE:1;          
    uint16_t DMAINT:1;         
    uint16_t BWRRDY:1;         
    uint16_t BRDRDY:1;         
    uint16_t CINS:1;           
    uint16_t CREM:1;           
    uint16_t CINT:1;           
    uint16_t :6;               
    uint16_t ERRINT:1;         
  } bit;                       
  struct { // EMMC mode
    uint16_t CMDC:1;           
    uint16_t TRFC:1;           
    uint16_t BLKGE:1;          
    uint16_t DMAINT:1;         
    uint16_t BWRRDY:1;         
    uint16_t BRDRDY:1;         
    uint16_t :8;               
    uint16_t BOOTAR:1;         
    uint16_t ERRINT:1;         
  } EMMC;                      
  uint16_t reg;                
} SDHC_NISTR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_NISTR_OFFSET           0x030        
#define SDHC_NISTR_RESETVALUE       _U_(0x0000)  
#define SDHC_NISTR_CMDC_Pos         0            
#define SDHC_NISTR_CMDC             (_U_(0x1) << SDHC_NISTR_CMDC_Pos)
#define   SDHC_NISTR_CMDC_NO_Val          _U_(0x0)   
#define   SDHC_NISTR_CMDC_YES_Val         _U_(0x1)   
#define SDHC_NISTR_CMDC_NO          (SDHC_NISTR_CMDC_NO_Val        << SDHC_NISTR_CMDC_Pos)
#define SDHC_NISTR_CMDC_YES         (SDHC_NISTR_CMDC_YES_Val       << SDHC_NISTR_CMDC_Pos)
#define SDHC_NISTR_TRFC_Pos         1            
#define SDHC_NISTR_TRFC             (_U_(0x1) << SDHC_NISTR_TRFC_Pos)
#define   SDHC_NISTR_TRFC_NO_Val          _U_(0x0)   
#define   SDHC_NISTR_TRFC_YES_Val         _U_(0x1)   
#define SDHC_NISTR_TRFC_NO          (SDHC_NISTR_TRFC_NO_Val        << SDHC_NISTR_TRFC_Pos)
#define SDHC_NISTR_TRFC_YES         (SDHC_NISTR_TRFC_YES_Val       << SDHC_NISTR_TRFC_Pos)
#define SDHC_NISTR_BLKGE_Pos        2            
#define SDHC_NISTR_BLKGE            (_U_(0x1) << SDHC_NISTR_BLKGE_Pos)
#define   SDHC_NISTR_BLKGE_NO_Val         _U_(0x0)   
#define   SDHC_NISTR_BLKGE_STOP_Val       _U_(0x1)   
#define SDHC_NISTR_BLKGE_NO         (SDHC_NISTR_BLKGE_NO_Val       << SDHC_NISTR_BLKGE_Pos)
#define SDHC_NISTR_BLKGE_STOP       (SDHC_NISTR_BLKGE_STOP_Val     << SDHC_NISTR_BLKGE_Pos)
#define SDHC_NISTR_DMAINT_Pos       3            
#define SDHC_NISTR_DMAINT           (_U_(0x1) << SDHC_NISTR_DMAINT_Pos)
#define   SDHC_NISTR_DMAINT_NO_Val        _U_(0x0)   
#define   SDHC_NISTR_DMAINT_YES_Val       _U_(0x1)   
#define SDHC_NISTR_DMAINT_NO        (SDHC_NISTR_DMAINT_NO_Val      << SDHC_NISTR_DMAINT_Pos)
#define SDHC_NISTR_DMAINT_YES       (SDHC_NISTR_DMAINT_YES_Val     << SDHC_NISTR_DMAINT_Pos)
#define SDHC_NISTR_BWRRDY_Pos       4            
#define SDHC_NISTR_BWRRDY           (_U_(0x1) << SDHC_NISTR_BWRRDY_Pos)
#define   SDHC_NISTR_BWRRDY_NO_Val        _U_(0x0)   
#define   SDHC_NISTR_BWRRDY_YES_Val       _U_(0x1)   
#define SDHC_NISTR_BWRRDY_NO        (SDHC_NISTR_BWRRDY_NO_Val      << SDHC_NISTR_BWRRDY_Pos)
#define SDHC_NISTR_BWRRDY_YES       (SDHC_NISTR_BWRRDY_YES_Val     << SDHC_NISTR_BWRRDY_Pos)
#define SDHC_NISTR_BRDRDY_Pos       5            
#define SDHC_NISTR_BRDRDY           (_U_(0x1) << SDHC_NISTR_BRDRDY_Pos)
#define   SDHC_NISTR_BRDRDY_NO_Val        _U_(0x0)   
#define   SDHC_NISTR_BRDRDY_YES_Val       _U_(0x1)   
#define SDHC_NISTR_BRDRDY_NO        (SDHC_NISTR_BRDRDY_NO_Val      << SDHC_NISTR_BRDRDY_Pos)
#define SDHC_NISTR_BRDRDY_YES       (SDHC_NISTR_BRDRDY_YES_Val     << SDHC_NISTR_BRDRDY_Pos)
#define SDHC_NISTR_CINS_Pos         6            
#define SDHC_NISTR_CINS             (_U_(0x1) << SDHC_NISTR_CINS_Pos)
#define   SDHC_NISTR_CINS_NO_Val          _U_(0x0)   
#define   SDHC_NISTR_CINS_YES_Val         _U_(0x1)   
#define SDHC_NISTR_CINS_NO          (SDHC_NISTR_CINS_NO_Val        << SDHC_NISTR_CINS_Pos)
#define SDHC_NISTR_CINS_YES         (SDHC_NISTR_CINS_YES_Val       << SDHC_NISTR_CINS_Pos)
#define SDHC_NISTR_CREM_Pos         7            
#define SDHC_NISTR_CREM             (_U_(0x1) << SDHC_NISTR_CREM_Pos)
#define   SDHC_NISTR_CREM_NO_Val          _U_(0x0)   
#define   SDHC_NISTR_CREM_YES_Val         _U_(0x1)   
#define SDHC_NISTR_CREM_NO          (SDHC_NISTR_CREM_NO_Val        << SDHC_NISTR_CREM_Pos)
#define SDHC_NISTR_CREM_YES         (SDHC_NISTR_CREM_YES_Val       << SDHC_NISTR_CREM_Pos)
#define SDHC_NISTR_CINT_Pos         8            
#define SDHC_NISTR_CINT             (_U_(0x1) << SDHC_NISTR_CINT_Pos)
#define   SDHC_NISTR_CINT_NO_Val          _U_(0x0)   
#define   SDHC_NISTR_CINT_YES_Val         _U_(0x1)   
#define SDHC_NISTR_CINT_NO          (SDHC_NISTR_CINT_NO_Val        << SDHC_NISTR_CINT_Pos)
#define SDHC_NISTR_CINT_YES         (SDHC_NISTR_CINT_YES_Val       << SDHC_NISTR_CINT_Pos)
#define SDHC_NISTR_ERRINT_Pos       15           
#define SDHC_NISTR_ERRINT           (_U_(0x1) << SDHC_NISTR_ERRINT_Pos)
#define   SDHC_NISTR_ERRINT_NO_Val        _U_(0x0)   
#define   SDHC_NISTR_ERRINT_YES_Val       _U_(0x1)   
#define SDHC_NISTR_ERRINT_NO        (SDHC_NISTR_ERRINT_NO_Val      << SDHC_NISTR_ERRINT_Pos)
#define SDHC_NISTR_ERRINT_YES       (SDHC_NISTR_ERRINT_YES_Val     << SDHC_NISTR_ERRINT_Pos)
#define SDHC_NISTR_MASK             _U_(0x81FF)  
// EMMC mode
#define SDHC_NISTR_EMMC_CMDC_Pos    0            
#define SDHC_NISTR_EMMC_CMDC        (_U_(0x1) << SDHC_NISTR_EMMC_CMDC_Pos)
#define   SDHC_NISTR_EMMC_CMDC_NO_Val     _U_(0x0)   
#define   SDHC_NISTR_EMMC_CMDC_YES_Val    _U_(0x1)   
#define SDHC_NISTR_EMMC_CMDC_NO     (SDHC_NISTR_EMMC_CMDC_NO_Val   << SDHC_NISTR_EMMC_CMDC_Pos)
#define SDHC_NISTR_EMMC_CMDC_YES    (SDHC_NISTR_EMMC_CMDC_YES_Val  << SDHC_NISTR_EMMC_CMDC_Pos)
#define SDHC_NISTR_EMMC_TRFC_Pos    1            
#define SDHC_NISTR_EMMC_TRFC        (_U_(0x1) << SDHC_NISTR_EMMC_TRFC_Pos)
#define   SDHC_NISTR_EMMC_TRFC_NO_Val     _U_(0x0)   
#define   SDHC_NISTR_EMMC_TRFC_YES_Val    _U_(0x1)   
#define SDHC_NISTR_EMMC_TRFC_NO     (SDHC_NISTR_EMMC_TRFC_NO_Val   << SDHC_NISTR_EMMC_TRFC_Pos)
#define SDHC_NISTR_EMMC_TRFC_YES    (SDHC_NISTR_EMMC_TRFC_YES_Val  << SDHC_NISTR_EMMC_TRFC_Pos)
#define SDHC_NISTR_EMMC_BLKGE_Pos   2            
#define SDHC_NISTR_EMMC_BLKGE       (_U_(0x1) << SDHC_NISTR_EMMC_BLKGE_Pos)
#define   SDHC_NISTR_EMMC_BLKGE_NO_Val    _U_(0x0)   
#define   SDHC_NISTR_EMMC_BLKGE_STOP_Val  _U_(0x1)   
#define SDHC_NISTR_EMMC_BLKGE_NO    (SDHC_NISTR_EMMC_BLKGE_NO_Val  << SDHC_NISTR_EMMC_BLKGE_Pos)
#define SDHC_NISTR_EMMC_BLKGE_STOP  (SDHC_NISTR_EMMC_BLKGE_STOP_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
#define SDHC_NISTR_EMMC_DMAINT_Pos  3            
#define SDHC_NISTR_EMMC_DMAINT      (_U_(0x1) << SDHC_NISTR_EMMC_DMAINT_Pos)
#define   SDHC_NISTR_EMMC_DMAINT_NO_Val   _U_(0x0)   
#define   SDHC_NISTR_EMMC_DMAINT_YES_Val  _U_(0x1)   
#define SDHC_NISTR_EMMC_DMAINT_NO   (SDHC_NISTR_EMMC_DMAINT_NO_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
#define SDHC_NISTR_EMMC_DMAINT_YES  (SDHC_NISTR_EMMC_DMAINT_YES_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
#define SDHC_NISTR_EMMC_BWRRDY_Pos  4            
#define SDHC_NISTR_EMMC_BWRRDY      (_U_(0x1) << SDHC_NISTR_EMMC_BWRRDY_Pos)
#define   SDHC_NISTR_EMMC_BWRRDY_NO_Val   _U_(0x0)   
#define   SDHC_NISTR_EMMC_BWRRDY_YES_Val  _U_(0x1)   
#define SDHC_NISTR_EMMC_BWRRDY_NO   (SDHC_NISTR_EMMC_BWRRDY_NO_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
#define SDHC_NISTR_EMMC_BWRRDY_YES  (SDHC_NISTR_EMMC_BWRRDY_YES_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
#define SDHC_NISTR_EMMC_BRDRDY_Pos  5            
#define SDHC_NISTR_EMMC_BRDRDY      (_U_(0x1) << SDHC_NISTR_EMMC_BRDRDY_Pos)
#define   SDHC_NISTR_EMMC_BRDRDY_NO_Val   _U_(0x0)   
#define   SDHC_NISTR_EMMC_BRDRDY_YES_Val  _U_(0x1)   
#define SDHC_NISTR_EMMC_BRDRDY_NO   (SDHC_NISTR_EMMC_BRDRDY_NO_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
#define SDHC_NISTR_EMMC_BRDRDY_YES  (SDHC_NISTR_EMMC_BRDRDY_YES_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
#define SDHC_NISTR_EMMC_BOOTAR_Pos  14           
#define SDHC_NISTR_EMMC_BOOTAR      (_U_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos)
#define SDHC_NISTR_EMMC_ERRINT_Pos  15           
#define SDHC_NISTR_EMMC_ERRINT      (_U_(0x1) << SDHC_NISTR_EMMC_ERRINT_Pos)
#define   SDHC_NISTR_EMMC_ERRINT_NO_Val   _U_(0x0)   
#define   SDHC_NISTR_EMMC_ERRINT_YES_Val  _U_(0x1)   
#define SDHC_NISTR_EMMC_ERRINT_NO   (SDHC_NISTR_EMMC_ERRINT_NO_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
#define SDHC_NISTR_EMMC_ERRINT_YES  (SDHC_NISTR_EMMC_ERRINT_YES_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
#define SDHC_NISTR_EMMC_MASK        _U_(0xC03F)  
/* -------- SDHC_EISTR : (SDHC Offset: 0x032) (R/W 16) Error Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CMDTEO:1;         
    uint16_t CMDCRC:1;         
    uint16_t CMDEND:1;         
    uint16_t CMDIDX:1;         
    uint16_t DATTEO:1;         
    uint16_t DATCRC:1;         
    uint16_t DATEND:1;         
    uint16_t CURLIM:1;         
    uint16_t ACMD:1;           
    uint16_t ADMA:1;           
    uint16_t :6;               
  } bit;                       
  struct { // EMMC mode
    uint16_t CMDTEO:1;         
    uint16_t CMDCRC:1;         
    uint16_t CMDEND:1;         
    uint16_t CMDIDX:1;         
    uint16_t DATTEO:1;         
    uint16_t DATCRC:1;         
    uint16_t DATEND:1;         
    uint16_t CURLIM:1;         
    uint16_t ACMD:1;           
    uint16_t ADMA:1;           
    uint16_t :2;               
    uint16_t BOOTAE:1;         
    uint16_t :3;               
  } EMMC;                      
  uint16_t reg;                
} SDHC_EISTR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_EISTR_OFFSET           0x032        
#define SDHC_EISTR_RESETVALUE       _U_(0x0000)  
#define SDHC_EISTR_CMDTEO_Pos       0            
#define SDHC_EISTR_CMDTEO           (_U_(0x1) << SDHC_EISTR_CMDTEO_Pos)
#define   SDHC_EISTR_CMDTEO_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_CMDTEO_YES_Val       _U_(0x1)   
#define SDHC_EISTR_CMDTEO_NO        (SDHC_EISTR_CMDTEO_NO_Val      << SDHC_EISTR_CMDTEO_Pos)
#define SDHC_EISTR_CMDTEO_YES       (SDHC_EISTR_CMDTEO_YES_Val     << SDHC_EISTR_CMDTEO_Pos)
#define SDHC_EISTR_CMDCRC_Pos       1            
#define SDHC_EISTR_CMDCRC           (_U_(0x1) << SDHC_EISTR_CMDCRC_Pos)
#define   SDHC_EISTR_CMDCRC_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_CMDCRC_YES_Val       _U_(0x1)   
#define SDHC_EISTR_CMDCRC_NO        (SDHC_EISTR_CMDCRC_NO_Val      << SDHC_EISTR_CMDCRC_Pos)
#define SDHC_EISTR_CMDCRC_YES       (SDHC_EISTR_CMDCRC_YES_Val     << SDHC_EISTR_CMDCRC_Pos)
#define SDHC_EISTR_CMDEND_Pos       2            
#define SDHC_EISTR_CMDEND           (_U_(0x1) << SDHC_EISTR_CMDEND_Pos)
#define   SDHC_EISTR_CMDEND_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_CMDEND_YES_Val       _U_(0x1)   
#define SDHC_EISTR_CMDEND_NO        (SDHC_EISTR_CMDEND_NO_Val      << SDHC_EISTR_CMDEND_Pos)
#define SDHC_EISTR_CMDEND_YES       (SDHC_EISTR_CMDEND_YES_Val     << SDHC_EISTR_CMDEND_Pos)
#define SDHC_EISTR_CMDIDX_Pos       3            
#define SDHC_EISTR_CMDIDX           (_U_(0x1) << SDHC_EISTR_CMDIDX_Pos)
#define   SDHC_EISTR_CMDIDX_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_CMDIDX_YES_Val       _U_(0x1)   
#define SDHC_EISTR_CMDIDX_NO        (SDHC_EISTR_CMDIDX_NO_Val      << SDHC_EISTR_CMDIDX_Pos)
#define SDHC_EISTR_CMDIDX_YES       (SDHC_EISTR_CMDIDX_YES_Val     << SDHC_EISTR_CMDIDX_Pos)
#define SDHC_EISTR_DATTEO_Pos       4            
#define SDHC_EISTR_DATTEO           (_U_(0x1) << SDHC_EISTR_DATTEO_Pos)
#define   SDHC_EISTR_DATTEO_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_DATTEO_YES_Val       _U_(0x1)   
#define SDHC_EISTR_DATTEO_NO        (SDHC_EISTR_DATTEO_NO_Val      << SDHC_EISTR_DATTEO_Pos)
#define SDHC_EISTR_DATTEO_YES       (SDHC_EISTR_DATTEO_YES_Val     << SDHC_EISTR_DATTEO_Pos)
#define SDHC_EISTR_DATCRC_Pos       5            
#define SDHC_EISTR_DATCRC           (_U_(0x1) << SDHC_EISTR_DATCRC_Pos)
#define   SDHC_EISTR_DATCRC_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_DATCRC_YES_Val       _U_(0x1)   
#define SDHC_EISTR_DATCRC_NO        (SDHC_EISTR_DATCRC_NO_Val      << SDHC_EISTR_DATCRC_Pos)
#define SDHC_EISTR_DATCRC_YES       (SDHC_EISTR_DATCRC_YES_Val     << SDHC_EISTR_DATCRC_Pos)
#define SDHC_EISTR_DATEND_Pos       6            
#define SDHC_EISTR_DATEND           (_U_(0x1) << SDHC_EISTR_DATEND_Pos)
#define   SDHC_EISTR_DATEND_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_DATEND_YES_Val       _U_(0x1)   
#define SDHC_EISTR_DATEND_NO        (SDHC_EISTR_DATEND_NO_Val      << SDHC_EISTR_DATEND_Pos)
#define SDHC_EISTR_DATEND_YES       (SDHC_EISTR_DATEND_YES_Val     << SDHC_EISTR_DATEND_Pos)
#define SDHC_EISTR_CURLIM_Pos       7            
#define SDHC_EISTR_CURLIM           (_U_(0x1) << SDHC_EISTR_CURLIM_Pos)
#define   SDHC_EISTR_CURLIM_NO_Val        _U_(0x0)   
#define   SDHC_EISTR_CURLIM_YES_Val       _U_(0x1)   
#define SDHC_EISTR_CURLIM_NO        (SDHC_EISTR_CURLIM_NO_Val      << SDHC_EISTR_CURLIM_Pos)
#define SDHC_EISTR_CURLIM_YES       (SDHC_EISTR_CURLIM_YES_Val     << SDHC_EISTR_CURLIM_Pos)
#define SDHC_EISTR_ACMD_Pos         8            
#define SDHC_EISTR_ACMD             (_U_(0x1) << SDHC_EISTR_ACMD_Pos)
#define   SDHC_EISTR_ACMD_NO_Val          _U_(0x0)   
#define   SDHC_EISTR_ACMD_YES_Val         _U_(0x1)   
#define SDHC_EISTR_ACMD_NO          (SDHC_EISTR_ACMD_NO_Val        << SDHC_EISTR_ACMD_Pos)
#define SDHC_EISTR_ACMD_YES         (SDHC_EISTR_ACMD_YES_Val       << SDHC_EISTR_ACMD_Pos)
#define SDHC_EISTR_ADMA_Pos         9            
#define SDHC_EISTR_ADMA             (_U_(0x1) << SDHC_EISTR_ADMA_Pos)
#define   SDHC_EISTR_ADMA_NO_Val          _U_(0x0)   
#define   SDHC_EISTR_ADMA_YES_Val         _U_(0x1)   
#define SDHC_EISTR_ADMA_NO          (SDHC_EISTR_ADMA_NO_Val        << SDHC_EISTR_ADMA_Pos)
#define SDHC_EISTR_ADMA_YES         (SDHC_EISTR_ADMA_YES_Val       << SDHC_EISTR_ADMA_Pos)
#define SDHC_EISTR_MASK             _U_(0x03FF)  
// EMMC mode
#define SDHC_EISTR_EMMC_CMDTEO_Pos  0            
#define SDHC_EISTR_EMMC_CMDTEO      (_U_(0x1) << SDHC_EISTR_EMMC_CMDTEO_Pos)
#define   SDHC_EISTR_EMMC_CMDTEO_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_CMDTEO_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_CMDTEO_NO   (SDHC_EISTR_EMMC_CMDTEO_NO_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
#define SDHC_EISTR_EMMC_CMDTEO_YES  (SDHC_EISTR_EMMC_CMDTEO_YES_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
#define SDHC_EISTR_EMMC_CMDCRC_Pos  1            
#define SDHC_EISTR_EMMC_CMDCRC      (_U_(0x1) << SDHC_EISTR_EMMC_CMDCRC_Pos)
#define   SDHC_EISTR_EMMC_CMDCRC_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_CMDCRC_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_CMDCRC_NO   (SDHC_EISTR_EMMC_CMDCRC_NO_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
#define SDHC_EISTR_EMMC_CMDCRC_YES  (SDHC_EISTR_EMMC_CMDCRC_YES_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
#define SDHC_EISTR_EMMC_CMDEND_Pos  2            
#define SDHC_EISTR_EMMC_CMDEND      (_U_(0x1) << SDHC_EISTR_EMMC_CMDEND_Pos)
#define   SDHC_EISTR_EMMC_CMDEND_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_CMDEND_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_CMDEND_NO   (SDHC_EISTR_EMMC_CMDEND_NO_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
#define SDHC_EISTR_EMMC_CMDEND_YES  (SDHC_EISTR_EMMC_CMDEND_YES_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
#define SDHC_EISTR_EMMC_CMDIDX_Pos  3            
#define SDHC_EISTR_EMMC_CMDIDX      (_U_(0x1) << SDHC_EISTR_EMMC_CMDIDX_Pos)
#define   SDHC_EISTR_EMMC_CMDIDX_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_CMDIDX_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_CMDIDX_NO   (SDHC_EISTR_EMMC_CMDIDX_NO_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
#define SDHC_EISTR_EMMC_CMDIDX_YES  (SDHC_EISTR_EMMC_CMDIDX_YES_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
#define SDHC_EISTR_EMMC_DATTEO_Pos  4            
#define SDHC_EISTR_EMMC_DATTEO      (_U_(0x1) << SDHC_EISTR_EMMC_DATTEO_Pos)
#define   SDHC_EISTR_EMMC_DATTEO_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_DATTEO_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_DATTEO_NO   (SDHC_EISTR_EMMC_DATTEO_NO_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
#define SDHC_EISTR_EMMC_DATTEO_YES  (SDHC_EISTR_EMMC_DATTEO_YES_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
#define SDHC_EISTR_EMMC_DATCRC_Pos  5            
#define SDHC_EISTR_EMMC_DATCRC      (_U_(0x1) << SDHC_EISTR_EMMC_DATCRC_Pos)
#define   SDHC_EISTR_EMMC_DATCRC_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_DATCRC_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_DATCRC_NO   (SDHC_EISTR_EMMC_DATCRC_NO_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
#define SDHC_EISTR_EMMC_DATCRC_YES  (SDHC_EISTR_EMMC_DATCRC_YES_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
#define SDHC_EISTR_EMMC_DATEND_Pos  6            
#define SDHC_EISTR_EMMC_DATEND      (_U_(0x1) << SDHC_EISTR_EMMC_DATEND_Pos)
#define   SDHC_EISTR_EMMC_DATEND_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_DATEND_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_DATEND_NO   (SDHC_EISTR_EMMC_DATEND_NO_Val << SDHC_EISTR_EMMC_DATEND_Pos)
#define SDHC_EISTR_EMMC_DATEND_YES  (SDHC_EISTR_EMMC_DATEND_YES_Val << SDHC_EISTR_EMMC_DATEND_Pos)
#define SDHC_EISTR_EMMC_CURLIM_Pos  7            
#define SDHC_EISTR_EMMC_CURLIM      (_U_(0x1) << SDHC_EISTR_EMMC_CURLIM_Pos)
#define   SDHC_EISTR_EMMC_CURLIM_NO_Val   _U_(0x0)   
#define   SDHC_EISTR_EMMC_CURLIM_YES_Val  _U_(0x1)   
#define SDHC_EISTR_EMMC_CURLIM_NO   (SDHC_EISTR_EMMC_CURLIM_NO_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
#define SDHC_EISTR_EMMC_CURLIM_YES  (SDHC_EISTR_EMMC_CURLIM_YES_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
#define SDHC_EISTR_EMMC_ACMD_Pos    8            
#define SDHC_EISTR_EMMC_ACMD        (_U_(0x1) << SDHC_EISTR_EMMC_ACMD_Pos)
#define   SDHC_EISTR_EMMC_ACMD_NO_Val     _U_(0x0)   
#define   SDHC_EISTR_EMMC_ACMD_YES_Val    _U_(0x1)   
#define SDHC_EISTR_EMMC_ACMD_NO     (SDHC_EISTR_EMMC_ACMD_NO_Val   << SDHC_EISTR_EMMC_ACMD_Pos)
#define SDHC_EISTR_EMMC_ACMD_YES    (SDHC_EISTR_EMMC_ACMD_YES_Val  << SDHC_EISTR_EMMC_ACMD_Pos)
#define SDHC_EISTR_EMMC_ADMA_Pos    9            
#define SDHC_EISTR_EMMC_ADMA        (_U_(0x1) << SDHC_EISTR_EMMC_ADMA_Pos)
#define   SDHC_EISTR_EMMC_ADMA_NO_Val     _U_(0x0)   
#define   SDHC_EISTR_EMMC_ADMA_YES_Val    _U_(0x1)   
#define SDHC_EISTR_EMMC_ADMA_NO     (SDHC_EISTR_EMMC_ADMA_NO_Val   << SDHC_EISTR_EMMC_ADMA_Pos)
#define SDHC_EISTR_EMMC_ADMA_YES    (SDHC_EISTR_EMMC_ADMA_YES_Val  << SDHC_EISTR_EMMC_ADMA_Pos)
#define SDHC_EISTR_EMMC_BOOTAE_Pos  12           
#define SDHC_EISTR_EMMC_BOOTAE      (_U_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos)
#define   SDHC_EISTR_EMMC_BOOTAE_0_Val    _U_(0x0)   
#define   SDHC_EISTR_EMMC_BOOTAE_1_Val    _U_(0x1)   
#define SDHC_EISTR_EMMC_BOOTAE_0    (SDHC_EISTR_EMMC_BOOTAE_0_Val  << SDHC_EISTR_EMMC_BOOTAE_Pos)
#define SDHC_EISTR_EMMC_BOOTAE_1    (SDHC_EISTR_EMMC_BOOTAE_1_Val  << SDHC_EISTR_EMMC_BOOTAE_Pos)
#define SDHC_EISTR_EMMC_MASK        _U_(0x13FF)  
/* -------- SDHC_NISTER : (SDHC Offset: 0x034) (R/W 16) Normal Interrupt Status Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CMDC:1;           
    uint16_t TRFC:1;           
    uint16_t BLKGE:1;          
    uint16_t DMAINT:1;         
    uint16_t BWRRDY:1;         
    uint16_t BRDRDY:1;         
    uint16_t CINS:1;           
    uint16_t CREM:1;           
    uint16_t CINT:1;           
    uint16_t :7;               
  } bit;                       
  struct { // EMMC mode
    uint16_t CMDC:1;           
    uint16_t TRFC:1;           
    uint16_t BLKGE:1;          
    uint16_t DMAINT:1;         
    uint16_t BWRRDY:1;         
    uint16_t BRDRDY:1;         
    uint16_t :8;               
    uint16_t BOOTAR:1;         
    uint16_t :1;               
  } EMMC;                      
  uint16_t reg;                
} SDHC_NISTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_NISTER_OFFSET          0x034        
#define SDHC_NISTER_RESETVALUE      _U_(0x0000)  
#define SDHC_NISTER_CMDC_Pos        0            
#define SDHC_NISTER_CMDC            (_U_(0x1) << SDHC_NISTER_CMDC_Pos)
#define   SDHC_NISTER_CMDC_MASKED_Val     _U_(0x0)   
#define   SDHC_NISTER_CMDC_ENABLED_Val    _U_(0x1)   
#define SDHC_NISTER_CMDC_MASKED     (SDHC_NISTER_CMDC_MASKED_Val   << SDHC_NISTER_CMDC_Pos)
#define SDHC_NISTER_CMDC_ENABLED    (SDHC_NISTER_CMDC_ENABLED_Val  << SDHC_NISTER_CMDC_Pos)
#define SDHC_NISTER_TRFC_Pos        1            
#define SDHC_NISTER_TRFC            (_U_(0x1) << SDHC_NISTER_TRFC_Pos)
#define   SDHC_NISTER_TRFC_MASKED_Val     _U_(0x0)   
#define   SDHC_NISTER_TRFC_ENABLED_Val    _U_(0x1)   
#define SDHC_NISTER_TRFC_MASKED     (SDHC_NISTER_TRFC_MASKED_Val   << SDHC_NISTER_TRFC_Pos)
#define SDHC_NISTER_TRFC_ENABLED    (SDHC_NISTER_TRFC_ENABLED_Val  << SDHC_NISTER_TRFC_Pos)
#define SDHC_NISTER_BLKGE_Pos       2            
#define SDHC_NISTER_BLKGE           (_U_(0x1) << SDHC_NISTER_BLKGE_Pos)
#define   SDHC_NISTER_BLKGE_MASKED_Val    _U_(0x0)   
#define   SDHC_NISTER_BLKGE_ENABLED_Val   _U_(0x1)   
#define SDHC_NISTER_BLKGE_MASKED    (SDHC_NISTER_BLKGE_MASKED_Val  << SDHC_NISTER_BLKGE_Pos)
#define SDHC_NISTER_BLKGE_ENABLED   (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos)
#define SDHC_NISTER_DMAINT_Pos      3            
#define SDHC_NISTER_DMAINT          (_U_(0x1) << SDHC_NISTER_DMAINT_Pos)
#define   SDHC_NISTER_DMAINT_MASKED_Val   _U_(0x0)   
#define   SDHC_NISTER_DMAINT_ENABLED_Val  _U_(0x1)   
#define SDHC_NISTER_DMAINT_MASKED   (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos)
#define SDHC_NISTER_DMAINT_ENABLED  (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos)
#define SDHC_NISTER_BWRRDY_Pos      4            
#define SDHC_NISTER_BWRRDY          (_U_(0x1) << SDHC_NISTER_BWRRDY_Pos)
#define   SDHC_NISTER_BWRRDY_MASKED_Val   _U_(0x0)   
#define   SDHC_NISTER_BWRRDY_ENABLED_Val  _U_(0x1)   
#define SDHC_NISTER_BWRRDY_MASKED   (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos)
#define SDHC_NISTER_BWRRDY_ENABLED  (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos)
#define SDHC_NISTER_BRDRDY_Pos      5            
#define SDHC_NISTER_BRDRDY          (_U_(0x1) << SDHC_NISTER_BRDRDY_Pos)
#define   SDHC_NISTER_BRDRDY_MASKED_Val   _U_(0x0)   
#define   SDHC_NISTER_BRDRDY_ENABLED_Val  _U_(0x1)   
#define SDHC_NISTER_BRDRDY_MASKED   (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos)
#define SDHC_NISTER_BRDRDY_ENABLED  (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos)
#define SDHC_NISTER_CINS_Pos        6            
#define SDHC_NISTER_CINS            (_U_(0x1) << SDHC_NISTER_CINS_Pos)
#define   SDHC_NISTER_CINS_MASKED_Val     _U_(0x0)   
#define   SDHC_NISTER_CINS_ENABLED_Val    _U_(0x1)   
#define SDHC_NISTER_CINS_MASKED     (SDHC_NISTER_CINS_MASKED_Val   << SDHC_NISTER_CINS_Pos)
#define SDHC_NISTER_CINS_ENABLED    (SDHC_NISTER_CINS_ENABLED_Val  << SDHC_NISTER_CINS_Pos)
#define SDHC_NISTER_CREM_Pos        7            
#define SDHC_NISTER_CREM            (_U_(0x1) << SDHC_NISTER_CREM_Pos)
#define   SDHC_NISTER_CREM_MASKED_Val     _U_(0x0)   
#define   SDHC_NISTER_CREM_ENABLED_Val    _U_(0x1)   
#define SDHC_NISTER_CREM_MASKED     (SDHC_NISTER_CREM_MASKED_Val   << SDHC_NISTER_CREM_Pos)
#define SDHC_NISTER_CREM_ENABLED    (SDHC_NISTER_CREM_ENABLED_Val  << SDHC_NISTER_CREM_Pos)
#define SDHC_NISTER_CINT_Pos        8            
#define SDHC_NISTER_CINT            (_U_(0x1) << SDHC_NISTER_CINT_Pos)
#define   SDHC_NISTER_CINT_MASKED_Val     _U_(0x0)   
#define   SDHC_NISTER_CINT_ENABLED_Val    _U_(0x1)   
#define SDHC_NISTER_CINT_MASKED     (SDHC_NISTER_CINT_MASKED_Val   << SDHC_NISTER_CINT_Pos)
#define SDHC_NISTER_CINT_ENABLED    (SDHC_NISTER_CINT_ENABLED_Val  << SDHC_NISTER_CINT_Pos)
#define SDHC_NISTER_MASK            _U_(0x01FF)  
// EMMC mode
#define SDHC_NISTER_EMMC_CMDC_Pos   0            
#define SDHC_NISTER_EMMC_CMDC       (_U_(0x1) << SDHC_NISTER_EMMC_CMDC_Pos)
#define   SDHC_NISTER_EMMC_CMDC_MASKED_Val _U_(0x0)   
#define   SDHC_NISTER_EMMC_CMDC_ENABLED_Val _U_(0x1)   
#define SDHC_NISTER_EMMC_CMDC_MASKED (SDHC_NISTER_EMMC_CMDC_MASKED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
#define SDHC_NISTER_EMMC_CMDC_ENABLED (SDHC_NISTER_EMMC_CMDC_ENABLED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
#define SDHC_NISTER_EMMC_TRFC_Pos   1            
#define SDHC_NISTER_EMMC_TRFC       (_U_(0x1) << SDHC_NISTER_EMMC_TRFC_Pos)
#define   SDHC_NISTER_EMMC_TRFC_MASKED_Val _U_(0x0)   
#define   SDHC_NISTER_EMMC_TRFC_ENABLED_Val _U_(0x1)   
#define SDHC_NISTER_EMMC_TRFC_MASKED (SDHC_NISTER_EMMC_TRFC_MASKED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
#define SDHC_NISTER_EMMC_TRFC_ENABLED (SDHC_NISTER_EMMC_TRFC_ENABLED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
#define SDHC_NISTER_EMMC_BLKGE_Pos  2            
#define SDHC_NISTER_EMMC_BLKGE      (_U_(0x1) << SDHC_NISTER_EMMC_BLKGE_Pos)
#define   SDHC_NISTER_EMMC_BLKGE_MASKED_Val _U_(0x0)   
#define   SDHC_NISTER_EMMC_BLKGE_ENABLED_Val _U_(0x1)   
#define SDHC_NISTER_EMMC_BLKGE_MASKED (SDHC_NISTER_EMMC_BLKGE_MASKED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
#define SDHC_NISTER_EMMC_BLKGE_ENABLED (SDHC_NISTER_EMMC_BLKGE_ENABLED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
#define SDHC_NISTER_EMMC_DMAINT_Pos 3            
#define SDHC_NISTER_EMMC_DMAINT     (_U_(0x1) << SDHC_NISTER_EMMC_DMAINT_Pos)
#define   SDHC_NISTER_EMMC_DMAINT_MASKED_Val _U_(0x0)   
#define   SDHC_NISTER_EMMC_DMAINT_ENABLED_Val _U_(0x1)   
#define SDHC_NISTER_EMMC_DMAINT_MASKED (SDHC_NISTER_EMMC_DMAINT_MASKED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
#define SDHC_NISTER_EMMC_DMAINT_ENABLED (SDHC_NISTER_EMMC_DMAINT_ENABLED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
#define SDHC_NISTER_EMMC_BWRRDY_Pos 4            
#define SDHC_NISTER_EMMC_BWRRDY     (_U_(0x1) << SDHC_NISTER_EMMC_BWRRDY_Pos)
#define   SDHC_NISTER_EMMC_BWRRDY_MASKED_Val _U_(0x0)   
#define   SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val _U_(0x1)   
#define SDHC_NISTER_EMMC_BWRRDY_MASKED (SDHC_NISTER_EMMC_BWRRDY_MASKED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
#define SDHC_NISTER_EMMC_BWRRDY_ENABLED (SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
#define SDHC_NISTER_EMMC_BRDRDY_Pos 5            
#define SDHC_NISTER_EMMC_BRDRDY     (_U_(0x1) << SDHC_NISTER_EMMC_BRDRDY_Pos)
#define   SDHC_NISTER_EMMC_BRDRDY_MASKED_Val _U_(0x0)   
#define   SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val _U_(0x1)   
#define SDHC_NISTER_EMMC_BRDRDY_MASKED (SDHC_NISTER_EMMC_BRDRDY_MASKED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
#define SDHC_NISTER_EMMC_BRDRDY_ENABLED (SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
#define SDHC_NISTER_EMMC_BOOTAR_Pos 14           
#define SDHC_NISTER_EMMC_BOOTAR     (_U_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos)
#define SDHC_NISTER_EMMC_MASK       _U_(0x403F)  
/* -------- SDHC_EISTER : (SDHC Offset: 0x036) (R/W 16) Error Interrupt Status Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CMDTEO:1;         
    uint16_t CMDCRC:1;         
    uint16_t CMDEND:1;         
    uint16_t CMDIDX:1;         
    uint16_t DATTEO:1;         
    uint16_t DATCRC:1;         
    uint16_t DATEND:1;         
    uint16_t CURLIM:1;         
    uint16_t ACMD:1;           
    uint16_t ADMA:1;           
    uint16_t :6;               
  } bit;                       
  struct { // EMMC mode
    uint16_t CMDTEO:1;         
    uint16_t CMDCRC:1;         
    uint16_t CMDEND:1;         
    uint16_t CMDIDX:1;         
    uint16_t DATTEO:1;         
    uint16_t DATCRC:1;         
    uint16_t DATEND:1;         
    uint16_t CURLIM:1;         
    uint16_t ACMD:1;           
    uint16_t ADMA:1;           
    uint16_t :2;               
    uint16_t BOOTAE:1;         
    uint16_t :3;               
  } EMMC;                      
  uint16_t reg;                
} SDHC_EISTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_EISTER_OFFSET          0x036        
#define SDHC_EISTER_RESETVALUE      _U_(0x0000)  
#define SDHC_EISTER_CMDTEO_Pos      0            
#define SDHC_EISTER_CMDTEO          (_U_(0x1) << SDHC_EISTER_CMDTEO_Pos)
#define   SDHC_EISTER_CMDTEO_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_CMDTEO_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_CMDTEO_MASKED   (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos)
#define SDHC_EISTER_CMDTEO_ENABLED  (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos)
#define SDHC_EISTER_CMDCRC_Pos      1            
#define SDHC_EISTER_CMDCRC          (_U_(0x1) << SDHC_EISTER_CMDCRC_Pos)
#define   SDHC_EISTER_CMDCRC_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_CMDCRC_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_CMDCRC_MASKED   (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos)
#define SDHC_EISTER_CMDCRC_ENABLED  (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos)
#define SDHC_EISTER_CMDEND_Pos      2            
#define SDHC_EISTER_CMDEND          (_U_(0x1) << SDHC_EISTER_CMDEND_Pos)
#define   SDHC_EISTER_CMDEND_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_CMDEND_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_CMDEND_MASKED   (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos)
#define SDHC_EISTER_CMDEND_ENABLED  (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos)
#define SDHC_EISTER_CMDIDX_Pos      3            
#define SDHC_EISTER_CMDIDX          (_U_(0x1) << SDHC_EISTER_CMDIDX_Pos)
#define   SDHC_EISTER_CMDIDX_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_CMDIDX_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_CMDIDX_MASKED   (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos)
#define SDHC_EISTER_CMDIDX_ENABLED  (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos)
#define SDHC_EISTER_DATTEO_Pos      4            
#define SDHC_EISTER_DATTEO          (_U_(0x1) << SDHC_EISTER_DATTEO_Pos)
#define   SDHC_EISTER_DATTEO_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_DATTEO_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_DATTEO_MASKED   (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos)
#define SDHC_EISTER_DATTEO_ENABLED  (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos)
#define SDHC_EISTER_DATCRC_Pos      5            
#define SDHC_EISTER_DATCRC          (_U_(0x1) << SDHC_EISTER_DATCRC_Pos)
#define   SDHC_EISTER_DATCRC_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_DATCRC_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_DATCRC_MASKED   (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos)
#define SDHC_EISTER_DATCRC_ENABLED  (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos)
#define SDHC_EISTER_DATEND_Pos      6            
#define SDHC_EISTER_DATEND          (_U_(0x1) << SDHC_EISTER_DATEND_Pos)
#define   SDHC_EISTER_DATEND_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_DATEND_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_DATEND_MASKED   (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos)
#define SDHC_EISTER_DATEND_ENABLED  (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos)
#define SDHC_EISTER_CURLIM_Pos      7            
#define SDHC_EISTER_CURLIM          (_U_(0x1) << SDHC_EISTER_CURLIM_Pos)
#define   SDHC_EISTER_CURLIM_MASKED_Val   _U_(0x0)   
#define   SDHC_EISTER_CURLIM_ENABLED_Val  _U_(0x1)   
#define SDHC_EISTER_CURLIM_MASKED   (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos)
#define SDHC_EISTER_CURLIM_ENABLED  (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos)
#define SDHC_EISTER_ACMD_Pos        8            
#define SDHC_EISTER_ACMD            (_U_(0x1) << SDHC_EISTER_ACMD_Pos)
#define   SDHC_EISTER_ACMD_MASKED_Val     _U_(0x0)   
#define   SDHC_EISTER_ACMD_ENABLED_Val    _U_(0x1)   
#define SDHC_EISTER_ACMD_MASKED     (SDHC_EISTER_ACMD_MASKED_Val   << SDHC_EISTER_ACMD_Pos)
#define SDHC_EISTER_ACMD_ENABLED    (SDHC_EISTER_ACMD_ENABLED_Val  << SDHC_EISTER_ACMD_Pos)
#define SDHC_EISTER_ADMA_Pos        9            
#define SDHC_EISTER_ADMA            (_U_(0x1) << SDHC_EISTER_ADMA_Pos)
#define   SDHC_EISTER_ADMA_MASKED_Val     _U_(0x0)   
#define   SDHC_EISTER_ADMA_ENABLED_Val    _U_(0x1)   
#define SDHC_EISTER_ADMA_MASKED     (SDHC_EISTER_ADMA_MASKED_Val   << SDHC_EISTER_ADMA_Pos)
#define SDHC_EISTER_ADMA_ENABLED    (SDHC_EISTER_ADMA_ENABLED_Val  << SDHC_EISTER_ADMA_Pos)
#define SDHC_EISTER_MASK            _U_(0x03FF)  
// EMMC mode
#define SDHC_EISTER_EMMC_CMDTEO_Pos 0            
#define SDHC_EISTER_EMMC_CMDTEO     (_U_(0x1) << SDHC_EISTER_EMMC_CMDTEO_Pos)
#define   SDHC_EISTER_EMMC_CMDTEO_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_CMDTEO_MASKED (SDHC_EISTER_EMMC_CMDTEO_MASKED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
#define SDHC_EISTER_EMMC_CMDTEO_ENABLED (SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
#define SDHC_EISTER_EMMC_CMDCRC_Pos 1            
#define SDHC_EISTER_EMMC_CMDCRC     (_U_(0x1) << SDHC_EISTER_EMMC_CMDCRC_Pos)
#define   SDHC_EISTER_EMMC_CMDCRC_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_CMDCRC_MASKED (SDHC_EISTER_EMMC_CMDCRC_MASKED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
#define SDHC_EISTER_EMMC_CMDCRC_ENABLED (SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
#define SDHC_EISTER_EMMC_CMDEND_Pos 2            
#define SDHC_EISTER_EMMC_CMDEND     (_U_(0x1) << SDHC_EISTER_EMMC_CMDEND_Pos)
#define   SDHC_EISTER_EMMC_CMDEND_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_CMDEND_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_CMDEND_MASKED (SDHC_EISTER_EMMC_CMDEND_MASKED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
#define SDHC_EISTER_EMMC_CMDEND_ENABLED (SDHC_EISTER_EMMC_CMDEND_ENABLED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
#define SDHC_EISTER_EMMC_CMDIDX_Pos 3            
#define SDHC_EISTER_EMMC_CMDIDX     (_U_(0x1) << SDHC_EISTER_EMMC_CMDIDX_Pos)
#define   SDHC_EISTER_EMMC_CMDIDX_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_CMDIDX_MASKED (SDHC_EISTER_EMMC_CMDIDX_MASKED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
#define SDHC_EISTER_EMMC_CMDIDX_ENABLED (SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
#define SDHC_EISTER_EMMC_DATTEO_Pos 4            
#define SDHC_EISTER_EMMC_DATTEO     (_U_(0x1) << SDHC_EISTER_EMMC_DATTEO_Pos)
#define   SDHC_EISTER_EMMC_DATTEO_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_DATTEO_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_DATTEO_MASKED (SDHC_EISTER_EMMC_DATTEO_MASKED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
#define SDHC_EISTER_EMMC_DATTEO_ENABLED (SDHC_EISTER_EMMC_DATTEO_ENABLED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
#define SDHC_EISTER_EMMC_DATCRC_Pos 5            
#define SDHC_EISTER_EMMC_DATCRC     (_U_(0x1) << SDHC_EISTER_EMMC_DATCRC_Pos)
#define   SDHC_EISTER_EMMC_DATCRC_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_DATCRC_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_DATCRC_MASKED (SDHC_EISTER_EMMC_DATCRC_MASKED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
#define SDHC_EISTER_EMMC_DATCRC_ENABLED (SDHC_EISTER_EMMC_DATCRC_ENABLED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
#define SDHC_EISTER_EMMC_DATEND_Pos 6            
#define SDHC_EISTER_EMMC_DATEND     (_U_(0x1) << SDHC_EISTER_EMMC_DATEND_Pos)
#define   SDHC_EISTER_EMMC_DATEND_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_DATEND_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_DATEND_MASKED (SDHC_EISTER_EMMC_DATEND_MASKED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
#define SDHC_EISTER_EMMC_DATEND_ENABLED (SDHC_EISTER_EMMC_DATEND_ENABLED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
#define SDHC_EISTER_EMMC_CURLIM_Pos 7            
#define SDHC_EISTER_EMMC_CURLIM     (_U_(0x1) << SDHC_EISTER_EMMC_CURLIM_Pos)
#define   SDHC_EISTER_EMMC_CURLIM_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_CURLIM_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_CURLIM_MASKED (SDHC_EISTER_EMMC_CURLIM_MASKED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
#define SDHC_EISTER_EMMC_CURLIM_ENABLED (SDHC_EISTER_EMMC_CURLIM_ENABLED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
#define SDHC_EISTER_EMMC_ACMD_Pos   8            
#define SDHC_EISTER_EMMC_ACMD       (_U_(0x1) << SDHC_EISTER_EMMC_ACMD_Pos)
#define   SDHC_EISTER_EMMC_ACMD_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_ACMD_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_ACMD_MASKED (SDHC_EISTER_EMMC_ACMD_MASKED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
#define SDHC_EISTER_EMMC_ACMD_ENABLED (SDHC_EISTER_EMMC_ACMD_ENABLED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
#define SDHC_EISTER_EMMC_ADMA_Pos   9            
#define SDHC_EISTER_EMMC_ADMA       (_U_(0x1) << SDHC_EISTER_EMMC_ADMA_Pos)
#define   SDHC_EISTER_EMMC_ADMA_MASKED_Val _U_(0x0)   
#define   SDHC_EISTER_EMMC_ADMA_ENABLED_Val _U_(0x1)   
#define SDHC_EISTER_EMMC_ADMA_MASKED (SDHC_EISTER_EMMC_ADMA_MASKED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
#define SDHC_EISTER_EMMC_ADMA_ENABLED (SDHC_EISTER_EMMC_ADMA_ENABLED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
#define SDHC_EISTER_EMMC_BOOTAE_Pos 12           
#define SDHC_EISTER_EMMC_BOOTAE     (_U_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos)
#define SDHC_EISTER_EMMC_MASK       _U_(0x13FF)  
/* -------- SDHC_NISIER : (SDHC Offset: 0x038) (R/W 16) Normal Interrupt Signal Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CMDC:1;           
    uint16_t TRFC:1;           
    uint16_t BLKGE:1;          
    uint16_t DMAINT:1;         
    uint16_t BWRRDY:1;         
    uint16_t BRDRDY:1;         
    uint16_t CINS:1;           
    uint16_t CREM:1;           
    uint16_t CINT:1;           
    uint16_t :7;               
  } bit;                       
  struct { // EMMC mode
    uint16_t CMDC:1;           
    uint16_t TRFC:1;           
    uint16_t BLKGE:1;          
    uint16_t DMAINT:1;         
    uint16_t BWRRDY:1;         
    uint16_t BRDRDY:1;         
    uint16_t :8;               
    uint16_t BOOTAR:1;         
    uint16_t :1;               
  } EMMC;                      
  uint16_t reg;                
} SDHC_NISIER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_NISIER_OFFSET          0x038        
#define SDHC_NISIER_RESETVALUE      _U_(0x0000)  
#define SDHC_NISIER_CMDC_Pos        0            
#define SDHC_NISIER_CMDC            (_U_(0x1) << SDHC_NISIER_CMDC_Pos)
#define   SDHC_NISIER_CMDC_MASKED_Val     _U_(0x0)   
#define   SDHC_NISIER_CMDC_ENABLED_Val    _U_(0x1)   
#define SDHC_NISIER_CMDC_MASKED     (SDHC_NISIER_CMDC_MASKED_Val   << SDHC_NISIER_CMDC_Pos)
#define SDHC_NISIER_CMDC_ENABLED    (SDHC_NISIER_CMDC_ENABLED_Val  << SDHC_NISIER_CMDC_Pos)
#define SDHC_NISIER_TRFC_Pos        1            
#define SDHC_NISIER_TRFC            (_U_(0x1) << SDHC_NISIER_TRFC_Pos)
#define   SDHC_NISIER_TRFC_MASKED_Val     _U_(0x0)   
#define   SDHC_NISIER_TRFC_ENABLED_Val    _U_(0x1)   
#define SDHC_NISIER_TRFC_MASKED     (SDHC_NISIER_TRFC_MASKED_Val   << SDHC_NISIER_TRFC_Pos)
#define SDHC_NISIER_TRFC_ENABLED    (SDHC_NISIER_TRFC_ENABLED_Val  << SDHC_NISIER_TRFC_Pos)
#define SDHC_NISIER_BLKGE_Pos       2            
#define SDHC_NISIER_BLKGE           (_U_(0x1) << SDHC_NISIER_BLKGE_Pos)
#define   SDHC_NISIER_BLKGE_MASKED_Val    _U_(0x0)   
#define   SDHC_NISIER_BLKGE_ENABLED_Val   _U_(0x1)   
#define SDHC_NISIER_BLKGE_MASKED    (SDHC_NISIER_BLKGE_MASKED_Val  << SDHC_NISIER_BLKGE_Pos)
#define SDHC_NISIER_BLKGE_ENABLED   (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos)
#define SDHC_NISIER_DMAINT_Pos      3            
#define SDHC_NISIER_DMAINT          (_U_(0x1) << SDHC_NISIER_DMAINT_Pos)
#define   SDHC_NISIER_DMAINT_MASKED_Val   _U_(0x0)   
#define   SDHC_NISIER_DMAINT_ENABLED_Val  _U_(0x1)   
#define SDHC_NISIER_DMAINT_MASKED   (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos)
#define SDHC_NISIER_DMAINT_ENABLED  (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos)
#define SDHC_NISIER_BWRRDY_Pos      4            
#define SDHC_NISIER_BWRRDY          (_U_(0x1) << SDHC_NISIER_BWRRDY_Pos)
#define   SDHC_NISIER_BWRRDY_MASKED_Val   _U_(0x0)   
#define   SDHC_NISIER_BWRRDY_ENABLED_Val  _U_(0x1)   
#define SDHC_NISIER_BWRRDY_MASKED   (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos)
#define SDHC_NISIER_BWRRDY_ENABLED  (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos)
#define SDHC_NISIER_BRDRDY_Pos      5            
#define SDHC_NISIER_BRDRDY          (_U_(0x1) << SDHC_NISIER_BRDRDY_Pos)
#define   SDHC_NISIER_BRDRDY_MASKED_Val   _U_(0x0)   
#define   SDHC_NISIER_BRDRDY_ENABLED_Val  _U_(0x1)   
#define SDHC_NISIER_BRDRDY_MASKED   (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos)
#define SDHC_NISIER_BRDRDY_ENABLED  (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos)
#define SDHC_NISIER_CINS_Pos        6            
#define SDHC_NISIER_CINS            (_U_(0x1) << SDHC_NISIER_CINS_Pos)
#define   SDHC_NISIER_CINS_MASKED_Val     _U_(0x0)   
#define   SDHC_NISIER_CINS_ENABLED_Val    _U_(0x1)   
#define SDHC_NISIER_CINS_MASKED     (SDHC_NISIER_CINS_MASKED_Val   << SDHC_NISIER_CINS_Pos)
#define SDHC_NISIER_CINS_ENABLED    (SDHC_NISIER_CINS_ENABLED_Val  << SDHC_NISIER_CINS_Pos)
#define SDHC_NISIER_CREM_Pos        7            
#define SDHC_NISIER_CREM            (_U_(0x1) << SDHC_NISIER_CREM_Pos)
#define   SDHC_NISIER_CREM_MASKED_Val     _U_(0x0)   
#define   SDHC_NISIER_CREM_ENABLED_Val    _U_(0x1)   
#define SDHC_NISIER_CREM_MASKED     (SDHC_NISIER_CREM_MASKED_Val   << SDHC_NISIER_CREM_Pos)
#define SDHC_NISIER_CREM_ENABLED    (SDHC_NISIER_CREM_ENABLED_Val  << SDHC_NISIER_CREM_Pos)
#define SDHC_NISIER_CINT_Pos        8            
#define SDHC_NISIER_CINT            (_U_(0x1) << SDHC_NISIER_CINT_Pos)
#define   SDHC_NISIER_CINT_MASKED_Val     _U_(0x0)   
#define   SDHC_NISIER_CINT_ENABLED_Val    _U_(0x1)   
#define SDHC_NISIER_CINT_MASKED     (SDHC_NISIER_CINT_MASKED_Val   << SDHC_NISIER_CINT_Pos)
#define SDHC_NISIER_CINT_ENABLED    (SDHC_NISIER_CINT_ENABLED_Val  << SDHC_NISIER_CINT_Pos)
#define SDHC_NISIER_MASK            _U_(0x01FF)  
// EMMC mode
#define SDHC_NISIER_EMMC_CMDC_Pos   0            
#define SDHC_NISIER_EMMC_CMDC       (_U_(0x1) << SDHC_NISIER_EMMC_CMDC_Pos)
#define   SDHC_NISIER_EMMC_CMDC_MASKED_Val _U_(0x0)   
#define   SDHC_NISIER_EMMC_CMDC_ENABLED_Val _U_(0x1)   
#define SDHC_NISIER_EMMC_CMDC_MASKED (SDHC_NISIER_EMMC_CMDC_MASKED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
#define SDHC_NISIER_EMMC_CMDC_ENABLED (SDHC_NISIER_EMMC_CMDC_ENABLED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
#define SDHC_NISIER_EMMC_TRFC_Pos   1            
#define SDHC_NISIER_EMMC_TRFC       (_U_(0x1) << SDHC_NISIER_EMMC_TRFC_Pos)
#define   SDHC_NISIER_EMMC_TRFC_MASKED_Val _U_(0x0)   
#define   SDHC_NISIER_EMMC_TRFC_ENABLED_Val _U_(0x1)   
#define SDHC_NISIER_EMMC_TRFC_MASKED (SDHC_NISIER_EMMC_TRFC_MASKED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
#define SDHC_NISIER_EMMC_TRFC_ENABLED (SDHC_NISIER_EMMC_TRFC_ENABLED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
#define SDHC_NISIER_EMMC_BLKGE_Pos  2            
#define SDHC_NISIER_EMMC_BLKGE      (_U_(0x1) << SDHC_NISIER_EMMC_BLKGE_Pos)
#define   SDHC_NISIER_EMMC_BLKGE_MASKED_Val _U_(0x0)   
#define   SDHC_NISIER_EMMC_BLKGE_ENABLED_Val _U_(0x1)   
#define SDHC_NISIER_EMMC_BLKGE_MASKED (SDHC_NISIER_EMMC_BLKGE_MASKED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
#define SDHC_NISIER_EMMC_BLKGE_ENABLED (SDHC_NISIER_EMMC_BLKGE_ENABLED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
#define SDHC_NISIER_EMMC_DMAINT_Pos 3            
#define SDHC_NISIER_EMMC_DMAINT     (_U_(0x1) << SDHC_NISIER_EMMC_DMAINT_Pos)
#define   SDHC_NISIER_EMMC_DMAINT_MASKED_Val _U_(0x0)   
#define   SDHC_NISIER_EMMC_DMAINT_ENABLED_Val _U_(0x1)   
#define SDHC_NISIER_EMMC_DMAINT_MASKED (SDHC_NISIER_EMMC_DMAINT_MASKED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
#define SDHC_NISIER_EMMC_DMAINT_ENABLED (SDHC_NISIER_EMMC_DMAINT_ENABLED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
#define SDHC_NISIER_EMMC_BWRRDY_Pos 4            
#define SDHC_NISIER_EMMC_BWRRDY     (_U_(0x1) << SDHC_NISIER_EMMC_BWRRDY_Pos)
#define   SDHC_NISIER_EMMC_BWRRDY_MASKED_Val _U_(0x0)   
#define   SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val _U_(0x1)   
#define SDHC_NISIER_EMMC_BWRRDY_MASKED (SDHC_NISIER_EMMC_BWRRDY_MASKED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
#define SDHC_NISIER_EMMC_BWRRDY_ENABLED (SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
#define SDHC_NISIER_EMMC_BRDRDY_Pos 5            
#define SDHC_NISIER_EMMC_BRDRDY     (_U_(0x1) << SDHC_NISIER_EMMC_BRDRDY_Pos)
#define   SDHC_NISIER_EMMC_BRDRDY_MASKED_Val _U_(0x0)   
#define   SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val _U_(0x1)   
#define SDHC_NISIER_EMMC_BRDRDY_MASKED (SDHC_NISIER_EMMC_BRDRDY_MASKED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
#define SDHC_NISIER_EMMC_BRDRDY_ENABLED (SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
#define SDHC_NISIER_EMMC_BOOTAR_Pos 14           
#define SDHC_NISIER_EMMC_BOOTAR     (_U_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos)
#define SDHC_NISIER_EMMC_MASK       _U_(0x403F)  
/* -------- SDHC_EISIER : (SDHC Offset: 0x03A) (R/W 16) Error Interrupt Signal Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CMDTEO:1;         
    uint16_t CMDCRC:1;         
    uint16_t CMDEND:1;         
    uint16_t CMDIDX:1;         
    uint16_t DATTEO:1;         
    uint16_t DATCRC:1;         
    uint16_t DATEND:1;         
    uint16_t CURLIM:1;         
    uint16_t ACMD:1;           
    uint16_t ADMA:1;           
    uint16_t :6;               
  } bit;                       
  struct { // EMMC mode
    uint16_t CMDTEO:1;         
    uint16_t CMDCRC:1;         
    uint16_t CMDEND:1;         
    uint16_t CMDIDX:1;         
    uint16_t DATTEO:1;         
    uint16_t DATCRC:1;         
    uint16_t DATEND:1;         
    uint16_t CURLIM:1;         
    uint16_t ACMD:1;           
    uint16_t ADMA:1;           
    uint16_t :2;               
    uint16_t BOOTAE:1;         
    uint16_t :3;               
  } EMMC;                      
  uint16_t reg;                
} SDHC_EISIER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_EISIER_OFFSET          0x03A        
#define SDHC_EISIER_RESETVALUE      _U_(0x0000)  
#define SDHC_EISIER_CMDTEO_Pos      0            
#define SDHC_EISIER_CMDTEO          (_U_(0x1) << SDHC_EISIER_CMDTEO_Pos)
#define   SDHC_EISIER_CMDTEO_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_CMDTEO_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_CMDTEO_MASKED   (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos)
#define SDHC_EISIER_CMDTEO_ENABLED  (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos)
#define SDHC_EISIER_CMDCRC_Pos      1            
#define SDHC_EISIER_CMDCRC          (_U_(0x1) << SDHC_EISIER_CMDCRC_Pos)
#define   SDHC_EISIER_CMDCRC_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_CMDCRC_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_CMDCRC_MASKED   (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos)
#define SDHC_EISIER_CMDCRC_ENABLED  (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos)
#define SDHC_EISIER_CMDEND_Pos      2            
#define SDHC_EISIER_CMDEND          (_U_(0x1) << SDHC_EISIER_CMDEND_Pos)
#define   SDHC_EISIER_CMDEND_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_CMDEND_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_CMDEND_MASKED   (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos)
#define SDHC_EISIER_CMDEND_ENABLED  (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos)
#define SDHC_EISIER_CMDIDX_Pos      3            
#define SDHC_EISIER_CMDIDX          (_U_(0x1) << SDHC_EISIER_CMDIDX_Pos)
#define   SDHC_EISIER_CMDIDX_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_CMDIDX_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_CMDIDX_MASKED   (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos)
#define SDHC_EISIER_CMDIDX_ENABLED  (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos)
#define SDHC_EISIER_DATTEO_Pos      4            
#define SDHC_EISIER_DATTEO          (_U_(0x1) << SDHC_EISIER_DATTEO_Pos)
#define   SDHC_EISIER_DATTEO_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_DATTEO_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_DATTEO_MASKED   (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos)
#define SDHC_EISIER_DATTEO_ENABLED  (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos)
#define SDHC_EISIER_DATCRC_Pos      5            
#define SDHC_EISIER_DATCRC          (_U_(0x1) << SDHC_EISIER_DATCRC_Pos)
#define   SDHC_EISIER_DATCRC_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_DATCRC_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_DATCRC_MASKED   (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos)
#define SDHC_EISIER_DATCRC_ENABLED  (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos)
#define SDHC_EISIER_DATEND_Pos      6            
#define SDHC_EISIER_DATEND          (_U_(0x1) << SDHC_EISIER_DATEND_Pos)
#define   SDHC_EISIER_DATEND_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_DATEND_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_DATEND_MASKED   (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos)
#define SDHC_EISIER_DATEND_ENABLED  (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos)
#define SDHC_EISIER_CURLIM_Pos      7            
#define SDHC_EISIER_CURLIM          (_U_(0x1) << SDHC_EISIER_CURLIM_Pos)
#define   SDHC_EISIER_CURLIM_MASKED_Val   _U_(0x0)   
#define   SDHC_EISIER_CURLIM_ENABLED_Val  _U_(0x1)   
#define SDHC_EISIER_CURLIM_MASKED   (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos)
#define SDHC_EISIER_CURLIM_ENABLED  (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos)
#define SDHC_EISIER_ACMD_Pos        8            
#define SDHC_EISIER_ACMD            (_U_(0x1) << SDHC_EISIER_ACMD_Pos)
#define   SDHC_EISIER_ACMD_MASKED_Val     _U_(0x0)   
#define   SDHC_EISIER_ACMD_ENABLED_Val    _U_(0x1)   
#define SDHC_EISIER_ACMD_MASKED     (SDHC_EISIER_ACMD_MASKED_Val   << SDHC_EISIER_ACMD_Pos)
#define SDHC_EISIER_ACMD_ENABLED    (SDHC_EISIER_ACMD_ENABLED_Val  << SDHC_EISIER_ACMD_Pos)
#define SDHC_EISIER_ADMA_Pos        9            
#define SDHC_EISIER_ADMA            (_U_(0x1) << SDHC_EISIER_ADMA_Pos)
#define   SDHC_EISIER_ADMA_MASKED_Val     _U_(0x0)   
#define   SDHC_EISIER_ADMA_ENABLED_Val    _U_(0x1)   
#define SDHC_EISIER_ADMA_MASKED     (SDHC_EISIER_ADMA_MASKED_Val   << SDHC_EISIER_ADMA_Pos)
#define SDHC_EISIER_ADMA_ENABLED    (SDHC_EISIER_ADMA_ENABLED_Val  << SDHC_EISIER_ADMA_Pos)
#define SDHC_EISIER_MASK            _U_(0x03FF)  
// EMMC mode
#define SDHC_EISIER_EMMC_CMDTEO_Pos 0            
#define SDHC_EISIER_EMMC_CMDTEO     (_U_(0x1) << SDHC_EISIER_EMMC_CMDTEO_Pos)
#define   SDHC_EISIER_EMMC_CMDTEO_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_CMDTEO_MASKED (SDHC_EISIER_EMMC_CMDTEO_MASKED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
#define SDHC_EISIER_EMMC_CMDTEO_ENABLED (SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
#define SDHC_EISIER_EMMC_CMDCRC_Pos 1            
#define SDHC_EISIER_EMMC_CMDCRC     (_U_(0x1) << SDHC_EISIER_EMMC_CMDCRC_Pos)
#define   SDHC_EISIER_EMMC_CMDCRC_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_CMDCRC_MASKED (SDHC_EISIER_EMMC_CMDCRC_MASKED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
#define SDHC_EISIER_EMMC_CMDCRC_ENABLED (SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
#define SDHC_EISIER_EMMC_CMDEND_Pos 2            
#define SDHC_EISIER_EMMC_CMDEND     (_U_(0x1) << SDHC_EISIER_EMMC_CMDEND_Pos)
#define   SDHC_EISIER_EMMC_CMDEND_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_CMDEND_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_CMDEND_MASKED (SDHC_EISIER_EMMC_CMDEND_MASKED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
#define SDHC_EISIER_EMMC_CMDEND_ENABLED (SDHC_EISIER_EMMC_CMDEND_ENABLED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
#define SDHC_EISIER_EMMC_CMDIDX_Pos 3            
#define SDHC_EISIER_EMMC_CMDIDX     (_U_(0x1) << SDHC_EISIER_EMMC_CMDIDX_Pos)
#define   SDHC_EISIER_EMMC_CMDIDX_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_CMDIDX_MASKED (SDHC_EISIER_EMMC_CMDIDX_MASKED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
#define SDHC_EISIER_EMMC_CMDIDX_ENABLED (SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
#define SDHC_EISIER_EMMC_DATTEO_Pos 4            
#define SDHC_EISIER_EMMC_DATTEO     (_U_(0x1) << SDHC_EISIER_EMMC_DATTEO_Pos)
#define   SDHC_EISIER_EMMC_DATTEO_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_DATTEO_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_DATTEO_MASKED (SDHC_EISIER_EMMC_DATTEO_MASKED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
#define SDHC_EISIER_EMMC_DATTEO_ENABLED (SDHC_EISIER_EMMC_DATTEO_ENABLED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
#define SDHC_EISIER_EMMC_DATCRC_Pos 5            
#define SDHC_EISIER_EMMC_DATCRC     (_U_(0x1) << SDHC_EISIER_EMMC_DATCRC_Pos)
#define   SDHC_EISIER_EMMC_DATCRC_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_DATCRC_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_DATCRC_MASKED (SDHC_EISIER_EMMC_DATCRC_MASKED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
#define SDHC_EISIER_EMMC_DATCRC_ENABLED (SDHC_EISIER_EMMC_DATCRC_ENABLED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
#define SDHC_EISIER_EMMC_DATEND_Pos 6            
#define SDHC_EISIER_EMMC_DATEND     (_U_(0x1) << SDHC_EISIER_EMMC_DATEND_Pos)
#define   SDHC_EISIER_EMMC_DATEND_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_DATEND_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_DATEND_MASKED (SDHC_EISIER_EMMC_DATEND_MASKED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
#define SDHC_EISIER_EMMC_DATEND_ENABLED (SDHC_EISIER_EMMC_DATEND_ENABLED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
#define SDHC_EISIER_EMMC_CURLIM_Pos 7            
#define SDHC_EISIER_EMMC_CURLIM     (_U_(0x1) << SDHC_EISIER_EMMC_CURLIM_Pos)
#define   SDHC_EISIER_EMMC_CURLIM_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_CURLIM_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_CURLIM_MASKED (SDHC_EISIER_EMMC_CURLIM_MASKED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
#define SDHC_EISIER_EMMC_CURLIM_ENABLED (SDHC_EISIER_EMMC_CURLIM_ENABLED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
#define SDHC_EISIER_EMMC_ACMD_Pos   8            
#define SDHC_EISIER_EMMC_ACMD       (_U_(0x1) << SDHC_EISIER_EMMC_ACMD_Pos)
#define   SDHC_EISIER_EMMC_ACMD_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_ACMD_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_ACMD_MASKED (SDHC_EISIER_EMMC_ACMD_MASKED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
#define SDHC_EISIER_EMMC_ACMD_ENABLED (SDHC_EISIER_EMMC_ACMD_ENABLED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
#define SDHC_EISIER_EMMC_ADMA_Pos   9            
#define SDHC_EISIER_EMMC_ADMA       (_U_(0x1) << SDHC_EISIER_EMMC_ADMA_Pos)
#define   SDHC_EISIER_EMMC_ADMA_MASKED_Val _U_(0x0)   
#define   SDHC_EISIER_EMMC_ADMA_ENABLED_Val _U_(0x1)   
#define SDHC_EISIER_EMMC_ADMA_MASKED (SDHC_EISIER_EMMC_ADMA_MASKED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
#define SDHC_EISIER_EMMC_ADMA_ENABLED (SDHC_EISIER_EMMC_ADMA_ENABLED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
#define SDHC_EISIER_EMMC_BOOTAE_Pos 12           
#define SDHC_EISIER_EMMC_BOOTAE     (_U_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos)
#define SDHC_EISIER_EMMC_MASK       _U_(0x13FF)  
/* -------- SDHC_ACESR : (SDHC Offset: 0x03C) (R/  16) Auto CMD Error Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t ACMD12NE:1;       
    uint16_t ACMDTEO:1;        
    uint16_t ACMDCRC:1;        
    uint16_t ACMDEND:1;        
    uint16_t ACMDIDX:1;        
    uint16_t :2;               
    uint16_t CMDNI:1;          
    uint16_t :8;               
  } bit;                       
  uint16_t reg;                
} SDHC_ACESR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_ACESR_OFFSET           0x03C        
#define SDHC_ACESR_RESETVALUE       _U_(0x0000)  
#define SDHC_ACESR_ACMD12NE_Pos     0            
#define SDHC_ACESR_ACMD12NE         (_U_(0x1) << SDHC_ACESR_ACMD12NE_Pos)
#define   SDHC_ACESR_ACMD12NE_EXEC_Val    _U_(0x0)   
#define   SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _U_(0x1)   
#define SDHC_ACESR_ACMD12NE_EXEC    (SDHC_ACESR_ACMD12NE_EXEC_Val  << SDHC_ACESR_ACMD12NE_Pos)
#define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
#define SDHC_ACESR_ACMDTEO_Pos      1            
#define SDHC_ACESR_ACMDTEO          (_U_(0x1) << SDHC_ACESR_ACMDTEO_Pos)
#define   SDHC_ACESR_ACMDTEO_NO_Val       _U_(0x0)   
#define   SDHC_ACESR_ACMDTEO_YES_Val      _U_(0x1)   
#define SDHC_ACESR_ACMDTEO_NO       (SDHC_ACESR_ACMDTEO_NO_Val     << SDHC_ACESR_ACMDTEO_Pos)
#define SDHC_ACESR_ACMDTEO_YES      (SDHC_ACESR_ACMDTEO_YES_Val    << SDHC_ACESR_ACMDTEO_Pos)
#define SDHC_ACESR_ACMDCRC_Pos      2            
#define SDHC_ACESR_ACMDCRC          (_U_(0x1) << SDHC_ACESR_ACMDCRC_Pos)
#define   SDHC_ACESR_ACMDCRC_NO_Val       _U_(0x0)   
#define   SDHC_ACESR_ACMDCRC_YES_Val      _U_(0x1)   
#define SDHC_ACESR_ACMDCRC_NO       (SDHC_ACESR_ACMDCRC_NO_Val     << SDHC_ACESR_ACMDCRC_Pos)
#define SDHC_ACESR_ACMDCRC_YES      (SDHC_ACESR_ACMDCRC_YES_Val    << SDHC_ACESR_ACMDCRC_Pos)
#define SDHC_ACESR_ACMDEND_Pos      3            
#define SDHC_ACESR_ACMDEND          (_U_(0x1) << SDHC_ACESR_ACMDEND_Pos)
#define   SDHC_ACESR_ACMDEND_NO_Val       _U_(0x0)   
#define   SDHC_ACESR_ACMDEND_YES_Val      _U_(0x1)   
#define SDHC_ACESR_ACMDEND_NO       (SDHC_ACESR_ACMDEND_NO_Val     << SDHC_ACESR_ACMDEND_Pos)
#define SDHC_ACESR_ACMDEND_YES      (SDHC_ACESR_ACMDEND_YES_Val    << SDHC_ACESR_ACMDEND_Pos)
#define SDHC_ACESR_ACMDIDX_Pos      4            
#define SDHC_ACESR_ACMDIDX          (_U_(0x1) << SDHC_ACESR_ACMDIDX_Pos)
#define   SDHC_ACESR_ACMDIDX_NO_Val       _U_(0x0)   
#define   SDHC_ACESR_ACMDIDX_YES_Val      _U_(0x1)   
#define SDHC_ACESR_ACMDIDX_NO       (SDHC_ACESR_ACMDIDX_NO_Val     << SDHC_ACESR_ACMDIDX_Pos)
#define SDHC_ACESR_ACMDIDX_YES      (SDHC_ACESR_ACMDIDX_YES_Val    << SDHC_ACESR_ACMDIDX_Pos)
#define SDHC_ACESR_CMDNI_Pos        7            
#define SDHC_ACESR_CMDNI            (_U_(0x1) << SDHC_ACESR_CMDNI_Pos)
#define   SDHC_ACESR_CMDNI_OK_Val         _U_(0x0)   
#define   SDHC_ACESR_CMDNI_NOT_ISSUED_Val _U_(0x1)   
#define SDHC_ACESR_CMDNI_OK         (SDHC_ACESR_CMDNI_OK_Val       << SDHC_ACESR_CMDNI_Pos)
#define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos)
#define SDHC_ACESR_MASK             _U_(0x009F)  
/* -------- SDHC_HC2R : (SDHC Offset: 0x03E) (R/W 16) Host Control 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t UHSMS:3;          
    uint16_t VS18EN:1;         
    uint16_t DRVSEL:2;         
    uint16_t EXTUN:1;          
    uint16_t SLCKSEL:1;        
    uint16_t :6;               
    uint16_t ASINTEN:1;        
    uint16_t PVALEN:1;         
  } bit;                       
  struct { // EMMC mode
    uint16_t HS200EN:4;        
    uint16_t DRVSEL:2;         
    uint16_t EXTUN:1;          
    uint16_t SLCKSEL:1;        
    uint16_t :7;               
    uint16_t PVALEN:1;         
  } EMMC;                      
  uint16_t reg;                
} SDHC_HC2R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_HC2R_OFFSET            0x03E        
#define SDHC_HC2R_RESETVALUE        _U_(0x0000)  
#define SDHC_HC2R_UHSMS_Pos         0            
#define SDHC_HC2R_UHSMS_Msk         (_U_(0x7) << SDHC_HC2R_UHSMS_Pos)
#define SDHC_HC2R_UHSMS(value)      (SDHC_HC2R_UHSMS_Msk & ((value) << SDHC_HC2R_UHSMS_Pos))
#define   SDHC_HC2R_UHSMS_SDR12_Val       _U_(0x0)   
#define   SDHC_HC2R_UHSMS_SDR25_Val       _U_(0x1)   
#define   SDHC_HC2R_UHSMS_SDR50_Val       _U_(0x2)   
#define   SDHC_HC2R_UHSMS_SDR104_Val      _U_(0x3)   
#define   SDHC_HC2R_UHSMS_DDR50_Val       _U_(0x4)   
#define SDHC_HC2R_UHSMS_SDR12       (SDHC_HC2R_UHSMS_SDR12_Val     << SDHC_HC2R_UHSMS_Pos)
#define SDHC_HC2R_UHSMS_SDR25       (SDHC_HC2R_UHSMS_SDR25_Val     << SDHC_HC2R_UHSMS_Pos)
#define SDHC_HC2R_UHSMS_SDR50       (SDHC_HC2R_UHSMS_SDR50_Val     << SDHC_HC2R_UHSMS_Pos)
#define SDHC_HC2R_UHSMS_SDR104      (SDHC_HC2R_UHSMS_SDR104_Val    << SDHC_HC2R_UHSMS_Pos)
#define SDHC_HC2R_UHSMS_DDR50       (SDHC_HC2R_UHSMS_DDR50_Val     << SDHC_HC2R_UHSMS_Pos)
#define SDHC_HC2R_VS18EN_Pos        3            
#define SDHC_HC2R_VS18EN            (_U_(0x1) << SDHC_HC2R_VS18EN_Pos)
#define   SDHC_HC2R_VS18EN_S33V_Val       _U_(0x0)   
#define   SDHC_HC2R_VS18EN_S18V_Val       _U_(0x1)   
#define SDHC_HC2R_VS18EN_S33V       (SDHC_HC2R_VS18EN_S33V_Val     << SDHC_HC2R_VS18EN_Pos)
#define SDHC_HC2R_VS18EN_S18V       (SDHC_HC2R_VS18EN_S18V_Val     << SDHC_HC2R_VS18EN_Pos)
#define SDHC_HC2R_DRVSEL_Pos        4            
#define SDHC_HC2R_DRVSEL_Msk        (_U_(0x3) << SDHC_HC2R_DRVSEL_Pos)
#define SDHC_HC2R_DRVSEL(value)     (SDHC_HC2R_DRVSEL_Msk & ((value) << SDHC_HC2R_DRVSEL_Pos))
#define   SDHC_HC2R_DRVSEL_B_Val          _U_(0x0)   
#define   SDHC_HC2R_DRVSEL_A_Val          _U_(0x1)   
#define   SDHC_HC2R_DRVSEL_C_Val          _U_(0x2)   
#define   SDHC_HC2R_DRVSEL_D_Val          _U_(0x3)   
#define SDHC_HC2R_DRVSEL_B          (SDHC_HC2R_DRVSEL_B_Val        << SDHC_HC2R_DRVSEL_Pos)
#define SDHC_HC2R_DRVSEL_A          (SDHC_HC2R_DRVSEL_A_Val        << SDHC_HC2R_DRVSEL_Pos)
#define SDHC_HC2R_DRVSEL_C          (SDHC_HC2R_DRVSEL_C_Val        << SDHC_HC2R_DRVSEL_Pos)
#define SDHC_HC2R_DRVSEL_D          (SDHC_HC2R_DRVSEL_D_Val        << SDHC_HC2R_DRVSEL_Pos)
#define SDHC_HC2R_EXTUN_Pos         6            
#define SDHC_HC2R_EXTUN             (_U_(0x1) << SDHC_HC2R_EXTUN_Pos)
#define   SDHC_HC2R_EXTUN_NO_Val          _U_(0x0)   
#define   SDHC_HC2R_EXTUN_REQUESTED_Val   _U_(0x1)   
#define SDHC_HC2R_EXTUN_NO          (SDHC_HC2R_EXTUN_NO_Val        << SDHC_HC2R_EXTUN_Pos)
#define SDHC_HC2R_EXTUN_REQUESTED   (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos)
#define SDHC_HC2R_SLCKSEL_Pos       7            
#define SDHC_HC2R_SLCKSEL           (_U_(0x1) << SDHC_HC2R_SLCKSEL_Pos)
#define   SDHC_HC2R_SLCKSEL_FIXED_Val     _U_(0x0)   
#define   SDHC_HC2R_SLCKSEL_TUNED_Val     _U_(0x1)   
#define SDHC_HC2R_SLCKSEL_FIXED     (SDHC_HC2R_SLCKSEL_FIXED_Val   << SDHC_HC2R_SLCKSEL_Pos)
#define SDHC_HC2R_SLCKSEL_TUNED     (SDHC_HC2R_SLCKSEL_TUNED_Val   << SDHC_HC2R_SLCKSEL_Pos)
#define SDHC_HC2R_ASINTEN_Pos       14           
#define SDHC_HC2R_ASINTEN           (_U_(0x1) << SDHC_HC2R_ASINTEN_Pos)
#define   SDHC_HC2R_ASINTEN_DISABLED_Val  _U_(0x0)   
#define   SDHC_HC2R_ASINTEN_ENABLED_Val   _U_(0x1)   
#define SDHC_HC2R_ASINTEN_DISABLED  (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos)
#define SDHC_HC2R_ASINTEN_ENABLED   (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos)
#define SDHC_HC2R_PVALEN_Pos        15           
#define SDHC_HC2R_PVALEN            (_U_(0x1) << SDHC_HC2R_PVALEN_Pos)
#define   SDHC_HC2R_PVALEN_HOST_Val       _U_(0x0)   
#define   SDHC_HC2R_PVALEN_AUTO_Val       _U_(0x1)   
#define SDHC_HC2R_PVALEN_HOST       (SDHC_HC2R_PVALEN_HOST_Val     << SDHC_HC2R_PVALEN_Pos)
#define SDHC_HC2R_PVALEN_AUTO       (SDHC_HC2R_PVALEN_AUTO_Val     << SDHC_HC2R_PVALEN_Pos)
#define SDHC_HC2R_MASK              _U_(0xC0FF)  
// EMMC mode
#define SDHC_HC2R_EMMC_HS200EN_Pos  0            
#define SDHC_HC2R_EMMC_HS200EN_Msk  (_U_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos)
#define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & ((value) << SDHC_HC2R_EMMC_HS200EN_Pos))
#define   SDHC_HC2R_EMMC_HS200EN_SDR12_Val _U_(0x0)   
#define   SDHC_HC2R_EMMC_HS200EN_SDR25_Val _U_(0x1)   
#define   SDHC_HC2R_EMMC_HS200EN_SDR50_Val _U_(0x2)   
#define   SDHC_HC2R_EMMC_HS200EN_SDR104_Val _U_(0x3)   
#define   SDHC_HC2R_EMMC_HS200EN_DDR50_Val _U_(0x4)   
#define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
#define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
#define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
#define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
#define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
#define SDHC_HC2R_EMMC_DRVSEL_Pos   4            
#define SDHC_HC2R_EMMC_DRVSEL_Msk   (_U_(0x3) << SDHC_HC2R_EMMC_DRVSEL_Pos)
#define SDHC_HC2R_EMMC_DRVSEL(value) (SDHC_HC2R_EMMC_DRVSEL_Msk & ((value) << SDHC_HC2R_EMMC_DRVSEL_Pos))
#define   SDHC_HC2R_EMMC_DRVSEL_B_Val     _U_(0x0)   
#define   SDHC_HC2R_EMMC_DRVSEL_A_Val     _U_(0x1)   
#define   SDHC_HC2R_EMMC_DRVSEL_C_Val     _U_(0x2)   
#define   SDHC_HC2R_EMMC_DRVSEL_D_Val     _U_(0x3)   
#define SDHC_HC2R_EMMC_DRVSEL_B     (SDHC_HC2R_EMMC_DRVSEL_B_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
#define SDHC_HC2R_EMMC_DRVSEL_A     (SDHC_HC2R_EMMC_DRVSEL_A_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
#define SDHC_HC2R_EMMC_DRVSEL_C     (SDHC_HC2R_EMMC_DRVSEL_C_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
#define SDHC_HC2R_EMMC_DRVSEL_D     (SDHC_HC2R_EMMC_DRVSEL_D_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
#define SDHC_HC2R_EMMC_EXTUN_Pos    6            
#define SDHC_HC2R_EMMC_EXTUN        (_U_(0x1) << SDHC_HC2R_EMMC_EXTUN_Pos)
#define   SDHC_HC2R_EMMC_EXTUN_NO_Val     _U_(0x0)   
#define   SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val _U_(0x1)   
#define SDHC_HC2R_EMMC_EXTUN_NO     (SDHC_HC2R_EMMC_EXTUN_NO_Val   << SDHC_HC2R_EMMC_EXTUN_Pos)
#define SDHC_HC2R_EMMC_EXTUN_REQUESTED (SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
#define SDHC_HC2R_EMMC_SLCKSEL_Pos  7            
#define SDHC_HC2R_EMMC_SLCKSEL      (_U_(0x1) << SDHC_HC2R_EMMC_SLCKSEL_Pos)
#define   SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val _U_(0x0)   
#define   SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val _U_(0x1)   
#define SDHC_HC2R_EMMC_SLCKSEL_FIXED (SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
#define SDHC_HC2R_EMMC_SLCKSEL_TUNED (SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
#define SDHC_HC2R_EMMC_PVALEN_Pos   15           
#define SDHC_HC2R_EMMC_PVALEN       (_U_(0x1) << SDHC_HC2R_EMMC_PVALEN_Pos)
#define   SDHC_HC2R_EMMC_PVALEN_HOST_Val  _U_(0x0)   
#define   SDHC_HC2R_EMMC_PVALEN_AUTO_Val  _U_(0x1)   
#define SDHC_HC2R_EMMC_PVALEN_HOST  (SDHC_HC2R_EMMC_PVALEN_HOST_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
#define SDHC_HC2R_EMMC_PVALEN_AUTO  (SDHC_HC2R_EMMC_PVALEN_AUTO_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
#define SDHC_HC2R_EMMC_MASK         _U_(0x80FF)  
/* -------- SDHC_CA0R : (SDHC Offset: 0x040) (R/  32) Capabilities 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t TEOCLKF:6;        
    uint32_t :1;               
    uint32_t TEOCLKU:1;        
    uint32_t BASECLKF:8;       
    uint32_t MAXBLKL:2;        
    uint32_t ED8SUP:1;         
    uint32_t ADMA2SUP:1;       
    uint32_t :1;               
    uint32_t HSSUP:1;          
    uint32_t SDMASUP:1;        
    uint32_t SRSUP:1;          
    uint32_t V33VSUP:1;        
    uint32_t V30VSUP:1;        
    uint32_t V18VSUP:1;        
    uint32_t :1;               
    uint32_t SB64SUP:1;        
    uint32_t ASINTSUP:1;       
    uint32_t SLTYPE:2;         
  } bit;                       
  uint32_t reg;                
} SDHC_CA0R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_CA0R_OFFSET            0x040        
#define SDHC_CA0R_RESETVALUE        _U_(0x27E80080) 
#define SDHC_CA0R_TEOCLKF_Pos       0            
#define SDHC_CA0R_TEOCLKF_Msk       (_U_(0x3F) << SDHC_CA0R_TEOCLKF_Pos)
#define SDHC_CA0R_TEOCLKF(value)    (SDHC_CA0R_TEOCLKF_Msk & ((value) << SDHC_CA0R_TEOCLKF_Pos))
#define   SDHC_CA0R_TEOCLKF_OTHER_Val     _U_(0x0)   
#define SDHC_CA0R_TEOCLKF_OTHER     (SDHC_CA0R_TEOCLKF_OTHER_Val   << SDHC_CA0R_TEOCLKF_Pos)
#define SDHC_CA0R_TEOCLKU_Pos       7            
#define SDHC_CA0R_TEOCLKU           (_U_(0x1) << SDHC_CA0R_TEOCLKU_Pos)
#define   SDHC_CA0R_TEOCLKU_KHZ_Val       _U_(0x0)   
#define   SDHC_CA0R_TEOCLKU_MHZ_Val       _U_(0x1)   
#define SDHC_CA0R_TEOCLKU_KHZ       (SDHC_CA0R_TEOCLKU_KHZ_Val     << SDHC_CA0R_TEOCLKU_Pos)
#define SDHC_CA0R_TEOCLKU_MHZ       (SDHC_CA0R_TEOCLKU_MHZ_Val     << SDHC_CA0R_TEOCLKU_Pos)
#define SDHC_CA0R_BASECLKF_Pos      8            
#define SDHC_CA0R_BASECLKF_Msk      (_U_(0xFF) << SDHC_CA0R_BASECLKF_Pos)
#define SDHC_CA0R_BASECLKF(value)   (SDHC_CA0R_BASECLKF_Msk & ((value) << SDHC_CA0R_BASECLKF_Pos))
#define   SDHC_CA0R_BASECLKF_OTHER_Val    _U_(0x0)   
#define SDHC_CA0R_BASECLKF_OTHER    (SDHC_CA0R_BASECLKF_OTHER_Val  << SDHC_CA0R_BASECLKF_Pos)
#define SDHC_CA0R_MAXBLKL_Pos       16           
#define SDHC_CA0R_MAXBLKL_Msk       (_U_(0x3) << SDHC_CA0R_MAXBLKL_Pos)
#define SDHC_CA0R_MAXBLKL(value)    (SDHC_CA0R_MAXBLKL_Msk & ((value) << SDHC_CA0R_MAXBLKL_Pos))
#define   SDHC_CA0R_MAXBLKL_512_Val       _U_(0x0)   
#define   SDHC_CA0R_MAXBLKL_1024_Val      _U_(0x1)   
#define   SDHC_CA0R_MAXBLKL_2048_Val      _U_(0x2)   
#define SDHC_CA0R_MAXBLKL_512       (SDHC_CA0R_MAXBLKL_512_Val     << SDHC_CA0R_MAXBLKL_Pos)
#define SDHC_CA0R_MAXBLKL_1024      (SDHC_CA0R_MAXBLKL_1024_Val    << SDHC_CA0R_MAXBLKL_Pos)
#define SDHC_CA0R_MAXBLKL_2048      (SDHC_CA0R_MAXBLKL_2048_Val    << SDHC_CA0R_MAXBLKL_Pos)
#define SDHC_CA0R_ED8SUP_Pos        18           
#define SDHC_CA0R_ED8SUP            (_U_(0x1) << SDHC_CA0R_ED8SUP_Pos)
#define   SDHC_CA0R_ED8SUP_NO_Val         _U_(0x0)   
#define   SDHC_CA0R_ED8SUP_YES_Val        _U_(0x1)   
#define SDHC_CA0R_ED8SUP_NO         (SDHC_CA0R_ED8SUP_NO_Val       << SDHC_CA0R_ED8SUP_Pos)
#define SDHC_CA0R_ED8SUP_YES        (SDHC_CA0R_ED8SUP_YES_Val      << SDHC_CA0R_ED8SUP_Pos)
#define SDHC_CA0R_ADMA2SUP_Pos      19           
#define SDHC_CA0R_ADMA2SUP          (_U_(0x1) << SDHC_CA0R_ADMA2SUP_Pos)
#define   SDHC_CA0R_ADMA2SUP_NO_Val       _U_(0x0)   
#define   SDHC_CA0R_ADMA2SUP_YES_Val      _U_(0x1)   
#define SDHC_CA0R_ADMA2SUP_NO       (SDHC_CA0R_ADMA2SUP_NO_Val     << SDHC_CA0R_ADMA2SUP_Pos)
#define SDHC_CA0R_ADMA2SUP_YES      (SDHC_CA0R_ADMA2SUP_YES_Val    << SDHC_CA0R_ADMA2SUP_Pos)
#define SDHC_CA0R_HSSUP_Pos         21           
#define SDHC_CA0R_HSSUP             (_U_(0x1) << SDHC_CA0R_HSSUP_Pos)
#define   SDHC_CA0R_HSSUP_NO_Val          _U_(0x0)   
#define   SDHC_CA0R_HSSUP_YES_Val         _U_(0x1)   
#define SDHC_CA0R_HSSUP_NO          (SDHC_CA0R_HSSUP_NO_Val        << SDHC_CA0R_HSSUP_Pos)
#define SDHC_CA0R_HSSUP_YES         (SDHC_CA0R_HSSUP_YES_Val       << SDHC_CA0R_HSSUP_Pos)
#define SDHC_CA0R_SDMASUP_Pos       22           
#define SDHC_CA0R_SDMASUP           (_U_(0x1) << SDHC_CA0R_SDMASUP_Pos)
#define   SDHC_CA0R_SDMASUP_NO_Val        _U_(0x0)   
#define   SDHC_CA0R_SDMASUP_YES_Val       _U_(0x1)   
#define SDHC_CA0R_SDMASUP_NO        (SDHC_CA0R_SDMASUP_NO_Val      << SDHC_CA0R_SDMASUP_Pos)
#define SDHC_CA0R_SDMASUP_YES       (SDHC_CA0R_SDMASUP_YES_Val     << SDHC_CA0R_SDMASUP_Pos)
#define SDHC_CA0R_SRSUP_Pos         23           
#define SDHC_CA0R_SRSUP             (_U_(0x1) << SDHC_CA0R_SRSUP_Pos)
#define   SDHC_CA0R_SRSUP_NO_Val          _U_(0x0)   
#define   SDHC_CA0R_SRSUP_YES_Val         _U_(0x1)   
#define SDHC_CA0R_SRSUP_NO          (SDHC_CA0R_SRSUP_NO_Val        << SDHC_CA0R_SRSUP_Pos)
#define SDHC_CA0R_SRSUP_YES         (SDHC_CA0R_SRSUP_YES_Val       << SDHC_CA0R_SRSUP_Pos)
#define SDHC_CA0R_V33VSUP_Pos       24           
#define SDHC_CA0R_V33VSUP           (_U_(0x1) << SDHC_CA0R_V33VSUP_Pos)
#define   SDHC_CA0R_V33VSUP_NO_Val        _U_(0x0)   
#define   SDHC_CA0R_V33VSUP_YES_Val       _U_(0x1)   
#define SDHC_CA0R_V33VSUP_NO        (SDHC_CA0R_V33VSUP_NO_Val      << SDHC_CA0R_V33VSUP_Pos)
#define SDHC_CA0R_V33VSUP_YES       (SDHC_CA0R_V33VSUP_YES_Val     << SDHC_CA0R_V33VSUP_Pos)
#define SDHC_CA0R_V30VSUP_Pos       25           
#define SDHC_CA0R_V30VSUP           (_U_(0x1) << SDHC_CA0R_V30VSUP_Pos)
#define   SDHC_CA0R_V30VSUP_NO_Val        _U_(0x0)   
#define   SDHC_CA0R_V30VSUP_YES_Val       _U_(0x1)   
#define SDHC_CA0R_V30VSUP_NO        (SDHC_CA0R_V30VSUP_NO_Val      << SDHC_CA0R_V30VSUP_Pos)
#define SDHC_CA0R_V30VSUP_YES       (SDHC_CA0R_V30VSUP_YES_Val     << SDHC_CA0R_V30VSUP_Pos)
#define SDHC_CA0R_V18VSUP_Pos       26           
#define SDHC_CA0R_V18VSUP           (_U_(0x1) << SDHC_CA0R_V18VSUP_Pos)
#define   SDHC_CA0R_V18VSUP_NO_Val        _U_(0x0)   
#define   SDHC_CA0R_V18VSUP_YES_Val       _U_(0x1)   
#define SDHC_CA0R_V18VSUP_NO        (SDHC_CA0R_V18VSUP_NO_Val      << SDHC_CA0R_V18VSUP_Pos)
#define SDHC_CA0R_V18VSUP_YES       (SDHC_CA0R_V18VSUP_YES_Val     << SDHC_CA0R_V18VSUP_Pos)
#define SDHC_CA0R_SB64SUP_Pos       28           
#define SDHC_CA0R_SB64SUP           (_U_(0x1) << SDHC_CA0R_SB64SUP_Pos)
#define   SDHC_CA0R_SB64SUP_NO_Val        _U_(0x0)   
#define   SDHC_CA0R_SB64SUP_YES_Val       _U_(0x1)   
#define SDHC_CA0R_SB64SUP_NO        (SDHC_CA0R_SB64SUP_NO_Val      << SDHC_CA0R_SB64SUP_Pos)
#define SDHC_CA0R_SB64SUP_YES       (SDHC_CA0R_SB64SUP_YES_Val     << SDHC_CA0R_SB64SUP_Pos)
#define SDHC_CA0R_ASINTSUP_Pos      29           
#define SDHC_CA0R_ASINTSUP          (_U_(0x1) << SDHC_CA0R_ASINTSUP_Pos)
#define   SDHC_CA0R_ASINTSUP_NO_Val       _U_(0x0)   
#define   SDHC_CA0R_ASINTSUP_YES_Val      _U_(0x1)   
#define SDHC_CA0R_ASINTSUP_NO       (SDHC_CA0R_ASINTSUP_NO_Val     << SDHC_CA0R_ASINTSUP_Pos)
#define SDHC_CA0R_ASINTSUP_YES      (SDHC_CA0R_ASINTSUP_YES_Val    << SDHC_CA0R_ASINTSUP_Pos)
#define SDHC_CA0R_SLTYPE_Pos        30           
#define SDHC_CA0R_SLTYPE_Msk        (_U_(0x3) << SDHC_CA0R_SLTYPE_Pos)
#define SDHC_CA0R_SLTYPE(value)     (SDHC_CA0R_SLTYPE_Msk & ((value) << SDHC_CA0R_SLTYPE_Pos))
#define   SDHC_CA0R_SLTYPE_REMOVABLE_Val  _U_(0x0)   
#define   SDHC_CA0R_SLTYPE_EMBEDDED_Val   _U_(0x1)   
#define SDHC_CA0R_SLTYPE_REMOVABLE  (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos)
#define SDHC_CA0R_SLTYPE_EMBEDDED   (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos)
#define SDHC_CA0R_MASK              _U_(0xF7EFFFBF) 
/* -------- SDHC_CA1R : (SDHC Offset: 0x044) (R/  32) Capabilities 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t SDR50SUP:1;       
    uint32_t SDR104SUP:1;      
    uint32_t DDR50SUP:1;       
    uint32_t :1;               
    uint32_t DRVASUP:1;        
    uint32_t DRVCSUP:1;        
    uint32_t DRVDSUP:1;        
    uint32_t :1;               
    uint32_t TCNTRT:4;         
    uint32_t :1;               
    uint32_t TSDR50:1;         
    uint32_t :2;               
    uint32_t CLKMULT:8;        
    uint32_t :8;               
  } bit;                       
  uint32_t reg;                
} SDHC_CA1R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_CA1R_OFFSET            0x044        
#define SDHC_CA1R_RESETVALUE        _U_(0x00000070) 
#define SDHC_CA1R_SDR50SUP_Pos      0            
#define SDHC_CA1R_SDR50SUP          (_U_(0x1) << SDHC_CA1R_SDR50SUP_Pos)
#define   SDHC_CA1R_SDR50SUP_NO_Val       _U_(0x0)   
#define   SDHC_CA1R_SDR50SUP_YES_Val      _U_(0x1)   
#define SDHC_CA1R_SDR50SUP_NO       (SDHC_CA1R_SDR50SUP_NO_Val     << SDHC_CA1R_SDR50SUP_Pos)
#define SDHC_CA1R_SDR50SUP_YES      (SDHC_CA1R_SDR50SUP_YES_Val    << SDHC_CA1R_SDR50SUP_Pos)
#define SDHC_CA1R_SDR104SUP_Pos     1            
#define SDHC_CA1R_SDR104SUP         (_U_(0x1) << SDHC_CA1R_SDR104SUP_Pos)
#define   SDHC_CA1R_SDR104SUP_NO_Val      _U_(0x0)   
#define   SDHC_CA1R_SDR104SUP_YES_Val     _U_(0x1)   
#define SDHC_CA1R_SDR104SUP_NO      (SDHC_CA1R_SDR104SUP_NO_Val    << SDHC_CA1R_SDR104SUP_Pos)
#define SDHC_CA1R_SDR104SUP_YES     (SDHC_CA1R_SDR104SUP_YES_Val   << SDHC_CA1R_SDR104SUP_Pos)
#define SDHC_CA1R_DDR50SUP_Pos      2            
#define SDHC_CA1R_DDR50SUP          (_U_(0x1) << SDHC_CA1R_DDR50SUP_Pos)
#define   SDHC_CA1R_DDR50SUP_NO_Val       _U_(0x0)   
#define   SDHC_CA1R_DDR50SUP_YES_Val      _U_(0x1)   
#define SDHC_CA1R_DDR50SUP_NO       (SDHC_CA1R_DDR50SUP_NO_Val     << SDHC_CA1R_DDR50SUP_Pos)
#define SDHC_CA1R_DDR50SUP_YES      (SDHC_CA1R_DDR50SUP_YES_Val    << SDHC_CA1R_DDR50SUP_Pos)
#define SDHC_CA1R_DRVASUP_Pos       4            
#define SDHC_CA1R_DRVASUP           (_U_(0x1) << SDHC_CA1R_DRVASUP_Pos)
#define   SDHC_CA1R_DRVASUP_NO_Val        _U_(0x0)   
#define   SDHC_CA1R_DRVASUP_YES_Val       _U_(0x1)   
#define SDHC_CA1R_DRVASUP_NO        (SDHC_CA1R_DRVASUP_NO_Val      << SDHC_CA1R_DRVASUP_Pos)
#define SDHC_CA1R_DRVASUP_YES       (SDHC_CA1R_DRVASUP_YES_Val     << SDHC_CA1R_DRVASUP_Pos)
#define SDHC_CA1R_DRVCSUP_Pos       5            
#define SDHC_CA1R_DRVCSUP           (_U_(0x1) << SDHC_CA1R_DRVCSUP_Pos)
#define   SDHC_CA1R_DRVCSUP_NO_Val        _U_(0x0)   
#define   SDHC_CA1R_DRVCSUP_YES_Val       _U_(0x1)   
#define SDHC_CA1R_DRVCSUP_NO        (SDHC_CA1R_DRVCSUP_NO_Val      << SDHC_CA1R_DRVCSUP_Pos)
#define SDHC_CA1R_DRVCSUP_YES       (SDHC_CA1R_DRVCSUP_YES_Val     << SDHC_CA1R_DRVCSUP_Pos)
#define SDHC_CA1R_DRVDSUP_Pos       6            
#define SDHC_CA1R_DRVDSUP           (_U_(0x1) << SDHC_CA1R_DRVDSUP_Pos)
#define   SDHC_CA1R_DRVDSUP_NO_Val        _U_(0x0)   
#define   SDHC_CA1R_DRVDSUP_YES_Val       _U_(0x1)   
#define SDHC_CA1R_DRVDSUP_NO        (SDHC_CA1R_DRVDSUP_NO_Val      << SDHC_CA1R_DRVDSUP_Pos)
#define SDHC_CA1R_DRVDSUP_YES       (SDHC_CA1R_DRVDSUP_YES_Val     << SDHC_CA1R_DRVDSUP_Pos)
#define SDHC_CA1R_TCNTRT_Pos        8            
#define SDHC_CA1R_TCNTRT_Msk        (_U_(0xF) << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT(value)     (SDHC_CA1R_TCNTRT_Msk & ((value) << SDHC_CA1R_TCNTRT_Pos))
#define   SDHC_CA1R_TCNTRT_DISABLED_Val   _U_(0x0)   
#define   SDHC_CA1R_TCNTRT_1S_Val         _U_(0x1)   
#define   SDHC_CA1R_TCNTRT_2S_Val         _U_(0x2)   
#define   SDHC_CA1R_TCNTRT_4S_Val         _U_(0x3)   
#define   SDHC_CA1R_TCNTRT_8S_Val         _U_(0x4)   
#define   SDHC_CA1R_TCNTRT_16S_Val        _U_(0x5)   
#define   SDHC_CA1R_TCNTRT_32S_Val        _U_(0x6)   
#define   SDHC_CA1R_TCNTRT_64S_Val        _U_(0x7)   
#define   SDHC_CA1R_TCNTRT_128S_Val       _U_(0x8)   
#define   SDHC_CA1R_TCNTRT_256S_Val       _U_(0x9)   
#define   SDHC_CA1R_TCNTRT_512S_Val       _U_(0xA)   
#define   SDHC_CA1R_TCNTRT_1024S_Val      _U_(0xB)   
#define   SDHC_CA1R_TCNTRT_OTHER_Val      _U_(0xF)   
#define SDHC_CA1R_TCNTRT_DISABLED   (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_1S         (SDHC_CA1R_TCNTRT_1S_Val       << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_2S         (SDHC_CA1R_TCNTRT_2S_Val       << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_4S         (SDHC_CA1R_TCNTRT_4S_Val       << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_8S         (SDHC_CA1R_TCNTRT_8S_Val       << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_16S        (SDHC_CA1R_TCNTRT_16S_Val      << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_32S        (SDHC_CA1R_TCNTRT_32S_Val      << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_64S        (SDHC_CA1R_TCNTRT_64S_Val      << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_128S       (SDHC_CA1R_TCNTRT_128S_Val     << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_256S       (SDHC_CA1R_TCNTRT_256S_Val     << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_512S       (SDHC_CA1R_TCNTRT_512S_Val     << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_1024S      (SDHC_CA1R_TCNTRT_1024S_Val    << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TCNTRT_OTHER      (SDHC_CA1R_TCNTRT_OTHER_Val    << SDHC_CA1R_TCNTRT_Pos)
#define SDHC_CA1R_TSDR50_Pos        13           
#define SDHC_CA1R_TSDR50            (_U_(0x1) << SDHC_CA1R_TSDR50_Pos)
#define   SDHC_CA1R_TSDR50_NO_Val         _U_(0x0)   
#define   SDHC_CA1R_TSDR50_YES_Val        _U_(0x1)   
#define SDHC_CA1R_TSDR50_NO         (SDHC_CA1R_TSDR50_NO_Val       << SDHC_CA1R_TSDR50_Pos)
#define SDHC_CA1R_TSDR50_YES        (SDHC_CA1R_TSDR50_YES_Val      << SDHC_CA1R_TSDR50_Pos)
#define SDHC_CA1R_CLKMULT_Pos       16           
#define SDHC_CA1R_CLKMULT_Msk       (_U_(0xFF) << SDHC_CA1R_CLKMULT_Pos)
#define SDHC_CA1R_CLKMULT(value)    (SDHC_CA1R_CLKMULT_Msk & ((value) << SDHC_CA1R_CLKMULT_Pos))
#define   SDHC_CA1R_CLKMULT_NO_Val        _U_(0x0)   
#define SDHC_CA1R_CLKMULT_NO        (SDHC_CA1R_CLKMULT_NO_Val      << SDHC_CA1R_CLKMULT_Pos)
#define SDHC_CA1R_MASK              _U_(0x00FF2F77) 
/* -------- SDHC_MCCAR : (SDHC Offset: 0x048) (R/  32) Maximum Current Capabilities -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t MAXCUR33V:8;      
    uint32_t MAXCUR30V:8;      
    uint32_t MAXCUR18V:8;      
    uint32_t :8;               
  } bit;                       
  uint32_t reg;                
} SDHC_MCCAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_MCCAR_OFFSET           0x048        
#define SDHC_MCCAR_RESETVALUE       _U_(0x00000000) 
#define SDHC_MCCAR_MAXCUR33V_Pos    0            
#define SDHC_MCCAR_MAXCUR33V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos)
#define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & ((value) << SDHC_MCCAR_MAXCUR33V_Pos))
#define   SDHC_MCCAR_MAXCUR33V_OTHER_Val  _U_(0x0)   
#define   SDHC_MCCAR_MAXCUR33V_4MA_Val    _U_(0x1)   
#define   SDHC_MCCAR_MAXCUR33V_8MA_Val    _U_(0x2)   
#define   SDHC_MCCAR_MAXCUR33V_12MA_Val   _U_(0x3)   
#define SDHC_MCCAR_MAXCUR33V_OTHER  (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos)
#define SDHC_MCCAR_MAXCUR33V_4MA    (SDHC_MCCAR_MAXCUR33V_4MA_Val  << SDHC_MCCAR_MAXCUR33V_Pos)
#define SDHC_MCCAR_MAXCUR33V_8MA    (SDHC_MCCAR_MAXCUR33V_8MA_Val  << SDHC_MCCAR_MAXCUR33V_Pos)
#define SDHC_MCCAR_MAXCUR33V_12MA   (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
#define SDHC_MCCAR_MAXCUR30V_Pos    8            
#define SDHC_MCCAR_MAXCUR30V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos)
#define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & ((value) << SDHC_MCCAR_MAXCUR30V_Pos))
#define   SDHC_MCCAR_MAXCUR30V_OTHER_Val  _U_(0x0)   
#define   SDHC_MCCAR_MAXCUR30V_4MA_Val    _U_(0x1)   
#define   SDHC_MCCAR_MAXCUR30V_8MA_Val    _U_(0x2)   
#define   SDHC_MCCAR_MAXCUR30V_12MA_Val   _U_(0x3)   
#define SDHC_MCCAR_MAXCUR30V_OTHER  (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos)
#define SDHC_MCCAR_MAXCUR30V_4MA    (SDHC_MCCAR_MAXCUR30V_4MA_Val  << SDHC_MCCAR_MAXCUR30V_Pos)
#define SDHC_MCCAR_MAXCUR30V_8MA    (SDHC_MCCAR_MAXCUR30V_8MA_Val  << SDHC_MCCAR_MAXCUR30V_Pos)
#define SDHC_MCCAR_MAXCUR30V_12MA   (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
#define SDHC_MCCAR_MAXCUR18V_Pos    16           
#define SDHC_MCCAR_MAXCUR18V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos)
#define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & ((value) << SDHC_MCCAR_MAXCUR18V_Pos))
#define   SDHC_MCCAR_MAXCUR18V_OTHER_Val  _U_(0x0)   
#define   SDHC_MCCAR_MAXCUR18V_4MA_Val    _U_(0x1)   
#define   SDHC_MCCAR_MAXCUR18V_8MA_Val    _U_(0x2)   
#define   SDHC_MCCAR_MAXCUR18V_12MA_Val   _U_(0x3)   
#define SDHC_MCCAR_MAXCUR18V_OTHER  (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos)
#define SDHC_MCCAR_MAXCUR18V_4MA    (SDHC_MCCAR_MAXCUR18V_4MA_Val  << SDHC_MCCAR_MAXCUR18V_Pos)
#define SDHC_MCCAR_MAXCUR18V_8MA    (SDHC_MCCAR_MAXCUR18V_8MA_Val  << SDHC_MCCAR_MAXCUR18V_Pos)
#define SDHC_MCCAR_MAXCUR18V_12MA   (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
#define SDHC_MCCAR_MASK             _U_(0x00FFFFFF) 
/* -------- SDHC_FERACES : (SDHC Offset: 0x050) ( /W 16) Force Event for Auto CMD Error Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t ACMD12NE:1;       
    uint16_t ACMDTEO:1;        
    uint16_t ACMDCRC:1;        
    uint16_t ACMDEND:1;        
    uint16_t ACMDIDX:1;        
    uint16_t :2;               
    uint16_t CMDNI:1;          
    uint16_t :8;               
  } bit;                       
  uint16_t reg;                
} SDHC_FERACES_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_FERACES_OFFSET         0x050        
#define SDHC_FERACES_RESETVALUE     _U_(0x0000)  
#define SDHC_FERACES_ACMD12NE_Pos   0            
#define SDHC_FERACES_ACMD12NE       (_U_(0x1) << SDHC_FERACES_ACMD12NE_Pos)
#define   SDHC_FERACES_ACMD12NE_NO_Val    _U_(0x0)   
#define   SDHC_FERACES_ACMD12NE_YES_Val   _U_(0x1)   
#define SDHC_FERACES_ACMD12NE_NO    (SDHC_FERACES_ACMD12NE_NO_Val  << SDHC_FERACES_ACMD12NE_Pos)
#define SDHC_FERACES_ACMD12NE_YES   (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos)
#define SDHC_FERACES_ACMDTEO_Pos    1            
#define SDHC_FERACES_ACMDTEO        (_U_(0x1) << SDHC_FERACES_ACMDTEO_Pos)
#define   SDHC_FERACES_ACMDTEO_NO_Val     _U_(0x0)   
#define   SDHC_FERACES_ACMDTEO_YES_Val    _U_(0x1)   
#define SDHC_FERACES_ACMDTEO_NO     (SDHC_FERACES_ACMDTEO_NO_Val   << SDHC_FERACES_ACMDTEO_Pos)
#define SDHC_FERACES_ACMDTEO_YES    (SDHC_FERACES_ACMDTEO_YES_Val  << SDHC_FERACES_ACMDTEO_Pos)
#define SDHC_FERACES_ACMDCRC_Pos    2            
#define SDHC_FERACES_ACMDCRC        (_U_(0x1) << SDHC_FERACES_ACMDCRC_Pos)
#define   SDHC_FERACES_ACMDCRC_NO_Val     _U_(0x0)   
#define   SDHC_FERACES_ACMDCRC_YES_Val    _U_(0x1)   
#define SDHC_FERACES_ACMDCRC_NO     (SDHC_FERACES_ACMDCRC_NO_Val   << SDHC_FERACES_ACMDCRC_Pos)
#define SDHC_FERACES_ACMDCRC_YES    (SDHC_FERACES_ACMDCRC_YES_Val  << SDHC_FERACES_ACMDCRC_Pos)
#define SDHC_FERACES_ACMDEND_Pos    3            
#define SDHC_FERACES_ACMDEND        (_U_(0x1) << SDHC_FERACES_ACMDEND_Pos)
#define   SDHC_FERACES_ACMDEND_NO_Val     _U_(0x0)   
#define   SDHC_FERACES_ACMDEND_YES_Val    _U_(0x1)   
#define SDHC_FERACES_ACMDEND_NO     (SDHC_FERACES_ACMDEND_NO_Val   << SDHC_FERACES_ACMDEND_Pos)
#define SDHC_FERACES_ACMDEND_YES    (SDHC_FERACES_ACMDEND_YES_Val  << SDHC_FERACES_ACMDEND_Pos)
#define SDHC_FERACES_ACMDIDX_Pos    4            
#define SDHC_FERACES_ACMDIDX        (_U_(0x1) << SDHC_FERACES_ACMDIDX_Pos)
#define   SDHC_FERACES_ACMDIDX_NO_Val     _U_(0x0)   
#define   SDHC_FERACES_ACMDIDX_YES_Val    _U_(0x1)   
#define SDHC_FERACES_ACMDIDX_NO     (SDHC_FERACES_ACMDIDX_NO_Val   << SDHC_FERACES_ACMDIDX_Pos)
#define SDHC_FERACES_ACMDIDX_YES    (SDHC_FERACES_ACMDIDX_YES_Val  << SDHC_FERACES_ACMDIDX_Pos)
#define SDHC_FERACES_CMDNI_Pos      7            
#define SDHC_FERACES_CMDNI          (_U_(0x1) << SDHC_FERACES_CMDNI_Pos)
#define   SDHC_FERACES_CMDNI_NO_Val       _U_(0x0)   
#define   SDHC_FERACES_CMDNI_YES_Val      _U_(0x1)   
#define SDHC_FERACES_CMDNI_NO       (SDHC_FERACES_CMDNI_NO_Val     << SDHC_FERACES_CMDNI_Pos)
#define SDHC_FERACES_CMDNI_YES      (SDHC_FERACES_CMDNI_YES_Val    << SDHC_FERACES_CMDNI_Pos)
#define SDHC_FERACES_MASK           _U_(0x009F)  
/* -------- SDHC_FEREIS : (SDHC Offset: 0x052) ( /W 16) Force Event for Error Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CMDTEO:1;         
    uint16_t CMDCRC:1;         
    uint16_t CMDEND:1;         
    uint16_t CMDIDX:1;         
    uint16_t DATTEO:1;         
    uint16_t DATCRC:1;         
    uint16_t DATEND:1;         
    uint16_t CURLIM:1;         
    uint16_t ACMD:1;           
    uint16_t ADMA:1;           
    uint16_t :2;               
    uint16_t BOOTAE:1;         
    uint16_t :3;               
  } bit;                       
  uint16_t reg;                
} SDHC_FEREIS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_FEREIS_OFFSET          0x052        
#define SDHC_FEREIS_RESETVALUE      _U_(0x0000)  
#define SDHC_FEREIS_CMDTEO_Pos      0            
#define SDHC_FEREIS_CMDTEO          (_U_(0x1) << SDHC_FEREIS_CMDTEO_Pos)
#define   SDHC_FEREIS_CMDTEO_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_CMDTEO_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_CMDTEO_NO       (SDHC_FEREIS_CMDTEO_NO_Val     << SDHC_FEREIS_CMDTEO_Pos)
#define SDHC_FEREIS_CMDTEO_YES      (SDHC_FEREIS_CMDTEO_YES_Val    << SDHC_FEREIS_CMDTEO_Pos)
#define SDHC_FEREIS_CMDCRC_Pos      1            
#define SDHC_FEREIS_CMDCRC          (_U_(0x1) << SDHC_FEREIS_CMDCRC_Pos)
#define   SDHC_FEREIS_CMDCRC_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_CMDCRC_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_CMDCRC_NO       (SDHC_FEREIS_CMDCRC_NO_Val     << SDHC_FEREIS_CMDCRC_Pos)
#define SDHC_FEREIS_CMDCRC_YES      (SDHC_FEREIS_CMDCRC_YES_Val    << SDHC_FEREIS_CMDCRC_Pos)
#define SDHC_FEREIS_CMDEND_Pos      2            
#define SDHC_FEREIS_CMDEND          (_U_(0x1) << SDHC_FEREIS_CMDEND_Pos)
#define   SDHC_FEREIS_CMDEND_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_CMDEND_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_CMDEND_NO       (SDHC_FEREIS_CMDEND_NO_Val     << SDHC_FEREIS_CMDEND_Pos)
#define SDHC_FEREIS_CMDEND_YES      (SDHC_FEREIS_CMDEND_YES_Val    << SDHC_FEREIS_CMDEND_Pos)
#define SDHC_FEREIS_CMDIDX_Pos      3            
#define SDHC_FEREIS_CMDIDX          (_U_(0x1) << SDHC_FEREIS_CMDIDX_Pos)
#define   SDHC_FEREIS_CMDIDX_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_CMDIDX_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_CMDIDX_NO       (SDHC_FEREIS_CMDIDX_NO_Val     << SDHC_FEREIS_CMDIDX_Pos)
#define SDHC_FEREIS_CMDIDX_YES      (SDHC_FEREIS_CMDIDX_YES_Val    << SDHC_FEREIS_CMDIDX_Pos)
#define SDHC_FEREIS_DATTEO_Pos      4            
#define SDHC_FEREIS_DATTEO          (_U_(0x1) << SDHC_FEREIS_DATTEO_Pos)
#define   SDHC_FEREIS_DATTEO_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_DATTEO_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_DATTEO_NO       (SDHC_FEREIS_DATTEO_NO_Val     << SDHC_FEREIS_DATTEO_Pos)
#define SDHC_FEREIS_DATTEO_YES      (SDHC_FEREIS_DATTEO_YES_Val    << SDHC_FEREIS_DATTEO_Pos)
#define SDHC_FEREIS_DATCRC_Pos      5            
#define SDHC_FEREIS_DATCRC          (_U_(0x1) << SDHC_FEREIS_DATCRC_Pos)
#define   SDHC_FEREIS_DATCRC_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_DATCRC_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_DATCRC_NO       (SDHC_FEREIS_DATCRC_NO_Val     << SDHC_FEREIS_DATCRC_Pos)
#define SDHC_FEREIS_DATCRC_YES      (SDHC_FEREIS_DATCRC_YES_Val    << SDHC_FEREIS_DATCRC_Pos)
#define SDHC_FEREIS_DATEND_Pos      6            
#define SDHC_FEREIS_DATEND          (_U_(0x1) << SDHC_FEREIS_DATEND_Pos)
#define   SDHC_FEREIS_DATEND_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_DATEND_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_DATEND_NO       (SDHC_FEREIS_DATEND_NO_Val     << SDHC_FEREIS_DATEND_Pos)
#define SDHC_FEREIS_DATEND_YES      (SDHC_FEREIS_DATEND_YES_Val    << SDHC_FEREIS_DATEND_Pos)
#define SDHC_FEREIS_CURLIM_Pos      7            
#define SDHC_FEREIS_CURLIM          (_U_(0x1) << SDHC_FEREIS_CURLIM_Pos)
#define   SDHC_FEREIS_CURLIM_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_CURLIM_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_CURLIM_NO       (SDHC_FEREIS_CURLIM_NO_Val     << SDHC_FEREIS_CURLIM_Pos)
#define SDHC_FEREIS_CURLIM_YES      (SDHC_FEREIS_CURLIM_YES_Val    << SDHC_FEREIS_CURLIM_Pos)
#define SDHC_FEREIS_ACMD_Pos        8            
#define SDHC_FEREIS_ACMD            (_U_(0x1) << SDHC_FEREIS_ACMD_Pos)
#define   SDHC_FEREIS_ACMD_NO_Val         _U_(0x0)   
#define   SDHC_FEREIS_ACMD_YES_Val        _U_(0x1)   
#define SDHC_FEREIS_ACMD_NO         (SDHC_FEREIS_ACMD_NO_Val       << SDHC_FEREIS_ACMD_Pos)
#define SDHC_FEREIS_ACMD_YES        (SDHC_FEREIS_ACMD_YES_Val      << SDHC_FEREIS_ACMD_Pos)
#define SDHC_FEREIS_ADMA_Pos        9            
#define SDHC_FEREIS_ADMA            (_U_(0x1) << SDHC_FEREIS_ADMA_Pos)
#define   SDHC_FEREIS_ADMA_NO_Val         _U_(0x0)   
#define   SDHC_FEREIS_ADMA_YES_Val        _U_(0x1)   
#define SDHC_FEREIS_ADMA_NO         (SDHC_FEREIS_ADMA_NO_Val       << SDHC_FEREIS_ADMA_Pos)
#define SDHC_FEREIS_ADMA_YES        (SDHC_FEREIS_ADMA_YES_Val      << SDHC_FEREIS_ADMA_Pos)
#define SDHC_FEREIS_BOOTAE_Pos      12           
#define SDHC_FEREIS_BOOTAE          (_U_(0x1) << SDHC_FEREIS_BOOTAE_Pos)
#define   SDHC_FEREIS_BOOTAE_NO_Val       _U_(0x0)   
#define   SDHC_FEREIS_BOOTAE_YES_Val      _U_(0x1)   
#define SDHC_FEREIS_BOOTAE_NO       (SDHC_FEREIS_BOOTAE_NO_Val     << SDHC_FEREIS_BOOTAE_Pos)
#define SDHC_FEREIS_BOOTAE_YES      (SDHC_FEREIS_BOOTAE_YES_Val    << SDHC_FEREIS_BOOTAE_Pos)
#define SDHC_FEREIS_MASK            _U_(0x13FF)  
/* -------- SDHC_AESR : (SDHC Offset: 0x054) (R/   8) ADMA Error Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  ERRST:2;          
    uint8_t  LMIS:1;           
    uint8_t  :5;               
  } bit;                       
  uint8_t reg;                 
} SDHC_AESR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_AESR_OFFSET            0x054        
#define SDHC_AESR_RESETVALUE        _U_(0x00)    
#define SDHC_AESR_ERRST_Pos         0            
#define SDHC_AESR_ERRST_Msk         (_U_(0x3) << SDHC_AESR_ERRST_Pos)
#define SDHC_AESR_ERRST(value)      (SDHC_AESR_ERRST_Msk & ((value) << SDHC_AESR_ERRST_Pos))
#define   SDHC_AESR_ERRST_STOP_Val        _U_(0x0)   
#define   SDHC_AESR_ERRST_FDS_Val         _U_(0x1)   
#define   SDHC_AESR_ERRST_2_Val           _U_(0x2)   
#define   SDHC_AESR_ERRST_TFR_Val         _U_(0x3)   
#define SDHC_AESR_ERRST_STOP        (SDHC_AESR_ERRST_STOP_Val      << SDHC_AESR_ERRST_Pos)
#define SDHC_AESR_ERRST_FDS         (SDHC_AESR_ERRST_FDS_Val       << SDHC_AESR_ERRST_Pos)
#define SDHC_AESR_ERRST_2           (SDHC_AESR_ERRST_2_Val         << SDHC_AESR_ERRST_Pos)
#define SDHC_AESR_ERRST_TFR         (SDHC_AESR_ERRST_TFR_Val       << SDHC_AESR_ERRST_Pos)
#define SDHC_AESR_LMIS_Pos          2            
#define SDHC_AESR_LMIS              (_U_(0x1) << SDHC_AESR_LMIS_Pos)
#define   SDHC_AESR_LMIS_NO_Val           _U_(0x0)   
#define   SDHC_AESR_LMIS_YES_Val          _U_(0x1)   
#define SDHC_AESR_LMIS_NO           (SDHC_AESR_LMIS_NO_Val         << SDHC_AESR_LMIS_Pos)
#define SDHC_AESR_LMIS_YES          (SDHC_AESR_LMIS_YES_Val        << SDHC_AESR_LMIS_Pos)
#define SDHC_AESR_MASK              _U_(0x07)    
/* -------- SDHC_ASAR : (SDHC Offset: 0x058) (R/W 32) ADMA System Address n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t ADMASA:32;        
  } bit;                       
  uint32_t reg;                
} SDHC_ASAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_ASAR_OFFSET            0x058        
#define SDHC_ASAR_RESETVALUE        _U_(0x00000000) 
#define SDHC_ASAR_ADMASA_Pos        0            
#define SDHC_ASAR_ADMASA_Msk        (_U_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos)
#define SDHC_ASAR_ADMASA(value)     (SDHC_ASAR_ADMASA_Msk & ((value) << SDHC_ASAR_ADMASA_Pos))
#define SDHC_ASAR_MASK              _U_(0xFFFFFFFF) 
/* -------- SDHC_PVR : (SDHC Offset: 0x060) (R/W 16) Preset Value n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t SDCLKFSEL:10;     
    uint16_t CLKGSEL:1;        
    uint16_t :3;               
    uint16_t DRVSEL:2;         
  } bit;                       
  uint16_t reg;                
} SDHC_PVR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_PVR_OFFSET             0x060        
#define SDHC_PVR_RESETVALUE         _U_(0x0000)  
#define SDHC_PVR_SDCLKFSEL_Pos      0            
#define SDHC_PVR_SDCLKFSEL_Msk      (_U_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos)
#define SDHC_PVR_SDCLKFSEL(value)   (SDHC_PVR_SDCLKFSEL_Msk & ((value) << SDHC_PVR_SDCLKFSEL_Pos))
#define SDHC_PVR_CLKGSEL_Pos        10           
#define SDHC_PVR_CLKGSEL            (_U_(0x1) << SDHC_PVR_CLKGSEL_Pos)
#define   SDHC_PVR_CLKGSEL_DIV_Val        _U_(0x0)   
#define   SDHC_PVR_CLKGSEL_PROG_Val       _U_(0x1)   
#define SDHC_PVR_CLKGSEL_DIV        (SDHC_PVR_CLKGSEL_DIV_Val      << SDHC_PVR_CLKGSEL_Pos)
#define SDHC_PVR_CLKGSEL_PROG       (SDHC_PVR_CLKGSEL_PROG_Val     << SDHC_PVR_CLKGSEL_Pos)
#define SDHC_PVR_DRVSEL_Pos         14           
#define SDHC_PVR_DRVSEL_Msk         (_U_(0x3) << SDHC_PVR_DRVSEL_Pos)
#define SDHC_PVR_DRVSEL(value)      (SDHC_PVR_DRVSEL_Msk & ((value) << SDHC_PVR_DRVSEL_Pos))
#define   SDHC_PVR_DRVSEL_B_Val           _U_(0x0)   
#define   SDHC_PVR_DRVSEL_A_Val           _U_(0x1)   
#define   SDHC_PVR_DRVSEL_C_Val           _U_(0x2)   
#define   SDHC_PVR_DRVSEL_D_Val           _U_(0x3)   
#define SDHC_PVR_DRVSEL_B           (SDHC_PVR_DRVSEL_B_Val         << SDHC_PVR_DRVSEL_Pos)
#define SDHC_PVR_DRVSEL_A           (SDHC_PVR_DRVSEL_A_Val         << SDHC_PVR_DRVSEL_Pos)
#define SDHC_PVR_DRVSEL_C           (SDHC_PVR_DRVSEL_C_Val         << SDHC_PVR_DRVSEL_Pos)
#define SDHC_PVR_DRVSEL_D           (SDHC_PVR_DRVSEL_D_Val         << SDHC_PVR_DRVSEL_Pos)
#define SDHC_PVR_MASK               _U_(0xC7FF)  
/* -------- SDHC_SISR : (SDHC Offset: 0x0FC) (R/  16) Slot Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t INTSSL:1;         
    uint16_t :15;              
  } bit;                       
  uint16_t reg;                
} SDHC_SISR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_SISR_OFFSET            0x0FC        
#define SDHC_SISR_RESETVALUE        _U_(0x20000) 
#define SDHC_SISR_INTSSL_Pos        0            
#define SDHC_SISR_INTSSL_Msk        (_U_(0x1) << SDHC_SISR_INTSSL_Pos)
#define SDHC_SISR_INTSSL(value)     (SDHC_SISR_INTSSL_Msk & ((value) << SDHC_SISR_INTSSL_Pos))
#define SDHC_SISR_MASK              _U_(0x0001)  
/* -------- SDHC_HCVR : (SDHC Offset: 0x0FE) (R/  16) Host Controller Version -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t SVER:8;           
    uint16_t VVER:8;           
  } bit;                       
  uint16_t reg;                
} SDHC_HCVR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_HCVR_OFFSET            0x0FE        
#define SDHC_HCVR_RESETVALUE        _U_(0x1802)  
#define SDHC_HCVR_SVER_Pos          0            
#define SDHC_HCVR_SVER_Msk          (_U_(0xFF) << SDHC_HCVR_SVER_Pos)
#define SDHC_HCVR_SVER(value)       (SDHC_HCVR_SVER_Msk & ((value) << SDHC_HCVR_SVER_Pos))
#define SDHC_HCVR_VVER_Pos          8            
#define SDHC_HCVR_VVER_Msk          (_U_(0xFF) << SDHC_HCVR_VVER_Pos)
#define SDHC_HCVR_VVER(value)       (SDHC_HCVR_VVER_Msk & ((value) << SDHC_HCVR_VVER_Pos))
#define SDHC_HCVR_MASK              _U_(0xFFFF)  
/* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W  8) MMC Control 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  CMDTYP:2;         
    uint8_t  :1;               
    uint8_t  DDR:1;            
    uint8_t  OPD:1;            
    uint8_t  BOOTA:1;          
    uint8_t  RSTN:1;           
    uint8_t  FCD:1;            
  } bit;                       
  uint8_t reg;                 
} SDHC_MC1R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_MC1R_OFFSET            0x204        
#define SDHC_MC1R_RESETVALUE        _U_(0x00)    
#define SDHC_MC1R_CMDTYP_Pos        0            
#define SDHC_MC1R_CMDTYP_Msk        (_U_(0x3) << SDHC_MC1R_CMDTYP_Pos)
#define SDHC_MC1R_CMDTYP(value)     (SDHC_MC1R_CMDTYP_Msk & ((value) << SDHC_MC1R_CMDTYP_Pos))
#define   SDHC_MC1R_CMDTYP_NORMAL_Val     _U_(0x0)   
#define   SDHC_MC1R_CMDTYP_WAITIRQ_Val    _U_(0x1)   
#define   SDHC_MC1R_CMDTYP_STREAM_Val     _U_(0x2)   
#define   SDHC_MC1R_CMDTYP_BOOT_Val       _U_(0x3)   
#define SDHC_MC1R_CMDTYP_NORMAL     (SDHC_MC1R_CMDTYP_NORMAL_Val   << SDHC_MC1R_CMDTYP_Pos)
#define SDHC_MC1R_CMDTYP_WAITIRQ    (SDHC_MC1R_CMDTYP_WAITIRQ_Val  << SDHC_MC1R_CMDTYP_Pos)
#define SDHC_MC1R_CMDTYP_STREAM     (SDHC_MC1R_CMDTYP_STREAM_Val   << SDHC_MC1R_CMDTYP_Pos)
#define SDHC_MC1R_CMDTYP_BOOT       (SDHC_MC1R_CMDTYP_BOOT_Val     << SDHC_MC1R_CMDTYP_Pos)
#define SDHC_MC1R_DDR_Pos           3            
#define SDHC_MC1R_DDR               (_U_(0x1) << SDHC_MC1R_DDR_Pos)
#define SDHC_MC1R_OPD_Pos           4            
#define SDHC_MC1R_OPD               (_U_(0x1) << SDHC_MC1R_OPD_Pos)
#define SDHC_MC1R_BOOTA_Pos         5            
#define SDHC_MC1R_BOOTA             (_U_(0x1) << SDHC_MC1R_BOOTA_Pos)
#define SDHC_MC1R_RSTN_Pos          6            
#define SDHC_MC1R_RSTN              (_U_(0x1) << SDHC_MC1R_RSTN_Pos)
#define SDHC_MC1R_FCD_Pos           7            
#define SDHC_MC1R_FCD               (_U_(0x1) << SDHC_MC1R_FCD_Pos)
#define SDHC_MC1R_MASK              _U_(0xFB)    
/* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W  8) MMC Control 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  SRESP:1;          
    uint8_t  ABOOT:1;          
    uint8_t  :6;               
  } bit;                       
  uint8_t reg;                 
} SDHC_MC2R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_MC2R_OFFSET            0x205        
#define SDHC_MC2R_RESETVALUE        _U_(0x00)    
#define SDHC_MC2R_SRESP_Pos         0            
#define SDHC_MC2R_SRESP             (_U_(0x1) << SDHC_MC2R_SRESP_Pos)
#define SDHC_MC2R_ABOOT_Pos         1            
#define SDHC_MC2R_ABOOT             (_U_(0x1) << SDHC_MC2R_ABOOT_Pos)
#define SDHC_MC2R_MASK              _U_(0x03)    
/* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t BMAX:2;           
    uint32_t :30;              
  } bit;                       
  uint32_t reg;                
} SDHC_ACR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_ACR_OFFSET             0x208        
#define SDHC_ACR_RESETVALUE         _U_(0x00000000) 
#define SDHC_ACR_BMAX_Pos           0            
#define SDHC_ACR_BMAX_Msk           (_U_(0x3) << SDHC_ACR_BMAX_Pos)
#define SDHC_ACR_BMAX(value)        (SDHC_ACR_BMAX_Msk & ((value) << SDHC_ACR_BMAX_Pos))
#define   SDHC_ACR_BMAX_INCR16_Val        _U_(0x0)   
#define   SDHC_ACR_BMAX_INCR8_Val         _U_(0x1)   
#define   SDHC_ACR_BMAX_INCR4_Val         _U_(0x2)   
#define   SDHC_ACR_BMAX_SINGLE_Val        _U_(0x3)   
#define SDHC_ACR_BMAX_INCR16        (SDHC_ACR_BMAX_INCR16_Val      << SDHC_ACR_BMAX_Pos)
#define SDHC_ACR_BMAX_INCR8         (SDHC_ACR_BMAX_INCR8_Val       << SDHC_ACR_BMAX_Pos)
#define SDHC_ACR_BMAX_INCR4         (SDHC_ACR_BMAX_INCR4_Val       << SDHC_ACR_BMAX_Pos)
#define SDHC_ACR_BMAX_SINGLE        (SDHC_ACR_BMAX_SINGLE_Val      << SDHC_ACR_BMAX_Pos)
#define SDHC_ACR_MASK               _U_(0x00000003) 
/* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t FSDCLKD:1;        
    uint32_t :31;              
  } bit;                       
  uint32_t reg;                
} SDHC_CC2R_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_CC2R_OFFSET            0x20C        
#define SDHC_CC2R_RESETVALUE        _U_(0x00000000) 
#define SDHC_CC2R_FSDCLKD_Pos       0            
#define SDHC_CC2R_FSDCLKD           (_U_(0x1) << SDHC_CC2R_FSDCLKD_Pos)
#define   SDHC_CC2R_FSDCLKD_NOEFFECT_Val  _U_(0x0)   
#define   SDHC_CC2R_FSDCLKD_DISABLE_Val   _U_(0x1)   
#define SDHC_CC2R_FSDCLKD_NOEFFECT  (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos)
#define SDHC_CC2R_FSDCLKD_DISABLE   (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos)
#define SDHC_CC2R_MASK              _U_(0x00000001) 
/* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t CAPWREN:1;        
    uint32_t :7;               
    uint32_t KEY:8;            
    uint32_t :16;              
  } bit;                       
  uint32_t reg;                
} SDHC_CACR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_CACR_OFFSET            0x230        
#define SDHC_CACR_RESETVALUE        _U_(0x00000000) 
#define SDHC_CACR_CAPWREN_Pos       0            
#define SDHC_CACR_CAPWREN           (_U_(0x1) << SDHC_CACR_CAPWREN_Pos)
#define SDHC_CACR_KEY_Pos           8            
#define SDHC_CACR_KEY_Msk           (_U_(0xFF) << SDHC_CACR_KEY_Pos)
#define SDHC_CACR_KEY(value)        (SDHC_CACR_KEY_Msk & ((value) << SDHC_CACR_KEY_Pos))
#define SDHC_CACR_MASK              _U_(0x0000FF01) 
/* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W  8) Debug -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  NIDBG:1;          
    uint8_t  :7;               
  } bit;                       
  uint8_t reg;                 
} SDHC_DBGR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define SDHC_DBGR_OFFSET            0x234        
#define SDHC_DBGR_RESETVALUE        _U_(0x00)    
#define SDHC_DBGR_NIDBG_Pos         0            
#define SDHC_DBGR_NIDBG             (_U_(0x1) << SDHC_DBGR_NIDBG_Pos)
#define   SDHC_DBGR_NIDBG_IDBG_Val        _U_(0x0)   
#define   SDHC_DBGR_NIDBG_NIDBG_Val       _U_(0x1)   
#define SDHC_DBGR_NIDBG_IDBG        (SDHC_DBGR_NIDBG_IDBG_Val      << SDHC_DBGR_NIDBG_Pos)
#define SDHC_DBGR_NIDBG_NIDBG       (SDHC_DBGR_NIDBG_NIDBG_Val     << SDHC_DBGR_NIDBG_Pos)
#define SDHC_DBGR_MASK              _U_(0x01)    
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __IO SDHC_SSAR_Type            SSAR;        
  __IO SDHC_BSR_Type             BSR;         
  __IO SDHC_BCR_Type             BCR;         
  __IO SDHC_ARG1R_Type           ARG1R;       
  __IO SDHC_TMR_Type             TMR;         
  __IO SDHC_CR_Type              CR;          
  __I  SDHC_RR_Type              RR[4];       
  __IO SDHC_BDPR_Type            BDPR;        
  __I  SDHC_PSR_Type             PSR;         
  __IO SDHC_HC1R_Type            HC1R;        
  __IO SDHC_PCR_Type             PCR;         
  __IO SDHC_BGCR_Type            BGCR;        
  __IO SDHC_WCR_Type             WCR;         
  __IO SDHC_CCR_Type             CCR;         
  __IO SDHC_TCR_Type             TCR;         
  __IO SDHC_SRR_Type             SRR;         
  __IO SDHC_NISTR_Type           NISTR;       
  __IO SDHC_EISTR_Type           EISTR;       
  __IO SDHC_NISTER_Type          NISTER;      
  __IO SDHC_EISTER_Type          EISTER;      
  __IO SDHC_NISIER_Type          NISIER;      
  __IO SDHC_EISIER_Type          EISIER;      
  __I  SDHC_ACESR_Type           ACESR;       
  __IO SDHC_HC2R_Type            HC2R;        
  __I  SDHC_CA0R_Type            CA0R;        
  __I  SDHC_CA1R_Type            CA1R;        
  __I  SDHC_MCCAR_Type           MCCAR;       
       RoReg8                    Reserved1[0x4];
  __O  SDHC_FERACES_Type         FERACES;     
  __O  SDHC_FEREIS_Type          FEREIS;      
  __I  SDHC_AESR_Type            AESR;        
       RoReg8                    Reserved2[0x3];
  __IO SDHC_ASAR_Type            ASAR[1];     
       RoReg8                    Reserved3[0x4];
  __IO SDHC_PVR_Type             PVR[8];      
       RoReg8                    Reserved4[0x8C];
  __I  SDHC_SISR_Type            SISR;        
  __I  SDHC_HCVR_Type            HCVR;        
       RoReg8                    Reserved5[0x104];
  __IO SDHC_MC1R_Type            MC1R;        
  __O  SDHC_MC2R_Type            MC2R;        
       RoReg8                    Reserved6[0x2];
  __IO SDHC_ACR_Type             ACR;         
  __IO SDHC_CC2R_Type            CC2R;        
       RoReg8                    Reserved7[0x20];
  __IO SDHC_CACR_Type            CACR;        
  __IO SDHC_DBGR_Type            DBGR;        
} Sdhc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#endif /* _SAME54_SDHC_COMPONENT_ */