ePenguin
/
ePenguin-Software-Framework
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

updated config with less options but same functionality

Browse Source
stable
penguin 4 years ago
parent 15d2ed1ef7
commit 0596887e45
4 changed files with 40 additions and 81 deletions
Show Stats Download Patch File Download Diff File

36
test/same54p20a_test/ESF/modules/core/clocks.c
Unescape Escape View File

@ -1,6 +1,42 @@
#include "clocks.h" #include "clocks.h"
#include "conf_core.h" #include "conf_core.h"
#if CORE_CONF_CLK_XOSC0_FREQUENCY > 24000000
#define CORE_CONF_CLK_XOSC0_IPTAT (3)
#define CORE_CONF_CLK_XOSC0_IMULT (6)
#define CORE_CONF_CLK_XOSC0_CFDPRESC (0x0)
#elif CORE_CONF_CLK_XOSC0_FREQUENCY > 16000000
#define CORE_CONF_CLK_XOSC0_IPTAT (3)
#define CORE_CONF_CLK_XOSC0_IMULT (5)
#define CORE_CONF_CLK_XOSC0_CFDPRESC (0x1)
#elif CORE_CONF_CLK_XOSC0_FREQUENCY > 8000000
#define CORE_CONF_CLK_XOSC0_IPTAT (3)
#define CORE_CONF_CLK_XOSC0_IMULT (4)
#define CORE_CONF_CLK_XOSC0_CFDPRESC (0x2)
#else
#define CORE_CONF_CLK_XOSC0_IPTAT (2)
#define CORE_CONF_CLK_XOSC0_IMULT (3)
#define CORE_CONF_CLK_XOSC0_CFDPRESC (0x3)
#endif
#if CORE_CONF_CLK_XOSC1_FREQUENCY > 24000000
#define CORE_CONF_CLK_XOSC1_IPTAT (3)
#define CORE_CONF_CLK_XOSC1_IMULT (6)
#define CORE_CONF_CLK_XOSC1_CFDPRESC (0x0)
#elif CORE_CONF_CLK_XOSC1_FREQUENCY > 16000000
#define CORE_CONF_CLK_XOSC1_IPTAT (3)
#define CORE_CONF_CLK_XOSC1_IMULT (5)
#define CORE_CONF_CLK_XOSC1_CFDPRESC (0x1)
#elif CORE_CONF_CLK_XOSC1_FREQUENCY > 8000000
#define CORE_CONF_CLK_XOSC1_IPTAT (3)
#define CORE_CONF_CLK_XOSC1_IMULT (4)
#define CORE_CONF_CLK_XOSC1_CFDPRESC (0x2)
#else
#define CORE_CONF_CLK_XOSC1_IPTAT (2)
#define CORE_CONF_CLK_XOSC1_IMULT (3)
#define CORE_CONF_CLK_XOSC1_CFDPRESC (0x3)
#endif
void clock_osc32k_init(void) void clock_osc32k_init(void)
{ {
#if CORE_CONF_CLK_XOSC32K_ENABLE == 1 #if CORE_CONF_CLK_XOSC32K_ENABLE == 1

1
test/same54p20a_test/ESF/modules/core/core.c
Unescape Escape View File

@ -23,7 +23,6 @@ void mcu_init(void)
// port event init // port event init
// cache init // cache init
mem_cache_init(); mem_cache_init();
} }

10
test/same54p20a_test/cfg/conf_core.h
Unescape Escape View File

@ -2,7 +2,7 @@
#define _CONF_CLOCKS_H_ #define _CONF_CLOCKS_H_
#include "clocks.h" #include "clocks.h"
#define CORE_CONF_MCLK_NVM_WAIT_STATE 0x0 #define CORE_CONF_MCLK_NVM_WAIT_STATE 0x5
#define CORE_CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val #define CORE_CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
// DMA Config // DMA Config
@ -19,13 +19,11 @@
#define CORE_CONF_CLK_XOSC0_RUNSTDBY (0) #define CORE_CONF_CLK_XOSC0_RUNSTDBY (0)
#define CORE_CONF_CLK_XOSC0_ONDEMAND (0) #define CORE_CONF_CLK_XOSC0_ONDEMAND (0)
#define CORE_CONF_CLK_XOSC0_LOWBUFGAIN (0) #define CORE_CONF_CLK_XOSC0_LOWBUFGAIN (0)
#define CORE_CONF_CLK_XOSC0_IPTAT CORE_CONF_CLK_XOSCCTRL_IPTAT_8MHZ_TO_16MHZ
#define CORE_CONF_CLK_XOSC0_IMULT CORE_CONF_CLK_XOSCCTRL_IMULT_8MHZ_TO_16MHZ
#define CORE_CONF_CLK_XOSC0_ENALC (1) #define CORE_CONF_CLK_XOSC0_ENALC (1)
#define CORE_CONF_CLK_XOSC0_CFDEN (1) #define CORE_CONF_CLK_XOSC0_CFDEN (1)
#define CORE_CONF_CLK_XOSC0_SWBEN (0) #define CORE_CONF_CLK_XOSC0_SWBEN (0)
#define CORE_CONF_CLK_XOSC0_STARTUP_TIME CORE_CONF_CLK_XOSCCTRL_STARTUP_31us #define CORE_CONF_CLK_XOSC0_STARTUP_TIME CORE_CONF_CLK_XOSCCTRL_STARTUP_31us
#define CORE_CONF_CLK_XOSC0_CFDPRESC (0x03) #define CORE_CONF_CLK_XOSC0_FREQUENCY 12000000
// XOSC1 Config // XOSC1 Config
#define CORE_CONF_CLK_XOSC1_ENABLE (0) #define CORE_CONF_CLK_XOSC1_ENABLE (0)
@ -33,13 +31,11 @@
#define CORE_CONF_CLK_XOSC1_RUNSTDBY (0) #define CORE_CONF_CLK_XOSC1_RUNSTDBY (0)
#define CORE_CONF_CLK_XOSC1_ONDEMAND (0) #define CORE_CONF_CLK_XOSC1_ONDEMAND (0)
#define CORE_CONF_CLK_XOSC1_LOWBUFGAIN (0) #define CORE_CONF_CLK_XOSC1_LOWBUFGAIN (0)
#define CORE_CONF_CLK_XOSC1_IPTAT CORE_CONF_CLK_XOSCCTRL_IPTAT_8MHZ
#define CORE_CONF_CLK_XOSC1_IMULT CORE_CONF_CLK_XOSCCTRL_IMULT_8MHZ
#define CORE_CONF_CLK_XOSC1_ENALC (0) #define CORE_CONF_CLK_XOSC1_ENALC (0)
#define CORE_CONF_CLK_XOSC1_CFDEN (0) #define CORE_CONF_CLK_XOSC1_CFDEN (0)
#define CORE_CONF_CLK_XOSC1_SWBEN (0) #define CORE_CONF_CLK_XOSC1_SWBEN (0)
#define CORE_CONF_CLK_XOSC1_STARTUP_TIME CORE_CONF_CLK_XOSCCTRL_STARTUP_31us #define CORE_CONF_CLK_XOSC1_STARTUP_TIME CORE_CONF_CLK_XOSCCTRL_STARTUP_31us
#define CORE_CONF_CLK_XOSC1_CFDPRESC (0) #define CORE_CONF_CLK_XOSC1_FREQUENCY 12000000
// XOSC32K Config // XOSC32K Config
#define CORE_CONF_CLK_XOSC32K_ENABLE (0) #define CORE_CONF_CLK_XOSC32K_ENABLE (0)

74
test/same54p20a_test/src/main.c
Unescape Escape View File

@ -2,82 +2,10 @@
#include "core.h" #include "core.h"
int main() int main()
{ {
/* // HRI_NVMCTRL_SET_CTRLA_RWS_bf */
/* // osc32kctrl_init */
/* // oscctrl_init */
/* // mclk_init */
/* // if GCLK_INIT_1ST */
/* // gclk_init_generators_by_freq FIRST */
/* // endif */
/* // oscctrl_init_referenced_generators */
/* // gclk_init_generators_by_fref LAST */
/* // */
/* // if dmac enable */
/* // hri_mclk_set_AHBMASK_DMAC_bit */
/* // dma init */
/* // endif */
/* // if CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | 2 | 3 */
/* // port event init */
/* // endif */
/* // if CONF_CMCC_ENABLE */
/* // cache init */
/* // endif */
/* // Run with 12mhz external crystal on XOSC0 */
/* // Automatic Loop Control */
/* // 0 - disable */
/* // 1 - enable */
/* OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; */
/* // Current Multiplier */
/* // 6 - >24MHz to 48MHz */
/* // 5 - >16MHz to 24MHz */
/* // 4 - >8MHz to 16MHz */
/* // 3 - 8MHz */
/* OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; */
/* // 3 - >24MHz to 48MHz */
/* // 3 - >16MHz to 24MHz */
/* // 3 - >8MHz to 16MHz */
/* // 2 - 8MHz */
/* OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; */
/* OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; */
/* OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; */
/* OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; */
/* while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); */
/* OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; */
/* OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; */
/* OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; */
/* // 0 - GCLK */
/* // 1 - XOSC32 */
/* // 2 - XOSC0 */
/* // 3 - XOSC1 */
/* OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; */
/* OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; */
/* OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; */
/* // wait for pll to be locked and ready */
/* while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK */
/* || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); */
/* // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB */
/* GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; */
/* while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); */
mcu_init(); mcu_init();
asm volatile("nop");
for(;;) for(;;)
{ {
asm volatile ("nop");
} }
return 0; return 0;
} }

Write Preview
Loading…
Cancel
Save