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Target voltage: 3.3V
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Available Targets:
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No. Att Driver
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1 Microchip SAME54N19A (rev A) M3/M4
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[31mCannot write the dashboard
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Traceback (most recent call last):
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File "<string>", line 511, in render
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File "<string>", line 601, in get_term_size
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IOError: [Errno 25] Inappropriate ioctl for device[0m
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0x000119d6 in ?? ()
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Breakpoint 1 at 0x330: file ../../../src/main.c, line 7.
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Loading section .text, size 0x39c lma 0x0
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Start address 0x0, load size 924
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Transfer rate: 18 KB/sec, 924 bytes/write.
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Traceback (most recent call last):
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File "<string>", line 417, in on_continue
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File "<string>", line 601, in get_term_size
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IOError: [Errno 25] Inappropriate ioctl for device
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Note: automatically using hardware breakpoints for read-only addresses.
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[31mCannot write the dashboard
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Traceback (most recent call last):
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File "<string>", line 511, in render
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File "<string>", line 601, in get_term_size
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IOError: [Errno 25] Inappropriate ioctl for device[0m
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Breakpoint 1, main () at ../../../src/main.c:7
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7 }
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Target voltage: 3.3V
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Available Targets:
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No. Att Driver
|
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|
1 Microchip SAME54N19A (rev A) M3/M4
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m0x000002e8[0m [1;30mReset_Handler+22[0m ldr r2, [pc, #60] ; (0x328 <Reset_Handler+86>)
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[1;30m0x000002ea[0m [1;30mReset_Handler+24[0m bic.w r3, r3, #127 ; 0x7f
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[1;30m0x000002ee[0m [1;30mReset_Handler+28[0m str r3, [r2, #8]
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[1;30m0x000002f0[0m [1;30mReset_Handler+30[0m bl 0x334 <__libc_init_array>
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[32m0x000002f4[0m[32m [0m[32m[0m[32mReset_Handler+34[0m[32m bl 0x330 <main>[0m
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[1;32m0x000002f8[0m[1;32m [0m[1;32m[0m[1;32mReset_Handler+38[0m[1;32m b.n 0x2f8 <Reset_Handler+38>[0m
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[1;30m0x000002fa[0m [1;30mReset_Handler+40[0m ldr r1, [pc, #48] ; (0x32c <Reset_Handler+90>)
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[1;30m0x000002fc[0m [1;30mReset_Handler+42[0m subs r2, #4
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[1;30m0x000002fe[0m [1;30mReset_Handler+44[0m cmp r3, r1
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[1;30m0x00000300[0m [1;30mReset_Handler+46[0m bcs.n 0x2dc <Reset_Handler+10>
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[36m───[0m [33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [1;32m0x00000000[0m [1;30mr1[0m [1;32m0x00000000[0m [1;30mr2[0m [1;32m0xe000ed00[0m [1;30mr3[0m [1;32m0x00000000[0m [1;30mr4[0m [1;32m0x000119d5[0m [1;30mr5[0m [1;32m0x20008abc[0m
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[1;30mr6[0m [1;32m0x200059d8[0m [1;30mr7[0m [1;32m0x000125c1[0m [1;30mr8[0m [1;32m0x000125b5[0m [1;30mr9[0m [1;32m0x200059d8[0m [1;30mr10[0m [1;32m0x20005a48[0m [1;30mr11[0m [1;32m0x2000db94[0m
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[1;30mr12[0m [1;32m0x00000000[0m [1;30msp[0m [1;32m0x20010018[0m [1;30mlr[0m [1;32m0x000002f9[0m [1;30mpc[0m [1;32m0x000002f8[0m [1;30mxpsr[0m [1;32m0x61000000[0m [1;30mfpscr[0m [1;32m0x00000000[0m
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[1;30mmsp[0m [1;32m0x20010018[0m [1;30mpsp[0m [1;32m0xfdff277c[0m [1;30mprimask[0m [1;32m0x00[0m [1;30mbasepri[0m [1;32m0x00[0m [1;30mfaultmask[0m [1;32m0x00[0m [1;30mcontrol[0m [1;32m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m523[0m /* Enable FPU */
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[1;30m524[0m SCB->CPACR |= (0xFu << 20);
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[1;30m525[0m __DSB();
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[1;30m526[0m __ISB();
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[1;30m527[0m #endif
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[1;30m528[0m
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[1;30m529[0m /* Initialize the C library */
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[1;30m530[0m __libc_init_array();
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[1;30m531[0m
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[1;30m532[0m /* Branch to main function */
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[1;32m533 main();
[0m
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[1;30m534[0m
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[1;30m535[0m /* Infinite loop */
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[1;30m536[0m while (1);
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[1;30m537[0m }
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[1;30m538[0m
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[1;30m539[0m /**
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[1;30m540[0m * \brief Default interrupt handler for unused IRQs.
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[1;30m541[0m */
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[1;30m542[0m void Dummy_Handler(void)
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m0[0m] from [1;32m0x000002f8[0m in [1;32mReset_Handler[0m+[1;32m38[0m at [1;32m../../../ESF/mcu/src/startup_same54.c[0m:[1;32m533[0m
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[[32m1[0m] from [32m0xfffffffe[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] id [1;32m0[0m from [1;32m0x000002f8[0m in [1;32mReset_Handler[0m+[1;32m38[0m at [1;32m../../../ESF/mcu/src/startup_same54.c[0m:[1;32m533[0m
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[36m───[0m [1;33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mloc[0m [1;37mpDest[0m [1;30m=[0m <optimized out>
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
0x000002f8 in Reset_Handler () at ../../../ESF/mcu/src/startup_same54.c:533
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533 main();
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Breakpoint 1 at 0x330: file ../../../src/main.c, line 7.
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Loading section .text, size 0x39c lma 0x0
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Start address 0x0, load size 924
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Transfer rate: 17 KB/sec, 924 bytes/write.
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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Note: automatically using hardware breakpoints for read-only addresses.
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[0;41m![0m[1;32m0x00000330[0m[1;32m [0m[1;32m[0m[1;32mmain+0[0m[1;32m movs r0, #0[0m
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[32m0x00000332[0m[32m [0m[32m[0m[32mmain+2[0m[32m bx lr[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m7[0m for [1;32mmain[0m hit [1;32m1[0m time
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [1;32m0x0000039c[0m [1;30mr1[0m [m0x00000000[0m [1;30mr2[0m [m0xe000ed00[0m [1;30mr3[0m [m0x00000000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
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[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
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[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000330[0m [1;30mxpsr[0m [m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
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[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m1[0m #include "igloo.h"
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[1;30m2[0m
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[1;30m3[0m
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[1;30m4[0m int main()
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[1;30m5[0m {
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[1;30m6[0m return 0;
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[0;41m![0m[1;32m7 }[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m0[0m] from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m7[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m7[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
Breakpoint 1, main () at ../../../src/main.c:7
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7 }
|
|
|
|
|
|
Target voltage: 3.3V
|
|
|
|
|
|
Available Targets:
|
|
|
|
|
|
No. Att Driver
|
|
|
|
|
|
1 Microchip SAME54N19A (rev A) M3/M4
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x000002e8[0m [1;30mReset_Handler+22[0m ldr r2, [pc, #60] ; (0x328 <Reset_Handler+86>)
|
|
|
|
|
|
[1;30m0x000002ea[0m [1;30mReset_Handler+24[0m bic.w r3, r3, #127 ; 0x7f
|
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|
|
|
|
[1;30m0x000002ee[0m [1;30mReset_Handler+28[0m str r3, [r2, #8]
|
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[1;30m0x000002f0[0m [1;30mReset_Handler+30[0m bl 0x334 <__libc_init_array>
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[32m0x000002f4[0m[32m [0m[32m[0m[32mReset_Handler+34[0m[32m bl 0x330 <main>[0m
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[1;32m0x000002f8[0m[1;32m [0m[1;32m[0m[1;32mReset_Handler+38[0m[1;32m b.n 0x2f8 <Reset_Handler+38>[0m
|
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|
[1;30m0x000002fa[0m [1;30mReset_Handler+40[0m ldr r1, [pc, #48] ; (0x32c <Reset_Handler+90>)
|
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[1;30m0x000002fc[0m [1;30mReset_Handler+42[0m subs r2, #4
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[1;30m0x000002fe[0m [1;30mReset_Handler+44[0m cmp r3, r1
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[1;30m0x00000300[0m [1;30mReset_Handler+46[0m bcs.n 0x2dc <Reset_Handler+10>
|
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[36m───[0m [33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[1;30mr0[0m [1;32m0x00000000[0m [1;30mr1[0m [1;32m0x00000000[0m [1;30mr2[0m [1;32m0xe000ed00[0m [1;30mr3[0m [1;32m0x00000000[0m [1;30mr4[0m [1;32m0x000119d5[0m [1;30mr5[0m [1;32m0x20008abc[0m
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[1;30mr6[0m [1;32m0x200059d8[0m [1;30mr7[0m [1;32m0x000125c1[0m [1;30mr8[0m [1;32m0x000125b5[0m [1;30mr9[0m [1;32m0x200059d8[0m [1;30mr10[0m [1;32m0x20005a48[0m [1;30mr11[0m [1;32m0x2000db94[0m
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[1;30mr12[0m [1;32m0x00000000[0m [1;30msp[0m [1;32m0x20010018[0m [1;30mlr[0m [1;32m0x000002f9[0m [1;30mpc[0m [1;32m0x000002f8[0m [1;30mxpsr[0m [1;32m0x61000000[0m [1;30mfpscr[0m [1;32m0x00000000[0m
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[1;30mmsp[0m [1;32m0x20010018[0m [1;30mpsp[0m [1;32m0xfdff277c[0m [1;30mprimask[0m [1;32m0x00[0m [1;30mbasepri[0m [1;32m0x00[0m [1;30mfaultmask[0m [1;32m0x00[0m [1;30mcontrol[0m [1;32m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[1;30m523[0m /* Enable FPU */
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[1;30m524[0m SCB->CPACR |= (0xFu << 20);
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[1;30m525[0m __DSB();
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[1;30m526[0m __ISB();
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[1;30m527[0m #endif
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[1;30m528[0m
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[1;30m529[0m /* Initialize the C library */
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[1;30m530[0m __libc_init_array();
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[1;30m531[0m
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[1;30m532[0m /* Branch to main function */
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[1;32m533 main();
[0m
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[1;30m534[0m
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[1;30m535[0m /* Infinite loop */
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[1;30m536[0m while (1);
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[1;30m537[0m }
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[1;30m538[0m
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[1;30m539[0m /**
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[1;30m540[0m * \brief Default interrupt handler for unused IRQs.
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[1;30m541[0m */
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[1;30m542[0m void Dummy_Handler(void)
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m0[0m] from [1;32m0x000002f8[0m in [1;32mReset_Handler[0m+[1;32m38[0m at [1;32m../../../ESF/mcu/src/startup_same54.c[0m:[1;32m533[0m
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[[32m1[0m] from [32m0xfffffffe[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] id [1;32m0[0m from [1;32m0x000002f8[0m in [1;32mReset_Handler[0m+[1;32m38[0m at [1;32m../../../ESF/mcu/src/startup_same54.c[0m:[1;32m533[0m
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[36m───[0m [1;33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mloc[0m [1;37mpDest[0m [1;30m=[0m <optimized out>
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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0x000002f8 in Reset_Handler () at ../../../ESF/mcu/src/startup_same54.c:533
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533 main();
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Breakpoint 1 at 0x332
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Loading section .text, size 0x39c lma 0x0
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Start address 0x0, load size 924
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Transfer rate: 18 KB/sec, 924 bytes/write.
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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Note: automatically using hardware breakpoints for read-only addresses.
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[0;41m![0m[1;32m0x00000330[0m[1;32m [0m[1;32m[0m[1;32mmain+0[0m[1;32m b.n 0x330 <main>[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m5[0m for [1;32mmain[0m hit [1;32m1[0m time
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [1;32m0x0000039c[0m [1;30mr1[0m [m0x00000000[0m [1;30mr2[0m [m0xe000ed00[0m [1;30mr3[0m [m0x00000000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
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[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
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[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000330[0m [1;30mxpsr[0m [m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
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[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m 1[0m #include "igloo.h"
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[1;30m 2[0m
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[1;30m 3[0m
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[1;30m 4[0m int main()
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[0;41m![0m[1;32m 5 {[0m
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[1;30m 6[0m for(;;)
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[1;30m 7[0m {
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[1;30m 8[0m
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[1;30m 9[0m }
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[1;30m10[0m return 0;
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[1;30m11[0m }
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
|
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[[1;32m0[0m] from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m5[0m
|
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m5[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
Breakpoint 1, main () at ../../../src/main.c:5
|
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|
|
5 {
|
|
|
|
|
|
Target voltage: 3.3V
|
|
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|
|
|
Available Targets:
|
|
|
|
|
|
No. Att Driver
|
|
|
|
|
|
1 Microchip SAME54N19A (rev A) M3/M4
|
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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|
|
[1;32m0x00000330[0m[1;32m [0m[1;32m[0m[1;32mmain+0[0m[1;32m b.n 0x330 <main>[0m
|
|
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|
|
[32m0x00000332[0m[32m [0m[32m[0m[32mmain+2[0m[32m movs r0, r0[0m
|
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|
[32m0x00000334[0m[32m [0m[32m[0m[32mmain+4[0m[32m push {r4, r5, r6, lr}[0m
|
|
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|
[32m0x00000336[0m[32m [0m[32m[0m[32mmain+6[0m[32m ldr r6, [pc, #52] ; (0x36c <main+60>)[0m
|
|
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|
|
[32m0x00000338[0m[32m [0m[32m[0m[32mmain+8[0m[32m ldr r4, [pc, #52] ; (0x370 <__libc_init_array>)[0m
|
|
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|
|
[36m───[0m [33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
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|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
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|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[1;30mr0[0m [1;32m0x0000039c[0m [1;30mr1[0m [1;32m0x00000000[0m [1;30mr2[0m [1;32m0xe000ed00[0m [1;30mr3[0m [1;32m0x00000000[0m [1;30mr4[0m [1;32m0x000119d5[0m [1;30mr5[0m [1;32m0x20008abc[0m
|
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|
|
|
|
[1;30mr6[0m [1;32m0x200059d8[0m [1;30mr7[0m [1;32m0x000125c1[0m [1;30mr8[0m [1;32m0x000125b5[0m [1;30mr9[0m [1;32m0x200059d8[0m [1;30mr10[0m [1;32m0x20005a48[0m [1;30mr11[0m [1;32m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [1;32m0x00000000[0m [1;30msp[0m [1;32m0x20010018[0m [1;30mlr[0m [1;32m0x000002f9[0m [1;30mpc[0m [1;32m0x00000330[0m [1;30mxpsr[0m [1;32m0x61000000[0m [1;30mfpscr[0m [1;32m0x00000000[0m
|
|
|
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|
|
[1;30mmsp[0m [1;32m0x20010018[0m [1;30mpsp[0m [1;32m0xfdff277c[0m [1;30mprimask[0m [1;32m0x00[0m [1;30mbasepri[0m [1;32m0x00[0m [1;30mfaultmask[0m [1;32m0x00[0m [1;30mcontrol[0m [1;32m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m 1[0m #include "igloo.h"
|
|
|
|
|
|
[1;30m 2[0m
|
|
|
|
|
|
[1;30m 3[0m
|
|
|
|
|
|
[1;30m 4[0m int main()
|
|
|
|
|
|
[1;30m 5[0m {
|
|
|
|
|
|
[1;30m 6[0m // Run with 12mhz external crystal on XOSC0
|
|
|
|
|
|
[1;30m 7[0m
|
|
|
|
|
|
[1;30m 8[0m // Automatic Loop Control
|
|
|
|
|
|
[1;30m 9[0m // 0 - disable
|
|
|
|
|
|
[1;30m10[0m // 1 - enable
|
|
|
|
|
|
[1;32m11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;[0m
|
|
|
|
|
|
[1;30m12[0m // Current Multiplier
|
|
|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
|
|
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|
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|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
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|
|
|
[[1;32m1[0m] id [1;32m0[0m from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
|
|
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|
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|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
main () at ../../../src/main.c:11
|
|
|
|
|
|
11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
|
|
|
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|
|
Breakpoint 1 at 0x330: file ../../../src/main.c, line 11.
|
|
|
|
|
|
Loading section .text, size 0x3d8 lma 0x0
|
|
|
|
|
|
Start address 0x0, load size 984
|
|
|
|
|
|
Transfer rate: 19 KB/sec, 984 bytes/write.
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
Note: automatically using hardware breakpoints for read-only addresses.
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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|
[0;41m![0m[1;32m0x00000330[0m[1;32m [0m[1;32m[0m[1;32mmain+0[0m[1;32m b.n 0x330 <main>[0m
|
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[32m0x00000332[0m[32m [0m[32m[0m[32mmain+2[0m[32m movs r0, r0[0m
|
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|
|
|
[32m0x00000334[0m[32m [0m[32m[0m[32mmain+4[0m[32m push {r4, r5, r6, lr}[0m
|
|
|
|
|
|
[32m0x00000336[0m[32m [0m[32m[0m[32mmain+6[0m[32m ldr r6, [pc, #52] ; (0x36c <main+60>)[0m
|
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|
|
[32m0x00000338[0m[32m [0m[32m[0m[32mmain+8[0m[32m ldr r4, [pc, #52] ; (0x370 <__libc_init_array>)[0m
|
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|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
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|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [1;32m0x000003d8[0m [1;30mr1[0m [m0x00000000[0m [1;30mr2[0m [m0xe000ed00[0m [1;30mr3[0m [m0x00000000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
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[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
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[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [m0x00000330[0m [1;30mxpsr[0m [m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
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[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m 1[0m #include "igloo.h"
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[1;30m 2[0m
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[1;30m 3[0m
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[1;30m 4[0m int main()
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[1;30m 5[0m {
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[1;30m 6[0m // Run with 12mhz external crystal on XOSC0
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[1;30m 7[0m
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[1;30m 8[0m // Automatic Loop Control
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[1;30m 9[0m // 0 - disable
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[1;30m10[0m // 1 - enable
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[0;41m![0m[1;32m11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;[0m
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[1;30m12[0m // Current Multiplier
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[1;30m13[0m // 6 - >24MHz to 48MHz
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[1;30m14[0m // 5 - >16MHz to 24MHz
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[1;30m15[0m // 4 - >8MHz to 16MHz
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[1;30m16[0m // 3 - 8MHz
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[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
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[1;30m18[0m // 3 - >24MHz to 48MHz
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[1;30m19[0m // 3 - >16MHz to 24MHz
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[1;30m20[0m // 3 - >8MHz to 16MHz
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m0[0m] from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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Breakpoint 1, main () at ../../../src/main.c:11
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11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[0;41m![0m[1;30m0x00000330[0m [1;30mmain+0 [0m b.n 0x330 <main>
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[1;30m0x00000332[0m [1;30mmain+2 [0m movs r0, r0
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[1;30m0x00000334[0m [1;30mmain+4 [0m push {r4, r5, r6, lr}
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[1;30m0x00000336[0m [1;30mmain+6 [0m ldr r6, [pc, #52] ; (0x36c <main+60>)
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[1;30m0x00000338[0m [1;30mmain+8 [0m ldr r4, [pc, #52] ; (0x370 <__libc_init_array>)
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[1;32m0x0000033a[0m[1;32m [0m[1;32m[0m[1;32mmain+10[0m[1;32m subs r4, r4, r6[0m
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[32m0x0000033c[0m[32m [0m[32m[0m[32mmain+12[0m[32m asrs r4, r4, #2[0m
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[32m0x0000033e[0m[32m [0m[32m[0m[32mmain+14[0m[32m movs r5, #0[0m
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[32m0x00000340[0m[32m [0m[32m[0m[32mmain+16[0m[32m cmp r5, r4[0m
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[32m0x00000342[0m[32m [0m[32m[0m[32mmain+18[0m[32m bne.n 0x358 <main+40>[0m
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|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
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|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000000[0m [1;30mr2[0m [1;32m0x00008080[0m [1;30mr3[0m [1;32m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000033a[0m [1;30mxpsr[0m [m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m 7[0m
|
|
|
|
|
|
[1;30m 8[0m // Automatic Loop Control
|
|
|
|
|
|
[1;30m 9[0m // 0 - disable
|
|
|
|
|
|
[1;30m10[0m // 1 - enable
|
|
|
|
|
|
[0;41m![0m[1;30m11[0m OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
|
|
|
|
|
|
[1;30m12[0m // Current Multiplier
|
|
|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;32m17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;[0m
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000033a[0m in [1;32mmain[0m+[1;32m10[0m at [1;32m../../../src/main.c[0m:[1;32m17[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000033a[0m in [1;32mmain[0m+[1;32m10[0m at [1;32m../../../src/main.c[0m:[1;32m17[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000033a[0m [1;30mmain+10[0m subs r4, r4, r6
|
|
|
|
|
|
[1;30m0x0000033c[0m [1;30mmain+12[0m asrs r4, r4, #2
|
|
|
|
|
|
[1;30m0x0000033e[0m [1;30mmain+14[0m movs r5, #0
|
|
|
|
|
|
[1;30m0x00000340[0m [1;30mmain+16[0m cmp r5, r4
|
|
|
|
|
|
[1;30m0x00000342[0m [1;30mmain+18[0m bne.n 0x358 <main+40>
|
|
|
|
|
|
[1;32m0x00000344[0m[1;32m [0m[1;32m[0m[1;32mmain+20[0m[1;32m ldr r6, [pc, #44] ; (0x374 <__libc_init_array+4>)[0m
|
|
|
|
|
|
[32m0x00000346[0m[32m [0m[32m[0m[32mmain+22[0m[32m ldr r4, [pc, #48] ; (0x378 <__libc_init_array+8>)[0m
|
|
|
|
|
|
[32m0x00000348[0m[32m [0m[32m[0m[32mmain+24[0m[32m bl 0x37c <__libc_init_array+12>[0m
|
|
|
|
|
|
[1;30m0x0000034c[0m [1;30mmain+28[0m subs r4, r4, r6
|
|
|
|
|
|
[1;30m0x0000034e[0m [1;30mmain+30[0m asrs r4, r4, #2
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [1;32m0x00000004[0m [1;30mr2[0m [1;32m0x0000a080[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000344[0m [1;30mxpsr[0m [1;32m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m12[0m // Current Multiplier
|
|
|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;32m22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;[0m
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000344[0m in [1;32mmain[0m+[1;32m20[0m at [1;32m../../../src/main.c[0m:[1;32m22[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000344[0m in [1;32mmain[0m+[1;32m20[0m at [1;32m../../../src/main.c[0m:[1;32m22[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000340[0m [1;30mmain+16[0m cmp r5, r4
|
|
|
|
|
|
[1;30m0x00000342[0m [1;30mmain+18[0m bne.n 0x358 <main+40>
|
|
|
|
|
|
[1;30m0x00000344[0m [1;30mmain+20[0m ldr r6, [pc, #44] ; (0x374 <__libc_init_array+4>)
|
|
|
|
|
|
[1;30m0x00000346[0m [1;30mmain+22[0m ldr r4, [pc, #48] ; (0x378 <__libc_init_array+8>)
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[1;30m0x00000348[0m [1;30mmain+24[0m bl 0x37c <__libc_init_array+12>
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[1;32m0x0000034c[0m[1;32m [0m[1;32m[0m[1;32mmain+28[0m[1;32m subs r4, r4, r6[0m
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[32m0x0000034e[0m[32m [0m[32m[0m[32mmain+30[0m[32m asrs r4, r4, #2[0m
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[32m0x00000350[0m[32m [0m[32m[0m[32mmain+32[0m[32m movs r5, #0[0m
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[32m0x00000352[0m[32m [0m[32m[0m[32mmain+34[0m[32m cmp r5, r4[0m
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[1;30m0x00000354[0m [1;30mmain+36[0m bne.n 0x362 <main+50>
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a680[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
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[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
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[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000034c[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
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[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[1;30m13[0m // 6 - >24MHz to 48MHz
|
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[1;30m14[0m // 5 - >16MHz to 24MHz
|
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[1;30m15[0m // 4 - >8MHz to 16MHz
|
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[1;30m16[0m // 3 - 8MHz
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|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
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|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
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|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
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[1;30m20[0m // 3 - >8MHz to 16MHz
|
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[1;30m21[0m // 2 - 8MHz
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|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
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|
[1;32m23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;[0m
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|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
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|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
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|
|
[1;30m26[0m
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[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
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|
[1;30m28[0m
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[1;30m29[0m
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[1;30m30[0m asm volatile("nop");
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[1;30m31[0m for(;;)
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[1;30m32[0m {
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|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
[[1;32m0[0m] from [1;32m0x0000034c[0m in [1;32mmain[0m+[1;32m28[0m at [1;32m../../../src/main.c[0m:[1;32m23[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000034c[0m in [1;32mmain[0m+[1;32m28[0m at [1;32m../../../src/main.c[0m:[1;32m23[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[1;30m0x00000348[0m [1;30mmain+24[0m bl 0x37c <__libc_init_array+12>
|
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[1;30m0x0000034c[0m [1;30mmain+28[0m subs r4, r4, r6
|
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[1;30m0x0000034e[0m [1;30mmain+30[0m asrs r4, r4, #2
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|
[1;30m0x00000350[0m [1;30mmain+32[0m movs r5, #0
|
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|
[1;30m0x00000352[0m [1;30mmain+34[0m cmp r5, r4
|
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[1;32m0x00000354[0m[1;32m [0m[1;32m[0m[1;32mmain+36[0m[1;32m bne.n 0x362 <main+50>[0m
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[32m0x00000356[0m[32m [0m[32m[0m[32mmain+38[0m[32m pop {r4, r5, r6, pc}[0m
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[32m0x00000358[0m[32m [0m[32m[0m[32mmain+40[0m[32m ldr.w r3, [r6, r5, lsl #2][0m
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|
[1;30m0x0000035c[0m [1;30mmain+44[0m blx r3
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|
[1;30m0x0000035e[0m [1;30mmain+46[0m adds r5, #1
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
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|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a600[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000354[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;32m24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;[0m
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000354[0m in [1;32mmain[0m+[1;32m36[0m at [1;32m../../../src/main.c[0m:[1;32m24[0m
|
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|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000354[0m in [1;32mmain[0m+[1;32m36[0m at [1;32m../../../src/main.c[0m:[1;32m24[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;32m0x0000035a[0m[1;32m [0m[1;32m[0m[1;32mmain+42[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
|
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|
|
|
|
[1;30m0x00000368[0m [1;30mmain+56[0m nop
|
|
|
|
|
|
[1;30m0x0000036a[0m [1;30mmain+58[0m b.n 0x36a <main+58>
|
|
|
|
|
|
[1;30m0x0000036c[0m [1;30mmain+60[0m asrs r0, r0, #32
|
|
|
|
|
|
[1;30m0x0000036e[0m [1;30mmain+62[0m ands r0, r0
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a604[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000035a[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;32m25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;[0m
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[1;30m34[0m }
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000035a[0m in [1;32mmain[0m+[1;32m42[0m at [1;32m../../../src/main.c[0m:[1;32m25[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000035a[0m in [1;32mmain[0m+[1;32m42[0m at [1;32m../../../src/main.c[0m:[1;32m25[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
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|
|
25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000356[0m [1;30mmain+38[0m orrs r2, r1
|
|
|
|
|
|
[1;30m0x00000358[0m [1;30mmain+40[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035a[0m [1;30mmain+42[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x00000362[0m[1;32m [0m[1;32m[0m[1;32mmain+50[0m[1;32m ldr r2, [r3, #16][0m
|
|
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|
|
|
[32m0x00000364[0m[32m [0m[32m[0m[32mmain+52[0m[32m lsls r2, r2, #31[0m
|
|
|
|
|
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[32m0x00000366[0m[32m [0m[32m[0m[32mmain+54[0m[32m bpl.n 0x362 <main+50>[0m
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|
|
|
[1;30m0x00000368[0m [1;30mmain+56[0m nop
|
|
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|
[1;30m0x0000036a[0m [1;30mmain+58[0m b.n 0x36a <main+58>
|
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|
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
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|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a606[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000362[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;32m27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);[0m
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[1;30m34[0m }
|
|
|
|
|
|
[1;30m35[0m return 0;
|
|
|
|
|
|
[1;30m36[0m }
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000362[0m in [1;32mmain[0m+[1;32m50[0m at [1;32m../../../src/main.c[0m:[1;32m27[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000362[0m in [1;32mmain[0m+[1;32m50[0m at [1;32m../../../src/main.c[0m:[1;32m27[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
|
|
|
|
|
|
[1;32m0x00000368[0m[1;32m [0m[1;32m[0m[1;32mmain+56[0m[1;32m nop[0m
|
|
|
|
|
|
[32m0x0000036a[0m[32m [0m[32m[0m[32mmain+58[0m[32m b.n 0x36a <main+58>[0m
|
|
|
|
|
|
[32m0x0000036c[0m[32m [0m[32m[0m[32mmain+60[0m[32m asrs r0, r0, #32[0m
|
|
|
|
|
|
[32m0x0000036e[0m[32m [0m[32m[0m[32mmain+62[0m[32m ands r0, r0[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x80000000[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000368[0m [1;30mxpsr[0m [1;32m0x81000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;32m30 asm volatile("nop");[0m
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[1;30m34[0m }
|
|
|
|
|
|
[1;30m35[0m return 0;
|
|
|
|
|
|
[1;30m36[0m }
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000368[0m in [1;32mmain[0m+[1;32m56[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000368[0m in [1;32mmain[0m+[1;32m56[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
30 asm volatile("nop");
|
|
|
|
|
|
Cannot access memory at address 0x40001010
|
|
|
|
|
|
$1 = {
|
|
|
|
|
|
bit = {
|
|
|
|
|
|
XOSCRDY0 = 1,
|
|
|
|
|
|
XOSCRDY1 = 0,
|
|
|
|
|
|
XOSCFAIL0 = 0,
|
|
|
|
|
|
XOSCFAIL1 = 0,
|
|
|
|
|
|
XOSCCKSW0 = 0,
|
|
|
|
|
|
XOSCCKSW1 = 0,
|
|
|
|
|
|
DFLLRDY = 1,
|
|
|
|
|
|
DFLLOOB = 0,
|
|
|
|
|
|
DFLLLCKF = 0,
|
|
|
|
|
|
DFLLLCKC = 0,
|
|
|
|
|
|
DFLLRCS = 0,
|
|
|
|
|
|
DPLL0LCKR = 0,
|
|
|
|
|
|
DPLL0LCKF = 0,
|
|
|
|
|
|
DPLL0TO = 0,
|
|
|
|
|
|
DPLL0LDRTO = 0,
|
|
|
|
|
|
DPLL1LCKR = 0,
|
|
|
|
|
|
DPLL1LCKF = 0,
|
|
|
|
|
|
DPLL1TO = 0,
|
|
|
|
|
|
DPLL1LDRTO = 0
|
|
|
|
|
|
},
|
|
|
|
|
|
vec = {
|
|
|
|
|
|
XOSCRDY = 1,
|
|
|
|
|
|
XOSCFAIL = 0,
|
|
|
|
|
|
XOSCCKSW = 0
|
|
|
|
|
|
},
|
|
|
|
|
|
reg = 257
|
|
|
|
|
|
}
|
|
|
|
|
|
$2 = 1
|
|
|
|
|
|
Target voltage: 3.3V
|
|
|
|
|
|
Available Targets:
|
|
|
|
|
|
No. Att Driver
|
|
|
|
|
|
1 Microchip SAME54N19A (rev A) M3/M4
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
|
|
|
|
|
|
[32m0x00000368[0m[32m [0m[32m[0m[32mmain+56[0m[32m nop[0m
|
|
|
|
|
|
[1;32m0x0000036a[0m[1;32m [0m[1;32m[0m[1;32mmain+58[0m[1;32m b.n 0x36a <main+58>[0m
|
|
|
|
|
|
[32m0x0000036c[0m[32m [0m[32m[0m[32mmain+60[0m[32m asrs r0, r0, #32[0m
|
|
|
|
|
|
[32m0x0000036e[0m[32m [0m[32m[0m[32mmain+62[0m[32m ands r0, r0[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [1;32m0x000003d8[0m [1;30mr1[0m [1;32m0x00000004[0m [1;30mr2[0m [1;32m0x80000000[0m [1;30mr3[0m [1;32m0x40001000[0m [1;30mr4[0m [1;32m0x000119d5[0m [1;30mr5[0m [1;32m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [1;32m0x200059d8[0m [1;30mr7[0m [1;32m0x000125c1[0m [1;30mr8[0m [1;32m0x000125b5[0m [1;30mr9[0m [1;32m0x200059d8[0m [1;30mr10[0m [1;32m0x20005a48[0m [1;30mr11[0m [1;32m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [1;32m0x00000000[0m [1;30msp[0m [1;32m0x20010018[0m [1;30mlr[0m [1;32m0x000002f9[0m [1;30mpc[0m [1;32m0x0000036a[0m [1;30mxpsr[0m [1;32m0x81000000[0m [1;30mfpscr[0m [1;32m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [1;32m0x20010018[0m [1;30mpsp[0m [1;32m0xfdff277c[0m [1;30mprimask[0m [1;32m0x00[0m [1;30mbasepri[0m [1;32m0x00[0m [1;30mfaultmask[0m [1;32m0x00[0m [1;30mcontrol[0m [1;32m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
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|
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[1;30m29[0m
|
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|
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|
[1;32m30 asm volatile("nop");[0m
|
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[1;30m31[0m for(;;)
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[1;30m32[0m {
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[1;30m33[0m
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[1;30m34[0m }
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|
[1;30m35[0m return 0;
|
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|
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|
[1;30m36[0m }
|
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|
[1;30m~[0m
|
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[1;30m~[0m
|
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[1;30m~[0m
|
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[[1;32m0[0m] from [1;32m0x0000036a[0m in [1;32mmain[0m+[1;32m58[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m1[0m] id [1;32m0[0m from [1;32m0x0000036a[0m in [1;32mmain[0m+[1;32m58[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
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|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
0x0000036a in main () at ../../../src/main.c:30
|
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|
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30 asm volatile("nop");
|
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Breakpoint 1 at 0x330: file ../../../src/main.c, line 11.
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Loading section .text, size 0x3d8 lma 0x0
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|
|
Start address 0x0, load size 984
|
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|
|
|
Transfer rate: 19 KB/sec, 984 bytes/write.
|
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|
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
Note: automatically using hardware breakpoints for read-only addresses.
|
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|
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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[1;30m~[0m
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|
[0;41m![0m[1;32m0x00000330[0m[1;32m [0m[1;32m[0m[1;32mmain+0 [0m[1;32m ldr r3, [pc, #56] ; (0x36c <main+60>)[0m
|
|
|
|
|
|
[32m0x00000332[0m[32m [0m[32m[0m[32mmain+2 [0m[32m ldr r2, [r3, #20][0m
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|
|
|
[32m0x00000334[0m[32m [0m[32m[0m[32mmain+4 [0m[32m orr.w r2, r2, #32768 ; 0x8000[0m
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|
[32m0x00000338[0m[32m [0m[32m[0m[32mmain+8 [0m[32m str r2, [r3, #20][0m
|
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|
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[1;30m0x0000033a[0m [1;30mmain+10[0m ldr r2, [r3, #20]
|
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|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
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|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [1;32m0x00000000[0m [1;30mr2[0m [1;32m0xe000ed00[0m [1;30mr3[0m [1;32m0x00000000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000330[0m [1;30mxpsr[0m [1;32m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m 1[0m #include "igloo.h"
|
|
|
|
|
|
[1;30m 2[0m
|
|
|
|
|
|
[1;30m 3[0m
|
|
|
|
|
|
[1;30m 4[0m int main()
|
|
|
|
|
|
[1;30m 5[0m {
|
|
|
|
|
|
[1;30m 6[0m // Run with 12mhz external crystal on XOSC0
|
|
|
|
|
|
[1;30m 7[0m
|
|
|
|
|
|
[1;30m 8[0m // Automatic Loop Control
|
|
|
|
|
|
[1;30m 9[0m // 0 - disable
|
|
|
|
|
|
[1;30m10[0m // 1 - enable
|
|
|
|
|
|
[0;41m![0m[1;32m11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;[0m
|
|
|
|
|
|
[1;30m12[0m // Current Multiplier
|
|
|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
|
|
|
|
|
|
Breakpoint 1, main () at ../../../src/main.c:11
|
|
|
|
|
|
11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
|
|
|
|
|
|
$1 = (Oscctrl *) 0x40001000
|
|
|
|
|
|
Cannot access memory at address 0x40001014
|
|
|
|
|
|
Target voltage: 3.3V
|
|
|
|
|
|
Available Targets:
|
|
|
|
|
|
No. Att Driver
|
|
|
|
|
|
1 Microchip SAME54N19A (rev A) M3/M4
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
|
|
|
|
|
|
[32m0x00000368[0m[32m [0m[32m[0m[32mmain+56[0m[32m nop[0m
|
|
|
|
|
|
[1;32m0x0000036a[0m[1;32m [0m[1;32m[0m[1;32mmain+58[0m[1;32m b.n 0x36a <main+58>[0m
|
|
|
|
|
|
[32m0x0000036c[0m[32m [0m[32m[0m[32mmain+60[0m[32m asrs r0, r0, #32[0m
|
|
|
|
|
|
[32m0x0000036e[0m[32m [0m[32m[0m[32mmain+62[0m[32m ands r0, r0[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [1;32m0x000003d8[0m [1;30mr1[0m [1;32m0x00000004[0m [1;30mr2[0m [1;32m0x80000000[0m [1;30mr3[0m [1;32m0x40001000[0m [1;30mr4[0m [1;32m0x000119d5[0m [1;30mr5[0m [1;32m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [1;32m0x200059d8[0m [1;30mr7[0m [1;32m0x000125c1[0m [1;30mr8[0m [1;32m0x000125b5[0m [1;30mr9[0m [1;32m0x200059d8[0m [1;30mr10[0m [1;32m0x20005a48[0m [1;30mr11[0m [1;32m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [1;32m0x00000000[0m [1;30msp[0m [1;32m0x20010018[0m [1;30mlr[0m [1;32m0x000002f9[0m [1;30mpc[0m [1;32m0x0000036a[0m [1;30mxpsr[0m [1;32m0x81000000[0m [1;30mfpscr[0m [1;32m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [1;32m0x20010018[0m [1;30mpsp[0m [1;32m0xfdff277c[0m [1;30mprimask[0m [1;32m0x00[0m [1;30mbasepri[0m [1;32m0x00[0m [1;30mfaultmask[0m [1;32m0x00[0m [1;30mcontrol[0m [1;32m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;32m30 asm volatile("nop");[0m
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[1;30m34[0m }
|
|
|
|
|
|
[1;30m35[0m return 0;
|
|
|
|
|
|
[1;30m36[0m }
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000036a[0m in [1;32mmain[0m+[1;32m58[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m0[0m from [1;32m0x0000036a[0m in [1;32mmain[0m+[1;32m58[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
0x0000036a in main () at ../../../src/main.c:30
|
|
|
|
|
|
30 asm volatile("nop");
|
|
|
|
|
|
Breakpoint 1 at 0x330: file ../../../src/main.c, line 11.
|
|
|
|
|
|
Loading section .text, size 0x3d8 lma 0x0
|
|
|
|
|
|
Start address 0x0, load size 984
|
|
|
|
|
|
Transfer rate: 19 KB/sec, 984 bytes/write.
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
Note: automatically using hardware breakpoints for read-only addresses.
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[0;41m![0m[1;32m0x00000330[0m[1;32m [0m[1;32m[0m[1;32mmain+0 [0m[1;32m ldr r3, [pc, #56] ; (0x36c <main+60>)[0m
|
|
|
|
|
|
[32m0x00000332[0m[32m [0m[32m[0m[32mmain+2 [0m[32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x00000334[0m[32m [0m[32m[0m[32mmain+4 [0m[32m orr.w r2, r2, #32768 ; 0x8000[0m
|
|
|
|
|
|
[32m0x00000338[0m[32m [0m[32m[0m[32mmain+8 [0m[32m str r2, [r3, #20][0m
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[1;30m0x0000033a[0m [1;30mmain+10[0m ldr r2, [r3, #20]
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
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|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [1;32m0x00000000[0m [1;30mr2[0m [1;32m0xe000ed00[0m [1;30mr3[0m [1;32m0x00000000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
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|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
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|
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|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000330[0m [1;30mxpsr[0m [1;32m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
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|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
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[1;30m 1[0m #include "igloo.h"
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[1;30m 2[0m
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[1;30m 3[0m
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[1;30m 4[0m int main()
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[1;30m 5[0m {
|
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[1;30m 6[0m // Run with 12mhz external crystal on XOSC0
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|
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[1;30m 7[0m
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[1;30m 8[0m // Automatic Loop Control
|
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[1;30m 9[0m // 0 - disable
|
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|
|
|
[1;30m10[0m // 1 - enable
|
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[0;41m![0m[1;32m11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;[0m
|
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|
|
[1;30m12[0m // Current Multiplier
|
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|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
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|
|
|
[1;30m16[0m // 3 - 8MHz
|
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|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
|
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|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m11[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
Breakpoint 1, main () at ../../../src/main.c:11
|
|
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|
|
|
11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
|
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|
|
|
$1 = {
|
|
|
|
|
|
bit = {
|
|
|
|
|
|
ENABLE = 0,
|
|
|
|
|
|
XTALEN = 0,
|
|
|
|
|
|
RUNSTDBY = 0,
|
|
|
|
|
|
ONDEMAND = 1,
|
|
|
|
|
|
LOWBUFGAIN = 0,
|
|
|
|
|
|
IPTAT = 0,
|
|
|
|
|
|
IMULT = 0,
|
|
|
|
|
|
ENALC = 0,
|
|
|
|
|
|
CFDEN = 0,
|
|
|
|
|
|
SWBEN = 0,
|
|
|
|
|
|
STARTUP = 0,
|
|
|
|
|
|
CFDPRESC = 0
|
|
|
|
|
|
},
|
|
|
|
|
|
reg = 128
|
|
|
|
|
|
}
|
|
|
|
|
|
Quit
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[0;41m![0m[1;30m0x00000330[0m [1;30mmain+0 [0m ldr r3, [pc, #56] ; (0x36c <main+60>)
|
|
|
|
|
|
[1;30m0x00000332[0m [1;30mmain+2 [0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000334[0m [1;30mmain+4 [0m orr.w r2, r2, #32768 ; 0x8000
|
|
|
|
|
|
[1;30m0x00000338[0m [1;30mmain+8 [0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x0000033a[0m[1;32m [0m[1;32m[0m[1;32mmain+10[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x0000033c[0m[32m [0m[32m[0m[32mmain+12[0m[32m movs r1, #4[0m
|
|
|
|
|
|
[32m0x0000033e[0m[32m [0m[32m[0m[32mmain+14[0m[32m bfi r2, r1, #11, #4[0m
|
|
|
|
|
|
[32m0x00000342[0m[32m [0m[32m[0m[32mmain+18[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x00000344[0m [1;30mmain+20[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;37m$$0[0m [1;30m=[0m {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN[0;41m…[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000000[0m [1;30mr2[0m [1;32m0x00008080[0m [1;30mr3[0m [1;32m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000033a[0m [1;30mxpsr[0m [m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m 7[0m
|
|
|
|
|
|
[1;30m 8[0m // Automatic Loop Control
|
|
|
|
|
|
[1;30m 9[0m // 0 - disable
|
|
|
|
|
|
[1;30m10[0m // 1 - enable
|
|
|
|
|
|
[0;41m![0m[1;30m11[0m OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
|
|
|
|
|
|
[1;30m12[0m // Current Multiplier
|
|
|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;32m17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;[0m
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000033a[0m in [1;32mmain[0m+[1;32m10[0m at [1;32m../../../src/main.c[0m:[1;32m17[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000033a[0m in [1;32mmain[0m+[1;32m10[0m at [1;32m../../../src/main.c[0m:[1;32m17[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000338[0m [1;30mmain+8 [0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000033a[0m [1;30mmain+10[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000033c[0m [1;30mmain+12[0m movs r1, #4
|
|
|
|
|
|
[1;30m0x0000033e[0m [1;30mmain+14[0m bfi r2, r1, #11, #4
|
|
|
|
|
|
[1;30m0x00000342[0m [1;30mmain+18[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x00000344[0m[1;32m [0m[1;32m[0m[1;32mmain+20[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x00000346[0m[32m [0m[32m[0m[32mmain+22[0m[32m orr.w r2, r2, #1536 ; 0x600[0m
|
|
|
|
|
|
[32m0x0000034a[0m[32m [0m[32m[0m[32mmain+26[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x0000034c[0m [1;30mmain+28[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000034e[0m [1;30mmain+30[0m bfc r2, #7, #1
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;37m$$0[0m [1;30m=[0m {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN[0;41m…[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [1;32m0x00000004[0m [1;30mr2[0m [1;32m0x0000a080[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000344[0m [1;30mxpsr[0m [1;32m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m12[0m // Current Multiplier
|
|
|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;32m22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;[0m
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
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[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
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|
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|
[1;30m26[0m
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|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
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[1;30m28[0m
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[1;30m29[0m
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[1;30m30[0m asm volatile("nop");
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[1;30m31[0m for(;;)
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m0[0m] from [1;32m0x00000344[0m in [1;32mmain[0m+[1;32m20[0m at [1;32m../../../src/main.c[0m:[1;32m22[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000344[0m in [1;32mmain[0m+[1;32m20[0m at [1;32m../../../src/main.c[0m:[1;32m22[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m0x0000033e[0m [1;30mmain+14[0m bfi r2, r1, #11, #4
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[1;30m0x00000342[0m [1;30mmain+18[0m str r2, [r3, #20]
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[1;30m0x00000344[0m [1;30mmain+20[0m ldr r2, [r3, #20]
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[1;30m0x00000346[0m [1;30mmain+22[0m orr.w r2, r2, #1536 ; 0x600
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[1;30m0x0000034a[0m [1;30mmain+26[0m str r2, [r3, #20]
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[1;32m0x0000034c[0m[1;32m [0m[1;32m[0m[1;32mmain+28[0m[1;32m ldr r2, [r3, #20][0m
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[32m0x0000034e[0m[32m [0m[32m[0m[32mmain+30[0m[32m bfc r2, #7, #1[0m
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[32m0x00000352[0m[32m [0m[32m[0m[32mmain+34[0m[32m str r2, [r3, #20][0m
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|
|
[1;30m0x00000354[0m [1;30mmain+36[0m ldr r2, [r3, #20]
|
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[1;30m0x00000356[0m [1;30mmain+38[0m orrs r2, r1
|
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[36m───[0m [1;33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[1;37m$$0[0m [1;30m=[0m {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN[0;41m…[0m
|
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|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a680[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000034c[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m13[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;32m23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;[0m
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000034c[0m in [1;32mmain[0m+[1;32m28[0m at [1;32m../../../src/main.c[0m:[1;32m23[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000034c[0m in [1;32mmain[0m+[1;32m28[0m at [1;32m../../../src/main.c[0m:[1;32m23[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000346[0m [1;30mmain+22[0m orr.w r2, r2, #1536 ; 0x600
|
|
|
|
|
|
[1;30m0x0000034a[0m [1;30mmain+26[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000034c[0m [1;30mmain+28[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000034e[0m [1;30mmain+30[0m bfc r2, #7, #1
|
|
|
|
|
|
[1;30m0x00000352[0m [1;30mmain+34[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x00000354[0m[1;32m [0m[1;32m[0m[1;32mmain+36[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x00000356[0m[32m [0m[32m[0m[32mmain+38[0m[32m orrs r2, r1[0m
|
|
|
|
|
|
[32m0x00000358[0m[32m [0m[32m[0m[32mmain+40[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x0000035a[0m [1;30mmain+42[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;37m$$0[0m [1;30m=[0m {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN[0;41m…[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a600[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000354[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m14[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;32m24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;[0m
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000354[0m in [1;32mmain[0m+[1;32m36[0m at [1;32m../../../src/main.c[0m:[1;32m24[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000354[0m in [1;32mmain[0m+[1;32m36[0m at [1;32m../../../src/main.c[0m:[1;32m24[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000034e[0m [1;30mmain+30[0m bfc r2, #7, #1
|
|
|
|
|
|
[1;30m0x00000352[0m [1;30mmain+34[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000354[0m [1;30mmain+36[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000356[0m [1;30mmain+38[0m orrs r2, r1
|
|
|
|
|
|
[1;30m0x00000358[0m [1;30mmain+40[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x0000035a[0m[1;32m [0m[1;32m[0m[1;32mmain+42[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x0000035c[0m[32m [0m[32m[0m[32mmain+44[0m[32m orr.w r2, r2, #2[0m
|
|
|
|
|
|
[32m0x00000360[0m[32m [0m[32m[0m[32mmain+48[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;37m$$0[0m [1;30m=[0m {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN[0;41m…[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a604[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000035a[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m15[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m16[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;32m25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;[0m
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[1;30m34[0m }
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000035a[0m in [1;32mmain[0m+[1;32m42[0m at [1;32m../../../src/main.c[0m:[1;32m25[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000035a[0m in [1;32mmain[0m+[1;32m42[0m at [1;32m../../../src/main.c[0m:[1;32m25[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000356[0m [1;30mmain+38[0m orrs r2, r1
|
|
|
|
|
|
[1;30m0x00000358[0m [1;30mmain+40[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035a[0m [1;30mmain+42[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x00000362[0m[1;32m [0m[1;32m[0m[1;32mmain+50[0m[1;32m ldr r2, [r3, #16][0m
|
|
|
|
|
|
[32m0x00000364[0m[32m [0m[32m[0m[32mmain+52[0m[32m lsls r2, r2, #31[0m
|
|
|
|
|
|
[32m0x00000366[0m[32m [0m[32m[0m[32mmain+54[0m[32m bpl.n 0x362 <main+50>[0m
|
|
|
|
|
|
[1;30m0x00000368[0m [1;30mmain+56[0m nop
|
|
|
|
|
|
[1;30m0x0000036a[0m [1;30mmain+58[0m b.n 0x36a <main+58>
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;37m$$0[0m [1;30m=[0m {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN[0;41m…[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a606[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000362[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m17[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m18[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m19[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;32m27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);[0m
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;30m30[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[1;30m34[0m }
|
|
|
|
|
|
[1;30m35[0m return 0;
|
|
|
|
|
|
[1;30m36[0m }
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000362[0m in [1;32mmain[0m+[1;32m50[0m at [1;32m../../../src/main.c[0m:[1;32m27[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000362[0m in [1;32mmain[0m+[1;32m50[0m at [1;32m../../../src/main.c[0m:[1;32m27[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
|
|
|
|
|
|
[1;32m0x00000368[0m[1;32m [0m[1;32m[0m[1;32mmain+56[0m[1;32m nop[0m
|
|
|
|
|
|
[32m0x0000036a[0m[32m [0m[32m[0m[32mmain+58[0m[32m b.n 0x36a <main+58>[0m
|
|
|
|
|
|
[32m0x0000036c[0m[32m [0m[32m[0m[32mmain+60[0m[32m asrs r0, r0, #32[0m
|
|
|
|
|
|
[32m0x0000036e[0m[32m [0m[32m[0m[32mmain+62[0m[32m ands r0, r0[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m11[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;37m$$0[0m [1;30m=[0m {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN[0;41m…[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x000003d8[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x80000000[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000368[0m [1;30mxpsr[0m [1;32m0x81000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m20[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m21[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m22[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m23[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m24[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m25[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m26[0m
|
|
|
|
|
|
[1;30m27[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m28[0m
|
|
|
|
|
|
[1;30m29[0m
|
|
|
|
|
|
[1;32m30 asm volatile("nop");[0m
|
|
|
|
|
|
[1;30m31[0m for(;;)
|
|
|
|
|
|
[1;30m32[0m {
|
|
|
|
|
|
[1;30m33[0m
|
|
|
|
|
|
[1;30m34[0m }
|
|
|
|
|
|
[1;30m35[0m return 0;
|
|
|
|
|
|
[1;30m36[0m }
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000368[0m in [1;32mmain[0m+[1;32m56[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000368[0m in [1;32mmain[0m+[1;32m56[0m at [1;32m../../../src/main.c[0m:[1;32m30[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
30 asm volatile("nop");
|
|
|
|
|
|
$2 = {
|
|
|
|
|
|
bit = {
|
|
|
|
|
|
ENABLE = 1,
|
|
|
|
|
|
XTALEN = 1,
|
|
|
|
|
|
RUNSTDBY = 0,
|
|
|
|
|
|
ONDEMAND = 0,
|
|
|
|
|
|
LOWBUFGAIN = 0,
|
|
|
|
|
|
IPTAT = 3,
|
|
|
|
|
|
IMULT = 4,
|
|
|
|
|
|
ENALC = 1,
|
|
|
|
|
|
CFDEN = 0,
|
|
|
|
|
|
SWBEN = 0,
|
|
|
|
|
|
STARTUP = 0,
|
|
|
|
|
|
CFDPRESC = 0
|
|
|
|
|
|
},
|
|
|
|
|
|
reg = 42502
|
|
|
|
|
|
}
|
|
|
|
|
|
Quit
|
|
|
|
|
|
Target voltage: 3.3V
|
|
|
|
|
|
Available Targets:
|
|
|
|
|
|
No. Att Driver
|
|
|
|
|
|
1 Microchip SAME54N19A (rev A) M3/M4
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
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[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
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[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
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[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
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[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
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[32m0x00000368[0m[32m [0m[32m[0m[32mmain+56[0m[32m nop[0m
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[1;32m0x0000036a[0m[1;32m [0m[1;32m[0m[1;32mmain+58[0m[1;32m b.n 0x36a <main+58>[0m
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[32m0x0000036c[0m[32m [0m[32m[0m[32mmain+60[0m[32m asrs r0, r0, #32[0m
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[32m0x0000036e[0m[32m [0m[32m[0m[32mmain+62[0m[32m ands r0, r0[0m
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[1;30m0x00000370[0m [1;30mmain+64[0m push {r4, r5, r6, lr}
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[1;30m0x00000372[0m [1;30mmain+66[0m ldr r6, [pc, #52] ; (0x3a8 <main+120>)
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[36m───[0m [33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [1;32m0x000003d8[0m [1;30mr1[0m [1;32m0x00000004[0m [1;30mr2[0m [1;32m0x80000000[0m [1;30mr3[0m [1;32m0x40001000[0m [1;30mr4[0m [1;32m0x000119d5[0m [1;30mr5[0m [1;32m0x20008abc[0m
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[1;30mr6[0m [1;32m0x200059d8[0m [1;30mr7[0m [1;32m0x000125c1[0m [1;30mr8[0m [1;32m0x000125b5[0m [1;30mr9[0m [1;32m0x200059d8[0m [1;30mr10[0m [1;32m0x20005a48[0m [1;30mr11[0m [1;32m0x2000db94[0m
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[1;30mr12[0m [1;32m0x00000000[0m [1;30msp[0m [1;32m0x20010018[0m [1;30mlr[0m [1;32m0x000002f9[0m [1;30mpc[0m [1;32m0x0000036a[0m [1;30mxpsr[0m [1;32m0x81000000[0m [1;30mfpscr[0m [1;32m0x00000000[0m
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[1;30mmsp[0m [1;32m0x20010018[0m [1;30mpsp[0m [1;32m0xfdff277c[0m [1;30mprimask[0m [1;32m0x00[0m [1;30mbasepri[0m [1;32m0x00[0m [1;30mfaultmask[0m [1;32m0x00[0m [1;30mcontrol[0m [1;32m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
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[1;30m47[0m // 3 - >8MHz to 16MHz
|
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[1;30m48[0m // 2 - 8MHz
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|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
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|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
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[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
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[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
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[1;30m53[0m
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[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
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[1;30m55[0m
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|
[1;32m56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;[0m
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|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
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|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
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[1;30m59[0m // 0 - GCLK
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[1;30m60[0m // 1 - XOSC32
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[1;30m61[0m // 2 - XOSC0
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[1;30m62[0m // 3 - XOSC1
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|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
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|
|
[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
|
|
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|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
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|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m0[0m] from [1;32m0x0000036a[0m in [1;32mmain[0m+[1;32m58[0m at [1;32m../../../src/main.c[0m:[1;32m56[0m
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|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m1[0m] id [1;32m0[0m from [1;32m0x0000036a[0m in [1;32mmain[0m+[1;32m58[0m at [1;32m../../../src/main.c[0m:[1;32m56[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
0x0000036a in main () at ../../../src/main.c:56
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|
|
56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
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|
Breakpoint 1 at 0x330: file ../../../src/main.c, line 38.
|
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|
Loading section .text, size 0x438 lma 0x0
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|
Start address 0x0, load size 1080
|
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|
Transfer rate: 19 KB/sec, 540 bytes/write.
|
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|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
Note: automatically using hardware breakpoints for read-only addresses.
|
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|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[1;30m~[0m
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|
[1;30m~[0m
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|
[1;30m~[0m
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|
[1;30m~[0m
|
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|
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|
[1;30m~[0m
|
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|
|
|
[0;41m![0m[1;32m0x00000330[0m[1;32m [0m[1;32m[0m[1;32mmain+0 [0m[1;32m ldr r3, [pc, #56] ; (0x36c <main+60>)[0m
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|
[32m0x00000332[0m[32m [0m[32m[0m[32mmain+2 [0m[32m ldr r2, [r3, #20][0m
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|
|
|
[32m0x00000334[0m[32m [0m[32m[0m[32mmain+4 [0m[32m orr.w r2, r2, #32768 ; 0x8000[0m
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|
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|
[32m0x00000338[0m[32m [0m[32m[0m[32mmain+8 [0m[32m str r2, [r3, #20][0m
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|
[1;30m0x0000033a[0m [1;30mmain+10[0m ldr r2, [r3, #20]
|
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|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
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|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [1;32m0x00000438[0m [1;30mr1[0m [1;32m0x00000000[0m [1;30mr2[0m [1;32m0xe000ed00[0m [1;30mr3[0m [1;32m0x00000000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000330[0m [1;30mxpsr[0m [1;32m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[1;30m28[0m // cache init
|
|
|
|
|
|
[1;30m29[0m // endif
|
|
|
|
|
|
[1;30m30[0m
|
|
|
|
|
|
[1;30m31[0m
|
|
|
|
|
|
[1;30m32[0m
|
|
|
|
|
|
[1;30m33[0m // Run with 12mhz external crystal on XOSC0
|
|
|
|
|
|
[1;30m34[0m
|
|
|
|
|
|
[1;30m35[0m // Automatic Loop Control
|
|
|
|
|
|
[1;30m36[0m // 0 - disable
|
|
|
|
|
|
[1;30m37[0m // 1 - enable
|
|
|
|
|
|
[0;41m![0m[1;32m38 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;[0m
|
|
|
|
|
|
[1;30m39[0m // Current Multiplier
|
|
|
|
|
|
[1;30m40[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m41[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m42[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m43[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m44[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m45[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m38[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000330[0m in [1;32mmain[0m+[1;32m0[0m at [1;32m../../../src/main.c[0m:[1;32m38[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
|
|
|
|
|
|
Breakpoint 1, main () at ../../../src/main.c:38
|
|
|
|
|
|
38 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[0;41m![0m[1;30m0x00000330[0m [1;30mmain+0 [0m ldr r3, [pc, #56] ; (0x36c <main+60>)
|
|
|
|
|
|
[1;30m0x00000332[0m [1;30mmain+2 [0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000334[0m [1;30mmain+4 [0m orr.w r2, r2, #32768 ; 0x8000
|
|
|
|
|
|
[1;30m0x00000338[0m [1;30mmain+8 [0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x0000033a[0m[1;32m [0m[1;32m[0m[1;32mmain+10[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x0000033c[0m[32m [0m[32m[0m[32mmain+12[0m[32m movs r1, #4[0m
|
|
|
|
|
|
[32m0x0000033e[0m[32m [0m[32m[0m[32mmain+14[0m[32m bfi r2, r1, #11, #4[0m
|
|
|
|
|
|
[32m0x00000342[0m[32m [0m[32m[0m[32mmain+18[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x00000344[0m [1;30mmain+20[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000000[0m [1;30mr2[0m [1;32m0x00008080[0m [1;30mr3[0m [1;32m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000033a[0m [1;30mxpsr[0m [m0x61000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m34[0m
|
|
|
|
|
|
[1;30m35[0m // Automatic Loop Control
|
|
|
|
|
|
[1;30m36[0m // 0 - disable
|
|
|
|
|
|
[1;30m37[0m // 1 - enable
|
|
|
|
|
|
[0;41m![0m[1;30m38[0m OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
|
|
|
|
|
|
[1;30m39[0m // Current Multiplier
|
|
|
|
|
|
[1;30m40[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m41[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m42[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m43[0m // 3 - 8MHz
|
|
|
|
|
|
[1;32m44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;[0m
|
|
|
|
|
|
[1;30m45[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
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|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m0[0m] from [1;32m0x0000033a[0m in [1;32mmain[0m+[1;32m10[0m at [1;32m../../../src/main.c[0m:[1;32m44[0m
|
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000033a[0m in [1;32mmain[0m+[1;32m10[0m at [1;32m../../../src/main.c[0m:[1;32m44[0m
|
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[1;30m0x00000338[0m [1;30mmain+8 [0m str r2, [r3, #20]
|
|
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|
|
|
[1;30m0x0000033a[0m [1;30mmain+10[0m ldr r2, [r3, #20]
|
|
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|
|
[1;30m0x0000033c[0m [1;30mmain+12[0m movs r1, #4
|
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|
|
|
|
[1;30m0x0000033e[0m [1;30mmain+14[0m bfi r2, r1, #11, #4
|
|
|
|
|
|
[1;30m0x00000342[0m [1;30mmain+18[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x00000344[0m[1;32m [0m[1;32m[0m[1;32mmain+20[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x00000346[0m[32m [0m[32m[0m[32mmain+22[0m[32m orr.w r2, r2, #1536 ; 0x600[0m
|
|
|
|
|
|
[32m0x0000034a[0m[32m [0m[32m[0m[32mmain+26[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x0000034c[0m [1;30mmain+28[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000034e[0m [1;30mmain+30[0m bfc r2, #7, #1
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [1;32m0x00000004[0m [1;30mr2[0m [1;32m0x0000a080[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000344[0m [1;30mxpsr[0m [1;32m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m39[0m // Current Multiplier
|
|
|
|
|
|
[1;30m40[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m41[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m42[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m43[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m44[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m45[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;32m49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;[0m
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000344[0m in [1;32mmain[0m+[1;32m20[0m at [1;32m../../../src/main.c[0m:[1;32m49[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000344[0m in [1;32mmain[0m+[1;32m20[0m at [1;32m../../../src/main.c[0m:[1;32m49[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000033e[0m [1;30mmain+14[0m bfi r2, r1, #11, #4
|
|
|
|
|
|
[1;30m0x00000342[0m [1;30mmain+18[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000344[0m [1;30mmain+20[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000346[0m [1;30mmain+22[0m orr.w r2, r2, #1536 ; 0x600
|
|
|
|
|
|
[1;30m0x0000034a[0m [1;30mmain+26[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x0000034c[0m[1;32m [0m[1;32m[0m[1;32mmain+28[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x0000034e[0m[32m [0m[32m[0m[32mmain+30[0m[32m bfc r2, #7, #1[0m
|
|
|
|
|
|
[32m0x00000352[0m[32m [0m[32m[0m[32mmain+34[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x00000354[0m [1;30mmain+36[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000356[0m [1;30mmain+38[0m orrs r2, r1
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a680[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000034c[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m40[0m // 6 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m41[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m42[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m43[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m44[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m45[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;32m50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;[0m
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000034c[0m in [1;32mmain[0m+[1;32m28[0m at [1;32m../../../src/main.c[0m:[1;32m50[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000034c[0m in [1;32mmain[0m+[1;32m28[0m at [1;32m../../../src/main.c[0m:[1;32m50[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000346[0m [1;30mmain+22[0m orr.w r2, r2, #1536 ; 0x600
|
|
|
|
|
|
[1;30m0x0000034a[0m [1;30mmain+26[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000034c[0m [1;30mmain+28[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000034e[0m [1;30mmain+30[0m bfc r2, #7, #1
|
|
|
|
|
|
[1;30m0x00000352[0m [1;30mmain+34[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x00000354[0m[1;32m [0m[1;32m[0m[1;32mmain+36[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x00000356[0m[32m [0m[32m[0m[32mmain+38[0m[32m orrs r2, r1[0m
|
|
|
|
|
|
[32m0x00000358[0m[32m [0m[32m[0m[32mmain+40[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x0000035a[0m [1;30mmain+42[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a600[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000354[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
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|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m41[0m // 5 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m42[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m43[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m44[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m45[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;32m51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;[0m
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000354[0m in [1;32mmain[0m+[1;32m36[0m at [1;32m../../../src/main.c[0m:[1;32m51[0m
|
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|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000354[0m in [1;32mmain[0m+[1;32m36[0m at [1;32m../../../src/main.c[0m:[1;32m51[0m
|
|
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|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
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|
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|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000034e[0m [1;30mmain+30[0m bfc r2, #7, #1
|
|
|
|
|
|
[1;30m0x00000352[0m [1;30mmain+34[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000354[0m [1;30mmain+36[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000356[0m [1;30mmain+38[0m orrs r2, r1
|
|
|
|
|
|
[1;30m0x00000358[0m [1;30mmain+40[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x0000035a[0m[1;32m [0m[1;32m[0m[1;32mmain+42[0m[1;32m ldr r2, [r3, #20][0m
|
|
|
|
|
|
[32m0x0000035c[0m[32m [0m[32m[0m[32mmain+44[0m[32m orr.w r2, r2, #2[0m
|
|
|
|
|
|
[32m0x00000360[0m[32m [0m[32m[0m[32mmain+48[0m[32m str r2, [r3, #20][0m
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a604[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000035a[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m42[0m // 4 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m43[0m // 3 - 8MHz
|
|
|
|
|
|
[1;30m44[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m45[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;32m52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;[0m
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000035a[0m in [1;32mmain[0m+[1;32m42[0m at [1;32m../../../src/main.c[0m:[1;32m52[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000035a[0m in [1;32mmain[0m+[1;32m42[0m at [1;32m../../../src/main.c[0m:[1;32m52[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000356[0m [1;30mmain+38[0m orrs r2, r1
|
|
|
|
|
|
[1;30m0x00000358[0m [1;30mmain+40[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035a[0m [1;30mmain+42[0m ldr r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;32m0x00000362[0m[1;32m [0m[1;32m[0m[1;32mmain+50[0m[1;32m ldr r2, [r3, #16][0m
|
|
|
|
|
|
[32m0x00000364[0m[32m [0m[32m[0m[32mmain+52[0m[32m lsls r2, r2, #31[0m
|
|
|
|
|
|
[32m0x00000366[0m[32m [0m[32m[0m[32mmain+54[0m[32m bpl.n 0x362 <main+50>[0m
|
|
|
|
|
|
[1;30m0x00000368[0m [1;30mmain+56[0m nop
|
|
|
|
|
|
[1;30m0x0000036a[0m [1;30mmain+58[0m b.n 0x36a <main+58>
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x0000a606[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000362[0m [1;30mxpsr[0m [m0x21000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m44[0m OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
|
|
|
|
|
|
[1;30m45[0m // 3 - >24MHz to 48MHz
|
|
|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;32m54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);[0m
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
|
|
|
|
|
[1;30m62[0m // 3 - XOSC1
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000362[0m in [1;32mmain[0m+[1;32m50[0m at [1;32m../../../src/main.c[0m:[1;32m54[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000362[0m in [1;32mmain[0m+[1;32m50[0m at [1;32m../../../src/main.c[0m:[1;32m54[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000035c[0m [1;30mmain+44[0m orr.w r2, r2, #2
|
|
|
|
|
|
[1;30m0x00000360[0m [1;30mmain+48[0m str r2, [r3, #20]
|
|
|
|
|
|
[1;30m0x00000362[0m [1;30mmain+50[0m ldr r2, [r3, #16]
|
|
|
|
|
|
[1;30m0x00000364[0m [1;30mmain+52[0m lsls r2, r2, #31
|
|
|
|
|
|
[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
|
|
|
|
|
|
[1;32m0x00000368[0m[1;32m [0m[1;32m[0m[1;32mmain+56[0m[1;32m nop[0m
|
|
|
|
|
|
[32m0x0000036a[0m[32m [0m[32m[0m[32mmain+58[0m[32m b.n 0x36a <main+58>[0m
|
|
|
|
|
|
[32m0x0000036c[0m[32m [0m[32m[0m[32mmain+60[0m[32m asrs r0, r0, #32[0m
|
|
|
|
|
|
[32m0x0000036e[0m[32m [0m[32m[0m[32mmain+62[0m[32m ands r0, r0[0m
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|
|
[1;30m0x00000370[0m [1;30mmain+64[0m push {r4, r5, r6, lr}
|
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|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x80000000[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
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|
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[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
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|
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|
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[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000368[0m [1;30mxpsr[0m [1;32m0x81000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
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|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[1;30m46[0m // 3 - >16MHz to 24MHz
|
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|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;32m56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;[0m
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
|
|
|
|
|
[1;30m62[0m // 3 - XOSC1
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000368[0m in [1;32mmain[0m+[1;32m56[0m at [1;32m../../../src/main.c[0m:[1;32m56[0m
|
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|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000368[0m in [1;32mmain[0m+[1;32m56[0m at [1;32m../../../src/main.c[0m:[1;32m56[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
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|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[1;30m0x00000366[0m [1;30mmain+54[0m bpl.n 0x362 <main+50>
|
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|
|
|
[1;30m0x00000368[0m [1;30mmain+56[0m nop
|
|
|
|
|
|
[1;30m0x0000036a[0m [1;30mmain+58[0m b.n 0x36a <main+58>
|
|
|
|
|
|
[1;30m0x0000036c[0m [1;30mmain+60[0m asrs r0, r0, #32
|
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|
|
|
|
[1;30m0x0000036e[0m [1;30mmain+62[0m ands r0, r0
|
|
|
|
|
|
[1;32m0x00000370[0m[1;32m [0m[1;32m[0m[1;32mmain+64[0m[1;32m push {r4, r5, r6, lr}[0m
|
|
|
|
|
|
[32m0x00000372[0m[32m [0m[32m[0m[32mmain+66[0m[32m ldr r6, [pc, #52] ; (0x3a8 <main+120>)[0m
|
|
|
|
|
|
[32m0x00000374[0m[32m [0m[32m[0m[32mmain+68[0m[32m ldr r4, [pc, #52] ; (0x3ac <main+124>)[0m
|
|
|
|
|
|
[32m0x00000376[0m[32m [0m[32m[0m[32mmain+70[0m[32m subs r4, r4, r6[0m
|
|
|
|
|
|
[32m0x00000378[0m[32m [0m[32m[0m[32mmain+72[0m[32m asrs r4, r4, #2[0m
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000004[0m [1;30mr2[0m [1;32m0x00000000[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000370[0m [1;30mxpsr[0m [m0x81000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m47[0m // 3 - >8MHz to 16MHz
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;32m57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;[0m
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
|
|
|
|
|
[1;30m62[0m // 3 - XOSC1
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m66[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x00000370[0m in [1;32mmain[0m+[1;32m64[0m at [1;32m../../../src/main.c[0m:[1;32m57[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000370[0m in [1;32mmain[0m+[1;32m64[0m at [1;32m../../../src/main.c[0m:[1;32m57[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x00000370[0m [1;30mmain+64[0m push {r4, r5, r6, lr}
|
|
|
|
|
|
[1;30m0x00000372[0m [1;30mmain+66[0m ldr r6, [pc, #52] ; (0x3a8 <main+120>)
|
|
|
|
|
|
[1;30m0x00000374[0m [1;30mmain+68[0m ldr r4, [pc, #52] ; (0x3ac <main+124>)
|
|
|
|
|
|
[1;30m0x00000376[0m [1;30mmain+70[0m subs r4, r4, r6
|
|
|
|
|
|
[1;30m0x00000378[0m [1;30mmain+72[0m asrs r4, r4, #2
|
|
|
|
|
|
[1;32m0x0000037a[0m[1;32m [0m[1;32m[0m[1;32mmain+74[0m[1;32m movs r5, #0[0m
|
|
|
|
|
|
[32m0x0000037c[0m[32m [0m[32m[0m[32mmain+76[0m[32m cmp r5, r4[0m
|
|
|
|
|
|
[32m0x0000037e[0m[32m [0m[32m[0m[32mmain+78[0m[32m bne.n 0x394 <main+100>[0m
|
|
|
|
|
|
[32m0x00000380[0m[32m [0m[32m[0m[32mmain+80[0m[32m ldr r6, [pc, #44] ; (0x3b0 <main+128>)[0m
|
|
|
|
|
|
[32m0x00000382[0m[32m [0m[32m[0m[32mmain+82[0m[32m ldr r4, [pc, #48] ; (0x3b4 <main+132>)[0m
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [1;32m0x00000077[0m [1;30mr2[0m [1;32m0x00000077[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000037a[0m [1;30mxpsr[0m [1;32m0x01000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m48[0m // 2 - 8MHz
|
|
|
|
|
|
[1;30m49[0m OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
|
|
|
|
|
|
[1;30m50[0m OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m51[0m OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
|
|
|
|
|
|
[1;30m52[0m OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m53[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;32m58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;[0m
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
|
|
|
|
|
[1;30m62[0m // 3 - XOSC1
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m66[0m
|
|
|
|
|
|
[1;30m67[0m // wait for pll to be locked and ready
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x0000037a[0m in [1;32mmain[0m+[1;32m74[0m at [1;32m../../../src/main.c[0m:[1;32m58[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000037a[0m in [1;32mmain[0m+[1;32m74[0m at [1;32m../../../src/main.c[0m:[1;32m58[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m0x0000037a[0m [1;30mmain+74[0m movs r5, #0
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[1;30m0x0000037c[0m [1;30mmain+76[0m cmp r5, r4
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[1;30m0x0000037e[0m [1;30mmain+78[0m bne.n 0x394 <main+100>
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[1;30m0x00000380[0m [1;30mmain+80[0m ldr r6, [pc, #44] ; (0x3b0 <main+128>)
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[1;30m0x00000382[0m [1;30mmain+82[0m ldr r4, [pc, #48] ; (0x3b4 <main+132>)
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[1;32m0x00000384[0m[1;32m [0m[1;32m[0m[1;32mmain+84[0m[1;32m bl 0x3b8 <main+136>[0m
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[32m0x00000388[0m[32m [0m[32m[0m[32mmain+88[0m[32m subs r4, r4, r6[0m
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[32m0x0000038a[0m[32m [0m[32m[0m[32mmain+90[0m[32m asrs r4, r4, #2[0m
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[32m0x0000038c[0m[32m [0m[32m[0m[32mmain+92[0m[32m movs r5, #0[0m
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[1;30m0x0000038e[0m [1;30mmain+94[0m cmp r5, r4
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [1;32m0x00000005[0m [1;30mr2[0m [1;32m0x00050020[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
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[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
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[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x00000384[0m [1;30mxpsr[0m [m0x01000000[0m [1;30mfpscr[0m [m0x00000000[0m
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[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[1;30m53[0m
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[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
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[1;30m55[0m
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[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
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[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
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[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
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[1;30m59[0m // 0 - GCLK
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[1;30m60[0m // 1 - XOSC32
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[1;30m61[0m // 2 - XOSC0
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[1;30m62[0m // 3 - XOSC1
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[1;32m63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;[0m
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[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
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[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
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[1;30m66[0m
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[1;30m67[0m // wait for pll to be locked and ready
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|
|
[1;30m68[0m while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
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|
[1;30m69[0m || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
|
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|
|
[1;30m70[0m
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|
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[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
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[1;30m72[0m GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
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|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
[[1;32m0[0m] from [1;32m0x00000384[0m in [1;32mmain[0m+[1;32m84[0m at [1;32m../../../src/main.c[0m:[1;32m63[0m
|
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|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x00000384[0m in [1;32mmain[0m+[1;32m84[0m at [1;32m../../../src/main.c[0m:[1;32m63[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
[1;30m0x00000382[0m [1;30mmain+82 [0m ldr r4, [pc, #48] ; (0x3b4 <main+132>)
|
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|
|
[1;30m0x00000384[0m [1;30mmain+84 [0m bl 0x3b8 <main+136>
|
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|
|
|
[1;30m0x00000388[0m [1;30mmain+88 [0m subs r4, r4, r6
|
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|
|
|
[1;30m0x0000038a[0m [1;30mmain+90 [0m asrs r4, r4, #2
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|
|
[1;30m0x0000038c[0m [1;30mmain+92 [0m movs r5, #0
|
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|
[1;32m0x0000038e[0m[1;32m [0m[1;32m[0m[1;32mmain+94 [0m[1;32m cmp r5, r4[0m
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[32m0x00000390[0m[32m [0m[32m[0m[32mmain+96 [0m[32m bne.n 0x39e <main+110>[0m
|
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|
[32m0x00000392[0m[32m [0m[32m[0m[32mmain+98 [0m[32m pop {r4, r5, r6, pc}[0m
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[32m0x00000394[0m[32m [0m[32m[0m[32mmain+100[0m[32m ldr.w r3, [r6, r5, lsl #2][0m
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[32m0x00000398[0m[32m [0m[32m[0m[32mmain+104[0m[32m blx r3[0m
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|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
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|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [1;32m0x00000002[0m [1;30mr2[0m [1;32m0x00050040[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
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|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
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|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000038e[0m [1;30mxpsr[0m [m0x01000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
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|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
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|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m54[0m while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
|
|
|
|
|
|
[1;30m55[0m
|
|
|
|
|
|
[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
|
|
|
|
|
|
[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
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|
|
|
|
[1;30m62[0m // 3 - XOSC1
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[1;32m64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;[0m
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|
|
|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m66[0m
|
|
|
|
|
|
[1;30m67[0m // wait for pll to be locked and ready
|
|
|
|
|
|
[1;30m68[0m while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
|
|
|
|
|
|
[1;30m69[0m || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
|
|
|
|
|
|
[1;30m70[0m
|
|
|
|
|
|
[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
|
|
|
|
|
|
[1;30m72[0m GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
|
|
|
|
|
|
[1;30m73[0m while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[[1;32m0[0m] from [1;32m0x0000038e[0m in [1;32mmain[0m+[1;32m94[0m at [1;32m../../../src/main.c[0m:[1;32m64[0m
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|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000038e[0m in [1;32mmain[0m+[1;32m94[0m at [1;32m../../../src/main.c[0m:[1;32m64[0m
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|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
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|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x0000038e[0m [1;30mmain+94 [0m cmp r5, r4
|
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|
|
|
|
[1;30m0x00000390[0m [1;30mmain+96 [0m bne.n 0x39e <main+110>
|
|
|
|
|
|
[1;30m0x00000392[0m [1;30mmain+98 [0m pop {r4, r5, r6, pc}
|
|
|
|
|
|
[1;30m0x00000394[0m [1;30mmain+100[0m ldr.w r3, [r6, r5, lsl #2]
|
|
|
|
|
|
[1;30m0x00000398[0m [1;30mmain+104[0m blx r3
|
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|
|
|
|
[1;32m0x0000039a[0m[1;32m [0m[1;32m[0m[1;32mmain+106[0m[1;32m adds r5, #1[0m
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|
|
|
|
[32m0x0000039c[0m[32m [0m[32m[0m[32mmain+108[0m[32m b.n 0x37c <main+76>[0m
|
|
|
|
|
|
[32m0x0000039e[0m[32m [0m[32m[0m[32mmain+110[0m[32m ldr.w r3, [r6, r5, lsl #2][0m
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|
|
|
|
|
[32m0x000003a2[0m[32m [0m[32m[0m[32mmain+114[0m[32m blx r3[0m
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|
|
|
|
[1;30m0x000003a4[0m [1;30mmain+116[0m adds r5, #1
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000002[0m [1;30mr2[0m [1;32m0x00000000[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x0000039a[0m [1;30mxpsr[0m [m0x01000000[0m [1;30mfpscr[0m [m0x00000000[0m
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|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m55[0m
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[1;30m56[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
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[1;30m57[0m OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
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[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
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[1;30m59[0m // 0 - GCLK
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[1;30m60[0m // 1 - XOSC32
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[1;30m61[0m // 2 - XOSC0
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[1;30m62[0m // 3 - XOSC1
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[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
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[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
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[1;32m65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;[0m
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[1;30m66[0m
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[1;30m67[0m // wait for pll to be locked and ready
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[1;30m68[0m while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
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[1;30m69[0m || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
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[1;30m70[0m
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[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
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[1;30m72[0m GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
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[1;30m73[0m while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
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[1;30m74[0m
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m0[0m] from [1;32m0x0000039a[0m in [1;32mmain[0m+[1;32m106[0m at [1;32m../../../src/main.c[0m:[1;32m65[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x0000039a[0m in [1;32mmain[0m+[1;32m106[0m at [1;32m../../../src/main.c[0m:[1;32m65[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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[1;30m0x00000398[0m [1;30mmain+104[0m blx r3
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[1;30m0x0000039a[0m [1;30mmain+106[0m adds r5, #1
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[1;30m0x0000039c[0m [1;30mmain+108[0m b.n 0x37c <main+76>
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[1;30m0x0000039e[0m [1;30mmain+110[0m ldr.w r3, [r6, r5, lsl #2]
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[1;30m0x000003a2[0m [1;30mmain+114[0m blx r3
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[1;32m0x000003a4[0m[1;32m [0m[1;32m[0m[1;32mmain+116[0m[1;32m adds r5, #1[0m
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[32m0x000003a6[0m[32m [0m[32m[0m[32mmain+118[0m[32m b.n 0x38e <main+94>[0m
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[32m0x000003a8[0m[32m [0m[32m[0m[32mmain+120[0m[32m lsls r4, r0, #15[0m
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|
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[32m0x000003aa[0m[32m [0m[32m[0m[32mmain+122[0m[32m movs r0, r0[0m
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|
|
[1;30m0x000003ac[0m [1;30mmain+124[0m lsls r4, r0, #15
|
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|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
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|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x00000438[0m [1;30mr1[0m [m0x00000002[0m [1;30mr2[0m [1;32m0x00000002[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
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|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x000003a4[0m [1;30mxpsr[0m [m0x01000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
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|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m58[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
|
|
|
|
|
[1;30m62[0m // 3 - XOSC1
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m66[0m
|
|
|
|
|
|
[1;30m67[0m // wait for pll to be locked and ready
|
|
|
|
|
|
[1;32m68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK[0m
|
|
|
|
|
|
[1;30m69[0m || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
|
|
|
|
|
|
[1;30m70[0m
|
|
|
|
|
|
[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
|
|
|
|
|
|
[1;30m72[0m GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
|
|
|
|
|
|
[1;30m73[0m while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
|
|
|
|
|
|
[1;30m74[0m
|
|
|
|
|
|
[1;30m75[0m
|
|
|
|
|
|
[1;30m76[0m
|
|
|
|
|
|
[1;30m77[0m asm volatile("nop");
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x000003a4[0m in [1;32mmain[0m+[1;32m116[0m at [1;32m../../../src/main.c[0m:[1;32m68[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x000003a4[0m in [1;32mmain[0m+[1;32m116[0m at [1;32m../../../src/main.c[0m:[1;32m68[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x000003a2[0m [1;30mmain+114[0m blx r3
|
|
|
|
|
|
[1;30m0x000003a4[0m [1;30mmain+116[0m adds r5, #1
|
|
|
|
|
|
[1;30m0x000003a6[0m [1;30mmain+118[0m b.n 0x38e <main+94>
|
|
|
|
|
|
[1;30m0x000003a8[0m [1;30mmain+120[0m lsls r4, r0, #15
|
|
|
|
|
|
[1;30m0x000003aa[0m [1;30mmain+122[0m movs r0, r0
|
|
|
|
|
|
[1;32m0x000003ac[0m[1;32m [0m[1;32m[0m[1;32mmain+124[0m[1;32m lsls r4, r0, #15[0m
|
|
|
|
|
|
[32m0x000003ae[0m[32m [0m[32m[0m[32mmain+126[0m[32m movs r0, r0[0m
|
|
|
|
|
|
[32m0x000003b0[0m[32m [0m[32m[0m[32mmain+128[0m[32m lsls r4, r0, #15[0m
|
|
|
|
|
|
[1;30m0x000003b2[0m [1;30mmain+130[0m movs r0, r0
|
|
|
|
|
|
[1;30m0x000003b4[0m [1;30mmain+132[0m lsls r0, r1, #15
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [1;32m0x80000000[0m [1;30mr1[0m [m0x00000002[0m [1;30mr2[0m [1;32m0x00000003[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x000003ac[0m [1;30mxpsr[0m [1;32m0xa1000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m59[0m // 0 - GCLK
|
|
|
|
|
|
[1;30m60[0m // 1 - XOSC32
|
|
|
|
|
|
[1;30m61[0m // 2 - XOSC0
|
|
|
|
|
|
[1;30m62[0m // 3 - XOSC1
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m66[0m
|
|
|
|
|
|
[1;30m67[0m // wait for pll to be locked and ready
|
|
|
|
|
|
[1;30m68[0m while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
|
|
|
|
|
|
[1;32m69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);[0m
|
|
|
|
|
|
[1;30m70[0m
|
|
|
|
|
|
[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
|
|
|
|
|
|
[1;30m72[0m GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
|
|
|
|
|
|
[1;30m73[0m while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
|
|
|
|
|
|
[1;30m74[0m
|
|
|
|
|
|
[1;30m75[0m
|
|
|
|
|
|
[1;30m76[0m
|
|
|
|
|
|
[1;30m77[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m78[0m for(;;)
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x000003ac[0m in [1;32mmain[0m+[1;32m124[0m at [1;32m../../../src/main.c[0m:[1;32m69[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x000003ac[0m in [1;32mmain[0m+[1;32m124[0m at [1;32m../../../src/main.c[0m:[1;32m69[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x000003a8[0m [1;30mmain+120[0m lsls r4, r0, #15
|
|
|
|
|
|
[1;30m0x000003aa[0m [1;30mmain+122[0m movs r0, r0
|
|
|
|
|
|
[1;30m0x000003ac[0m [1;30mmain+124[0m lsls r4, r0, #15
|
|
|
|
|
|
[1;30m0x000003ae[0m [1;30mmain+126[0m movs r0, r0
|
|
|
|
|
|
[1;30m0x000003b0[0m [1;30mmain+128[0m lsls r4, r0, #15
|
|
|
|
|
|
[1;32m0x000003b2[0m[1;32m [0m[1;32m[0m[1;32mmain+130[0m[1;32m movs r0, r0[0m
|
|
|
|
|
|
[32m0x000003b4[0m[32m [0m[32m[0m[32mmain+132[0m[32m lsls r0, r1, #15[0m
|
|
|
|
|
|
[32m0x000003b6[0m[32m [0m[32m[0m[32mmain+134[0m[32m movs r0, r0[0m
|
|
|
|
|
|
[1;30m0x000003b8[0m [1;30mmain+136[0m push {r3, r4, r5, r6, r7, lr}
|
|
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|
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[1;30m0x000003ba[0m [1;30mmain+138[0m nop
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30mr0[0m [m0x80000000[0m [1;30mr1[0m [1;32m0xc0000000[0m [1;30mr2[0m [m0x00000003[0m [1;30mr3[0m [m0x40001000[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
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[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
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[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x000003b2[0m [1;30mxpsr[0m [1;32m0x81000000[0m [1;30mfpscr[0m [m0x00000000[0m
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[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
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[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m62[0m // 3 - XOSC1
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[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
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[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
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[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
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[1;30m66[0m
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[1;30m67[0m // wait for pll to be locked and ready
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[1;30m68[0m while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
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[1;30m69[0m || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
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[1;30m70[0m
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[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
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[1;32m72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;[0m
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[1;30m73[0m while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
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[1;30m74[0m
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[1;30m75[0m
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[1;30m76[0m
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[1;30m77[0m asm volatile("nop");
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[1;30m78[0m for(;;)
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[1;30m79[0m {
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[1;30m80[0m
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[1;30m81[0m }
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[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m0[0m] from [1;32m0x000003b2[0m in [1;32mmain[0m+[1;32m130[0m at [1;32m../../../src/main.c[0m:[1;32m72[0m
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[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x000003b2[0m in [1;32mmain[0m+[1;32m130[0m at [1;32m../../../src/main.c[0m:[1;32m72[0m
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[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
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[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[1;30m0x000003ae[0m [1;30mmain+126[0m movs r0, r0
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[1;30m0x000003b0[0m [1;30mmain+128[0m lsls r4, r0, #15
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[1;30m0x000003b2[0m [1;30mmain+130[0m movs r0, r0
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[1;30m0x000003b4[0m [1;30mmain+132[0m lsls r0, r1, #15
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[1;30m0x000003b6[0m [1;30mmain+134[0m movs r0, r0
|
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[1;32m0x000003b8[0m[1;32m [0m[1;32m[0m[1;32mmain+136[0m[1;32m push {r3, r4, r5, r6, r7, lr}[0m
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[32m0x000003ba[0m[32m [0m[32m[0m[32mmain+138[0m[32m nop[0m
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[32m0x000003bc[0m[32m [0m[32m[0m[32mmain+140[0m[32m pop {r3, r4, r5, r6, r7}[0m
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[1;30m0x000003be[0m [1;30mmain+142[0m pop {r3}
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[1;30m0x000003c0[0m [1;30mmain+144[0m mov lr, r3
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[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
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[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
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[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
[1;30mr0[0m [m0x80000000[0m [1;30mr1[0m [m0xc0000000[0m [1;30mr2[0m [1;32m0x00010107[0m [1;30mr3[0m [1;32m0x40001c00[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
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|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
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|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x000003b8[0m [1;30mxpsr[0m [m0x81000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
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|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
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|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m63[0m OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
|
|
|
|
|
|
[1;30m64[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
|
|
|
|
|
|
[1;30m65[0m OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
|
|
|
|
|
|
[1;30m66[0m
|
|
|
|
|
|
[1;30m67[0m // wait for pll to be locked and ready
|
|
|
|
|
|
[1;30m68[0m while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
|
|
|
|
|
|
[1;30m69[0m || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
|
|
|
|
|
|
[1;30m70[0m
|
|
|
|
|
|
[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
|
|
|
|
|
|
[1;30m72[0m GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
|
|
|
|
|
|
[1;32m73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);[0m
|
|
|
|
|
|
[1;30m74[0m
|
|
|
|
|
|
[1;30m75[0m
|
|
|
|
|
|
[1;30m76[0m
|
|
|
|
|
|
[1;30m77[0m asm volatile("nop");
|
|
|
|
|
|
[1;30m78[0m for(;;)
|
|
|
|
|
|
[1;30m79[0m {
|
|
|
|
|
|
[1;30m80[0m
|
|
|
|
|
|
[1;30m81[0m }
|
|
|
|
|
|
[1;30m82[0m return 0;
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x000003b8[0m in [1;32mmain[0m+[1;32m136[0m at [1;32m../../../src/main.c[0m:[1;32m73[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x000003b8[0m in [1;32mmain[0m+[1;32m136[0m at [1;32m../../../src/main.c[0m:[1;32m73[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
|
|
|
|
|
|
[H[J[3J[36m───[0m [1;33mOutput/messages[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mAssembly[0m [36m────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m0x000003b4[0m [1;30mmain+132[0m lsls r0, r1, #15
|
|
|
|
|
|
[1;30m0x000003b6[0m [1;30mmain+134[0m movs r0, r0
|
|
|
|
|
|
[1;30m0x000003b8[0m [1;30mmain+136[0m push {r3, r4, r5, r6, r7, lr}
|
|
|
|
|
|
[1;30m0x000003ba[0m [1;30mmain+138[0m nop
|
|
|
|
|
|
[1;30m0x000003bc[0m [1;30mmain+140[0m pop {r3, r4, r5, r6, r7}
|
|
|
|
|
|
[1;32m0x000003be[0m[1;32m [0m[1;32m[0m[1;32mmain+142[0m[1;32m pop {r3}[0m
|
|
|
|
|
|
[32m0x000003c0[0m[32m [0m[32m[0m[32mmain+144[0m[32m mov lr, r3[0m
|
|
|
|
|
|
[32m0x000003c2[0m[32m [0m[32m[0m[32mmain+146[0m[32m bx lr[0m
|
|
|
|
|
|
[32m0x000003c4[0m[32m [0m[32m[0m[32mmain+148[0m[32m lsls r1, r1, #10[0m
|
|
|
|
|
|
[32m0x000003c6[0m[32m [0m[32m[0m[32mmain+150[0m[32m movs r0, r0[0m
|
|
|
|
|
|
[36m───[0m [1;33mBreakpoints[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] [1;32mbreak[0m at [1;32m0x00000330[0m in [1;32m../../../src/main.c[0m:[1;32m38[0m for [1;32mmain[0m hit [1;32m1[0m time
|
|
|
|
|
|
[36m───[0m [33mExpressions[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mHistory[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [33mMemory[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m───[0m [1;33mRegisters[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30mr0[0m [m0x80000000[0m [1;30mr1[0m [m0xc0000000[0m [1;30mr2[0m [1;32m0x00000000[0m [1;30mr3[0m [m0x40001c00[0m [1;30mr4[0m [m0x000119d5[0m [1;30mr5[0m [m0x20008abc[0m
|
|
|
|
|
|
[1;30mr6[0m [m0x200059d8[0m [1;30mr7[0m [m0x000125c1[0m [1;30mr8[0m [m0x000125b5[0m [1;30mr9[0m [m0x200059d8[0m [1;30mr10[0m [m0x20005a48[0m [1;30mr11[0m [m0x2000db94[0m
|
|
|
|
|
|
[1;30mr12[0m [m0x00000000[0m [1;30msp[0m [m0x20010018[0m [1;30mlr[0m [m0x000002f9[0m [1;30mpc[0m [1;32m0x000003be[0m [1;30mxpsr[0m [1;32m0x41000000[0m [1;30mfpscr[0m [m0x00000000[0m
|
|
|
|
|
|
[1;30mmsp[0m [m0x20010018[0m [1;30mpsp[0m [m0xfdff277c[0m [1;30mprimask[0m [m0x00[0m [1;30mbasepri[0m [m0x00[0m [1;30mfaultmask[0m [m0x00[0m [1;30mcontrol[0m [m0x00[0m
|
|
|
|
|
|
[36m───[0m [1;33mSource[0m [36m──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[1;30m67[0m // wait for pll to be locked and ready
|
|
|
|
|
|
[1;30m68[0m while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
|
|
|
|
|
|
[1;30m69[0m || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
|
|
|
|
|
|
[1;30m70[0m
|
|
|
|
|
|
[1;30m71[0m // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
|
|
|
|
|
|
[1;30m72[0m GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
|
|
|
|
|
|
[1;30m73[0m while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
|
|
|
|
|
|
[1;30m74[0m
|
|
|
|
|
|
[1;30m75[0m
|
|
|
|
|
|
[1;30m76[0m
|
|
|
|
|
|
[1;32m77 asm volatile("nop");[0m
|
|
|
|
|
|
[1;30m78[0m for(;;)
|
|
|
|
|
|
[1;30m79[0m {
|
|
|
|
|
|
[1;30m80[0m
|
|
|
|
|
|
[1;30m81[0m }
|
|
|
|
|
|
[1;30m82[0m return 0;
|
|
|
|
|
|
[1;30m83[0m }
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[1;30m~[0m
|
|
|
|
|
|
[36m───[0m [1;33mStack[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m0[0m] from [1;32m0x000003be[0m in [1;32mmain[0m+[1;32m142[0m at [1;32m../../../src/main.c[0m:[1;32m77[0m
|
|
|
|
|
|
[36m───[0m [1;33mThreads[0m [36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[[1;32m1[0m] id [1;32m-1[0m from [1;32m0x000003be[0m in [1;32mmain[0m+[1;32m142[0m at [1;32m../../../src/main.c[0m:[1;32m77[0m
|
|
|
|
|
|
[36m───[0m [33mVariables[0m [36m───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
|
|
|
|
|
[36m─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────[0m
|
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|
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77 asm volatile("nop");
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$1 = {
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bit = {
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SWRST = 0,
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GENCTRL0 = 0,
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GENCTRL1 = 0,
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GENCTRL2 = 0,
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GENCTRL3 = 0,
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GENCTRL4 = 0,
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GENCTRL5 = 0,
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GENCTRL6 = 0,
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GENCTRL7 = 0,
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GENCTRL8 = 0,
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GENCTRL9 = 0,
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GENCTRL10 = 0,
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GENCTRL11 = 0
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},
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vec = {
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GENCTRL = 0
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},
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reg = 0
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}
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