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82 lines
3.4 KiB
HTML
82 lines
3.4 KiB
HTML
4 years ago
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<title>MIPS Coprocessors - GNU Compiler Collection (GCC) Internals</title>
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Target-Macros.html#Target-Macros" title="Target Macros">
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<link rel="prev" href="Emulated-TLS.html#Emulated-TLS" title="Emulated TLS">
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<link rel="next" href="PCH-Target.html#PCH-Target" title="PCH Target">
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Copyright (C) 1988-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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<body>
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<div class="node">
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<a name="MIPS-Coprocessors"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="PCH-Target.html#PCH-Target">PCH Target</a>,
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Previous: <a rel="previous" accesskey="p" href="Emulated-TLS.html#Emulated-TLS">Emulated TLS</a>,
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Up: <a rel="up" accesskey="u" href="Target-Macros.html#Target-Macros">Target Macros</a>
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<hr>
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</div>
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<h3 class="section">17.26 Defining coprocessor specifics for MIPS targets.</h3>
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<p><a name="index-MIPS-coprocessor_002ddefinition-macros-4862"></a>
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The MIPS specification allows MIPS implementations to have as many as 4
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coprocessors, each with as many as 32 private registers. GCC supports
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accessing these registers and transferring values between the registers
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and memory using asm-ized variables. For example:
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<pre class="smallexample"> register unsigned int cp0count asm ("c0r1");
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unsigned int d;
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d = cp0count + 3;
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</pre>
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<p>(“c0r1” is the default name of register 1 in coprocessor 0; alternate
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names may be added as described below, or the default names may be
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overridden entirely in <code>SUBTARGET_CONDITIONAL_REGISTER_USAGE</code>.)
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<p>Coprocessor registers are assumed to be epilogue-used; sets to them will
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be preserved even if it does not appear that the register is used again
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later in the function.
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<p>Another note: according to the MIPS spec, coprocessor 1 (if present) is
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the FPU. One accesses COP1 registers through standard mips
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floating-point support; they are not included in this mechanism.
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