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78 lines
5.9 KiB
C
78 lines
5.9 KiB
C
4 years ago
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/**
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* \brief Component description for UTMI
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-04T11:03:42Z */
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#ifndef _SAME70_UTMI_COMPONENT_H_
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#define _SAME70_UTMI_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR UTMI */
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/* ************************************************************************** */
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/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) (R/W 32) OHCI Interrupt Configuration Register -------- */
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#define UTMI_OHCIICR_RES0_Pos _U_(0) /**< (UTMI_OHCIICR) USB PORTx Reset Position */
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#define UTMI_OHCIICR_RES0_Msk (_U_(0x1) << UTMI_OHCIICR_RES0_Pos) /**< (UTMI_OHCIICR) USB PORTx Reset Mask */
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#define UTMI_OHCIICR_RES0(value) (UTMI_OHCIICR_RES0_Msk & ((value) << UTMI_OHCIICR_RES0_Pos))
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#define UTMI_OHCIICR_ARIE_Pos _U_(4) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Position */
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#define UTMI_OHCIICR_ARIE_Msk (_U_(0x1) << UTMI_OHCIICR_ARIE_Pos) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Mask */
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#define UTMI_OHCIICR_ARIE(value) (UTMI_OHCIICR_ARIE_Msk & ((value) << UTMI_OHCIICR_ARIE_Pos))
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#define UTMI_OHCIICR_APPSTART_Pos _U_(5) /**< (UTMI_OHCIICR) Reserved Position */
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#define UTMI_OHCIICR_APPSTART_Msk (_U_(0x1) << UTMI_OHCIICR_APPSTART_Pos) /**< (UTMI_OHCIICR) Reserved Mask */
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#define UTMI_OHCIICR_APPSTART(value) (UTMI_OHCIICR_APPSTART_Msk & ((value) << UTMI_OHCIICR_APPSTART_Pos))
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#define UTMI_OHCIICR_UDPPUDIS_Pos _U_(23) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Position */
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#define UTMI_OHCIICR_UDPPUDIS_Msk (_U_(0x1) << UTMI_OHCIICR_UDPPUDIS_Pos) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Mask */
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#define UTMI_OHCIICR_UDPPUDIS(value) (UTMI_OHCIICR_UDPPUDIS_Msk & ((value) << UTMI_OHCIICR_UDPPUDIS_Pos))
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#define UTMI_OHCIICR_Msk _U_(0x00800031) /**< (UTMI_OHCIICR) Register Mask */
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#define UTMI_OHCIICR_RES_Pos _U_(0) /**< (UTMI_OHCIICR Position) USB PORTx Reset */
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#define UTMI_OHCIICR_RES_Msk (_U_(0x1) << UTMI_OHCIICR_RES_Pos) /**< (UTMI_OHCIICR Mask) RES */
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#define UTMI_OHCIICR_RES(value) (UTMI_OHCIICR_RES_Msk & ((value) << UTMI_OHCIICR_RES_Pos))
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/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) (R/W 32) UTMI Clock Trimming Register -------- */
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#define UTMI_CKTRIM_FREQ_Pos _U_(0) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Position */
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#define UTMI_CKTRIM_FREQ_Msk (_U_(0x3) << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Mask */
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#define UTMI_CKTRIM_FREQ(value) (UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))
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#define UTMI_CKTRIM_FREQ_XTAL12_Val _U_(0x0) /**< (UTMI_CKTRIM) 12 MHz reference clock */
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#define UTMI_CKTRIM_FREQ_XTAL16_Val _U_(0x1) /**< (UTMI_CKTRIM) 16 MHz reference clock */
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#define UTMI_CKTRIM_FREQ_XTAL12 (UTMI_CKTRIM_FREQ_XTAL12_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 12 MHz reference clock Position */
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#define UTMI_CKTRIM_FREQ_XTAL16 (UTMI_CKTRIM_FREQ_XTAL16_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 16 MHz reference clock Position */
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#define UTMI_CKTRIM_Msk _U_(0x00000003) /**< (UTMI_CKTRIM) Register Mask */
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/** \brief UTMI register offsets definitions */
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#define UTMI_OHCIICR_REG_OFST (0x10) /**< (UTMI_OHCIICR) OHCI Interrupt Configuration Register Offset */
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#define UTMI_CKTRIM_REG_OFST (0x30) /**< (UTMI_CKTRIM) UTMI Clock Trimming Register Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief UTMI register API structure */
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typedef struct
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{
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__I uint8_t Reserved1[0x10];
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__IO uint32_t UTMI_OHCIICR; /**< Offset: 0x10 (R/W 32) OHCI Interrupt Configuration Register */
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__I uint8_t Reserved2[0x1C];
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__IO uint32_t UTMI_CKTRIM; /**< Offset: 0x30 (R/W 32) UTMI Clock Trimming Register */
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} utmi_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_UTMI_COMPONENT_H_ */
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