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/**
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* \file
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*
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* \brief Component description for PM
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAME54_PM_COMPONENT_
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#define _SAME54_PM_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR PM */
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/* ========================================================================== */
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/** \addtogroup SAME54_PM Power Manager */
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/*@{*/
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#define PM_U2406
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#define REV_PM 0x100
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/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t :2; /*!< bit: 0.. 1 Reserved */
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uint8_t IORET:1; /*!< bit: 2 I/O Retention */
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uint8_t :5; /*!< bit: 3.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_CTRLA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */
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#define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */
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#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */
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#define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
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#define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */
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/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
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uint8_t :5; /*!< bit: 3.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_SLEEPCFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
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#define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
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#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
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#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
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#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
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#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
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#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
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#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
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#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
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#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
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#define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
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#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
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/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_INTENCLR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
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#define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
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#define PM_INTENCLR_SLEEPRDY_Pos 0 /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
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#define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
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#define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */
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/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_INTENSET_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
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#define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
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#define PM_INTENSET_SLEEPRDY_Pos 0 /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
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#define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
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#define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */
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/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union { // __I to avoid read-modify-write on write-to-clear register
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struct {
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__I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */
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__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_INTFLAG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
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#define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
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#define PM_INTFLAG_SLEEPRDY_Pos 0 /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
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#define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
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#define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */
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/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
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uint8_t :2; /*!< bit: 2.. 3 Reserved */
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uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */
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uint8_t :2; /*!< bit: 6.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_STDBYCFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
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#define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
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#define PM_STDBYCFG_RAMCFG_Pos 0 /**< \brief (PM_STDBYCFG) Ram Configuration */
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#define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
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#define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
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#define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All the RAMs are retained */
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#define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
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#define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
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#define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
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#define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
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#define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
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#define PM_STDBYCFG_FASTWKUP_Pos 4 /**< \brief (PM_STDBYCFG) Fast Wakeup */
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#define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
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#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
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#define PM_STDBYCFG_MASK _U_(0x33) /**< \brief (PM_STDBYCFG) MASK Register */
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/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
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uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */
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uint8_t :4; /*!< bit: 4.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_HIBCFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_HIBCFG_OFFSET 0x09 /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
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#define PM_HIBCFG_RESETVALUE _U_(0x00) /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
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#define PM_HIBCFG_RAMCFG_Pos 0 /**< \brief (PM_HIBCFG) Ram Configuration */
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#define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
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#define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
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#define PM_HIBCFG_BRAMCFG_Pos 2 /**< \brief (PM_HIBCFG) Backup Ram Configuration */
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#define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
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#define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
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#define PM_HIBCFG_MASK _U_(0x0F) /**< \brief (PM_HIBCFG) MASK Register */
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/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
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uint8_t :6; /*!< bit: 2.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_BKUPCFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_BKUPCFG_OFFSET 0x0A /**< \brief (PM_BKUPCFG offset) Backup Configuration */
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#define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
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#define PM_BKUPCFG_BRAMCFG_Pos 0 /**< \brief (PM_BKUPCFG) Ram Configuration */
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#define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
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#define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
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#define PM_BKUPCFG_MASK _U_(0x03) /**< \brief (PM_BKUPCFG) MASK Register */
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/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */
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uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_PWSAKDLY_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_PWSAKDLY_OFFSET 0x12 /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
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#define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
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#define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */
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#define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
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#define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
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#define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
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#define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
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#define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */
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/** \brief PM hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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__IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
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RoReg8 Reserved1[0x2];
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__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
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__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
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__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
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RoReg8 Reserved2[0x1];
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__IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */
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__IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */
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__IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */
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RoReg8 Reserved3[0x7];
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__IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */
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} Pm;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAME54_PM_COMPONENT_ */
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