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438 lines
12 KiB
C
438 lines
12 KiB
C
/* Auto-generated config file hpl_sercom_config.h */
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#ifndef HPL_SERCOM_CONFIG_H
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#define HPL_SERCOM_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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#ifndef CONF_SERCOM_2_USART_ENABLE
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#define CONF_SERCOM_2_USART_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <q> Receive buffer enable
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// <i> Enable input buffer in SERCOM module
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// <id> usart_rx_enable
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#ifndef CONF_SERCOM_2_USART_RXEN
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#define CONF_SERCOM_2_USART_RXEN 1
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#endif
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// <q> Transmitt buffer enable
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// <i> Enable output buffer in SERCOM module
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// <id> usart_tx_enable
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#ifndef CONF_SERCOM_2_USART_TXEN
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#define CONF_SERCOM_2_USART_TXEN 1
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#endif
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// <o> Frame parity
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// <0x0=>No parity
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// <0x1=>Even parity
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// <0x2=>Odd parity
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// <i> Parity bit mode for USART frame
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// <id> usart_parity
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#ifndef CONF_SERCOM_2_USART_PARITY
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#define CONF_SERCOM_2_USART_PARITY 0x0
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#endif
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// <o> Character Size
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// <0x0=>8 bits
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// <0x1=>9 bits
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// <0x5=>5 bits
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// <0x6=>6 bits
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// <0x7=>7 bits
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// <i> Data character size in USART frame
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// <id> usart_character_size
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#ifndef CONF_SERCOM_2_USART_CHSIZE
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#define CONF_SERCOM_2_USART_CHSIZE 0x0
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#endif
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// <o> Stop Bit
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// <0=>One stop bit
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// <1=>Two stop bits
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// <i> Number of stop bits in USART frame
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// <id> usart_stop_bit
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#ifndef CONF_SERCOM_2_USART_SBMODE
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#define CONF_SERCOM_2_USART_SBMODE 0
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#endif
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// <o> Baud rate <1-6250000>
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// <i> USART baud rate setting
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// <id> usart_baud_rate
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#ifndef CONF_SERCOM_2_USART_BAUD
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#define CONF_SERCOM_2_USART_BAUD 115200
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#endif
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// </h>
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// <e> Advanced configuration
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// <id> usart_advanced
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#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
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#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
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#endif
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// <q> Run in stand-by
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// <i> Keep the module running in standby sleep mode
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// <id> usart_arch_runstdby
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#ifndef CONF_SERCOM_2_USART_RUNSTDBY
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#define CONF_SERCOM_2_USART_RUNSTDBY 0
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#endif
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// <q> Immediate Buffer Overflow Notification
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// <i> Controls when the BUFOVF status bit is asserted
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// <id> usart_arch_ibon
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#ifndef CONF_SERCOM_2_USART_IBON
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#define CONF_SERCOM_2_USART_IBON 0
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#endif
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// <q> Start of Frame Detection Enable
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// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
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// <id> usart_arch_sfde
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#ifndef CONF_SERCOM_2_USART_SFDE
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#define CONF_SERCOM_2_USART_SFDE 0
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#endif
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// <q> Collision Detection Enable
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// <i> Collision detection enable
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// <id> usart_arch_cloden
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#ifndef CONF_SERCOM_2_USART_CLODEN
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#define CONF_SERCOM_2_USART_CLODEN 0
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#endif
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// <o> Operating Mode
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// <0x0=>USART with external clock
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// <0x1=>USART with internal clock
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// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
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// <id> usart_arch_clock_mode
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#ifndef CONF_SERCOM_2_USART_MODE
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#define CONF_SERCOM_2_USART_MODE 0x1
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#endif
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// <o> Sample Rate
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// <0x0=>16x arithmetic
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// <0x1=>16x fractional
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// <0x2=>8x arithmetic
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// <0x3=>8x fractional
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// <0x4=>3x arithmetic
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// <i> How many over-sampling bits used when sampling data state
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// <id> usart_arch_sampr
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#ifndef CONF_SERCOM_2_USART_SAMPR
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#define CONF_SERCOM_2_USART_SAMPR 0x0
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#endif
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// <o> Sample Adjustment
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// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
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// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
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// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
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// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
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// <i> Adjust which samples to use for data sampling in asynchronous mode
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// <id> usart_arch_sampa
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#ifndef CONF_SERCOM_2_USART_SAMPA
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#define CONF_SERCOM_2_USART_SAMPA 0x0
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#endif
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// <o> Fractional Part <0-7>
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// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
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// <id> usart_arch_fractional
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#ifndef CONF_SERCOM_2_USART_FRACTIONAL
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#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
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#endif
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// <o> Data Order
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// <0=>MSB is transmitted first
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// <1=>LSB is transmitted first
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// <i> Data order of the data bits in the frame
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// <id> usart_arch_dord
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#ifndef CONF_SERCOM_2_USART_DORD
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#define CONF_SERCOM_2_USART_DORD 1
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#endif
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// Does not do anything in UART mode
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#define CONF_SERCOM_2_USART_CPOL 0
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// <o> Encoding Format
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// <0=>No encoding
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// <1=>IrDA encoded
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// <id> usart_arch_enc
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#ifndef CONF_SERCOM_2_USART_ENC
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#define CONF_SERCOM_2_USART_ENC 0
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#endif
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// <o> LIN Slave Enable
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// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
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// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
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// <0=>Disable
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// <1=>Enable
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// <id> usart_arch_lin_slave_enable
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#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
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#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
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#endif
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// <o> Debug Stop Mode
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// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
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// <0=>Keep running
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// <1=>Halt
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// <id> usart_arch_dbgstop
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#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
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#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
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#endif
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// </e>
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#ifndef CONF_SERCOM_2_USART_INACK
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#define CONF_SERCOM_2_USART_INACK 0x0
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#endif
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#ifndef CONF_SERCOM_2_USART_DSNACK
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#define CONF_SERCOM_2_USART_DSNACK 0x0
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#endif
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#ifndef CONF_SERCOM_2_USART_MAXITER
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#define CONF_SERCOM_2_USART_MAXITER 0x7
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#endif
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#ifndef CONF_SERCOM_2_USART_GTIME
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#define CONF_SERCOM_2_USART_GTIME 0x2
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#endif
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#define CONF_SERCOM_2_USART_RXINV 0x0
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#define CONF_SERCOM_2_USART_TXINV 0x0
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#ifndef CONF_SERCOM_2_USART_CMODE
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#define CONF_SERCOM_2_USART_CMODE 0
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#endif
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#ifndef CONF_SERCOM_2_USART_RXPO
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#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
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#endif
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#ifndef CONF_SERCOM_2_USART_TXPO
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#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
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#endif
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/* Set correct parity settings in register interface based on PARITY setting */
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#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
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#if CONF_SERCOM_2_USART_PARITY == 0
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#define CONF_SERCOM_2_USART_PMODE 0
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#define CONF_SERCOM_2_USART_FORM 4
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#else
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#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
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#define CONF_SERCOM_2_USART_FORM 5
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#endif
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#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
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#if CONF_SERCOM_2_USART_PARITY == 0
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#define CONF_SERCOM_2_USART_PMODE 0
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#define CONF_SERCOM_2_USART_FORM 0
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#else
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#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
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#define CONF_SERCOM_2_USART_FORM 1
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#endif
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#endif
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// Calculate BAUD register value in UART mode
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#if CONF_SERCOM_2_USART_SAMPR == 0
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#ifndef CONF_SERCOM_2_USART_BAUD_RATE
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#define CONF_SERCOM_2_USART_BAUD_RATE \
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65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
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#endif
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#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_2_USART_SAMPR == 1
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#ifndef CONF_SERCOM_2_USART_BAUD_RATE
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#define CONF_SERCOM_2_USART_BAUD_RATE \
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((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
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#endif
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#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_2_USART_SAMPR == 2
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#ifndef CONF_SERCOM_2_USART_BAUD_RATE
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#define CONF_SERCOM_2_USART_BAUD_RATE \
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65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
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#endif
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#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_2_USART_SAMPR == 3
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#ifndef CONF_SERCOM_2_USART_BAUD_RATE
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#define CONF_SERCOM_2_USART_BAUD_RATE \
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((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
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#endif
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#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_2_USART_SAMPR == 4
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#ifndef CONF_SERCOM_2_USART_BAUD_RATE
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#define CONF_SERCOM_2_USART_BAUD_RATE \
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65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
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#endif
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#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#endif
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#include <peripheral_clk_config.h>
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// Enable configuration of module
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#ifndef CONF_SERCOM_4_SPI_ENABLE
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#define CONF_SERCOM_4_SPI_ENABLE 1
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#endif
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// Set module in SPI Master mode
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#ifndef CONF_SERCOM_4_SPI_MODE
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#define CONF_SERCOM_4_SPI_MODE 0x03
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#endif
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// <h> Basic Configuration
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// <q> Receive buffer enable
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// <i> Enable receive buffer to receive data from slave (RXEN)
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// <id> spi_master_rx_enable
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#ifndef CONF_SERCOM_4_SPI_RXEN
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#define CONF_SERCOM_4_SPI_RXEN 0x1
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#endif
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// <o> Character Size
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// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
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// <0x0=>8 bits
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// <0x1=>9 bits
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// <id> spi_master_character_size
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#ifndef CONF_SERCOM_4_SPI_CHSIZE
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#define CONF_SERCOM_4_SPI_CHSIZE 0x0
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#endif
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// <o> Baud rate <1-18000000>
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// <i> The SPI data transfer rate
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// <id> spi_master_baud_rate
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#ifndef CONF_SERCOM_4_SPI_BAUD
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#define CONF_SERCOM_4_SPI_BAUD 50000
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#endif
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// </h>
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// <e> Advanced Configuration
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// <id> spi_master_advanced
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#ifndef CONF_SERCOM_4_SPI_ADVANCED
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#define CONF_SERCOM_4_SPI_ADVANCED 0
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#endif
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// <o> Dummy byte <0x00-0x1ff>
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// <id> spi_master_dummybyte
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// <i> Dummy byte used when reading data from the slave without sending any data
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#ifndef CONF_SERCOM_4_SPI_DUMMYBYTE
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#define CONF_SERCOM_4_SPI_DUMMYBYTE 0x1ff
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#endif
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// <o> Data Order
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// <0=>MSB first
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// <1=>LSB first
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// <i> I least significant or most significant bit is shifted out first (DORD)
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// <id> spi_master_arch_dord
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#ifndef CONF_SERCOM_4_SPI_DORD
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#define CONF_SERCOM_4_SPI_DORD 0x0
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#endif
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// <o> Clock Polarity
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// <0=>SCK is low when idle
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// <1=>SCK is high when idle
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// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
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// <id> spi_master_arch_cpol
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#ifndef CONF_SERCOM_4_SPI_CPOL
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#define CONF_SERCOM_4_SPI_CPOL 0x0
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#endif
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// <o> Clock Phase
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// <0x0=>Sample input on leading edge
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// <0x1=>Sample input on trailing edge
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// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
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// <id> spi_master_arch_cpha
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#ifndef CONF_SERCOM_4_SPI_CPHA
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#define CONF_SERCOM_4_SPI_CPHA 0x0
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#endif
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// <o> Immediate Buffer Overflow Notification
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// <i> Controls when OVF is asserted (IBON)
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// <0x0=>In data stream
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// <0x1=>On buffer overflow
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// <id> spi_master_arch_ibon
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#ifndef CONF_SERCOM_4_SPI_IBON
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#define CONF_SERCOM_4_SPI_IBON 0x0
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#endif
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// <q> Run in stand-by
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// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
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// <id> spi_master_arch_runstdby
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#ifndef CONF_SERCOM_4_SPI_RUNSTDBY
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#define CONF_SERCOM_4_SPI_RUNSTDBY 0x0
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#endif
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// <o> Debug Stop Mode
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// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
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// <0=>Keep running
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// <1=>Halt
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// <id> spi_master_arch_dbgstop
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#ifndef CONF_SERCOM_4_SPI_DBGSTOP
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#define CONF_SERCOM_4_SPI_DBGSTOP 0
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#endif
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// </e>
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// Address mode disabled in master mode
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#ifndef CONF_SERCOM_4_SPI_AMODE_EN
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#define CONF_SERCOM_4_SPI_AMODE_EN 0
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#endif
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#ifndef CONF_SERCOM_4_SPI_AMODE
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#define CONF_SERCOM_4_SPI_AMODE 0
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#endif
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#ifndef CONF_SERCOM_4_SPI_ADDR
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#define CONF_SERCOM_4_SPI_ADDR 0
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#endif
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#ifndef CONF_SERCOM_4_SPI_ADDRMASK
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#define CONF_SERCOM_4_SPI_ADDRMASK 0
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#endif
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#ifndef CONF_SERCOM_4_SPI_SSDE
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#define CONF_SERCOM_4_SPI_SSDE 0
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#endif
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#ifndef CONF_SERCOM_4_SPI_MSSEN
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#define CONF_SERCOM_4_SPI_MSSEN 0x0
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#endif
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#ifndef CONF_SERCOM_4_SPI_PLOADEN
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#define CONF_SERCOM_4_SPI_PLOADEN 0
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#endif
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// <o> Receive Data Pinout
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// <0x0=>PAD[0]
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// <0x1=>PAD[1]
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// <0x2=>PAD[2]
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// <0x3=>PAD[3]
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// <id> spi_master_rxpo
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#ifndef CONF_SERCOM_4_SPI_RXPO
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#define CONF_SERCOM_4_SPI_RXPO 3
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#endif
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// <o> Transmit Data Pinout
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// <0x0=>PAD[0,1]_DO_SCK
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// <0x1=>PAD[2,3]_DO_SCK
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// <0x2=>PAD[3,1]_DO_SCK
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// <0x3=>PAD[0,3]_DO_SCK
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// <id> spi_master_txpo
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#ifndef CONF_SERCOM_4_SPI_TXPO
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#define CONF_SERCOM_4_SPI_TXPO 0
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#endif
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// Calculate baud register value from requested baudrate value
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#ifndef CONF_SERCOM_4_SPI_BAUD_RATE
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#define CONF_SERCOM_4_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM4_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_4_SPI_BAUD)) - 1
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_SERCOM_CONFIG_H
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