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244 lines
8.2 KiB
C
244 lines
8.2 KiB
C
/**
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* \file
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*
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* \brief SPI Slave Async related functionality declaration.
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
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#define _HPL_SPI_M_ASYNC_H_INCLUDED
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#include <hpl_spi.h>
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#include <hpl_spi_async.h>
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/**
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* \addtogroup hpl_spi HPL SPI
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*
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*
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*@{
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Uses common SPI async device driver. */
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#define _spi_m_async_dev _spi_async_dev
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#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
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/** Uses common SPI async device driver complete callback type. */
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#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
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/** Uses common SPI async device driver transfer callback type. */
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#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
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/**
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* \name HPL functions
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*/
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//@{
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/**
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* \brief Initialize SPI for access with interrupts
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* It will load default hardware configuration and software struct.
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* \param[in, out] dev Pointer to the SPI device instance.
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* \param[in] hw Pointer to the hardware base.
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* \retval ERR_INVALID_ARG Input parameter problem.
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* \retval ERR_BUSY SPI hardware not ready (resetting).
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* \retval ERR_DENIED SPI has been enabled.
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
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/**
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* \brief Initialize SPI for access with interrupts
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* Disable, reset the hardware and the software struct.
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* \param[in, out] dev Pointer to the SPI device instance.
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* \return Operation status.
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
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/**
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* \brief Enable SPI for access with interrupts
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* Enable the SPI and enable callback generation of receive and error
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* interrupts.
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* \param[in, out] dev Pointer to the SPI device instance.
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* \return Operation status.
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* \retval ERR_INVALID_ARG Input parameter problem.
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* \retval ERR_BUSY SPI hardware not ready (resetting).
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
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/**
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* \brief Disable SPI for access without interrupts
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* Disable SPI and interrupts. Deactivate all CS pins if works as master.
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* \param[in, out] dev Pointer to the SPI device instance.
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* \return Operation status.
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
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/**
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* \brief Set SPI transfer mode
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* Set SPI transfer mode (\ref spi_transfer_mode),
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* which controls clock polarity and clock phase.
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* Mode 0: leading edge is rising edge, data sample on leading edge.
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* Mode 1: leading edge is rising edge, data sample on trailing edge.
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* Mode 2: leading edge is falling edge, data sample on leading edge.
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* Mode 3: leading edge is falling edge, data sample on trailing edge.
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* \param[in, out] dev Pointer to the SPI device instance.
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* \param[in] mode The SPI transfer mode.
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* \return Operation status.
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* \retval ERR_BUSY SPI is not ready to accept new setting.
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
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/**
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* \brief Set SPI baudrate
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* \param[in, out] dev Pointer to the SPI device instance.
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* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
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* how it's generated.
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* \return Operation status.
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* \retval ERR_BUSY SPI is not ready to accept new setting.
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
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/**
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* \brief Set SPI baudrate
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* \param[in, out] dev Pointer to the SPI device instance.
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* \param[in] char_size The character size, see \ref spi_char_size.
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* \return Operation status.
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* \retval ERR_INVALID_ARG The character size is not supported.
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* \retval ERR_BUSY SPI is not ready to accept new setting.
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
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/**
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* \brief Set SPI data order
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* \param[in, out] dev Pointer to the SPI device instance.
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* \param[in] dord SPI data order (LSB/MSB first).
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* \return Operation status.
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* \retval ERR_INVALID_ARG The character size is not supported.
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* \retval ERR_BUSY SPI is not ready to accept new setting.
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* \retval 0 Operation done successfully.
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*/
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int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
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/**
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* \brief Enable interrupt on character output
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*
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* Enable interrupt when a new character can be written
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* to the SPI device.
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*
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* \param[in] dev Pointer to the SPI device instance
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* \param[in] state true = enable output interrupt
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* false = disable output interrupt
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*
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* \return Status code
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* \retval 0 Ok status
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*/
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int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
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/**
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* \brief Enable interrupt on character input
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*
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* Enable interrupt when a new character is ready to be
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* read from the SPI device.
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*
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* \param[in] dev Pointer to the SPI device instance
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* \param[in] state true = enable input interrupts
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* false = disable input interrupt
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*
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* \return Status code
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* \retvat 0 OK Status
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*/
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int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
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/**
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* \brief Enable interrupt on after data transmission complate
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*
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* \param[in] dev Pointer to the SPI device instance
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* \param[in] state true = enable input interrupts
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* false = disable input interrupt
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*
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* \return Status code
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* \retvat 0 OK Status
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*/
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int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
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/**
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* \brief Read one character to SPI device instance
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* \param[in, out] dev Pointer to the SPI device instance.
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*
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* \return Character read from SPI module
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*/
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uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
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/**
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* \brief Write one character to assigned buffer
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* \param[in, out] dev Pointer to the SPI device instance.
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* \param[in] data
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*
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* \return Status code of write operation
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* \retval 0 Write operation OK
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*/
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int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
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/**
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* \brief Register the SPI device callback
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* \param[in, out] dev Pointer to the SPI device instance.
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* \param[in] cb_type The callback type.
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* \param[in] func The callback function to register. NULL to disable callback.
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* \return Always 0.
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*/
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int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
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const FUNC_PTR func);
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/**
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* \brief Enable/disable SPI master interrupt
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*
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* param[in] device The pointer to SPI master device instance
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* param[in] type The type of interrupt to disable/enable if applicable
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* param[in] state Enable or disable
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*/
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void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
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const bool state);
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//@}
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#ifdef __cplusplus
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}
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#endif
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/**@}*/
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#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */
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