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278 lines
7.2 KiB
C
278 lines
7.2 KiB
C
/**
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* \file
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*
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* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
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*
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* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef HPL_CMCC_H_
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#define HPL_CMCC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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/**
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* \Cache driver MACROS
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*/
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#define CMCC_DISABLE 0U
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#define CMCC_ENABLE 1U
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#define IS_CMCC_DISABLED 0U
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#define IS_CMCC_ENABLED 1U
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#define CMCC_WAY_NOS 4U
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#define CMCC_LINE_NOS 64U
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#define CMCC_MONITOR_DISABLE 0U
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/**
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* \brief Cache size configurations
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*/
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enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
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/**
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* \brief Way Numbers
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*/
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enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
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/**
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* \brief Cache monitor configurations
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*/
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enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
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/**
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* \brief Cache configuration structure
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*/
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struct _cache_cfg {
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enum conf_cache_size cache_size;
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bool data_cache_disable;
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bool inst_cache_disable;
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bool gclk_gate_disable;
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};
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/**
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* \brief Cache enable status
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*/
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static inline bool _is_cache_enabled(const void *hw)
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{
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return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
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}
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/**
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* \brief Cache disable status
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*/
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static inline bool _is_cache_disabled(const void *hw)
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{
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return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
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}
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/**
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* \brief Cache enable
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*/
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static inline int32_t _cmcc_enable(const void *hw)
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{
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int32_t return_value;
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if (_is_cache_disabled(hw)) {
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hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
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return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
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} else {
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return_value = ERR_NO_CHANGE;
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}
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return return_value;
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}
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/**
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* \brief Cache disable
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*/
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static inline int32_t _cmcc_disable(const void *hw)
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{
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hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
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while (!(_is_cache_disabled(hw)))
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;
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return ERR_NONE;
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}
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/**
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* \brief Initialize Cache Module
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*
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* This function initialize low level cmcc module configuration.
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*
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* \return initialize status
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*/
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int32_t _cmcc_init(void);
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/**
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* \brief Configure CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] cache configuration structure pointer
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*
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* \return status of operation
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*/
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int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
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/**
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* \brief Enable data cache in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
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*
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* \return status of operation
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*/
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int32_t _cmcc_enable_data_cache(const void *hw, bool value);
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/**
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* \brief Enable instruction cache in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
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*
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* \return status of operation
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*/
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int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
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/**
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* \brief Enable clock gating in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
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*
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* \return status of operation
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*/
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int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
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/**
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* \brief Configure the cache size in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] element from cache size configuration enumerator
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* 0->1K, 1->2K, 2->4K(default)
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*
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* \return status of operation
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*/
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int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
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/**
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* \brief Lock the mentioned WAY in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] element from "way_num_index" enumerator
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*
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* \return status of operation
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*/
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int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
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/**
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* \brief Unlock the mentioned WAY in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] element from "way_num_index" enumerator
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*
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* \return status of operation
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*/
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int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
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/**
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* \brief Invalidate the mentioned cache line in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] element from "way_num" enumerator (valid arg is 0-3)
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* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
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*
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* \return status of operation
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*/
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int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
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/**
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* \brief Invalidate entire cache entries in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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*
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* \return status of operation
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*/
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int32_t _cmcc_invalidate_all(const void *hw);
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/**
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* \brief Configure cache monitor in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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* \param[in] element from cache monitor configurations enumerator
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*
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* \return status of operation
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*/
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int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
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/**
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* \brief Enable cache monitor in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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*
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* \return status of operation
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*/
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int32_t _cmcc_enable_monitor(const void *hw);
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/**
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* \brief Disable cache monitor in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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*
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* \return status of operation
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*/
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int32_t _cmcc_disable_monitor(const void *hw);
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/**
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* \brief Reset cache monitor in CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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*
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* \return status of operation
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*/
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int32_t _cmcc_reset_monitor(const void *hw);
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/**
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* \brief Get cache monitor event counter value from CMCC module
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*
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* \param[in] pointer pointing to the starting address of CMCC module
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*
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* \return event counter value
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*/
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uint32_t _cmcc_get_monitor_event_count(const void *hw);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HPL_CMCC_H_ */
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