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spi_sd_mmc_e54_lib
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spi_sd_mmc_e54_lib/build/spi_sd_mmc_lib.lss

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spi_sd_mmc_lib.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00001814 00000000 00000000 00010000 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 00000064 20000000 00001814 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .bkupram 00000000 47000000 47000000 00020064 2**0
CONTENTS
3 .qspi 00000000 04000000 04000000 00020064 2**0
CONTENTS
4 .bss 00000074 20000064 00001878 00020064 2**2
ALLOC
5 .stack 00010000 200000d8 000018ec 00020064 2**0
ALLOC
6 .ARM.attributes 0000002e 00000000 00000000 00020064 2**0
CONTENTS, READONLY
7 .comment 0000001e 00000000 00000000 00020092 2**0
CONTENTS, READONLY
8 .debug_info 00017882 00000000 00000000 000200b0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
9 .debug_abbrev 00002575 00000000 00000000 00037932 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
10 .debug_loc 00008376 00000000 00000000 00039ea7 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
11 .debug_aranges 00000950 00000000 00000000 0004221d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
12 .debug_ranges 00001408 00000000 00000000 00042b6d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_macro 00032644 00000000 00000000 00043f75 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_line 00011073 00000000 00000000 000765b9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_str 00118e12 00000000 00000000 0008762c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_frame 00001d94 00000000 00000000 001a0440 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
00000000 <exception_table>:
* \brief Delay loop to delay n number of cycles
*/
void _delay_cycles(void *const hw, uint32_t cycles)
{
(void)hw;
uint8_t n = cycles >> 24;
0: d8 00 01 20 75 06 00 00 71 06 00 00 71 06 00 00 ... u...q...q...
uint32_t buf = cycles;
while (n--) {
10: 71 06 00 00 71 06 00 00 71 06 00 00 00 00 00 00 q...q...q.......
...
SysTick->LOAD = 0xFFFFFF;
2c: 71 06 00 00 71 06 00 00 00 00 00 00 71 06 00 00 q...q.......q...
3c: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
4c: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
5c: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
6c: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
7c: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
8c: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
9c: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
ac: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
bc: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
cc: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
dc: 71 06 00 00 71 06 00 00 71 06 00 00 00 00 00 00 q...q...q.......
...
f4: 39 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 9...q...q...q...
104: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
114: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
124: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
134: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
144: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
154: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
164: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
174: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
184: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
194: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
1a4: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
1b4: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
1c4: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
1d4: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
1e4: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
1f4: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
204: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
214: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
224: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
234: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
244: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
254: 71 06 00 00 71 06 00 00 71 06 00 00 71 06 00 00 q...q...q...q...
00000264 <__do_global_dtors_aux>:
264: b510 push {r4, lr}
266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>)
268: 7823 ldrb r3, [r4, #0]
26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16>
26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>)
26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12>
270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>)
272: f3af 8000 nop.w
276: 2301 movs r3, #1
278: 7023 strb r3, [r4, #0]
27a: bd10 pop {r4, pc}
27c: 20000064 .word 0x20000064
280: 00000000 .word 0x00000000
284: 00001814 .word 0x00001814
00000288 <frame_dummy>:
288: b508 push {r3, lr}
28a: 4b03 ldr r3, [pc, #12] ; (298 <frame_dummy+0x10>)
28c: b11b cbz r3, 296 <frame_dummy+0xe>
28e: 4903 ldr r1, [pc, #12] ; (29c <frame_dummy+0x14>)
290: 4803 ldr r0, [pc, #12] ; (2a0 <frame_dummy+0x18>)
292: f3af 8000 nop.w
296: bd08 pop {r3, pc}
298: 00000000 .word 0x00000000
29c: 20000068 .word 0x20000068
2a0: 00001814 .word 0x00001814
000002a4 <io_write>:
/**
* \brief I/O write interface
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
2a4: b570 push {r4, r5, r6, lr}
2a6: 460d mov r5, r1
2a8: 4616 mov r6, r2
ASSERT(io_descr && buf);
2aa: 4604 mov r4, r0
2ac: b110 cbz r0, 2b4 <io_write+0x10>
2ae: 1e08 subs r0, r1, #0
2b0: bf18 it ne
2b2: 2001 movne r0, #1
2b4: 4905 ldr r1, [pc, #20] ; (2cc <io_write+0x28>)
2b6: 4b06 ldr r3, [pc, #24] ; (2d0 <io_write+0x2c>)
2b8: 2234 movs r2, #52 ; 0x34
2ba: 4798 blx r3
return io_descr->write(io_descr, buf, length);
2bc: 6823 ldr r3, [r4, #0]
2be: 4632 mov r2, r6
2c0: 4629 mov r1, r5
2c2: 4620 mov r0, r4
}
2c4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return io_descr->write(io_descr, buf, length);
2c8: 4718 bx r3
2ca: bf00 nop
2cc: 00001674 .word 0x00001674
2d0: 00000485 .word 0x00000485
000002d4 <_delay_init>:
2d4: f04f 23e0 mov.w r3, #3758153728 ; 0xe000e000
2d8: f06f 427f mvn.w r2, #4278190080 ; 0xff000000
2dc: 615a str r2, [r3, #20]
2de: 2205 movs r2, #5
2e0: 611a str r2, [r3, #16]
2e2: 4770 bx lr
000002e4 <_sbrk>:
extern caddr_t _sbrk(int incr)
{
static unsigned char *heap = NULL;
unsigned char * prev_heap;
if (heap == NULL) {
2e4: 4a04 ldr r2, [pc, #16] ; (2f8 <_sbrk+0x14>)
2e6: 6811 ldr r1, [r2, #0]
{
2e8: 4603 mov r3, r0
if (heap == NULL) {
2ea: b909 cbnz r1, 2f0 <_sbrk+0xc>
heap = (unsigned char *)&_end;
2ec: 4903 ldr r1, [pc, #12] ; (2fc <_sbrk+0x18>)
2ee: 6011 str r1, [r2, #0]
}
prev_heap = heap;
2f0: 6810 ldr r0, [r2, #0]
heap += incr;
2f2: 4403 add r3, r0
2f4: 6013 str r3, [r2, #0]
return (caddr_t)prev_heap;
}
2f6: 4770 bx lr
2f8: 20000080 .word 0x20000080
2fc: 200100d8 .word 0x200100d8
00000300 <spi_m_sync_init>:
ASSERT(spi);
spi->func = (struct _spi_m_sync_hpl_interface *)func;
}
int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw)
{
300: b538 push {r3, r4, r5, lr}
302: 460d mov r5, r1
int32_t rc = 0;
ASSERT(spi && hw);
304: 4604 mov r4, r0
306: b110 cbz r0, 30e <spi_m_sync_init+0xe>
308: 1e08 subs r0, r1, #0
30a: bf18 it ne
30c: 2001 movne r0, #1
30e: 490a ldr r1, [pc, #40] ; (338 <spi_m_sync_init+0x38>)
310: 4b0a ldr r3, [pc, #40] ; (33c <spi_m_sync_init+0x3c>)
312: 2240 movs r2, #64 ; 0x40
314: 4798 blx r3
spi->dev.prvt = (void *)hw;
316: 4620 mov r0, r4
rc = _spi_m_sync_init(&spi->dev, hw);
318: 4b09 ldr r3, [pc, #36] ; (340 <spi_m_sync_init+0x40>)
spi->dev.prvt = (void *)hw;
31a: f840 5f04 str.w r5, [r0, #4]!
rc = _spi_m_sync_init(&spi->dev, hw);
31e: 4629 mov r1, r5
320: 4798 blx r3
if (rc < 0) {
322: 2800 cmp r0, #0
324: db07 blt.n 336 <spi_m_sync_init+0x36>
return rc;
}
spi->flags = SPI_DEACTIVATE_NEXT;
326: f44f 4300 mov.w r3, #32768 ; 0x8000
32a: 82a3 strh r3, [r4, #20]
spi->io.read = _spi_m_sync_io_read;
32c: 4b05 ldr r3, [pc, #20] ; (344 <spi_m_sync_init+0x44>)
32e: 6123 str r3, [r4, #16]
spi->io.write = _spi_m_sync_io_write;
330: 4b05 ldr r3, [pc, #20] ; (348 <spi_m_sync_init+0x48>)
332: 60e3 str r3, [r4, #12]
return ERR_NONE;
334: 2000 movs r0, #0
}
336: bd38 pop {r3, r4, r5, pc}
338: 00001688 .word 0x00001688
33c: 00000485 .word 0x00000485
340: 00000a85 .word 0x00000a85
344: 000003c1 .word 0x000003c1
348: 00000389 .word 0x00000389
0000034c <spi_m_sync_transfer>:
return spi_m_sync_transfer(spi, &xfer);
}
int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer)
{
34c: b530 push {r4, r5, lr}
34e: 460c mov r4, r1
350: b085 sub sp, #20
struct spi_msg msg;
ASSERT(spi && p_xfer);
352: 4605 mov r5, r0
354: b110 cbz r0, 35c <spi_m_sync_transfer+0x10>
356: 1e08 subs r0, r1, #0
358: bf18 it ne
35a: 2001 movne r0, #1
35c: 22b3 movs r2, #179 ; 0xb3
35e: 4907 ldr r1, [pc, #28] ; (37c <spi_m_sync_transfer+0x30>)
360: 4b07 ldr r3, [pc, #28] ; (380 <spi_m_sync_transfer+0x34>)
362: 4798 blx r3
msg.txbuf = p_xfer->txbuf;
364: 6823 ldr r3, [r4, #0]
366: 9301 str r3, [sp, #4]
msg.rxbuf = p_xfer->rxbuf;
368: 6863 ldr r3, [r4, #4]
36a: 9302 str r3, [sp, #8]
msg.size = p_xfer->size;
36c: 68a3 ldr r3, [r4, #8]
36e: 9303 str r3, [sp, #12]
return _spi_m_sync_trans(&spi->dev, &msg);
370: a901 add r1, sp, #4
372: 4b04 ldr r3, [pc, #16] ; (384 <spi_m_sync_transfer+0x38>)
374: 1d28 adds r0, r5, #4
376: 4798 blx r3
}
378: b005 add sp, #20
37a: bd30 pop {r4, r5, pc}
37c: 00001688 .word 0x00001688
380: 00000485 .word 0x00000485
384: 00000bb9 .word 0x00000bb9
00000388 <_spi_m_sync_io_write>:
{
388: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
ASSERT(io);
38a: 4604 mov r4, r0
38c: 3800 subs r0, #0
38e: bf18 it ne
390: 2001 movne r0, #1
{
392: 460e mov r6, r1
394: 4615 mov r5, r2
ASSERT(io);
396: 4907 ldr r1, [pc, #28] ; (3b4 <_spi_m_sync_io_write+0x2c>)
398: 4b07 ldr r3, [pc, #28] ; (3b8 <_spi_m_sync_io_write+0x30>)
39a: 22a3 movs r2, #163 ; 0xa3
39c: 4798 blx r3
xfer.rxbuf = 0;
39e: 2300 movs r3, #0
xfer.txbuf = (uint8_t *)buf;
3a0: e9cd 6301 strd r6, r3, [sp, #4]
return spi_m_sync_transfer(spi, &xfer);
3a4: a901 add r1, sp, #4
3a6: 4b05 ldr r3, [pc, #20] ; (3bc <_spi_m_sync_io_write+0x34>)
xfer.size = length;
3a8: 9503 str r5, [sp, #12]
return spi_m_sync_transfer(spi, &xfer);
3aa: f1a4 000c sub.w r0, r4, #12
3ae: 4798 blx r3
}
3b0: b004 add sp, #16
3b2: bd70 pop {r4, r5, r6, pc}
3b4: 00001688 .word 0x00001688
3b8: 00000485 .word 0x00000485
3bc: 0000034d .word 0x0000034d
000003c0 <_spi_m_sync_io_read>:
{
3c0: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
ASSERT(io);
3c2: 4604 mov r4, r0
3c4: 3800 subs r0, #0
3c6: bf18 it ne
3c8: 2001 movne r0, #1
{
3ca: 460e mov r6, r1
3cc: 4615 mov r5, r2
ASSERT(io);
3ce: 4907 ldr r1, [pc, #28] ; (3ec <_spi_m_sync_io_read+0x2c>)
3d0: 4b07 ldr r3, [pc, #28] ; (3f0 <_spi_m_sync_io_read+0x30>)
3d2: 2287 movs r2, #135 ; 0x87
3d4: 4798 blx r3
xfer.txbuf = 0;
3d6: 2300 movs r3, #0
3d8: 9301 str r3, [sp, #4]
return spi_m_sync_transfer(spi, &xfer);
3da: a901 add r1, sp, #4
3dc: 4b05 ldr r3, [pc, #20] ; (3f4 <_spi_m_sync_io_read+0x34>)
xfer.rxbuf = buf;
3de: 9602 str r6, [sp, #8]
return spi_m_sync_transfer(spi, &xfer);
3e0: f1a4 000c sub.w r0, r4, #12
xfer.size = length;
3e4: 9503 str r5, [sp, #12]
return spi_m_sync_transfer(spi, &xfer);
3e6: 4798 blx r3
}
3e8: b004 add sp, #16
3ea: bd70 pop {r4, r5, r6, pc}
3ec: 00001688 .word 0x00001688
3f0: 00000485 .word 0x00000485
3f4: 0000034d .word 0x0000034d
000003f8 <delay_init>:
/**
* \brief Initialize Delay driver
*/
void delay_init(void *const hw)
{
_delay_init(hardware = hw);
3f8: 4b01 ldr r3, [pc, #4] ; (400 <delay_init+0x8>)
3fa: 6018 str r0, [r3, #0]
3fc: 4b01 ldr r3, [pc, #4] ; (404 <delay_init+0xc>)
3fe: 4718 bx r3
400: 20000084 .word 0x20000084
404: 000002d5 .word 0x000002d5
00000408 <_init_chip>:
}
static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
{
NVMCTRL_CRITICAL_SECTION_ENTER();
((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
408: 4a0a ldr r2, [pc, #40] ; (434 <_init_chip+0x2c>)
40a: 8813 ldrh r3, [r2, #0]
40c: b29b uxth r3, r3
/**
* \brief Initialize the hardware abstraction layer
*/
void _init_chip(void)
{
40e: b510 push {r4, lr}
410: f443 63a0 orr.w r3, r3, #1280 ; 0x500
414: 8013 strh r3, [r2, #0]
hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
_osc32kctrl_init_sources();
416: 4b08 ldr r3, [pc, #32] ; (438 <_init_chip+0x30>)
418: 4798 blx r3
_oscctrl_init_sources();
41a: 4b08 ldr r3, [pc, #32] ; (43c <_init_chip+0x34>)
41c: 4798 blx r3
_mclk_init();
41e: 4b08 ldr r3, [pc, #32] ; (440 <_init_chip+0x38>)
420: 4798 blx r3
#if _GCLK_INIT_1ST
_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
#endif
_oscctrl_init_referenced_generators();
422: 4b08 ldr r3, [pc, #32] ; (444 <_init_chip+0x3c>)
424: 4798 blx r3
#endif
#if CONF_CMCC_ENABLE
cache_init();
#endif
}
426: e8bd 4010 ldmia.w sp!, {r4, lr}
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
42a: 4b07 ldr r3, [pc, #28] ; (448 <_init_chip+0x40>)
42c: f640 70ff movw r0, #4095 ; 0xfff
430: 4718 bx r3
432: bf00 nop
434: 41004000 .word 0x41004000
438: 00000729 .word 0x00000729
43c: 0000048b .word 0x0000048b
440: 0000062d .word 0x0000062d
444: 0000048d .word 0x0000048d
448: 0000044d .word 0x0000044d
0000044c <_gclk_init_generators_by_fref>:
void _gclk_init_generators_by_fref(uint32_t bm)
{
#if CONF_GCLK_GENERATOR_0_CONFIG == 1
if (bm & (1ul << 0)) {
44c: 07c2 lsls r2, r0, #31
44e: d507 bpl.n 460 <_gclk_init_generators_by_fref+0x14>
}
static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg = data;
450: 4b09 ldr r3, [pc, #36] ; (478 <_gclk_init_generators_by_fref+0x2c>)
452: 4a0a ldr r2, [pc, #40] ; (47c <_gclk_init_generators_by_fref+0x30>)
454: 621a str r2, [r3, #32]
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
456: f643 72fd movw r2, #16381 ; 0x3ffd
45a: 6859 ldr r1, [r3, #4]
45c: 4211 tst r1, r2
45e: d1fc bne.n 45a <_gclk_init_generators_by_fref+0xe>
| (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_3_CONFIG == 1
if (bm & (1ul << 3)) {
460: 0703 lsls r3, r0, #28
462: d507 bpl.n 474 <_gclk_init_generators_by_fref+0x28>
((Gclk *)hw)->GENCTRL[index].reg = data;
464: 4b04 ldr r3, [pc, #16] ; (478 <_gclk_init_generators_by_fref+0x2c>)
466: 4a06 ldr r2, [pc, #24] ; (480 <_gclk_init_generators_by_fref+0x34>)
468: 62da str r2, [r3, #44] ; 0x2c
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
46a: f643 72fd movw r2, #16381 ; 0x3ffd
46e: 6859 ldr r1, [r3, #4]
470: 4211 tst r1, r2
472: d1fc bne.n 46e <_gclk_init_generators_by_fref+0x22>
| (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
}
#endif
}
474: 4770 bx lr
476: bf00 nop
478: 40001c00 .word 0x40001c00
47c: 00010107 .word 0x00010107
480: 00010105 .word 0x00010105
00000484 <assert>:
/**
* \brief Assert function
*/
void assert(const bool condition, const char *const file, const int line)
{
if (!(condition)) {
484: b900 cbnz r0, 488 <assert+0x4>
__asm("BKPT #0");
486: be00 bkpt 0x0000
}
(void)file;
(void)line;
}
488: 4770 bx lr
0000048a <_oscctrl_init_sources>:
hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1);
#endif
#endif
(void)hw;
}
48a: 4770 bx lr
0000048c <_oscctrl_init_referenced_generators>:
static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
hri_oscctrl_dpllratio_reg_t data)
{
OSCCTRL_CRITICAL_SECTION_ENTER();
((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data;
48c: 4b0c ldr r3, [pc, #48] ; (4c0 <_oscctrl_init_referenced_generators+0x34>)
48e: 4a0d ldr r2, [pc, #52] ; (4c4 <_oscctrl_init_referenced_generators+0x38>)
490: 635a str r2, [r3, #52] ; 0x34
while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
492: 6bda ldr r2, [r3, #60] ; 0x3c
494: f012 0f06 tst.w r2, #6
498: d1fb bne.n 492 <_oscctrl_init_referenced_generators+0x6>
static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
hri_oscctrl_dpllctrlb_reg_t data)
{
OSCCTRL_CRITICAL_SECTION_ENTER();
((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data;
49a: f44f 6202 mov.w r2, #2080 ; 0x820
49e: 639a str r2, [r3, #56] ; 0x38
((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data;
4a0: 2202 movs r2, #2
4a2: f883 2030 strb.w r2, [r3, #48] ; 0x30
while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
4a6: 4a06 ldr r2, [pc, #24] ; (4c0 <_oscctrl_init_referenced_generators+0x34>)
4a8: 6bd3 ldr r3, [r2, #60] ; 0x3c
4aa: 0798 lsls r0, r3, #30
4ac: d4fc bmi.n 4a8 <_oscctrl_init_referenced_generators+0x1c>
return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
4ae: 4b04 ldr r3, [pc, #16] ; (4c0 <_oscctrl_init_referenced_generators+0x34>)
4b0: 6c1a ldr r2, [r3, #64] ; 0x40
#endif
#endif
#if CONF_FDPLL0_CONFIG == 1
#if CONF_FDPLL0_ENABLE == 1
while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0)))
4b2: 07d1 lsls r1, r2, #31
4b4: d402 bmi.n 4bc <_oscctrl_init_referenced_generators+0x30>
return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
4b6: 6c1a ldr r2, [r3, #64] ; 0x40
4b8: 0792 lsls r2, r2, #30
4ba: d5f9 bpl.n 4b0 <_oscctrl_init_referenced_generators+0x24>
hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE);
while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
;
#endif
(void)hw;
}
4bc: 4770 bx lr
4be: bf00 nop
4c0: 40001000 .word 0x40001000
4c4: 00010e4d .word 0x00010e4d
000004c8 <usart_sync_write>:
* \param[in] length The number of bytes to write
*
* \return The number of bytes written.
*/
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
4c8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
4cc: 460e mov r6, r1
4ce: 4615 mov r5, r2
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
4d0: 4604 mov r4, r0
4d2: b118 cbz r0, 4dc <usart_sync_write+0x14>
4d4: b329 cbz r1, 522 <usart_sync_write+0x5a>
4d6: 1e10 subs r0, r2, #0
4d8: bf18 it ne
4da: 2001 movne r0, #1
4dc: 4912 ldr r1, [pc, #72] ; (528 <usart_sync_write+0x60>)
4de: 4b13 ldr r3, [pc, #76] ; (52c <usart_sync_write+0x64>)
while (!_usart_sync_is_ready_to_send(&descr->device))
4e0: 4f13 ldr r7, [pc, #76] ; (530 <usart_sync_write+0x68>)
ASSERT(io_descr && buf && length);
4e2: 22f1 movs r2, #241 ; 0xf1
4e4: 4798 blx r3
while (!_usart_sync_is_ready_to_send(&descr->device))
4e6: 3408 adds r4, #8
4e8: 46b9 mov r9, r7
4ea: 4620 mov r0, r4
4ec: 47b8 blx r7
4ee: 2800 cmp r0, #0
4f0: d0fb beq.n 4ea <usart_sync_write+0x22>
;
do {
_usart_sync_write_byte(&descr->device, buf[offset]);
4f2: f8df 8044 ldr.w r8, [pc, #68] ; 538 <usart_sync_write+0x70>
uint32_t offset = 0;
4f6: 2700 movs r7, #0
_usart_sync_write_byte(&descr->device, buf[offset]);
4f8: 5df1 ldrb r1, [r6, r7]
4fa: 4620 mov r0, r4
4fc: 47c0 blx r8
while (!_usart_sync_is_ready_to_send(&descr->device))
4fe: 4620 mov r0, r4
500: 47c8 blx r9
502: 2800 cmp r0, #0
504: d0fb beq.n 4fe <usart_sync_write+0x36>
;
} while (++offset < length);
506: 3701 adds r7, #1
508: 42bd cmp r5, r7
50a: d8f5 bhi.n 4f8 <usart_sync_write+0x30>
50c: 2d00 cmp r5, #0
while (!_usart_sync_is_transmit_done(&descr->device))
50e: 4e09 ldr r6, [pc, #36] ; (534 <usart_sync_write+0x6c>)
} while (++offset < length);
510: bf08 it eq
512: 2501 moveq r5, #1
while (!_usart_sync_is_transmit_done(&descr->device))
514: 4620 mov r0, r4
516: 47b0 blx r6
518: 2800 cmp r0, #0
51a: d0fb beq.n 514 <usart_sync_write+0x4c>
;
return (int32_t)offset;
}
51c: 4628 mov r0, r5
51e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(io_descr && buf && length);
522: 4608 mov r0, r1
524: e7da b.n 4dc <usart_sync_write+0x14>
526: bf00 nop
528: 000016a4 .word 0x000016a4
52c: 00000485 .word 0x00000485
530: 00000a67 .word 0x00000a67
534: 00000a71 .word 0x00000a71
538: 00000a59 .word 0x00000a59
0000053c <usart_sync_read>:
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
{
53c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
540: 460e mov r6, r1
542: 4615 mov r5, r2
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
544: 4604 mov r4, r0
546: b118 cbz r0, 550 <usart_sync_read+0x14>
548: b1e9 cbz r1, 586 <usart_sync_read+0x4a>
54a: 1e10 subs r0, r2, #0
54c: bf18 it ne
54e: 2001 movne r0, #1
550: 490e ldr r1, [pc, #56] ; (58c <usart_sync_read+0x50>)
552: 4b0f ldr r3, [pc, #60] ; (590 <usart_sync_read+0x54>)
do {
while (!_usart_sync_is_byte_received(&descr->device))
554: f8df 903c ldr.w r9, [pc, #60] ; 594 <usart_sync_read+0x58>
;
buf[offset] = _usart_sync_read_byte(&descr->device);
558: f8df 803c ldr.w r8, [pc, #60] ; 598 <usart_sync_read+0x5c>
ASSERT(io_descr && buf && length);
55c: f44f 7286 mov.w r2, #268 ; 0x10c
560: 4798 blx r3
uint32_t offset = 0;
562: 2700 movs r7, #0
while (!_usart_sync_is_byte_received(&descr->device))
564: 3408 adds r4, #8
566: 4620 mov r0, r4
568: 47c8 blx r9
56a: 2800 cmp r0, #0
56c: d0fb beq.n 566 <usart_sync_read+0x2a>
buf[offset] = _usart_sync_read_byte(&descr->device);
56e: 4620 mov r0, r4
570: 47c0 blx r8
572: 55f0 strb r0, [r6, r7]
} while (++offset < length);
574: 3701 adds r7, #1
576: 42bd cmp r5, r7
578: d8f5 bhi.n 566 <usart_sync_read+0x2a>
57a: 2d00 cmp r5, #0
return (int32_t)offset;
}
57c: bf14 ite ne
57e: 4628 movne r0, r5
580: 2001 moveq r0, #1
582: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(io_descr && buf && length);
586: 4608 mov r0, r1
588: e7e2 b.n 550 <usart_sync_read+0x14>
58a: bf00 nop
58c: 000016a4 .word 0x000016a4
590: 00000485 .word 0x00000485
594: 00000a7b .word 0x00000a7b
598: 00000a5f .word 0x00000a5f
0000059c <usart_sync_init>:
{
59c: b538 push {r3, r4, r5, lr}
59e: 460d mov r5, r1
ASSERT(descr && hw);
5a0: 4604 mov r4, r0
5a2: b110 cbz r0, 5aa <usart_sync_init+0xe>
5a4: 1e08 subs r0, r1, #0
5a6: bf18 it ne
5a8: 2001 movne r0, #1
5aa: 4907 ldr r1, [pc, #28] ; (5c8 <usart_sync_init+0x2c>)
5ac: 4b07 ldr r3, [pc, #28] ; (5cc <usart_sync_init+0x30>)
5ae: 2234 movs r2, #52 ; 0x34
5b0: 4798 blx r3
init_status = _usart_sync_init(&descr->device, hw);
5b2: 4b07 ldr r3, [pc, #28] ; (5d0 <usart_sync_init+0x34>)
5b4: 4629 mov r1, r5
5b6: f104 0008 add.w r0, r4, #8
5ba: 4798 blx r3
if (init_status) {
5bc: b918 cbnz r0, 5c6 <usart_sync_init+0x2a>
descr->io.read = usart_sync_read;
5be: 4b05 ldr r3, [pc, #20] ; (5d4 <usart_sync_init+0x38>)
5c0: 6063 str r3, [r4, #4]
descr->io.write = usart_sync_write;
5c2: 4b05 ldr r3, [pc, #20] ; (5d8 <usart_sync_init+0x3c>)
5c4: 6023 str r3, [r4, #0]
}
5c6: bd38 pop {r3, r4, r5, pc}
5c8: 000016a4 .word 0x000016a4
5cc: 00000485 .word 0x00000485
5d0: 00000a19 .word 0x00000a19
5d4: 0000053d .word 0x0000053d
5d8: 000004c9 .word 0x000004c9
000005dc <usart_sync_enable>:
{
5dc: b510 push {r4, lr}
ASSERT(descr);
5de: 4604 mov r4, r0
5e0: 3800 subs r0, #0
5e2: bf18 it ne
5e4: 2001 movne r0, #1
5e6: 4905 ldr r1, [pc, #20] ; (5fc <usart_sync_enable+0x20>)
5e8: 4b05 ldr r3, [pc, #20] ; (600 <usart_sync_enable+0x24>)
5ea: 2253 movs r2, #83 ; 0x53
5ec: 4798 blx r3
_usart_sync_enable(&descr->device);
5ee: f104 0008 add.w r0, r4, #8
5f2: 4b04 ldr r3, [pc, #16] ; (604 <usart_sync_enable+0x28>)
5f4: 4798 blx r3
}
5f6: 2000 movs r0, #0
5f8: bd10 pop {r4, pc}
5fa: bf00 nop
5fc: 000016a4 .word 0x000016a4
600: 00000485 .word 0x00000485
604: 00000a45 .word 0x00000a45
00000608 <usart_sync_get_io_descriptor>:
{
608: b538 push {r3, r4, r5, lr}
60a: 460d mov r5, r1
ASSERT(descr && io);
60c: 4604 mov r4, r0
60e: b110 cbz r0, 616 <usart_sync_get_io_descriptor+0xe>
610: 1e08 subs r0, r1, #0
612: bf18 it ne
614: 2001 movne r0, #1
616: 4903 ldr r1, [pc, #12] ; (624 <usart_sync_get_io_descriptor+0x1c>)
618: 4b03 ldr r3, [pc, #12] ; (628 <usart_sync_get_io_descriptor+0x20>)
61a: 2269 movs r2, #105 ; 0x69
61c: 4798 blx r3
*io = &descr->io;
61e: 602c str r4, [r5, #0]
}
620: 2000 movs r0, #0
622: bd38 pop {r3, r4, r5, pc}
624: 000016a4 .word 0x000016a4
628: 00000485 .word 0x00000485
0000062c <_mclk_init>:
}
static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->CPUDIV.reg = data;
62c: 4b01 ldr r3, [pc, #4] ; (634 <_mclk_init+0x8>)
62e: 2201 movs r2, #1
630: 715a strb r2, [r3, #5]
*/
void _mclk_init(void)
{
void *hw = (void *)MCLK;
hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV));
}
632: 4770 bx lr
634: 40000800 .word 0x40000800
00000638 <RAMECC_Handler>:
return tmp;
}
static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
{
return ((Ramecc *)hw)->INTFLAG.reg;
638: 4a0b ldr r2, [pc, #44] ; (668 <RAMECC_Handler+0x30>)
63a: 7893 ldrb r3, [r2, #2]
/**
* \internal RAMECC interrupt handler
*/
void RAMECC_Handler(void)
{
63c: b082 sub sp, #8
63e: b2db uxtb r3, r3
struct _ramecc_device *dev = (struct _ramecc_device *)&device;
volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
640: 9301 str r3, [sp, #4]
if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
642: 9b01 ldr r3, [sp, #4]
644: 0799 lsls r1, r3, #30
646: d505 bpl.n 654 <RAMECC_Handler+0x1c>
648: 4b08 ldr r3, [pc, #32] ; (66c <RAMECC_Handler+0x34>)
64a: 681b ldr r3, [r3, #0]
64c: b113 cbz r3, 654 <RAMECC_Handler+0x1c>
return tmp;
}
static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
{
return ((Ramecc *)hw)->ERRADDR.reg;
64e: 6850 ldr r0, [r2, #4]
} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
} else {
return;
}
}
650: b002 add sp, #8
dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
652: 4718 bx r3
} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
654: 9b01 ldr r3, [sp, #4]
656: 07db lsls r3, r3, #31
658: d504 bpl.n 664 <RAMECC_Handler+0x2c>
65a: 4b04 ldr r3, [pc, #16] ; (66c <RAMECC_Handler+0x34>)
65c: 685b ldr r3, [r3, #4]
65e: b10b cbz r3, 664 <RAMECC_Handler+0x2c>
660: 4a01 ldr r2, [pc, #4] ; (668 <RAMECC_Handler+0x30>)
662: e7f4 b.n 64e <RAMECC_Handler+0x16>
}
664: b002 add sp, #8
666: 4770 bx lr
668: 41020000 .word 0x41020000
66c: 20000088 .word 0x20000088
00000670 <Dummy_Handler>:
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
670: e7fe b.n 670 <Dummy_Handler>
...
00000674 <Reset_Handler>:
if (pSrc != pDest) {
674: 4918 ldr r1, [pc, #96] ; (6d8 <Reset_Handler+0x64>)
676: 4819 ldr r0, [pc, #100] ; (6dc <Reset_Handler+0x68>)
678: 4281 cmp r1, r0
{
67a: b510 push {r4, lr}
if (pSrc != pDest) {
67c: d00a beq.n 694 <Reset_Handler+0x20>
*pDest++ = *pSrc++;
67e: 4b18 ldr r3, [pc, #96] ; (6e0 <Reset_Handler+0x6c>)
680: 1cda adds r2, r3, #3
682: 1a12 subs r2, r2, r0
684: f022 0203 bic.w r2, r2, #3
688: 1ec4 subs r4, r0, #3
68a: 42a3 cmp r3, r4
68c: bf38 it cc
68e: 2200 movcc r2, #0
690: 4b14 ldr r3, [pc, #80] ; (6e4 <Reset_Handler+0x70>)
692: 4798 blx r3
*pDest++ = 0;
694: 4b14 ldr r3, [pc, #80] ; (6e8 <Reset_Handler+0x74>)
696: 4815 ldr r0, [pc, #84] ; (6ec <Reset_Handler+0x78>)
698: 1cda adds r2, r3, #3
69a: 1a12 subs r2, r2, r0
69c: 1ec1 subs r1, r0, #3
69e: f022 0203 bic.w r2, r2, #3
6a2: 4299 cmp r1, r3
6a4: bf88 it hi
6a6: 2200 movhi r2, #0
6a8: 4b11 ldr r3, [pc, #68] ; (6f0 <Reset_Handler+0x7c>)
6aa: 2100 movs r1, #0
6ac: 4798 blx r3
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
6ae: 4a11 ldr r2, [pc, #68] ; (6f4 <Reset_Handler+0x80>)
6b0: 4b11 ldr r3, [pc, #68] ; (6f8 <Reset_Handler+0x84>)
6b2: f022 027f bic.w r2, r2, #127 ; 0x7f
6b6: 609a str r2, [r3, #8]
SCB->CPACR |= (0xFu << 20);
6b8: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88
6bc: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000
6c0: f8c3 2088 str.w r2, [r3, #136] ; 0x88
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
6c4: f3bf 8f4f dsb sy
__ASM volatile ("isb 0xF":::"memory");
6c8: f3bf 8f6f isb sy
__libc_init_array();
6cc: 4b0b ldr r3, [pc, #44] ; (6fc <Reset_Handler+0x88>)
6ce: 4798 blx r3
main();
6d0: 4b0b ldr r3, [pc, #44] ; (700 <Reset_Handler+0x8c>)
6d2: 4798 blx r3
while (1)
6d4: e7fe b.n 6d4 <Reset_Handler+0x60>
6d6: bf00 nop
6d8: 00001814 .word 0x00001814
6dc: 20000000 .word 0x20000000
6e0: 20000064 .word 0x20000064
6e4: 00000d5d .word 0x00000d5d
6e8: 200000d8 .word 0x200000d8
6ec: 20000064 .word 0x20000064
6f0: 00000d79 .word 0x00000d79
6f4: 00000000 .word 0x00000000
6f8: e000ed00 .word 0xe000ed00
6fc: 00000d15 .word 0x00000d15
700: 00000705 .word 0x00000705
00000704 <main>:
#include <atmel_start.h>
#include "pdebug.h"
int main(void)
{
704: b508 push {r3, lr}
/* Initializes MCU, drivers and middleware */
atmel_start_init();
706: 4b04 ldr r3, [pc, #16] ; (718 <main+0x14>)
708: 4798 blx r3
pdebug_init();
70a: 4b04 ldr r3, [pc, #16] ; (71c <main+0x18>)
70c: 4798 blx r3
printf("Hi\n");
70e: 4804 ldr r0, [pc, #16] ; (720 <main+0x1c>)
710: 4b04 ldr r3, [pc, #16] ; (724 <main+0x20>)
712: 4798 blx r3
/* Replace with your application code */
while (1) {
714: e7fe b.n 714 <main+0x10>
716: bf00 nop
718: 00000c79 .word 0x00000c79
71c: 00000ce1 .word 0x00000ce1
720: 000016c0 .word 0x000016c0
724: 00000c81 .word 0x00000c81
00000728 <_osc32kctrl_init_sources>:
}
static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->XOSC32K.reg = data;
728: 4b06 ldr r3, [pc, #24] ; (744 <_osc32kctrl_init_sources+0x1c>)
72a: f242 328e movw r2, #9102 ; 0x238e
72e: 829a strh r2, [r3, #20]
}
static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->CFDCTRL.reg = data;
730: 2200 movs r2, #0
732: 759a strb r2, [r3, #22]
}
static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->EVCTRL.reg = data;
734: 75da strb r2, [r3, #23]
}
static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
{
uint32_t tmp;
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
736: 69da ldr r2, [r3, #28]
calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
hri_osc32kctrl_write_OSCULP32K_reg(hw,
#if CONF_OSCULP32K_CALIB_ENABLE == 1
OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
#else
OSC32KCTRL_OSCULP32K_CALIB(calib)
738: f402 527c and.w r2, r2, #16128 ; 0x3f00
}
static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->OSCULP32K.reg = data;
73c: 61da str r2, [r3, #28]
((Osc32kctrl *)hw)->RTCCTRL.reg = data;
73e: 2201 movs r2, #1
740: 741a strb r2, [r3, #16]
#endif
#endif
hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
(void)calib;
}
742: 4770 bx lr
744: 40001400 .word 0x40001400
00000748 <_gpio_set_pin_function>:
* \brief Set gpio pin function
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
{
uint8_t port = GPIO_PORT(gpio);
uint8_t pin = GPIO_PIN(gpio);
748: f000 031f and.w r3, r0, #31
static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
bool value)
{
uint8_t tmp;
PORT_CRITICAL_SECTION_ENTER();
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
74c: f103 4182 add.w r1, r3, #1090519040 ; 0x41000000
750: f501 4100 add.w r1, r1, #32768 ; 0x8000
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
754: 085b lsrs r3, r3, #1
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
756: f891 20c0 ldrb.w r2, [r1, #192] ; 0xc0
tmp &= ~PORT_PINCFG_PMUXEN;
75a: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000
75e: f002 02fe and.w r2, r2, #254 ; 0xfe
tmp |= value << PORT_PINCFG_PMUXEN_Pos;
762: f042 0201 orr.w r2, r2, #1
((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
766: f503 4300 add.w r3, r3, #32768 ; 0x8000
76a: f881 20c0 strb.w r2, [r1, #192] ; 0xc0
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
76e: f893 20b0 ldrb.w r2, [r3, #176] ; 0xb0
hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false);
} else {
hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
if (pin & 1) {
772: f010 0f01 tst.w r0, #1
tmp &= ~PORT_PMUX_PMUXO_Msk;
776: bf15 itete ne
778: f002 020f andne.w r2, r2, #15
tmp &= ~PORT_PMUX_PMUXE_Msk;
77c: f002 02f0 andeq.w r2, r2, #240 ; 0xf0
tmp |= PORT_PMUX_PMUXO(data);
780: f042 0230 orrne.w r2, r2, #48 ; 0x30
tmp |= PORT_PMUX_PMUXE(data);
784: f042 0203 orreq.w r2, r2, #3
((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
788: f883 20b0 strb.w r2, [r3, #176] ; 0xb0
} else {
// Even numbered pin
hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
}
}
}
78c: 4770 bx lr
...
00000790 <USART_DBG_PORT_init>:
struct spi_m_sync_descriptor SPI_SD_MMC;
struct usart_sync_descriptor USART_DBG;
void USART_DBG_PORT_init(void)
{
790: b510 push {r4, lr}
* found in the header files for the device
*
*/
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
{
_gpio_set_pin_function(pin, function);
792: 4c05 ldr r4, [pc, #20] ; (7a8 <USART_DBG_PORT_init+0x18>)
794: 4905 ldr r1, [pc, #20] ; (7ac <USART_DBG_PORT_init+0x1c>)
796: 2039 movs r0, #57 ; 0x39
798: 47a0 blx r4
79a: 4623 mov r3, r4
79c: 4904 ldr r1, [pc, #16] ; (7b0 <USART_DBG_PORT_init+0x20>)
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
79e: e8bd 4010 ldmia.w sp!, {r4, lr}
7a2: 2038 movs r0, #56 ; 0x38
7a4: 4718 bx r3
7a6: bf00 nop
7a8: 00000749 .word 0x00000749
7ac: 00390003 .word 0x00390003
7b0: 00380003 .word 0x00380003
000007b4 <USART_DBG_CLOCK_init>:
}
static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg = data;
7b4: 4b06 ldr r3, [pc, #24] ; (7d0 <USART_DBG_CLOCK_init+0x1c>)
7b6: 2240 movs r2, #64 ; 0x40
7b8: f8c3 20dc str.w r2, [r3, #220] ; 0xdc
7bc: 2243 movs r2, #67 ; 0x43
7be: f8c3 208c str.w r2, [r3, #140] ; 0x8c
}
static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
7c2: 4a04 ldr r2, [pc, #16] ; (7d4 <USART_DBG_CLOCK_init+0x20>)
7c4: 6993 ldr r3, [r2, #24]
7c6: f443 7300 orr.w r3, r3, #512 ; 0x200
7ca: 6193 str r3, [r2, #24]
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
7cc: 4770 bx lr
7ce: bf00 nop
7d0: 40001c00 .word 0x40001c00
7d4: 40000800 .word 0x40000800
000007d8 <USART_DBG_init>:
void USART_DBG_init(void)
{
7d8: b510 push {r4, lr}
USART_DBG_CLOCK_init();
7da: 4b05 ldr r3, [pc, #20] ; (7f0 <USART_DBG_init+0x18>)
usart_sync_init(&USART_DBG, SERCOM2, (void *)NULL);
7dc: 4905 ldr r1, [pc, #20] ; (7f4 <USART_DBG_init+0x1c>)
7de: 4806 ldr r0, [pc, #24] ; (7f8 <USART_DBG_init+0x20>)
USART_DBG_CLOCK_init();
7e0: 4798 blx r3
usart_sync_init(&USART_DBG, SERCOM2, (void *)NULL);
7e2: 4b06 ldr r3, [pc, #24] ; (7fc <USART_DBG_init+0x24>)
7e4: 2200 movs r2, #0
7e6: 4798 blx r3
USART_DBG_PORT_init();
}
7e8: e8bd 4010 ldmia.w sp!, {r4, lr}
USART_DBG_PORT_init();
7ec: 4b04 ldr r3, [pc, #16] ; (800 <USART_DBG_init+0x28>)
7ee: 4718 bx r3
7f0: 000007b5 .word 0x000007b5
7f4: 41012000 .word 0x41012000
7f8: 20000098 .word 0x20000098
7fc: 0000059d .word 0x0000059d
800: 00000791 .word 0x00000791
00000804 <SPI_SD_MMC_PORT_init>:
void SPI_SD_MMC_PORT_init(void)
{
804: b570 push {r4, r5, r6, lr}
((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
806: 4c1b ldr r4, [pc, #108] ; (874 <SPI_SD_MMC_PORT_init+0x70>)
808: 4d1b ldr r5, [pc, #108] ; (878 <SPI_SD_MMC_PORT_init+0x74>)
80a: 491c ldr r1, [pc, #112] ; (87c <SPI_SD_MMC_PORT_init+0x78>)
80c: f04f 6300 mov.w r3, #134217728 ; 0x8000000
810: f8c4 3094 str.w r3, [r4, #148] ; 0x94
static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
hri_port_wrconfig_reg_t data)
{
PORT_CRITICAL_SECTION_ENTER();
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
814: f04f 4680 mov.w r6, #1073741824 ; 0x40000000
((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
818: f8c4 3088 str.w r3, [r4, #136] ; 0x88
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
81c: 4b18 ldr r3, [pc, #96] ; (880 <SPI_SD_MMC_PORT_init+0x7c>)
81e: f8c4 60a8 str.w r6, [r4, #168] ; 0xa8
822: 203b movs r0, #59 ; 0x3b
824: f8c4 30a8 str.w r3, [r4, #168] ; 0xa8
828: 47a8 blx r5
((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
82a: f04f 6380 mov.w r3, #67108864 ; 0x4000000
82e: f8c4 3094 str.w r3, [r4, #148] ; 0x94
((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
832: f8c4 3088 str.w r3, [r4, #136] ; 0x88
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
836: 4b13 ldr r3, [pc, #76] ; (884 <SPI_SD_MMC_PORT_init+0x80>)
838: f8c4 60a8 str.w r6, [r4, #168] ; 0xa8
83c: 4912 ldr r1, [pc, #72] ; (888 <SPI_SD_MMC_PORT_init+0x84>)
83e: f8c4 30a8 str.w r3, [r4, #168] ; 0xa8
842: 203a movs r0, #58 ; 0x3a
844: 47a8 blx r5
((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
846: f04f 5300 mov.w r3, #536870912 ; 0x20000000
84a: f8c4 3084 str.w r3, [r4, #132] ; 0x84
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
84e: 4b0f ldr r3, [pc, #60] ; (88c <SPI_SD_MMC_PORT_init+0x88>)
850: f8c4 30a8 str.w r3, [r4, #168] ; 0xa8
854: 4b0e ldr r3, [pc, #56] ; (890 <SPI_SD_MMC_PORT_init+0x8c>)
856: f8c4 30a8 str.w r3, [r4, #168] ; 0xa8
((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
85a: f894 30dd ldrb.w r3, [r4, #221] ; 0xdd
85e: 490d ldr r1, [pc, #52] ; (894 <SPI_SD_MMC_PORT_init+0x90>)
860: f003 03fb and.w r3, r3, #251 ; 0xfb
864: f884 30dd strb.w r3, [r4, #221] ; 0xdd
868: 203d movs r0, #61 ; 0x3d
86a: 462b mov r3, r5
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB29, PINMUX_PB29D_SERCOM4_PAD3);
}
86c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
870: 4718 bx r3
872: bf00 nop
874: 41008000 .word 0x41008000
878: 00000749 .word 0x00000749
87c: 003b0003 .word 0x003b0003
880: c0000800 .word 0xc0000800
884: c0000400 .word 0xc0000400
888: 003a0003 .word 0x003a0003
88c: 40020000 .word 0x40020000
890: c0022000 .word 0xc0022000
894: 003d0003 .word 0x003d0003
00000898 <SPI_SD_MMC_CLOCK_init>:
898: 4b06 ldr r3, [pc, #24] ; (8b4 <SPI_SD_MMC_CLOCK_init+0x1c>)
89a: 2240 movs r2, #64 ; 0x40
89c: f8c3 2108 str.w r2, [r3, #264] ; 0x108
8a0: 2243 movs r2, #67 ; 0x43
8a2: f8c3 208c str.w r2, [r3, #140] ; 0x8c
}
static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
8a6: 4a04 ldr r2, [pc, #16] ; (8b8 <SPI_SD_MMC_CLOCK_init+0x20>)
8a8: 6a13 ldr r3, [r2, #32]
8aa: f043 0301 orr.w r3, r3, #1
8ae: 6213 str r3, [r2, #32]
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
}
8b0: 4770 bx lr
8b2: bf00 nop
8b4: 40001c00 .word 0x40001c00
8b8: 40000800 .word 0x40000800
000008bc <SPI_SD_MMC_init>:
void SPI_SD_MMC_init(void)
{
8bc: b510 push {r4, lr}
SPI_SD_MMC_CLOCK_init();
8be: 4b05 ldr r3, [pc, #20] ; (8d4 <SPI_SD_MMC_init+0x18>)
spi_m_sync_init(&SPI_SD_MMC, SERCOM4);
8c0: 4805 ldr r0, [pc, #20] ; (8d8 <SPI_SD_MMC_init+0x1c>)
SPI_SD_MMC_CLOCK_init();
8c2: 4798 blx r3
spi_m_sync_init(&SPI_SD_MMC, SERCOM4);
8c4: f04f 4186 mov.w r1, #1124073472 ; 0x43000000
8c8: 4b04 ldr r3, [pc, #16] ; (8dc <SPI_SD_MMC_init+0x20>)
8ca: 4798 blx r3
SPI_SD_MMC_PORT_init();
}
8cc: e8bd 4010 ldmia.w sp!, {r4, lr}
SPI_SD_MMC_PORT_init();
8d0: 4b03 ldr r3, [pc, #12] ; (8e0 <SPI_SD_MMC_init+0x24>)
8d2: 4718 bx r3
8d4: 00000899 .word 0x00000899
8d8: 200000a4 .word 0x200000a4
8dc: 00000301 .word 0x00000301
8e0: 00000805 .word 0x00000805
000008e4 <delay_driver_init>:
void delay_driver_init(void)
{
delay_init(SysTick);
8e4: 4801 ldr r0, [pc, #4] ; (8ec <delay_driver_init+0x8>)
8e6: 4b02 ldr r3, [pc, #8] ; (8f0 <delay_driver_init+0xc>)
8e8: 4718 bx r3
8ea: bf00 nop
8ec: e000e010 .word 0xe000e010
8f0: 000003f9 .word 0x000003f9
000008f4 <system_init>:
}
void system_init(void)
{
8f4: b510 push {r4, lr}
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
8f6: 4b05 ldr r3, [pc, #20] ; (90c <system_init+0x18>)
8f8: 4798 blx r3
init_mcu();
USART_DBG_init();
8fa: 4b05 ldr r3, [pc, #20] ; (910 <system_init+0x1c>)
8fc: 4798 blx r3
SPI_SD_MMC_init();
8fe: 4b05 ldr r3, [pc, #20] ; (914 <system_init+0x20>)
900: 4798 blx r3
delay_driver_init();
}
902: e8bd 4010 ldmia.w sp!, {r4, lr}
delay_driver_init();
906: 4b04 ldr r3, [pc, #16] ; (918 <system_init+0x24>)
908: 4718 bx r3
90a: bf00 nop
90c: 00000409 .word 0x00000409
910: 000007d9 .word 0x000007d9
914: 000008bd .word 0x000008bd
918: 000008e5 .word 0x000008e5
0000091c <hri_sercomspi_wait_for_sync>:
return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
}
static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
{
while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
91c: 69c3 ldr r3, [r0, #28]
91e: 420b tst r3, r1
920: d1fc bne.n 91c <hri_sercomspi_wait_for_sync>
};
}
922: 4770 bx lr
00000924 <hri_sercomusart_wait_for_sync>:
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
}
static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
{
while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
924: 69c3 ldr r3, [r0, #28]
926: 420b tst r3, r1
928: d1fc bne.n 924 <hri_sercomusart_wait_for_sync>
};
}
92a: 4770 bx lr
0000092c <hri_sercomspi_clear_CTRLA_ENABLE_bit>:
}
static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
92c: 6802 ldr r2, [r0, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
92e: 4b03 ldr r3, [pc, #12] ; (93c <hri_sercomspi_clear_CTRLA_ENABLE_bit+0x10>)
((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
930: f022 0202 bic.w r2, r2, #2
934: 6002 str r2, [r0, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
936: 2103 movs r1, #3
938: 4718 bx r3
93a: bf00 nop
93c: 0000091d .word 0x0000091d
00000940 <hri_sercomusart_clear_CTRLA_ENABLE_bit>:
}
static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
940: 6802 ldr r2, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
942: 4b03 ldr r3, [pc, #12] ; (950 <hri_sercomusart_clear_CTRLA_ENABLE_bit+0x10>)
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
944: f022 0202 bic.w r2, r2, #2
948: 6002 str r2, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
94a: 2103 movs r1, #3
94c: 4718 bx r3
94e: bf00 nop
950: 00000925 .word 0x00000925
00000954 <_sercom_get_hardware_index>:
/**
* \brief Retrieve ordinal number of the given sercom hardware instance
*/
static uint8_t _sercom_get_hardware_index(const void *const hw)
{
954: b570 push {r4, r5, r6, lr}
Sercom *const sercom_modules[] = SERCOM_INSTS;
956: 4d0c ldr r5, [pc, #48] ; (988 <_sercom_get_hardware_index+0x34>)
{
958: 4606 mov r6, r0
Sercom *const sercom_modules[] = SERCOM_INSTS;
95a: cd0f ldmia r5!, {r0, r1, r2, r3}
{
95c: b088 sub sp, #32
Sercom *const sercom_modules[] = SERCOM_INSTS;
95e: 466c mov r4, sp
960: c40f stmia r4!, {r0, r1, r2, r3}
962: e895 000f ldmia.w r5, {r0, r1, r2, r3}
966: e884 000f stmia.w r4, {r0, r1, r2, r3}
/* Find index for SERCOM instance. */
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
96a: 466a mov r2, sp
96c: 2300 movs r3, #0
if ((uint32_t)hw == (uint32_t)sercom_modules[i]) {
96e: f852 1b04 ldr.w r1, [r2], #4
972: 42b1 cmp r1, r6
974: d102 bne.n 97c <_sercom_get_hardware_index+0x28>
return i;
976: b2d8 uxtb r0, r3
}
}
return 0;
}
978: b008 add sp, #32
97a: bd70 pop {r4, r5, r6, pc}
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
97c: 3301 adds r3, #1
97e: 2b08 cmp r3, #8
980: d1f5 bne.n 96e <_sercom_get_hardware_index+0x1a>
return 0;
982: 2000 movs r0, #0
984: e7f8 b.n 978 <_sercom_get_hardware_index+0x24>
986: bf00 nop
988: 000016e0 .word 0x000016e0
0000098c <_usart_init>:
* \param[in] hw The pointer to hardware instance
*
* \return The status of initialization
*/
static int32_t _usart_init(void *const hw)
{
98c: b538 push {r3, r4, r5, lr}
uint8_t sercom_offset = _sercom_get_hardware_index(hw);
98e: 4b1b ldr r3, [pc, #108] ; (9fc <_usart_init+0x70>)
{
990: 4604 mov r4, r0
uint8_t sercom_offset = _sercom_get_hardware_index(hw);
992: 4798 blx r3
if (_usarts[i].number == sercom_offset) {
994: 2802 cmp r0, #2
996: d005 beq.n 9a4 <_usart_init+0x18>
ASSERT(false);
998: 4919 ldr r1, [pc, #100] ; (a00 <_usart_init+0x74>)
99a: 4b1a ldr r3, [pc, #104] ; (a04 <_usart_init+0x78>)
99c: f240 2247 movw r2, #583 ; 0x247
9a0: 2000 movs r0, #0
9a2: 4798 blx r3
return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
9a4: 69e3 ldr r3, [r4, #28]
9a6: 4d18 ldr r5, [pc, #96] ; (a08 <_usart_init+0x7c>)
uint8_t i = _get_sercom_index(hw);
if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
9a8: f013 0f01 tst.w r3, #1
9ac: d10e bne.n 9cc <_usart_init+0x40>
static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw,
hri_sercomusart_ctrla_reg_t mask)
{
uint32_t tmp;
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
9ae: 2103 movs r1, #3
9b0: 4620 mov r0, r4
9b2: 47a8 blx r5
tmp = ((Sercom *)hw)->USART.CTRLA.reg;
9b4: 6823 ldr r3, [r4, #0]
uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk;
if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
9b6: 079b lsls r3, r3, #30
9b8: d503 bpl.n 9c2 <_usart_init+0x36>
hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
9ba: 4b14 ldr r3, [pc, #80] ; (a0c <_usart_init+0x80>)
9bc: 4798 blx r3
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
9be: 2102 movs r1, #2
9c0: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg = data;
9c2: 2305 movs r3, #5
9c4: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
9c6: 2103 movs r1, #3
9c8: 4620 mov r0, r4
9ca: 47a8 blx r5
}
hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
}
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
9cc: 4620 mov r0, r4
9ce: 2101 movs r1, #1
9d0: 47a8 blx r5
((Sercom *)hw)->USART.CTRLA.reg = data;
9d2: 4b0f ldr r3, [pc, #60] ; (a10 <_usart_init+0x84>)
9d4: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
9d6: 2103 movs r1, #3
9d8: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLB.reg = data;
9da: f44f 3340 mov.w r3, #196608 ; 0x30000
9de: 6063 str r3, [r4, #4]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
9e0: 211f movs r1, #31
9e2: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLC.reg = data;
9e4: 4b0b ldr r3, [pc, #44] ; (a14 <_usart_init+0x88>)
9e6: 60a3 str r3, [r4, #8]
}
static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.BAUD.reg = data;
9e8: f64f 4311 movw r3, #64529 ; 0xfc11
9ec: 81a3 strh r3, [r4, #12]
}
static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.RXPL.reg = data;
9ee: 2300 movs r3, #0
9f0: 73a3 strb r3, [r4, #14]
hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl);
hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl);
return ERR_NONE;
}
9f2: 4618 mov r0, r3
}
static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.DBGCTRL.reg = data;
9f4: f884 3030 strb.w r3, [r4, #48] ; 0x30
9f8: bd38 pop {r3, r4, r5, pc}
9fa: bf00 nop
9fc: 00000955 .word 0x00000955
a00: 000016c4 .word 0x000016c4
a04: 00000485 .word 0x00000485
a08: 00000925 .word 0x00000925
a0c: 00000941 .word 0x00000941
a10: 40100004 .word 0x40100004
a14: 00700002 .word 0x00700002
00000a18 <_usart_sync_init>:
{
a18: b570 push {r4, r5, r6, lr}
ASSERT(device);
a1a: 4605 mov r5, r0
a1c: 3800 subs r0, #0
{
a1e: 460c mov r4, r1
ASSERT(device);
a20: 4b05 ldr r3, [pc, #20] ; (a38 <_usart_sync_init+0x20>)
a22: 4906 ldr r1, [pc, #24] ; (a3c <_usart_sync_init+0x24>)
a24: bf18 it ne
a26: 2001 movne r0, #1
a28: 22bb movs r2, #187 ; 0xbb
a2a: 4798 blx r3
device->hw = hw;
a2c: 602c str r4, [r5, #0]
return _usart_init(hw);
a2e: 4620 mov r0, r4
a30: 4b03 ldr r3, [pc, #12] ; (a40 <_usart_sync_init+0x28>)
}
a32: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return _usart_init(hw);
a36: 4718 bx r3
a38: 00000485 .word 0x00000485
a3c: 000016c4 .word 0x000016c4
a40: 0000098d .word 0x0000098d
00000a44 <_usart_sync_enable>:
hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw);
a44: 6800 ldr r0, [r0, #0]
((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
a46: 6803 ldr r3, [r0, #0]
a48: f043 0302 orr.w r3, r3, #2
a4c: 6003 str r3, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
a4e: 2103 movs r1, #3
a50: 4b00 ldr r3, [pc, #0] ; (a54 <_usart_sync_enable+0x10>)
a52: 4718 bx r3
a54: 00000925 .word 0x00000925
00000a58 <_usart_sync_write_byte>:
hri_sercomusart_write_DATA_reg(device->hw, data);
a58: 6803 ldr r3, [r0, #0]
((Sercom *)hw)->USART.DATA.reg = data;
a5a: 6299 str r1, [r3, #40] ; 0x28
}
a5c: 4770 bx lr
00000a5e <_usart_sync_read_byte>:
return hri_sercomusart_read_DATA_reg(device->hw);
a5e: 6803 ldr r3, [r0, #0]
return ((Sercom *)hw)->USART.DATA.reg;
a60: 6a98 ldr r0, [r3, #40] ; 0x28
}
a62: b2c0 uxtb r0, r0
a64: 4770 bx lr
00000a66 <_usart_sync_is_ready_to_send>:
return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
a66: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
a68: 7e18 ldrb r0, [r3, #24]
}
a6a: f000 0001 and.w r0, r0, #1
a6e: 4770 bx lr
00000a70 <_usart_sync_is_transmit_done>:
return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
a70: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
a72: 7e18 ldrb r0, [r3, #24]
}
a74: f3c0 0040 ubfx r0, r0, #1, #1
a78: 4770 bx lr
00000a7a <_usart_sync_is_byte_received>:
return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
a7a: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
a7c: 7e18 ldrb r0, [r3, #24]
}
a7e: f3c0 0080 ubfx r0, r0, #2, #1
a82: 4770 bx lr
00000a84 <_spi_m_sync_init>:
return NULL;
}
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
{
a84: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
a88: 4b44 ldr r3, [pc, #272] ; (b9c <_spi_m_sync_init+0x118>)
return NULL;
a8a: 4d45 ldr r5, [pc, #276] ; (ba0 <_spi_m_sync_init+0x11c>)
{
a8c: 4607 mov r7, r0
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
a8e: 4608 mov r0, r1
{
a90: 460c mov r4, r1
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
a92: 4798 blx r3
return NULL;
a94: 2804 cmp r0, #4
a96: bf18 it ne
a98: 2500 movne r5, #0
const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
ASSERT(dev && hw);
a9a: 2f00 cmp r7, #0
a9c: d05d beq.n b5a <_spi_m_sync_init+0xd6>
a9e: 1e20 subs r0, r4, #0
aa0: bf18 it ne
aa2: 2001 movne r0, #1
aa4: 4e3f ldr r6, [pc, #252] ; (ba4 <_spi_m_sync_init+0x120>)
aa6: 4940 ldr r1, [pc, #256] ; (ba8 <_spi_m_sync_init+0x124>)
aa8: f640 123f movw r2, #2367 ; 0x93f
aac: 47b0 blx r6
if (regs == NULL) {
aae: 46b0 mov r8, r6
ab0: 2d00 cmp r5, #0
ab2: d070 beq.n b96 <_spi_m_sync_init+0x112>
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
ab4: 69e3 ldr r3, [r4, #28]
ab6: 4e3d ldr r6, [pc, #244] ; (bac <_spi_m_sync_init+0x128>)
return ERR_INVALID_ARG;
}
if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
ab8: f013 0f01 tst.w r3, #1
abc: d113 bne.n ae6 <_spi_m_sync_init+0x62>
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
abe: 2103 movs r1, #3
ac0: 4620 mov r0, r4
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
ac2: f8d5 9000 ldr.w r9, [r5]
ac6: 47b0 blx r6
tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
ac8: 6823 ldr r3, [r4, #0]
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
aca: 079b lsls r3, r3, #30
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
acc: f009 091c and.w r9, r9, #28
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
ad0: d503 bpl.n ada <_spi_m_sync_init+0x56>
hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
ad2: 4b37 ldr r3, [pc, #220] ; (bb0 <_spi_m_sync_init+0x12c>)
ad4: 4798 blx r3
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
ad6: 2102 movs r1, #2
ad8: 47b0 blx r6
}
hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
ada: f049 0301 orr.w r3, r9, #1
((Sercom *)hw)->SPI.CTRLA.reg = data;
ade: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
ae0: 2103 movs r1, #3
ae2: 4620 mov r0, r4
ae4: 47b0 blx r6
}
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
ae6: 2101 movs r1, #1
ae8: 4620 mov r0, r4
aea: 47b0 blx r6
dev->prvt = hw;
if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
aec: 682b ldr r3, [r5, #0]
aee: f8df 90c4 ldr.w r9, [pc, #196] ; bb4 <_spi_m_sync_init+0x130>
dev->prvt = hw;
af2: 603c str r4, [r7, #0]
if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
af4: f003 031c and.w r3, r3, #28
af8: 2b08 cmp r3, #8
afa: d130 bne.n b5e <_spi_m_sync_init+0xda>
ASSERT(hw && regs);
afc: 492a ldr r1, [pc, #168] ; (ba8 <_spi_m_sync_init+0x124>)
afe: 2001 movs r0, #1
b00: f640 121d movw r2, #2333 ; 0x91d
b04: 47c0 blx r8
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
b06: 682b ldr r3, [r5, #0]
hri_sercomspi_write_CTRLA_reg(
b08: ea03 0309 and.w r3, r3, r9
((Sercom *)hw)->SPI.CTRLA.reg = data;
b0c: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
b0e: 2103 movs r1, #3
b10: 4620 mov r0, r4
b12: 47b0 blx r6
(regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN))
b14: 686b ldr r3, [r5, #4]
| (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN));
b16: f423 3308 bic.w r3, r3, #139264 ; 0x22000
b1a: f423 7310 bic.w r3, r3, #576 ; 0x240
hri_sercomspi_write_CTRLB_reg(hw,
b1e: f443 3300 orr.w r3, r3, #131072 ; 0x20000
b22: f443 7310 orr.w r3, r3, #576 ; 0x240
((Sercom *)hw)->SPI.CTRLB.reg = data;
b26: 6063 str r3, [r4, #4]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
b28: 2117 movs r1, #23
b2a: 47b0 blx r6
hri_sercomspi_write_ADDR_reg(hw, regs->addr);
b2c: 68ab ldr r3, [r5, #8]
((Sercom *)hw)->SPI.ADDR.reg = data;
b2e: 6263 str r3, [r4, #36] ; 0x24
hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
b30: 7b6b ldrb r3, [r5, #13]
((Sercom *)hw)->SPI.DBGCTRL.reg = data;
b32: f884 3030 strb.w r3, [r4, #48] ; 0x30
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
b36: 69e3 ldr r3, [r4, #28]
while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF))
b38: 2b00 cmp r3, #0
b3a: d1fc bne.n b36 <_spi_m_sync_init+0xb2>
} else {
_spi_load_regs_master(hw, regs);
}
/* Load character size from default hardware configuration */
dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
b3c: 686b ldr r3, [r5, #4]
b3e: f013 0f07 tst.w r3, #7
b42: bf0c ite eq
b44: 2301 moveq r3, #1
b46: 2302 movne r3, #2
b48: 713b strb r3, [r7, #4]
dev->dummy_byte = regs->dummy_byte;
b4a: 7bab ldrb r3, [r5, #14]
b4c: 7bea ldrb r2, [r5, #15]
b4e: ea43 2302 orr.w r3, r3, r2, lsl #8
b52: 80fb strh r3, [r7, #6]
return ERR_NONE;
b54: 2000 movs r0, #0
}
b56: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(dev && hw);
b5a: 4638 mov r0, r7
b5c: e7a2 b.n aa4 <_spi_m_sync_init+0x20>
ASSERT(hw && regs);
b5e: 4912 ldr r1, [pc, #72] ; (ba8 <_spi_m_sync_init+0x124>)
b60: 2001 movs r0, #1
b62: f640 1209 movw r2, #2313 ; 0x909
b66: 47c0 blx r8
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
b68: 682b ldr r3, [r5, #0]
hri_sercomspi_write_CTRLA_reg(
b6a: ea03 0309 and.w r3, r3, r9
((Sercom *)hw)->SPI.CTRLA.reg = data;
b6e: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
b70: 2103 movs r1, #3
b72: 4620 mov r0, r4
b74: 47b0 blx r6
(regs->ctrlb
b76: 686b ldr r3, [r5, #4]
| (SERCOM_SPI_CTRLB_RXEN));
b78: f423 3338 bic.w r3, r3, #188416 ; 0x2e000
b7c: f423 7310 bic.w r3, r3, #576 ; 0x240
hri_sercomspi_write_CTRLB_reg(
b80: f443 3300 orr.w r3, r3, #131072 ; 0x20000
((Sercom *)hw)->SPI.CTRLB.reg = data;
b84: 6063 str r3, [r4, #4]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
b86: 2117 movs r1, #23
b88: 47b0 blx r6
hri_sercomspi_write_BAUD_reg(hw, regs->baud);
b8a: 7b2b ldrb r3, [r5, #12]
((Sercom *)hw)->SPI.BAUD.reg = data;
b8c: 7323 strb r3, [r4, #12]
hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
b8e: 7b6b ldrb r3, [r5, #13]
((Sercom *)hw)->SPI.DBGCTRL.reg = data;
b90: f884 3030 strb.w r3, [r4, #48] ; 0x30
}
b94: e7d2 b.n b3c <_spi_m_sync_init+0xb8>
return ERR_INVALID_ARG;
b96: f06f 000c mvn.w r0, #12
b9a: e7dc b.n b56 <_spi_m_sync_init+0xd2>
b9c: 00000955 .word 0x00000955
ba0: 00001718 .word 0x00001718
ba4: 00000485 .word 0x00000485
ba8: 000016c4 .word 0x000016c4
bac: 0000091d .word 0x0000091d
bb0: 0000092d .word 0x0000092d
bb4: fffffefc .word 0xfffffefc
00000bb8 <_spi_m_sync_trans>:
return ERR_NONE;
}
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg)
{
bb8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
void * hw = dev->prvt;
bbc: 6804 ldr r4, [r0, #0]
int32_t rc = 0;
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
bbe: f890 8004 ldrb.w r8, [r0, #4]
ASSERT(dev && hw);
bc2: 4b2a ldr r3, [pc, #168] ; (c6c <_spi_m_sync_trans+0xb4>)
{
bc4: 4607 mov r7, r0
ASSERT(dev && hw);
bc6: 1e20 subs r0, r4, #0
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
bc8: e9d1 6500 ldrd r6, r5, [r1]
ASSERT(dev && hw);
bcc: f640 22a3 movw r2, #2723 ; 0xaa3
bd0: bf18 it ne
bd2: 2001 movne r0, #1
{
bd4: 4689 mov r9, r1
ASSERT(dev && hw);
bd6: 4926 ldr r1, [pc, #152] ; (c70 <_spi_m_sync_trans+0xb8>)
bd8: 4798 blx r3
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
bda: 69e2 ldr r2, [r4, #28]
/* If settings are not applied (pending), we can not go on */
if (hri_sercomspi_is_syncing(
bdc: f012 0207 ands.w r2, r2, #7
be0: d13e bne.n c60 <_spi_m_sync_trans+0xa8>
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
be2: 4b24 ldr r3, [pc, #144] ; (c74 <_spi_m_sync_trans+0xbc>)
be4: 2103 movs r1, #3
be6: 4620 mov r0, r4
be8: 4798 blx r3
tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
bea: 6823 ldr r3, [r4, #0]
hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) {
return ERR_BUSY;
}
/* SPI must be enabled to start synchronous transfer */
if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) {
bec: 0799 lsls r1, r3, #30
bee: d53a bpl.n c66 <_spi_m_sync_trans+0xae>
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
bf0: 4611 mov r1, r2
return ((Sercom *)hw)->SPI.INTFLAG.reg;
bf2: 7e23 ldrb r3, [r4, #24]
bf4: b2d8 uxtb r0, r3
if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) {
bf6: 075b lsls r3, r3, #29
bf8: d40f bmi.n c1a <_spi_m_sync_trans+0x62>
uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw);
if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) {
/* In master mode, do not start next byte before previous byte received
* to make better output waveform */
if (ctrl.rxcnt >= ctrl.txcnt) {
bfa: 428a cmp r2, r1
bfc: d818 bhi.n c30 <_spi_m_sync_trans+0x78>
if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) {
bfe: 07c3 lsls r3, r0, #31
c00: d516 bpl.n c30 <_spi_m_sync_trans+0x78>
_spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte);
c02: 88fb ldrh r3, [r7, #6]
if (ctrl->txbuf) {
c04: b136 cbz r6, c14 <_spi_m_sync_trans+0x5c>
if (ctrl->char_size > 1) {
c06: f1b8 0f01 cmp.w r8, #1
data = *ctrl->txbuf++;
c0a: 7833 ldrb r3, [r6, #0]
data |= (*ctrl->txbuf) << 8;
c0c: bf8c ite hi
c0e: f836 3b02 ldrhhi.w r3, [r6], #2
data = *ctrl->txbuf++;
c12: 3601 addls r6, #1
ctrl->txcnt++;
c14: 3201 adds r2, #1
((Sercom *)hw)->SPI.DATA.reg = data;
c16: 62a3 str r3, [r4, #40] ; 0x28
}
c18: e00a b.n c30 <_spi_m_sync_trans+0x78>
return ((Sercom *)hw)->SPI.DATA.reg;
c1a: 6aa3 ldr r3, [r4, #40] ; 0x28
if (ctrl->rxbuf) {
c1c: b13d cbz r5, c2e <_spi_m_sync_trans+0x76>
if (ctrl->char_size > 1) {
c1e: f1b8 0f01 cmp.w r8, #1
*ctrl->rxbuf++ = (uint8_t)data;
c22: 702b strb r3, [r5, #0]
*ctrl->rxbuf++ = (uint8_t)(data >> 8);
c24: bf85 ittet hi
c26: 0a1b lsrhi r3, r3, #8
c28: 706b strbhi r3, [r5, #1]
*ctrl->rxbuf++ = (uint8_t)data;
c2a: 3501 addls r5, #1
*ctrl->rxbuf++ = (uint8_t)(data >> 8);
c2c: 3502 addhi r5, #2
ctrl->rxcnt++;
c2e: 3101 adds r1, #1
if (SERCOM_SPI_INTFLAG_ERROR & iflag) {
c30: 0600 lsls r0, r0, #24
c32: d407 bmi.n c44 <_spi_m_sync_trans+0x8c>
rc = _spi_err_check(iflag, hw);
if (rc < 0) {
break;
}
if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) {
c34: f8d9 3008 ldr.w r3, [r9, #8]
c38: 4293 cmp r3, r2
c3a: d8da bhi.n bf2 <_spi_m_sync_trans+0x3a>
c3c: 428b cmp r3, r1
c3e: d8d8 bhi.n bf2 <_spi_m_sync_trans+0x3a>
rc = ctrl.txcnt;
c40: 4610 mov r0, r2
while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
c42: e006 b.n c52 <_spi_m_sync_trans+0x9a>
}
static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.STATUS.reg = mask;
c44: f64f 73ff movw r3, #65535 ; 0xffff
c48: 8363 strh r3, [r4, #26]
((Sercom *)hw)->SPI.INTFLAG.reg = mask;
c4a: 2380 movs r3, #128 ; 0x80
c4c: 7623 strb r3, [r4, #24]
return ERR_OVERFLOW;
c4e: f06f 0012 mvn.w r0, #18
tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
c52: 7e23 ldrb r3, [r4, #24]
while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
c54: 079b lsls r3, r3, #30
c56: d0fc beq.n c52 <_spi_m_sync_trans+0x9a>
((Sercom *)hw)->SPI.INTFLAG.reg = mask;
c58: 2303 movs r3, #3
c5a: 7623 strb r3, [r4, #24]
}
/* Wait until SPI bus idle */
_spi_wait_bus_idle(hw);
return rc;
}
c5c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
return ERR_BUSY;
c60: f06f 0003 mvn.w r0, #3
c64: e7fa b.n c5c <_spi_m_sync_trans+0xa4>
return ERR_NOT_INITIALIZED;
c66: f06f 0013 mvn.w r0, #19
c6a: e7f7 b.n c5c <_spi_m_sync_trans+0xa4>
c6c: 00000485 .word 0x00000485
c70: 000016c4 .word 0x000016c4
c74: 0000091d .word 0x0000091d
00000c78 <atmel_start_init>:
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
c78: 4b00 ldr r3, [pc, #0] ; (c7c <atmel_start_init+0x4>)
c7a: 4718 bx r3
c7c: 000008f5 .word 0x000008f5
00000c80 <pprintf>:
return 0;
}
int pprintf(const char* fmt, ...)
{
c80: b40f push {r0, r1, r2, r3}
c82: b530 push {r4, r5, lr}
c84: b0c3 sub sp, #268 ; 0x10c
size_t size_str = strlen(fmt);
c86: 4c11 ldr r4, [pc, #68] ; (ccc <pprintf+0x4c>)
{
c88: 9d46 ldr r5, [sp, #280] ; 0x118
size_t size_str = strlen(fmt);
c8a: 4628 mov r0, r5
c8c: 47a0 blx r4
if (size_str >= MAX_PRINTF_BUFFER)
c8e: 28ff cmp r0, #255 ; 0xff
c90: d818 bhi.n cc4 <pprintf+0x44>
{
return -1;
}
uint8_t printf_buffer[MAX_PRINTF_BUFFER];
memset(printf_buffer, '\0', MAX_PRINTF_BUFFER);
c92: 4b0f ldr r3, [pc, #60] ; (cd0 <pprintf+0x50>)
c94: f44f 7280 mov.w r2, #256 ; 0x100
c98: 2100 movs r1, #0
c9a: a802 add r0, sp, #8
c9c: 4798 blx r3
va_list args;
va_start(args, fmt);
c9e: aa47 add r2, sp, #284 ; 0x11c
vsprintf((char*)printf_buffer, fmt, args);
ca0: 4b0c ldr r3, [pc, #48] ; (cd4 <pprintf+0x54>)
va_start(args, fmt);
ca2: 9201 str r2, [sp, #4]
vsprintf((char*)printf_buffer, fmt, args);
ca4: 4629 mov r1, r5
ca6: a802 add r0, sp, #8
ca8: 4798 blx r3
va_end(args);
return io_write(debug_io, (const uint8_t*)printf_buffer, strlen((const char*)printf_buffer));
caa: a802 add r0, sp, #8
cac: 47a0 blx r4
cae: 4b0a ldr r3, [pc, #40] ; (cd8 <pprintf+0x58>)
cb0: b282 uxth r2, r0
cb2: a902 add r1, sp, #8
cb4: 6818 ldr r0, [r3, #0]
cb6: 4b09 ldr r3, [pc, #36] ; (cdc <pprintf+0x5c>)
cb8: 4798 blx r3
}
cba: b043 add sp, #268 ; 0x10c
cbc: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
cc0: b004 add sp, #16
cc2: 4770 bx lr
return -1;
cc4: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
cc8: e7f7 b.n cba <pprintf+0x3a>
cca: bf00 nop
ccc: 00000d89 .word 0x00000d89
cd0: 00000d79 .word 0x00000d79
cd4: 00000dc5 .word 0x00000dc5
cd8: 200000bc .word 0x200000bc
cdc: 000002a5 .word 0x000002a5
00000ce0 <pdebug_init>:
{
ce0: b510 push {r4, lr}
usart_sync_get_io_descriptor(&USART_DBG, &debug_io);
ce2: 4c06 ldr r4, [pc, #24] ; (cfc <pdebug_init+0x1c>)
ce4: 4906 ldr r1, [pc, #24] ; (d00 <pdebug_init+0x20>)
ce6: 4b07 ldr r3, [pc, #28] ; (d04 <pdebug_init+0x24>)
ce8: 4620 mov r0, r4
cea: 4798 blx r3
usart_sync_enable(&USART_DBG);
cec: 4b06 ldr r3, [pc, #24] ; (d08 <pdebug_init+0x28>)
cee: 4620 mov r0, r4
cf0: 4798 blx r3
printf("Debug Initialized\n");
cf2: 4b06 ldr r3, [pc, #24] ; (d0c <pdebug_init+0x2c>)
cf4: 4806 ldr r0, [pc, #24] ; (d10 <pdebug_init+0x30>)
cf6: 4798 blx r3
}
cf8: 2000 movs r0, #0
cfa: bd10 pop {r4, pc}
cfc: 20000098 .word 0x20000098
d00: 200000bc .word 0x200000bc
d04: 00000609 .word 0x00000609
d08: 000005dd .word 0x000005dd
d0c: 00000c81 .word 0x00000c81
d10: 00001729 .word 0x00001729
00000d14 <__libc_init_array>:
d14: b570 push {r4, r5, r6, lr}
d16: 4d0d ldr r5, [pc, #52] ; (d4c <__libc_init_array+0x38>)
d18: 4c0d ldr r4, [pc, #52] ; (d50 <__libc_init_array+0x3c>)
d1a: 1b64 subs r4, r4, r5
d1c: 10a4 asrs r4, r4, #2
d1e: 2600 movs r6, #0
d20: 42a6 cmp r6, r4
d22: d109 bne.n d38 <__libc_init_array+0x24>
d24: 4d0b ldr r5, [pc, #44] ; (d54 <__libc_init_array+0x40>)
d26: 4c0c ldr r4, [pc, #48] ; (d58 <__libc_init_array+0x44>)
d28: f000 fd64 bl 17f4 <_init>
d2c: 1b64 subs r4, r4, r5
d2e: 10a4 asrs r4, r4, #2
d30: 2600 movs r6, #0
d32: 42a6 cmp r6, r4
d34: d105 bne.n d42 <__libc_init_array+0x2e>
d36: bd70 pop {r4, r5, r6, pc}
d38: f855 3b04 ldr.w r3, [r5], #4
d3c: 4798 blx r3
d3e: 3601 adds r6, #1
d40: e7ee b.n d20 <__libc_init_array+0xc>
d42: f855 3b04 ldr.w r3, [r5], #4
d46: 4798 blx r3
d48: 3601 adds r6, #1
d4a: e7f2 b.n d32 <__libc_init_array+0x1e>
d4c: 00001800 .word 0x00001800
d50: 00001800 .word 0x00001800
d54: 00001800 .word 0x00001800
d58: 00001804 .word 0x00001804
00000d5c <memcpy>:
d5c: 440a add r2, r1
d5e: 4291 cmp r1, r2
d60: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
d64: d100 bne.n d68 <memcpy+0xc>
d66: 4770 bx lr
d68: b510 push {r4, lr}
d6a: f811 4b01 ldrb.w r4, [r1], #1
d6e: f803 4f01 strb.w r4, [r3, #1]!
d72: 4291 cmp r1, r2
d74: d1f9 bne.n d6a <memcpy+0xe>
d76: bd10 pop {r4, pc}
00000d78 <memset>:
d78: 4402 add r2, r0
d7a: 4603 mov r3, r0
d7c: 4293 cmp r3, r2
d7e: d100 bne.n d82 <memset+0xa>
d80: 4770 bx lr
d82: f803 1b01 strb.w r1, [r3], #1
d86: e7f9 b.n d7c <memset+0x4>
00000d88 <strlen>:
d88: 4603 mov r3, r0
d8a: f813 2b01 ldrb.w r2, [r3], #1
d8e: 2a00 cmp r2, #0
d90: d1fb bne.n d8a <strlen+0x2>
d92: 1a18 subs r0, r3, r0
d94: 3801 subs r0, #1
d96: 4770 bx lr
00000d98 <_vsiprintf_r>:
d98: b500 push {lr}
d9a: b09b sub sp, #108 ; 0x6c
d9c: 9100 str r1, [sp, #0]
d9e: 9104 str r1, [sp, #16]
da0: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
da4: 9105 str r1, [sp, #20]
da6: 9102 str r1, [sp, #8]
da8: 4905 ldr r1, [pc, #20] ; (dc0 <_vsiprintf_r+0x28>)
daa: 9103 str r1, [sp, #12]
dac: 4669 mov r1, sp
dae: f000 f8cb bl f48 <_svfiprintf_r>
db2: 9b00 ldr r3, [sp, #0]
db4: 2200 movs r2, #0
db6: 701a strb r2, [r3, #0]
db8: b01b add sp, #108 ; 0x6c
dba: f85d fb04 ldr.w pc, [sp], #4
dbe: bf00 nop
dc0: ffff0208 .word 0xffff0208
00000dc4 <vsiprintf>:
dc4: 4613 mov r3, r2
dc6: 460a mov r2, r1
dc8: 4601 mov r1, r0
dca: 4802 ldr r0, [pc, #8] ; (dd4 <vsiprintf+0x10>)
dcc: 6800 ldr r0, [r0, #0]
dce: f7ff bfe3 b.w d98 <_vsiprintf_r>
dd2: bf00 nop
dd4: 20000000 .word 0x20000000
00000dd8 <__retarget_lock_acquire_recursive>:
dd8: 4770 bx lr
00000dda <__retarget_lock_release_recursive>:
dda: 4770 bx lr
00000ddc <_malloc_r>:
ddc: b5f8 push {r3, r4, r5, r6, r7, lr}
dde: 1ccd adds r5, r1, #3
de0: f025 0503 bic.w r5, r5, #3
de4: 3508 adds r5, #8
de6: 2d0c cmp r5, #12
de8: bf38 it cc
dea: 250c movcc r5, #12
dec: 2d00 cmp r5, #0
dee: 4606 mov r6, r0
df0: db01 blt.n df6 <_malloc_r+0x1a>
df2: 42a9 cmp r1, r5
df4: d903 bls.n dfe <_malloc_r+0x22>
df6: 230c movs r3, #12
df8: 6033 str r3, [r6, #0]
dfa: 2000 movs r0, #0
dfc: bdf8 pop {r3, r4, r5, r6, r7, pc}
dfe: f000 fbb1 bl 1564 <__malloc_lock>
e02: 4921 ldr r1, [pc, #132] ; (e88 <_malloc_r+0xac>)
e04: 680a ldr r2, [r1, #0]
e06: 4614 mov r4, r2
e08: b99c cbnz r4, e32 <_malloc_r+0x56>
e0a: 4f20 ldr r7, [pc, #128] ; (e8c <_malloc_r+0xb0>)
e0c: 683b ldr r3, [r7, #0]
e0e: b923 cbnz r3, e1a <_malloc_r+0x3e>
e10: 4621 mov r1, r4
e12: 4630 mov r0, r6
e14: f000 fb2c bl 1470 <_sbrk_r>
e18: 6038 str r0, [r7, #0]
e1a: 4629 mov r1, r5
e1c: 4630 mov r0, r6
e1e: f000 fb27 bl 1470 <_sbrk_r>
e22: 1c43 adds r3, r0, #1
e24: d123 bne.n e6e <_malloc_r+0x92>
e26: 230c movs r3, #12
e28: 6033 str r3, [r6, #0]
e2a: 4630 mov r0, r6
e2c: f000 fba0 bl 1570 <__malloc_unlock>
e30: e7e3 b.n dfa <_malloc_r+0x1e>
e32: 6823 ldr r3, [r4, #0]
e34: 1b5b subs r3, r3, r5
e36: d417 bmi.n e68 <_malloc_r+0x8c>
e38: 2b0b cmp r3, #11
e3a: d903 bls.n e44 <_malloc_r+0x68>
e3c: 6023 str r3, [r4, #0]
e3e: 441c add r4, r3
e40: 6025 str r5, [r4, #0]
e42: e004 b.n e4e <_malloc_r+0x72>
e44: 6863 ldr r3, [r4, #4]
e46: 42a2 cmp r2, r4
e48: bf0c ite eq
e4a: 600b streq r3, [r1, #0]
e4c: 6053 strne r3, [r2, #4]
e4e: 4630 mov r0, r6
e50: f000 fb8e bl 1570 <__malloc_unlock>
e54: f104 000b add.w r0, r4, #11
e58: 1d23 adds r3, r4, #4
e5a: f020 0007 bic.w r0, r0, #7
e5e: 1ac2 subs r2, r0, r3
e60: d0cc beq.n dfc <_malloc_r+0x20>
e62: 1a1b subs r3, r3, r0
e64: 50a3 str r3, [r4, r2]
e66: e7c9 b.n dfc <_malloc_r+0x20>
e68: 4622 mov r2, r4
e6a: 6864 ldr r4, [r4, #4]
e6c: e7cc b.n e08 <_malloc_r+0x2c>
e6e: 1cc4 adds r4, r0, #3
e70: f024 0403 bic.w r4, r4, #3
e74: 42a0 cmp r0, r4
e76: d0e3 beq.n e40 <_malloc_r+0x64>
e78: 1a21 subs r1, r4, r0
e7a: 4630 mov r0, r6
e7c: f000 faf8 bl 1470 <_sbrk_r>
e80: 3001 adds r0, #1
e82: d1dd bne.n e40 <_malloc_r+0x64>
e84: e7cf b.n e26 <_malloc_r+0x4a>
e86: bf00 nop
e88: 200000c0 .word 0x200000c0
e8c: 200000c4 .word 0x200000c4
00000e90 <__ssputs_r>:
e90: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
e94: 688e ldr r6, [r1, #8]
e96: 429e cmp r6, r3
e98: 4682 mov sl, r0
e9a: 460c mov r4, r1
e9c: 4690 mov r8, r2
e9e: 461f mov r7, r3
ea0: d838 bhi.n f14 <__ssputs_r+0x84>
ea2: 898a ldrh r2, [r1, #12]
ea4: f412 6f90 tst.w r2, #1152 ; 0x480
ea8: d032 beq.n f10 <__ssputs_r+0x80>
eaa: 6825 ldr r5, [r4, #0]
eac: 6909 ldr r1, [r1, #16]
eae: eba5 0901 sub.w r9, r5, r1
eb2: 6965 ldr r5, [r4, #20]
eb4: eb05 0545 add.w r5, r5, r5, lsl #1
eb8: eb05 75d5 add.w r5, r5, r5, lsr #31
ebc: 3301 adds r3, #1
ebe: 444b add r3, r9
ec0: 106d asrs r5, r5, #1
ec2: 429d cmp r5, r3
ec4: bf38 it cc
ec6: 461d movcc r5, r3
ec8: 0553 lsls r3, r2, #21
eca: d531 bpl.n f30 <__ssputs_r+0xa0>
ecc: 4629 mov r1, r5
ece: f7ff ff85 bl ddc <_malloc_r>
ed2: 4606 mov r6, r0
ed4: b950 cbnz r0, eec <__ssputs_r+0x5c>
ed6: 230c movs r3, #12
ed8: f8ca 3000 str.w r3, [sl]
edc: 89a3 ldrh r3, [r4, #12]
ede: f043 0340 orr.w r3, r3, #64 ; 0x40
ee2: 81a3 strh r3, [r4, #12]
ee4: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
ee8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
eec: 6921 ldr r1, [r4, #16]
eee: 464a mov r2, r9
ef0: f7ff ff34 bl d5c <memcpy>
ef4: 89a3 ldrh r3, [r4, #12]
ef6: f423 6390 bic.w r3, r3, #1152 ; 0x480
efa: f043 0380 orr.w r3, r3, #128 ; 0x80
efe: 81a3 strh r3, [r4, #12]
f00: 6126 str r6, [r4, #16]
f02: 6165 str r5, [r4, #20]
f04: 444e add r6, r9
f06: eba5 0509 sub.w r5, r5, r9
f0a: 6026 str r6, [r4, #0]
f0c: 60a5 str r5, [r4, #8]
f0e: 463e mov r6, r7
f10: 42be cmp r6, r7
f12: d900 bls.n f16 <__ssputs_r+0x86>
f14: 463e mov r6, r7
f16: 4632 mov r2, r6
f18: 6820 ldr r0, [r4, #0]
f1a: 4641 mov r1, r8
f1c: f000 fb08 bl 1530 <memmove>
f20: 68a3 ldr r3, [r4, #8]
f22: 6822 ldr r2, [r4, #0]
f24: 1b9b subs r3, r3, r6
f26: 4432 add r2, r6
f28: 60a3 str r3, [r4, #8]
f2a: 6022 str r2, [r4, #0]
f2c: 2000 movs r0, #0
f2e: e7db b.n ee8 <__ssputs_r+0x58>
f30: 462a mov r2, r5
f32: f000 fb71 bl 1618 <_realloc_r>
f36: 4606 mov r6, r0
f38: 2800 cmp r0, #0
f3a: d1e1 bne.n f00 <__ssputs_r+0x70>
f3c: 6921 ldr r1, [r4, #16]
f3e: 4650 mov r0, sl
f40: f000 fb1c bl 157c <_free_r>
f44: e7c7 b.n ed6 <__ssputs_r+0x46>
...
00000f48 <_svfiprintf_r>:
f48: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
f4c: 4698 mov r8, r3
f4e: 898b ldrh r3, [r1, #12]
f50: 061b lsls r3, r3, #24
f52: b09d sub sp, #116 ; 0x74
f54: 4607 mov r7, r0
f56: 460d mov r5, r1
f58: 4614 mov r4, r2
f5a: d50e bpl.n f7a <_svfiprintf_r+0x32>
f5c: 690b ldr r3, [r1, #16]
f5e: b963 cbnz r3, f7a <_svfiprintf_r+0x32>
f60: 2140 movs r1, #64 ; 0x40
f62: f7ff ff3b bl ddc <_malloc_r>
f66: 6028 str r0, [r5, #0]
f68: 6128 str r0, [r5, #16]
f6a: b920 cbnz r0, f76 <_svfiprintf_r+0x2e>
f6c: 230c movs r3, #12
f6e: 603b str r3, [r7, #0]
f70: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
f74: e0d1 b.n 111a <_svfiprintf_r+0x1d2>
f76: 2340 movs r3, #64 ; 0x40
f78: 616b str r3, [r5, #20]
f7a: 2300 movs r3, #0
f7c: 9309 str r3, [sp, #36] ; 0x24
f7e: 2320 movs r3, #32
f80: f88d 3029 strb.w r3, [sp, #41] ; 0x29
f84: f8cd 800c str.w r8, [sp, #12]
f88: 2330 movs r3, #48 ; 0x30
f8a: f8df 81a8 ldr.w r8, [pc, #424] ; 1134 <_svfiprintf_r+0x1ec>
f8e: f88d 302a strb.w r3, [sp, #42] ; 0x2a
f92: f04f 0901 mov.w r9, #1
f96: 4623 mov r3, r4
f98: 469a mov sl, r3
f9a: f813 2b01 ldrb.w r2, [r3], #1
f9e: b10a cbz r2, fa4 <_svfiprintf_r+0x5c>
fa0: 2a25 cmp r2, #37 ; 0x25
fa2: d1f9 bne.n f98 <_svfiprintf_r+0x50>
fa4: ebba 0b04 subs.w fp, sl, r4
fa8: d00b beq.n fc2 <_svfiprintf_r+0x7a>
faa: 465b mov r3, fp
fac: 4622 mov r2, r4
fae: 4629 mov r1, r5
fb0: 4638 mov r0, r7
fb2: f7ff ff6d bl e90 <__ssputs_r>
fb6: 3001 adds r0, #1
fb8: f000 80aa beq.w 1110 <_svfiprintf_r+0x1c8>
fbc: 9a09 ldr r2, [sp, #36] ; 0x24
fbe: 445a add r2, fp
fc0: 9209 str r2, [sp, #36] ; 0x24
fc2: f89a 3000 ldrb.w r3, [sl]
fc6: 2b00 cmp r3, #0
fc8: f000 80a2 beq.w 1110 <_svfiprintf_r+0x1c8>
fcc: 2300 movs r3, #0
fce: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
fd2: e9cd 2305 strd r2, r3, [sp, #20]
fd6: f10a 0a01 add.w sl, sl, #1
fda: 9304 str r3, [sp, #16]
fdc: 9307 str r3, [sp, #28]
fde: f88d 3053 strb.w r3, [sp, #83] ; 0x53
fe2: 931a str r3, [sp, #104] ; 0x68
fe4: 4654 mov r4, sl
fe6: 2205 movs r2, #5
fe8: f814 1b01 ldrb.w r1, [r4], #1
fec: 4851 ldr r0, [pc, #324] ; (1134 <_svfiprintf_r+0x1ec>)
fee: f000 fa4f bl 1490 <memchr>
ff2: 9a04 ldr r2, [sp, #16]
ff4: b9d8 cbnz r0, 102e <_svfiprintf_r+0xe6>
ff6: 06d0 lsls r0, r2, #27
ff8: bf44 itt mi
ffa: 2320 movmi r3, #32
ffc: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
1000: 0711 lsls r1, r2, #28
1002: bf44 itt mi
1004: 232b movmi r3, #43 ; 0x2b
1006: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
100a: f89a 3000 ldrb.w r3, [sl]
100e: 2b2a cmp r3, #42 ; 0x2a
1010: d015 beq.n 103e <_svfiprintf_r+0xf6>
1012: 9a07 ldr r2, [sp, #28]
1014: 4654 mov r4, sl
1016: 2000 movs r0, #0
1018: f04f 0c0a mov.w ip, #10
101c: 4621 mov r1, r4
101e: f811 3b01 ldrb.w r3, [r1], #1
1022: 3b30 subs r3, #48 ; 0x30
1024: 2b09 cmp r3, #9
1026: d94e bls.n 10c6 <_svfiprintf_r+0x17e>
1028: b1b0 cbz r0, 1058 <_svfiprintf_r+0x110>
102a: 9207 str r2, [sp, #28]
102c: e014 b.n 1058 <_svfiprintf_r+0x110>
102e: eba0 0308 sub.w r3, r0, r8
1032: fa09 f303 lsl.w r3, r9, r3
1036: 4313 orrs r3, r2
1038: 9304 str r3, [sp, #16]
103a: 46a2 mov sl, r4
103c: e7d2 b.n fe4 <_svfiprintf_r+0x9c>
103e: 9b03 ldr r3, [sp, #12]
1040: 1d19 adds r1, r3, #4
1042: 681b ldr r3, [r3, #0]
1044: 9103 str r1, [sp, #12]
1046: 2b00 cmp r3, #0
1048: bfbb ittet lt
104a: 425b neglt r3, r3
104c: f042 0202 orrlt.w r2, r2, #2
1050: 9307 strge r3, [sp, #28]
1052: 9307 strlt r3, [sp, #28]
1054: bfb8 it lt
1056: 9204 strlt r2, [sp, #16]
1058: 7823 ldrb r3, [r4, #0]
105a: 2b2e cmp r3, #46 ; 0x2e
105c: d10c bne.n 1078 <_svfiprintf_r+0x130>
105e: 7863 ldrb r3, [r4, #1]
1060: 2b2a cmp r3, #42 ; 0x2a
1062: d135 bne.n 10d0 <_svfiprintf_r+0x188>
1064: 9b03 ldr r3, [sp, #12]
1066: 1d1a adds r2, r3, #4
1068: 681b ldr r3, [r3, #0]
106a: 9203 str r2, [sp, #12]
106c: 2b00 cmp r3, #0
106e: bfb8 it lt
1070: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff
1074: 3402 adds r4, #2
1076: 9305 str r3, [sp, #20]
1078: f8df a0c8 ldr.w sl, [pc, #200] ; 1144 <_svfiprintf_r+0x1fc>
107c: 7821 ldrb r1, [r4, #0]
107e: 2203 movs r2, #3
1080: 4650 mov r0, sl
1082: f000 fa05 bl 1490 <memchr>
1086: b140 cbz r0, 109a <_svfiprintf_r+0x152>
1088: 2340 movs r3, #64 ; 0x40
108a: eba0 000a sub.w r0, r0, sl
108e: fa03 f000 lsl.w r0, r3, r0
1092: 9b04 ldr r3, [sp, #16]
1094: 4303 orrs r3, r0
1096: 3401 adds r4, #1
1098: 9304 str r3, [sp, #16]
109a: f814 1b01 ldrb.w r1, [r4], #1
109e: 4826 ldr r0, [pc, #152] ; (1138 <_svfiprintf_r+0x1f0>)
10a0: f88d 1028 strb.w r1, [sp, #40] ; 0x28
10a4: 2206 movs r2, #6
10a6: f000 f9f3 bl 1490 <memchr>
10aa: 2800 cmp r0, #0
10ac: d038 beq.n 1120 <_svfiprintf_r+0x1d8>
10ae: 4b23 ldr r3, [pc, #140] ; (113c <_svfiprintf_r+0x1f4>)
10b0: bb1b cbnz r3, 10fa <_svfiprintf_r+0x1b2>
10b2: 9b03 ldr r3, [sp, #12]
10b4: 3307 adds r3, #7
10b6: f023 0307 bic.w r3, r3, #7
10ba: 3308 adds r3, #8
10bc: 9303 str r3, [sp, #12]
10be: 9b09 ldr r3, [sp, #36] ; 0x24
10c0: 4433 add r3, r6
10c2: 9309 str r3, [sp, #36] ; 0x24
10c4: e767 b.n f96 <_svfiprintf_r+0x4e>
10c6: fb0c 3202 mla r2, ip, r2, r3
10ca: 460c mov r4, r1
10cc: 2001 movs r0, #1
10ce: e7a5 b.n 101c <_svfiprintf_r+0xd4>
10d0: 2300 movs r3, #0
10d2: 3401 adds r4, #1
10d4: 9305 str r3, [sp, #20]
10d6: 4619 mov r1, r3
10d8: f04f 0c0a mov.w ip, #10
10dc: 4620 mov r0, r4
10de: f810 2b01 ldrb.w r2, [r0], #1
10e2: 3a30 subs r2, #48 ; 0x30
10e4: 2a09 cmp r2, #9
10e6: d903 bls.n 10f0 <_svfiprintf_r+0x1a8>
10e8: 2b00 cmp r3, #0
10ea: d0c5 beq.n 1078 <_svfiprintf_r+0x130>
10ec: 9105 str r1, [sp, #20]
10ee: e7c3 b.n 1078 <_svfiprintf_r+0x130>
10f0: fb0c 2101 mla r1, ip, r1, r2
10f4: 4604 mov r4, r0
10f6: 2301 movs r3, #1
10f8: e7f0 b.n 10dc <_svfiprintf_r+0x194>
10fa: ab03 add r3, sp, #12
10fc: 9300 str r3, [sp, #0]
10fe: 462a mov r2, r5
1100: 4b0f ldr r3, [pc, #60] ; (1140 <_svfiprintf_r+0x1f8>)
1102: a904 add r1, sp, #16
1104: 4638 mov r0, r7
1106: f3af 8000 nop.w
110a: 1c42 adds r2, r0, #1
110c: 4606 mov r6, r0
110e: d1d6 bne.n 10be <_svfiprintf_r+0x176>
1110: 89ab ldrh r3, [r5, #12]
1112: 065b lsls r3, r3, #25
1114: f53f af2c bmi.w f70 <_svfiprintf_r+0x28>
1118: 9809 ldr r0, [sp, #36] ; 0x24
111a: b01d add sp, #116 ; 0x74
111c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
1120: ab03 add r3, sp, #12
1122: 9300 str r3, [sp, #0]
1124: 462a mov r2, r5
1126: 4b06 ldr r3, [pc, #24] ; (1140 <_svfiprintf_r+0x1f8>)
1128: a904 add r1, sp, #16
112a: 4638 mov r0, r7
112c: f000 f87a bl 1224 <_printf_i>
1130: e7eb b.n 110a <_svfiprintf_r+0x1c2>
1132: bf00 nop
1134: 000017c0 .word 0x000017c0
1138: 000017ca .word 0x000017ca
113c: 00000000 .word 0x00000000
1140: 00000e91 .word 0x00000e91
1144: 000017c6 .word 0x000017c6
00001148 <_printf_common>:
1148: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
114c: 4616 mov r6, r2
114e: 4699 mov r9, r3
1150: 688a ldr r2, [r1, #8]
1152: 690b ldr r3, [r1, #16]
1154: f8dd 8020 ldr.w r8, [sp, #32]
1158: 4293 cmp r3, r2
115a: bfb8 it lt
115c: 4613 movlt r3, r2
115e: 6033 str r3, [r6, #0]
1160: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
1164: 4607 mov r7, r0
1166: 460c mov r4, r1
1168: b10a cbz r2, 116e <_printf_common+0x26>
116a: 3301 adds r3, #1
116c: 6033 str r3, [r6, #0]
116e: 6823 ldr r3, [r4, #0]
1170: 0699 lsls r1, r3, #26
1172: bf42 ittt mi
1174: 6833 ldrmi r3, [r6, #0]
1176: 3302 addmi r3, #2
1178: 6033 strmi r3, [r6, #0]
117a: 6825 ldr r5, [r4, #0]
117c: f015 0506 ands.w r5, r5, #6
1180: d106 bne.n 1190 <_printf_common+0x48>
1182: f104 0a19 add.w sl, r4, #25
1186: 68e3 ldr r3, [r4, #12]
1188: 6832 ldr r2, [r6, #0]
118a: 1a9b subs r3, r3, r2
118c: 42ab cmp r3, r5
118e: dc26 bgt.n 11de <_printf_common+0x96>
1190: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
1194: 1e13 subs r3, r2, #0
1196: 6822 ldr r2, [r4, #0]
1198: bf18 it ne
119a: 2301 movne r3, #1
119c: 0692 lsls r2, r2, #26
119e: d42b bmi.n 11f8 <_printf_common+0xb0>
11a0: f104 0243 add.w r2, r4, #67 ; 0x43
11a4: 4649 mov r1, r9
11a6: 4638 mov r0, r7
11a8: 47c0 blx r8
11aa: 3001 adds r0, #1
11ac: d01e beq.n 11ec <_printf_common+0xa4>
11ae: 6823 ldr r3, [r4, #0]
11b0: 68e5 ldr r5, [r4, #12]
11b2: 6832 ldr r2, [r6, #0]
11b4: f003 0306 and.w r3, r3, #6
11b8: 2b04 cmp r3, #4
11ba: bf08 it eq
11bc: 1aad subeq r5, r5, r2
11be: 68a3 ldr r3, [r4, #8]
11c0: 6922 ldr r2, [r4, #16]
11c2: bf0c ite eq
11c4: ea25 75e5 biceq.w r5, r5, r5, asr #31
11c8: 2500 movne r5, #0
11ca: 4293 cmp r3, r2
11cc: bfc4 itt gt
11ce: 1a9b subgt r3, r3, r2
11d0: 18ed addgt r5, r5, r3
11d2: 2600 movs r6, #0
11d4: 341a adds r4, #26
11d6: 42b5 cmp r5, r6
11d8: d11a bne.n 1210 <_printf_common+0xc8>
11da: 2000 movs r0, #0
11dc: e008 b.n 11f0 <_printf_common+0xa8>
11de: 2301 movs r3, #1
11e0: 4652 mov r2, sl
11e2: 4649 mov r1, r9
11e4: 4638 mov r0, r7
11e6: 47c0 blx r8
11e8: 3001 adds r0, #1
11ea: d103 bne.n 11f4 <_printf_common+0xac>
11ec: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
11f0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
11f4: 3501 adds r5, #1
11f6: e7c6 b.n 1186 <_printf_common+0x3e>
11f8: 18e1 adds r1, r4, r3
11fa: 1c5a adds r2, r3, #1
11fc: 2030 movs r0, #48 ; 0x30
11fe: f881 0043 strb.w r0, [r1, #67] ; 0x43
1202: 4422 add r2, r4
1204: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
1208: f882 1043 strb.w r1, [r2, #67] ; 0x43
120c: 3302 adds r3, #2
120e: e7c7 b.n 11a0 <_printf_common+0x58>
1210: 2301 movs r3, #1
1212: 4622 mov r2, r4
1214: 4649 mov r1, r9
1216: 4638 mov r0, r7
1218: 47c0 blx r8
121a: 3001 adds r0, #1
121c: d0e6 beq.n 11ec <_printf_common+0xa4>
121e: 3601 adds r6, #1
1220: e7d9 b.n 11d6 <_printf_common+0x8e>
...
00001224 <_printf_i>:
1224: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
1228: 460c mov r4, r1
122a: 4691 mov r9, r2
122c: 7e27 ldrb r7, [r4, #24]
122e: 990c ldr r1, [sp, #48] ; 0x30
1230: 2f78 cmp r7, #120 ; 0x78
1232: 4680 mov r8, r0
1234: 469a mov sl, r3
1236: f104 0243 add.w r2, r4, #67 ; 0x43
123a: d807 bhi.n 124c <_printf_i+0x28>
123c: 2f62 cmp r7, #98 ; 0x62
123e: d80a bhi.n 1256 <_printf_i+0x32>
1240: 2f00 cmp r7, #0
1242: f000 80d8 beq.w 13f6 <_printf_i+0x1d2>
1246: 2f58 cmp r7, #88 ; 0x58
1248: f000 80a3 beq.w 1392 <_printf_i+0x16e>
124c: f104 0642 add.w r6, r4, #66 ; 0x42
1250: f884 7042 strb.w r7, [r4, #66] ; 0x42
1254: e03a b.n 12cc <_printf_i+0xa8>
1256: f1a7 0363 sub.w r3, r7, #99 ; 0x63
125a: 2b15 cmp r3, #21
125c: d8f6 bhi.n 124c <_printf_i+0x28>
125e: a001 add r0, pc, #4 ; (adr r0, 1264 <_printf_i+0x40>)
1260: f850 f023 ldr.w pc, [r0, r3, lsl #2]
1264: 000012bd .word 0x000012bd
1268: 000012d1 .word 0x000012d1
126c: 0000124d .word 0x0000124d
1270: 0000124d .word 0x0000124d
1274: 0000124d .word 0x0000124d
1278: 0000124d .word 0x0000124d
127c: 000012d1 .word 0x000012d1
1280: 0000124d .word 0x0000124d
1284: 0000124d .word 0x0000124d
1288: 0000124d .word 0x0000124d
128c: 0000124d .word 0x0000124d
1290: 000013dd .word 0x000013dd
1294: 00001301 .word 0x00001301
1298: 000013bf .word 0x000013bf
129c: 0000124d .word 0x0000124d
12a0: 0000124d .word 0x0000124d
12a4: 000013ff .word 0x000013ff
12a8: 0000124d .word 0x0000124d
12ac: 00001301 .word 0x00001301
12b0: 0000124d .word 0x0000124d
12b4: 0000124d .word 0x0000124d
12b8: 000013c7 .word 0x000013c7
12bc: 680b ldr r3, [r1, #0]
12be: 1d1a adds r2, r3, #4
12c0: 681b ldr r3, [r3, #0]
12c2: 600a str r2, [r1, #0]
12c4: f104 0642 add.w r6, r4, #66 ; 0x42
12c8: f884 3042 strb.w r3, [r4, #66] ; 0x42
12cc: 2301 movs r3, #1
12ce: e0a3 b.n 1418 <_printf_i+0x1f4>
12d0: 6825 ldr r5, [r4, #0]
12d2: 6808 ldr r0, [r1, #0]
12d4: 062e lsls r6, r5, #24
12d6: f100 0304 add.w r3, r0, #4
12da: d50a bpl.n 12f2 <_printf_i+0xce>
12dc: 6805 ldr r5, [r0, #0]
12de: 600b str r3, [r1, #0]
12e0: 2d00 cmp r5, #0
12e2: da03 bge.n 12ec <_printf_i+0xc8>
12e4: 232d movs r3, #45 ; 0x2d
12e6: 426d negs r5, r5
12e8: f884 3043 strb.w r3, [r4, #67] ; 0x43
12ec: 485e ldr r0, [pc, #376] ; (1468 <_printf_i+0x244>)
12ee: 230a movs r3, #10
12f0: e019 b.n 1326 <_printf_i+0x102>
12f2: f015 0f40 tst.w r5, #64 ; 0x40
12f6: 6805 ldr r5, [r0, #0]
12f8: 600b str r3, [r1, #0]
12fa: bf18 it ne
12fc: b22d sxthne r5, r5
12fe: e7ef b.n 12e0 <_printf_i+0xbc>
1300: 680b ldr r3, [r1, #0]
1302: 6825 ldr r5, [r4, #0]
1304: 1d18 adds r0, r3, #4
1306: 6008 str r0, [r1, #0]
1308: 0628 lsls r0, r5, #24
130a: d501 bpl.n 1310 <_printf_i+0xec>
130c: 681d ldr r5, [r3, #0]
130e: e002 b.n 1316 <_printf_i+0xf2>
1310: 0669 lsls r1, r5, #25
1312: d5fb bpl.n 130c <_printf_i+0xe8>
1314: 881d ldrh r5, [r3, #0]
1316: 4854 ldr r0, [pc, #336] ; (1468 <_printf_i+0x244>)
1318: 2f6f cmp r7, #111 ; 0x6f
131a: bf0c ite eq
131c: 2308 moveq r3, #8
131e: 230a movne r3, #10
1320: 2100 movs r1, #0
1322: f884 1043 strb.w r1, [r4, #67] ; 0x43
1326: 6866 ldr r6, [r4, #4]
1328: 60a6 str r6, [r4, #8]
132a: 2e00 cmp r6, #0
132c: bfa2 ittt ge
132e: 6821 ldrge r1, [r4, #0]
1330: f021 0104 bicge.w r1, r1, #4
1334: 6021 strge r1, [r4, #0]
1336: b90d cbnz r5, 133c <_printf_i+0x118>
1338: 2e00 cmp r6, #0
133a: d04d beq.n 13d8 <_printf_i+0x1b4>
133c: 4616 mov r6, r2
133e: fbb5 f1f3 udiv r1, r5, r3
1342: fb03 5711 mls r7, r3, r1, r5
1346: 5dc7 ldrb r7, [r0, r7]
1348: f806 7d01 strb.w r7, [r6, #-1]!
134c: 462f mov r7, r5
134e: 42bb cmp r3, r7
1350: 460d mov r5, r1
1352: d9f4 bls.n 133e <_printf_i+0x11a>
1354: 2b08 cmp r3, #8
1356: d10b bne.n 1370 <_printf_i+0x14c>
1358: 6823 ldr r3, [r4, #0]
135a: 07df lsls r7, r3, #31
135c: d508 bpl.n 1370 <_printf_i+0x14c>
135e: 6923 ldr r3, [r4, #16]
1360: 6861 ldr r1, [r4, #4]
1362: 4299 cmp r1, r3
1364: bfde ittt le
1366: 2330 movle r3, #48 ; 0x30
1368: f806 3c01 strble.w r3, [r6, #-1]
136c: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff
1370: 1b92 subs r2, r2, r6
1372: 6122 str r2, [r4, #16]
1374: f8cd a000 str.w sl, [sp]
1378: 464b mov r3, r9
137a: aa03 add r2, sp, #12
137c: 4621 mov r1, r4
137e: 4640 mov r0, r8
1380: f7ff fee2 bl 1148 <_printf_common>
1384: 3001 adds r0, #1
1386: d14c bne.n 1422 <_printf_i+0x1fe>
1388: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
138c: b004 add sp, #16
138e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
1392: 4835 ldr r0, [pc, #212] ; (1468 <_printf_i+0x244>)
1394: f884 7045 strb.w r7, [r4, #69] ; 0x45
1398: 6823 ldr r3, [r4, #0]
139a: 680e ldr r6, [r1, #0]
139c: 061f lsls r7, r3, #24
139e: f856 5b04 ldr.w r5, [r6], #4
13a2: 600e str r6, [r1, #0]
13a4: d514 bpl.n 13d0 <_printf_i+0x1ac>
13a6: 07d9 lsls r1, r3, #31
13a8: bf44 itt mi
13aa: f043 0320 orrmi.w r3, r3, #32
13ae: 6023 strmi r3, [r4, #0]
13b0: b91d cbnz r5, 13ba <_printf_i+0x196>
13b2: 6823 ldr r3, [r4, #0]
13b4: f023 0320 bic.w r3, r3, #32
13b8: 6023 str r3, [r4, #0]
13ba: 2310 movs r3, #16
13bc: e7b0 b.n 1320 <_printf_i+0xfc>
13be: 6823 ldr r3, [r4, #0]
13c0: f043 0320 orr.w r3, r3, #32
13c4: 6023 str r3, [r4, #0]
13c6: 2378 movs r3, #120 ; 0x78
13c8: 4828 ldr r0, [pc, #160] ; (146c <_printf_i+0x248>)
13ca: f884 3045 strb.w r3, [r4, #69] ; 0x45
13ce: e7e3 b.n 1398 <_printf_i+0x174>
13d0: 065e lsls r6, r3, #25
13d2: bf48 it mi
13d4: b2ad uxthmi r5, r5
13d6: e7e6 b.n 13a6 <_printf_i+0x182>
13d8: 4616 mov r6, r2
13da: e7bb b.n 1354 <_printf_i+0x130>
13dc: 680b ldr r3, [r1, #0]
13de: 6826 ldr r6, [r4, #0]
13e0: 6960 ldr r0, [r4, #20]
13e2: 1d1d adds r5, r3, #4
13e4: 600d str r5, [r1, #0]
13e6: 0635 lsls r5, r6, #24
13e8: 681b ldr r3, [r3, #0]
13ea: d501 bpl.n 13f0 <_printf_i+0x1cc>
13ec: 6018 str r0, [r3, #0]
13ee: e002 b.n 13f6 <_printf_i+0x1d2>
13f0: 0671 lsls r1, r6, #25
13f2: d5fb bpl.n 13ec <_printf_i+0x1c8>
13f4: 8018 strh r0, [r3, #0]
13f6: 2300 movs r3, #0
13f8: 6123 str r3, [r4, #16]
13fa: 4616 mov r6, r2
13fc: e7ba b.n 1374 <_printf_i+0x150>
13fe: 680b ldr r3, [r1, #0]
1400: 1d1a adds r2, r3, #4
1402: 600a str r2, [r1, #0]
1404: 681e ldr r6, [r3, #0]
1406: 6862 ldr r2, [r4, #4]
1408: 2100 movs r1, #0
140a: 4630 mov r0, r6
140c: f000 f840 bl 1490 <memchr>
1410: b108 cbz r0, 1416 <_printf_i+0x1f2>
1412: 1b80 subs r0, r0, r6
1414: 6060 str r0, [r4, #4]
1416: 6863 ldr r3, [r4, #4]
1418: 6123 str r3, [r4, #16]
141a: 2300 movs r3, #0
141c: f884 3043 strb.w r3, [r4, #67] ; 0x43
1420: e7a8 b.n 1374 <_printf_i+0x150>
1422: 6923 ldr r3, [r4, #16]
1424: 4632 mov r2, r6
1426: 4649 mov r1, r9
1428: 4640 mov r0, r8
142a: 47d0 blx sl
142c: 3001 adds r0, #1
142e: d0ab beq.n 1388 <_printf_i+0x164>
1430: 6823 ldr r3, [r4, #0]
1432: 079b lsls r3, r3, #30
1434: d413 bmi.n 145e <_printf_i+0x23a>
1436: 68e0 ldr r0, [r4, #12]
1438: 9b03 ldr r3, [sp, #12]
143a: 4298 cmp r0, r3
143c: bfb8 it lt
143e: 4618 movlt r0, r3
1440: e7a4 b.n 138c <_printf_i+0x168>
1442: 2301 movs r3, #1
1444: 4632 mov r2, r6
1446: 4649 mov r1, r9
1448: 4640 mov r0, r8
144a: 47d0 blx sl
144c: 3001 adds r0, #1
144e: d09b beq.n 1388 <_printf_i+0x164>
1450: 3501 adds r5, #1
1452: 68e3 ldr r3, [r4, #12]
1454: 9903 ldr r1, [sp, #12]
1456: 1a5b subs r3, r3, r1
1458: 42ab cmp r3, r5
145a: dcf2 bgt.n 1442 <_printf_i+0x21e>
145c: e7eb b.n 1436 <_printf_i+0x212>
145e: 2500 movs r5, #0
1460: f104 0619 add.w r6, r4, #25
1464: e7f5 b.n 1452 <_printf_i+0x22e>
1466: bf00 nop
1468: 000017d1 .word 0x000017d1
146c: 000017e2 .word 0x000017e2
00001470 <_sbrk_r>:
1470: b538 push {r3, r4, r5, lr}
1472: 4d06 ldr r5, [pc, #24] ; (148c <_sbrk_r+0x1c>)
1474: 2300 movs r3, #0
1476: 4604 mov r4, r0
1478: 4608 mov r0, r1
147a: 602b str r3, [r5, #0]
147c: f7fe ff32 bl 2e4 <_sbrk>
1480: 1c43 adds r3, r0, #1
1482: d102 bne.n 148a <_sbrk_r+0x1a>
1484: 682b ldr r3, [r5, #0]
1486: b103 cbz r3, 148a <_sbrk_r+0x1a>
1488: 6023 str r3, [r4, #0]
148a: bd38 pop {r3, r4, r5, pc}
148c: 200000d4 .word 0x200000d4
00001490 <memchr>:
1490: f001 01ff and.w r1, r1, #255 ; 0xff
1494: 2a10 cmp r2, #16
1496: db2b blt.n 14f0 <memchr+0x60>
1498: f010 0f07 tst.w r0, #7
149c: d008 beq.n 14b0 <memchr+0x20>
149e: f810 3b01 ldrb.w r3, [r0], #1
14a2: 3a01 subs r2, #1
14a4: 428b cmp r3, r1
14a6: d02d beq.n 1504 <memchr+0x74>
14a8: f010 0f07 tst.w r0, #7
14ac: b342 cbz r2, 1500 <memchr+0x70>
14ae: d1f6 bne.n 149e <memchr+0xe>
14b0: b4f0 push {r4, r5, r6, r7}
14b2: ea41 2101 orr.w r1, r1, r1, lsl #8
14b6: ea41 4101 orr.w r1, r1, r1, lsl #16
14ba: f022 0407 bic.w r4, r2, #7
14be: f07f 0700 mvns.w r7, #0
14c2: 2300 movs r3, #0
14c4: e8f0 5602 ldrd r5, r6, [r0], #8
14c8: 3c08 subs r4, #8
14ca: ea85 0501 eor.w r5, r5, r1
14ce: ea86 0601 eor.w r6, r6, r1
14d2: fa85 f547 uadd8 r5, r5, r7
14d6: faa3 f587 sel r5, r3, r7
14da: fa86 f647 uadd8 r6, r6, r7
14de: faa5 f687 sel r6, r5, r7
14e2: b98e cbnz r6, 1508 <memchr+0x78>
14e4: d1ee bne.n 14c4 <memchr+0x34>
14e6: bcf0 pop {r4, r5, r6, r7}
14e8: f001 01ff and.w r1, r1, #255 ; 0xff
14ec: f002 0207 and.w r2, r2, #7
14f0: b132 cbz r2, 1500 <memchr+0x70>
14f2: f810 3b01 ldrb.w r3, [r0], #1
14f6: 3a01 subs r2, #1
14f8: ea83 0301 eor.w r3, r3, r1
14fc: b113 cbz r3, 1504 <memchr+0x74>
14fe: d1f8 bne.n 14f2 <memchr+0x62>
1500: 2000 movs r0, #0
1502: 4770 bx lr
1504: 3801 subs r0, #1
1506: 4770 bx lr
1508: 2d00 cmp r5, #0
150a: bf06 itte eq
150c: 4635 moveq r5, r6
150e: 3803 subeq r0, #3
1510: 3807 subne r0, #7
1512: f015 0f01 tst.w r5, #1
1516: d107 bne.n 1528 <memchr+0x98>
1518: 3001 adds r0, #1
151a: f415 7f80 tst.w r5, #256 ; 0x100
151e: bf02 ittt eq
1520: 3001 addeq r0, #1
1522: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
1526: 3001 addeq r0, #1
1528: bcf0 pop {r4, r5, r6, r7}
152a: 3801 subs r0, #1
152c: 4770 bx lr
152e: bf00 nop
00001530 <memmove>:
1530: 4288 cmp r0, r1
1532: b510 push {r4, lr}
1534: eb01 0402 add.w r4, r1, r2
1538: d902 bls.n 1540 <memmove+0x10>
153a: 4284 cmp r4, r0
153c: 4623 mov r3, r4
153e: d807 bhi.n 1550 <memmove+0x20>
1540: 1e43 subs r3, r0, #1
1542: 42a1 cmp r1, r4
1544: d008 beq.n 1558 <memmove+0x28>
1546: f811 2b01 ldrb.w r2, [r1], #1
154a: f803 2f01 strb.w r2, [r3, #1]!
154e: e7f8 b.n 1542 <memmove+0x12>
1550: 4402 add r2, r0
1552: 4601 mov r1, r0
1554: 428a cmp r2, r1
1556: d100 bne.n 155a <memmove+0x2a>
1558: bd10 pop {r4, pc}
155a: f813 4d01 ldrb.w r4, [r3, #-1]!
155e: f802 4d01 strb.w r4, [r2, #-1]!
1562: e7f7 b.n 1554 <memmove+0x24>
00001564 <__malloc_lock>:
1564: 4801 ldr r0, [pc, #4] ; (156c <__malloc_lock+0x8>)
1566: f7ff bc37 b.w dd8 <__retarget_lock_acquire_recursive>
156a: bf00 nop
156c: 200000cc .word 0x200000cc
00001570 <__malloc_unlock>:
1570: 4801 ldr r0, [pc, #4] ; (1578 <__malloc_unlock+0x8>)
1572: f7ff bc32 b.w dda <__retarget_lock_release_recursive>
1576: bf00 nop
1578: 200000cc .word 0x200000cc
0000157c <_free_r>:
157c: b538 push {r3, r4, r5, lr}
157e: 4605 mov r5, r0
1580: 2900 cmp r1, #0
1582: d045 beq.n 1610 <_free_r+0x94>
1584: f851 3c04 ldr.w r3, [r1, #-4]
1588: 1f0c subs r4, r1, #4
158a: 2b00 cmp r3, #0
158c: bfb8 it lt
158e: 18e4 addlt r4, r4, r3
1590: f7ff ffe8 bl 1564 <__malloc_lock>
1594: 4a1f ldr r2, [pc, #124] ; (1614 <_free_r+0x98>)
1596: 6813 ldr r3, [r2, #0]
1598: 4610 mov r0, r2
159a: b933 cbnz r3, 15aa <_free_r+0x2e>
159c: 6063 str r3, [r4, #4]
159e: 6014 str r4, [r2, #0]
15a0: 4628 mov r0, r5
15a2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
15a6: f7ff bfe3 b.w 1570 <__malloc_unlock>
15aa: 42a3 cmp r3, r4
15ac: d90b bls.n 15c6 <_free_r+0x4a>
15ae: 6821 ldr r1, [r4, #0]
15b0: 1862 adds r2, r4, r1
15b2: 4293 cmp r3, r2
15b4: bf04 itt eq
15b6: 681a ldreq r2, [r3, #0]
15b8: 685b ldreq r3, [r3, #4]
15ba: 6063 str r3, [r4, #4]
15bc: bf04 itt eq
15be: 1852 addeq r2, r2, r1
15c0: 6022 streq r2, [r4, #0]
15c2: 6004 str r4, [r0, #0]
15c4: e7ec b.n 15a0 <_free_r+0x24>
15c6: 461a mov r2, r3
15c8: 685b ldr r3, [r3, #4]
15ca: b10b cbz r3, 15d0 <_free_r+0x54>
15cc: 42a3 cmp r3, r4
15ce: d9fa bls.n 15c6 <_free_r+0x4a>
15d0: 6811 ldr r1, [r2, #0]
15d2: 1850 adds r0, r2, r1
15d4: 42a0 cmp r0, r4
15d6: d10b bne.n 15f0 <_free_r+0x74>
15d8: 6820 ldr r0, [r4, #0]
15da: 4401 add r1, r0
15dc: 1850 adds r0, r2, r1
15de: 4283 cmp r3, r0
15e0: 6011 str r1, [r2, #0]
15e2: d1dd bne.n 15a0 <_free_r+0x24>
15e4: 6818 ldr r0, [r3, #0]
15e6: 685b ldr r3, [r3, #4]
15e8: 6053 str r3, [r2, #4]
15ea: 4401 add r1, r0
15ec: 6011 str r1, [r2, #0]
15ee: e7d7 b.n 15a0 <_free_r+0x24>
15f0: d902 bls.n 15f8 <_free_r+0x7c>
15f2: 230c movs r3, #12
15f4: 602b str r3, [r5, #0]
15f6: e7d3 b.n 15a0 <_free_r+0x24>
15f8: 6820 ldr r0, [r4, #0]
15fa: 1821 adds r1, r4, r0
15fc: 428b cmp r3, r1
15fe: bf04 itt eq
1600: 6819 ldreq r1, [r3, #0]
1602: 685b ldreq r3, [r3, #4]
1604: 6063 str r3, [r4, #4]
1606: bf04 itt eq
1608: 1809 addeq r1, r1, r0
160a: 6021 streq r1, [r4, #0]
160c: 6054 str r4, [r2, #4]
160e: e7c7 b.n 15a0 <_free_r+0x24>
1610: bd38 pop {r3, r4, r5, pc}
1612: bf00 nop
1614: 200000c0 .word 0x200000c0
00001618 <_realloc_r>:
1618: b5f8 push {r3, r4, r5, r6, r7, lr}
161a: 4607 mov r7, r0
161c: 4614 mov r4, r2
161e: 460e mov r6, r1
1620: b921 cbnz r1, 162c <_realloc_r+0x14>
1622: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
1626: 4611 mov r1, r2
1628: f7ff bbd8 b.w ddc <_malloc_r>
162c: b922 cbnz r2, 1638 <_realloc_r+0x20>
162e: f7ff ffa5 bl 157c <_free_r>
1632: 4625 mov r5, r4
1634: 4628 mov r0, r5
1636: bdf8 pop {r3, r4, r5, r6, r7, pc}
1638: f000 f814 bl 1664 <_malloc_usable_size_r>
163c: 42a0 cmp r0, r4
163e: d20f bcs.n 1660 <_realloc_r+0x48>
1640: 4621 mov r1, r4
1642: 4638 mov r0, r7
1644: f7ff fbca bl ddc <_malloc_r>
1648: 4605 mov r5, r0
164a: 2800 cmp r0, #0
164c: d0f2 beq.n 1634 <_realloc_r+0x1c>
164e: 4631 mov r1, r6
1650: 4622 mov r2, r4
1652: f7ff fb83 bl d5c <memcpy>
1656: 4631 mov r1, r6
1658: 4638 mov r0, r7
165a: f7ff ff8f bl 157c <_free_r>
165e: e7e9 b.n 1634 <_realloc_r+0x1c>
1660: 4635 mov r5, r6
1662: e7e7 b.n 1634 <_realloc_r+0x1c>
00001664 <_malloc_usable_size_r>:
1664: f851 3c04 ldr.w r3, [r1, #-4]
1668: 1f18 subs r0, r3, #4
166a: 2b00 cmp r3, #0
166c: bfbc itt lt
166e: 580b ldrlt r3, [r1, r0]
1670: 18c0 addlt r0, r0, r3
1672: 4770 bx lr
1674: 682f2e2e .word 0x682f2e2e
1678: 732f6c61 .word 0x732f6c61
167c: 682f6372 .word 0x682f6372
1680: 695f6c61 .word 0x695f6c61
1684: 00632e6f .word 0x00632e6f
1688: 682f2e2e .word 0x682f2e2e
168c: 732f6c61 .word 0x732f6c61
1690: 682f6372 .word 0x682f6372
1694: 735f6c61 .word 0x735f6c61
1698: 6d5f6970 .word 0x6d5f6970
169c: 6e79735f .word 0x6e79735f
16a0: 00632e63 .word 0x00632e63
16a4: 682f2e2e .word 0x682f2e2e
16a8: 732f6c61 .word 0x732f6c61
16ac: 682f6372 .word 0x682f6372
16b0: 755f6c61 .word 0x755f6c61
16b4: 74726173 .word 0x74726173
16b8: 6e79735f .word 0x6e79735f
16bc: 00632e63 .word 0x00632e63
16c0: 000a6948 .word 0x000a6948
16c4: 682f2e2e .word 0x682f2e2e
16c8: 732f6c70 .word 0x732f6c70
16cc: 6f637265 .word 0x6f637265
16d0: 70682f6d .word 0x70682f6d
16d4: 65735f6c .word 0x65735f6c
16d8: 6d6f6372 .word 0x6d6f6372
16dc: 0000632e .word 0x0000632e
16e0: 40003000 .word 0x40003000
16e4: 40003400 .word 0x40003400
16e8: 41012000 .word 0x41012000
16ec: 41014000 .word 0x41014000
16f0: 43000000 .word 0x43000000
16f4: 43000400 .word 0x43000400
16f8: 43000800 .word 0x43000800
16fc: 43000c00 .word 0x43000c00
00001700 <_i2cms>:
...
00001718 <sercomspi_regs>:
1718: 0030000c 00020000 00000000 01ff00fe ..0.............
1728: 62654404 49206775 6974696e 7a696c61 .Debug Initializ
1738: 000a6465 65737341 46207472 756c6961 ed..Assert Failu
1748: 61206572 696c2074 2520656e 25202c64 re at line %d, %
1758: 25203a73 00000a73 s: %s...
00001760 <__sf_fake_stderr>:
...
00001780 <__sf_fake_stdin>:
...
000017a0 <__sf_fake_stdout>:
...
17c0: 2b302d23 6c680020 6665004c 47464567 #-0+ .hlL.efgEFG
17d0: 32313000 36353433 41393837 45444342 .0123456789ABCDE
17e0: 31300046 35343332 39383736 64636261 F.0123456789abcd
17f0: 00006665 ef..
000017f4 <_init>:
17f4: b5f8 push {r3, r4, r5, r6, r7, lr}
17f6: bf00 nop
17f8: bcf8 pop {r3, r4, r5, r6, r7}
17fa: bc08 pop {r3}
17fc: 469e mov lr, r3
17fe: 4770 bx lr
00001800 <__frame_dummy_init_array_entry>:
1800: 0289 0000 ....
00001804 <_fini>:
1804: b5f8 push {r3, r4, r5, r6, r7, lr}
1806: bf00 nop
1808: bcf8 pop {r3, r4, r5, r6, r7}
180a: bc08 pop {r3}
180c: 469e mov lr, r3
180e: 4770 bx lr
00001810 <__do_global_dtors_aux_fini_array_entry>:
1810: 0265 0000 e...
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