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spi_sd_mmc_e54_lib
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spi_sd_mmc_e54_lib/build/spi_sd_mmc_lib.lss

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spi_sd_mmc_lib.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 000031c0 00000000 00000000 00010000 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 0000006c 20000000 000031c0 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .bkupram 00000000 47000000 47000000 0002006c 2**0
CONTENTS
3 .qspi 00000000 04000000 04000000 0002006c 2**0
CONTENTS
4 .bss 000002fc 20000070 00003230 0002006c 2**3
ALLOC
5 .stack 00010004 2000036c 0000352c 0002006c 2**0
ALLOC
6 .ARM.attributes 0000002e 00000000 00000000 0002006c 2**0
CONTENTS, READONLY
7 .comment 0000001e 00000000 00000000 0002009a 2**0
CONTENTS, READONLY
8 .debug_info 0002b3e2 00000000 00000000 000200b8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
9 .debug_abbrev 00004153 00000000 00000000 0004b49a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
10 .debug_loc 0000d96f 00000000 00000000 0004f5ed 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
11 .debug_aranges 00000e48 00000000 00000000 0005cf5c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
12 .debug_ranges 00001f20 00000000 00000000 0005dda4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_macro 0003942f 00000000 00000000 0005fcc4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_line 0001be9e 00000000 00000000 000990f3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_str 00126de5 00000000 00000000 000b4f91 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_frame 00002d24 00000000 00000000 001dbd78 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
00000000 <exception_table>:
* \brief Delay loop to delay n number of cycles
*/
void _delay_cycles(void *const hw, uint32_t cycles)
{
(void)hw;
uint8_t n = cycles >> 24;
0: 70 03 01 20 55 18 00 00 53 18 00 00 53 18 00 00 p.. U...S...S...
uint32_t buf = cycles;
while (n--) {
10: 53 18 00 00 53 18 00 00 53 18 00 00 00 00 00 00 S...S...S.......
...
SysTick->LOAD = 0xFFFFFF;
2c: 53 18 00 00 53 18 00 00 00 00 00 00 53 18 00 00 S...S.......S...
3c: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
4c: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
5c: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
6c: b5 19 00 00 53 18 00 00 53 18 00 00 53 18 00 00 ....S...S...S...
7c: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
8c: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
9c: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
ac: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
bc: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
cc: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
dc: 53 18 00 00 53 18 00 00 53 18 00 00 00 00 00 00 S...S...S.......
...
f4: 19 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 ....S...S...S...
104: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
114: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
124: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
134: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
144: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
154: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
164: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
174: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
184: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
194: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
1a4: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
1b4: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
1c4: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
1d4: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
1e4: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
1f4: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
204: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
214: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
224: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
234: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
244: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
254: 53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00 S...S...S...S...
00000264 <__do_global_dtors_aux>:
264: b510 push {r4, lr}
266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>)
268: 7823 ldrb r3, [r4, #0]
26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16>
26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>)
26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12>
270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>)
272: f3af 8000 nop.w
276: 2301 movs r3, #1
278: 7023 strb r3, [r4, #0]
27a: bd10 pop {r4, pc}
27c: 20000070 .word 0x20000070
280: 00000000 .word 0x00000000
284: 000031c0 .word 0x000031c0
00000288 <frame_dummy>:
288: b508 push {r3, lr}
28a: 4b03 ldr r3, [pc, #12] ; (298 <frame_dummy+0x10>)
28c: b11b cbz r3, 296 <frame_dummy+0xe>
28e: 4903 ldr r1, [pc, #12] ; (29c <frame_dummy+0x14>)
290: 4803 ldr r0, [pc, #12] ; (2a0 <frame_dummy+0x18>)
292: f3af 8000 nop.w
296: bd08 pop {r3, pc}
298: 00000000 .word 0x00000000
29c: 20000074 .word 0x20000074
2a0: 000031c0 .word 0x000031c0
000002a4 <io_write>:
/**
* \brief I/O write interface
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
2a4: b570 push {r4, r5, r6, lr}
2a6: 460d mov r5, r1
2a8: 4616 mov r6, r2
ASSERT(io_descr && buf);
2aa: 4604 mov r4, r0
2ac: b110 cbz r0, 2b4 <io_write+0x10>
2ae: 1e08 subs r0, r1, #0
2b0: bf18 it ne
2b2: 2001 movne r0, #1
2b4: 4905 ldr r1, [pc, #20] ; (2cc <io_write+0x28>)
2b6: 4b06 ldr r3, [pc, #24] ; (2d0 <io_write+0x2c>)
2b8: 2234 movs r2, #52 ; 0x34
2ba: 4798 blx r3
return io_descr->write(io_descr, buf, length);
2bc: 6823 ldr r3, [r4, #0]
2be: 4632 mov r2, r6
2c0: 4629 mov r1, r5
2c2: 4620 mov r0, r4
}
2c4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return io_descr->write(io_descr, buf, length);
2c8: 4718 bx r3
2ca: bf00 nop
2cc: 00002ae4 .word 0x00002ae4
2d0: 00001605 .word 0x00001605
000002d4 <io_read>:
/**
* \brief I/O read interface
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
{
2d4: b570 push {r4, r5, r6, lr}
2d6: 460d mov r5, r1
2d8: 4616 mov r6, r2
ASSERT(io_descr && buf);
2da: 4604 mov r4, r0
2dc: b110 cbz r0, 2e4 <io_read+0x10>
2de: 1e08 subs r0, r1, #0
2e0: bf18 it ne
2e2: 2001 movne r0, #1
2e4: 4905 ldr r1, [pc, #20] ; (2fc <io_read+0x28>)
2e6: 4b06 ldr r3, [pc, #24] ; (300 <io_read+0x2c>)
2e8: 223d movs r2, #61 ; 0x3d
2ea: 4798 blx r3
return io_descr->read(io_descr, buf, length);
2ec: 6863 ldr r3, [r4, #4]
2ee: 4632 mov r2, r6
2f0: 4629 mov r1, r5
2f2: 4620 mov r0, r4
}
2f4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return io_descr->read(io_descr, buf, length);
2f8: 4718 bx r3
2fa: bf00 nop
2fc: 00002ae4 .word 0x00002ae4
300: 00001605 .word 0x00001605
00000304 <_delay_init>:
304: f04f 23e0 mov.w r3, #3758153728 ; 0xe000e000
308: f06f 427f mvn.w r2, #4278190080 ; 0xff000000
30c: 615a str r2, [r3, #20]
30e: 2205 movs r2, #5
310: 611a str r2, [r3, #16]
312: 4770 bx lr
00000314 <calendar_init>:
}
/** \brief Initialize Calendar
*/
int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
{
314: b538 push {r3, r4, r5, lr}
int32_t ret = 0;
/* Sanity check arguments */
ASSERT(calendar);
316: 4604 mov r4, r0
318: 3800 subs r0, #0
31a: 4b0c ldr r3, [pc, #48] ; (34c <calendar_init+0x38>)
{
31c: 460d mov r5, r1
ASSERT(calendar);
31e: bf18 it ne
320: 2001 movne r0, #1
322: 490b ldr r1, [pc, #44] ; (350 <calendar_init+0x3c>)
324: f44f 72e0 mov.w r2, #448 ; 0x1c0
328: 4798 blx r3
if (calendar->device.hw == hw) {
32a: 6823 ldr r3, [r4, #0]
32c: 42ab cmp r3, r5
32e: d008 beq.n 342 <calendar_init+0x2e>
/* Already initialized with current configuration */
return ERR_NONE;
} else if (calendar->device.hw != NULL) {
330: b94b cbnz r3, 346 <calendar_init+0x32>
/* Initialized with another configuration */
return ERR_ALREADY_INITIALIZED;
}
calendar->device.hw = (void *)hw;
ret = _calendar_init(&calendar->device);
332: 4b08 ldr r3, [pc, #32] ; (354 <calendar_init+0x40>)
calendar->device.hw = (void *)hw;
334: 6025 str r5, [r4, #0]
ret = _calendar_init(&calendar->device);
336: 4620 mov r0, r4
338: 4798 blx r3
calendar->base_year = DEFAULT_BASE_YEAR;
33a: f240 73b2 movw r3, #1970 ; 0x7b2
33e: 61a3 str r3, [r4, #24]
return ret;
}
340: bd38 pop {r3, r4, r5, pc}
return ERR_NONE;
342: 2000 movs r0, #0
344: e7fc b.n 340 <calendar_init+0x2c>
return ERR_ALREADY_INITIALIZED;
346: f06f 0011 mvn.w r0, #17
34a: e7f9 b.n 340 <calendar_init+0x2c>
34c: 00001605 .word 0x00001605
350: 00002af8 .word 0x00002af8
354: 00001939 .word 0x00001939
00000358 <SDMMC_example>:
/*
* Example
*/
void SDMMC_example(void)
{
358: b537 push {r0, r1, r2, r4, r5, lr}
while (SD_MMC_OK != sd_mmc_check(0)) {
35a: 4d13 ldr r5, [pc, #76] ; (3a8 <SDMMC_example+0x50>)
35c: 2000 movs r0, #0
35e: 47a8 blx r5
360: 4604 mov r4, r0
362: 2800 cmp r0, #0
364: d1fa bne.n 35c <SDMMC_example+0x4>
/* Wait card ready. */
}
if (sd_mmc_get_type(0) & (CARD_TYPE_SD | CARD_TYPE_MMC)) {
366: 4d11 ldr r5, [pc, #68] ; (3ac <SDMMC_example+0x54>)
368: 47a8 blx r5
36a: 0782 lsls r2, r0, #30
36c: d00b beq.n 386 <SDMMC_example+0x2e>
/* Read card block 0 */
sd_mmc_init_read_blocks(0, 0, 1);
36e: 4b10 ldr r3, [pc, #64] ; (3b0 <SDMMC_example+0x58>)
370: 2201 movs r2, #1
372: 4621 mov r1, r4
374: 4620 mov r0, r4
376: 4798 blx r3
sd_mmc_start_read_blocks(sd_mmc_block, 1);
378: 4b0e ldr r3, [pc, #56] ; (3b4 <SDMMC_example+0x5c>)
37a: 480f ldr r0, [pc, #60] ; (3b8 <SDMMC_example+0x60>)
37c: 2101 movs r1, #1
37e: 4798 blx r3
sd_mmc_wait_end_of_read_blocks(false);
380: 4b0e ldr r3, [pc, #56] ; (3bc <SDMMC_example+0x64>)
382: 4620 mov r0, r4
384: 4798 blx r3
}
#if (CONF_SDIO_SUPPORT == 1)
if (sd_mmc_get_type(0) & CARD_TYPE_SDIO) {
386: 2000 movs r0, #0
388: 47a8 blx r5
38a: 0743 lsls r3, r0, #29
38c: d509 bpl.n 3a2 <SDMMC_example+0x4a>
/* Read 22 bytes from SDIO Function 0 (CIA) */
sdio_read_extended(0, 0, 0, 1, sd_mmc_block, 22);
38e: 2316 movs r3, #22
390: 2200 movs r2, #0
392: 9301 str r3, [sp, #4]
394: 4b08 ldr r3, [pc, #32] ; (3b8 <SDMMC_example+0x60>)
396: 9300 str r3, [sp, #0]
398: 4c09 ldr r4, [pc, #36] ; (3c0 <SDMMC_example+0x68>)
39a: 2301 movs r3, #1
39c: 4611 mov r1, r2
39e: 4610 mov r0, r2
3a0: 47a0 blx r4
}
#endif
}
3a2: b003 add sp, #12
3a4: bd30 pop {r4, r5, pc}
3a6: bf00 nop
3a8: 00000721 .word 0x00000721
3ac: 00000d09 .word 0x00000d09
3b0: 00000d2d .word 0x00000d2d
3b4: 00000db1 .word 0x00000db1
3b8: 2000008c .word 0x2000008c
3bc: 00000e01 .word 0x00000e01
3c0: 00000e5d .word 0x00000e5d
000003c4 <sd_mmc_stack_init>:
void sd_mmc_stack_init(void)
{
sd_mmc_init(&SPI_SD_MMC, SDMMC_cd, SDMMC_wp);
3c4: 4a02 ldr r2, [pc, #8] ; (3d0 <sd_mmc_stack_init+0xc>)
3c6: 4803 ldr r0, [pc, #12] ; (3d4 <sd_mmc_stack_init+0x10>)
3c8: 4b03 ldr r3, [pc, #12] ; (3d8 <sd_mmc_stack_init+0x14>)
3ca: 1d11 adds r1, r2, #4
3cc: 4718 bx r3
3ce: bf00 nop
3d0: 20000000 .word 0x20000000
3d4: 2000031c .word 0x2000031c
3d8: 00000709 .word 0x00000709
000003dc <_sbrk>:
extern caddr_t _sbrk(int incr)
{
static unsigned char *heap = NULL;
unsigned char * prev_heap;
if (heap == NULL) {
3dc: 4a04 ldr r2, [pc, #16] ; (3f0 <_sbrk+0x14>)
3de: 6811 ldr r1, [r2, #0]
{
3e0: 4603 mov r3, r0
if (heap == NULL) {
3e2: b909 cbnz r1, 3e8 <_sbrk+0xc>
heap = (unsigned char *)&_end;
3e4: 4903 ldr r1, [pc, #12] ; (3f4 <_sbrk+0x18>)
3e6: 6011 str r1, [r2, #0]
}
prev_heap = heap;
3e8: 6810 ldr r0, [r2, #0]
heap += incr;
3ea: 4403 add r3, r0
3ec: 6013 str r3, [r2, #0]
return (caddr_t)prev_heap;
}
3ee: 4770 bx lr
3f0: 2000028c .word 0x2000028c
3f4: 20010370 .word 0x20010370
000003f8 <SDMMC_UNSTUFF_BITS>:
* Used by : CSD, SCR, Switch status
*/
static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint16_t pos, uint8_t size)
{
uint32_t value;
value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
3f8: 1a89 subs r1, r1, r2
{
3fa: b570 push {r4, r5, r6, lr}
value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
3fc: 1dcc adds r4, r1, #7
3fe: bf48 it mi
400: f101 040e addmi.w r4, r1, #14
404: eb00 00e4 add.w r0, r0, r4, asr #3
408: f002 0207 and.w r2, r2, #7
40c: f810 1c01 ldrb.w r1, [r0, #-1]
if (((pos % 8) + size) > 8) {
410: 18d4 adds r4, r2, r3
412: 2c08 cmp r4, #8
value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
414: fa41 f102 asr.w r1, r1, r2
if (((pos % 8) + size) > 8) {
418: dd18 ble.n 44c <SDMMC_UNSTUFF_BITS+0x54>
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
41a: f810 5c02 ldrb.w r5, [r0, #-2]
41e: f1c2 0608 rsb r6, r2, #8
422: 40b5 lsls r5, r6
}
if (((pos % 8) + size) > 16) {
424: 2c10 cmp r4, #16
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
426: ea41 0105 orr.w r1, r1, r5
if (((pos % 8) + size) > 16) {
42a: dd0f ble.n 44c <SDMMC_UNSTUFF_BITS+0x54>
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
42c: f810 0c03 ldrb.w r0, [r0, #-3]
430: f1c2 0510 rsb r5, r2, #16
}
if (((pos % 8) + size) > 24) {
434: 2c18 cmp r4, #24
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (24 - (pos % 8));
436: bfc8 it gt
438: f1c2 0218 rsbgt r2, r2, #24
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
43c: fa00 f505 lsl.w r5, r0, r5
440: ea41 0105 orr.w r1, r1, r5
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (24 - (pos % 8));
444: bfc4 itt gt
446: fa00 f202 lslgt.w r2, r0, r2
44a: 4311 orrgt r1, r2
}
value &= ((uint32_t)1 << size) - 1;
44c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
450: 4098 lsls r0, r3
return value;
}
452: ea21 0000 bic.w r0, r1, r0
456: bd70 pop {r4, r5, r6, pc}
00000458 <gpio_get_pin_level>:
* Reads the level on pins connected to a port
*
* \param[in] pin The pin number for device
*/
static inline bool gpio_get_pin_level(const uint8_t pin)
{
458: b537 push {r0, r1, r2, r4, r5, lr}
*/
static inline uint32_t _gpio_get_level(const enum gpio_port port)
{
uint32_t tmp;
CRITICAL_SECTION_ENTER();
45a: 4b0e ldr r3, [pc, #56] ; (494 <gpio_get_pin_level+0x3c>)
45c: 4605 mov r5, r0
45e: a801 add r0, sp, #4
460: 4798 blx r3
return tmp;
}
static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
{
return ((Port *)hw)->Group[submodule_index].DIR.reg;
462: 4a0d ldr r2, [pc, #52] ; (498 <gpio_get_pin_level+0x40>)
464: 096b lsrs r3, r5, #5
466: 01d9 lsls r1, r3, #7
468: eb02 13c3 add.w r3, r2, r3, lsl #7
46c: 5851 ldr r1, [r2, r1]
return tmp;
}
static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
{
return ((Port *)hw)->Group[submodule_index].IN.reg;
46e: 6a1a ldr r2, [r3, #32]
return ((Port *)hw)->Group[submodule_index].OUT.reg;
470: 691c ldr r4, [r3, #16]
uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port);
tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp;
tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
CRITICAL_SECTION_LEAVE();
472: 4b0a ldr r3, [pc, #40] ; (49c <gpio_get_pin_level+0x44>)
tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
474: 4054 eors r4, r2
476: 400c ands r4, r1
CRITICAL_SECTION_LEAVE();
478: a801 add r0, sp, #4
tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
47a: 4054 eors r4, r2
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
47c: f005 051f and.w r5, r5, #31
CRITICAL_SECTION_LEAVE();
480: 4798 blx r3
482: 2001 movs r0, #1
484: fa00 f505 lsl.w r5, r0, r5
488: 4225 tst r5, r4
}
48a: bf08 it eq
48c: 2000 moveq r0, #0
48e: b003 add sp, #12
490: bd30 pop {r4, r5, pc}
492: bf00 nop
494: 00002099 .word 0x00002099
498: 41008000 .word 0x41008000
49c: 000020a7 .word 0x000020a7
000004a0 <sd_mmc_configure_slot>:
/**
* \brief Configures the driver with the selected card configuration
*/
static void sd_mmc_configure_slot(void)
{
4a0: b513 push {r0, r1, r4, lr}
driver_select_device(
sd_mmc_hal, sd_mmc_slot_sel, sd_mmc_card->clock, sd_mmc_card->bus_width, sd_mmc_card->high_speed);
4a2: 4807 ldr r0, [pc, #28] ; (4c0 <sd_mmc_configure_slot+0x20>)
driver_select_device(
4a4: 4c07 ldr r4, [pc, #28] ; (4c4 <sd_mmc_configure_slot+0x24>)
sd_mmc_hal, sd_mmc_slot_sel, sd_mmc_card->clock, sd_mmc_card->bus_width, sd_mmc_card->high_speed);
4a6: 6802 ldr r2, [r0, #0]
driver_select_device(
4a8: 7f91 ldrb r1, [r2, #30]
4aa: 7b53 ldrb r3, [r2, #13]
4ac: 3900 subs r1, #0
4ae: bf18 it ne
4b0: 2101 movne r1, #1
4b2: 9100 str r1, [sp, #0]
4b4: 7901 ldrb r1, [r0, #4]
4b6: 6812 ldr r2, [r2, #0]
4b8: 6880 ldr r0, [r0, #8]
4ba: 47a0 blx r4
}
4bc: b002 add sp, #8
4be: bd10 pop {r4, pc}
4c0: 20000290 .word 0x20000290
4c4: 000013f9 .word 0x000013f9
000004c8 <sd_mmc_select_slot>:
{
4c8: b538 push {r3, r4, r5, lr}
if (slot >= CONF_SD_MMC_MEM_CNT) {
4ca: 2800 cmp r0, #0
4cc: d143 bne.n 556 <sd_mmc_select_slot+0x8e>
if (_cd && _cd[slot].pin != -1) {
4ce: 4c23 ldr r4, [pc, #140] ; (55c <sd_mmc_select_slot+0x94>)
4d0: 68e3 ldr r3, [r4, #12]
4d2: 2b00 cmp r3, #0
4d4: d038 beq.n 548 <sd_mmc_select_slot+0x80>
4d6: f9b3 0000 ldrsh.w r0, [r3]
4da: 1c42 adds r2, r0, #1
4dc: d034 beq.n 548 <sd_mmc_select_slot+0x80>
if (gpio_get_pin_level(_cd[slot].pin) != _cd[slot].val) {
4de: 4b20 ldr r3, [pc, #128] ; (560 <sd_mmc_select_slot+0x98>)
4e0: b2c0 uxtb r0, r0
4e2: 4798 blx r3
4e4: 68e3 ldr r3, [r4, #12]
4e6: 885b ldrh r3, [r3, #2]
4e8: 4298 cmp r0, r3
4ea: d003 beq.n 4f4 <sd_mmc_select_slot+0x2c>
sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD;
4ec: 2304 movs r3, #4
sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_DEBOUNCE;
4ee: 76a3 strb r3, [r4, #26]
return SD_MMC_ERR_NO_CARD;
4f0: 2002 movs r0, #2
}
4f2: bd38 pop {r3, r4, r5, pc}
if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD) {
4f4: 7ea0 ldrb r0, [r4, #26]
4f6: 2804 cmp r0, #4
4f8: d101 bne.n 4fe <sd_mmc_select_slot+0x36>
sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_DEBOUNCE;
4fa: 2301 movs r3, #1
4fc: e7f7 b.n 4ee <sd_mmc_select_slot+0x26>
if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_DEBOUNCE) {
4fe: 2801 cmp r0, #1
500: d11f bne.n 542 <sd_mmc_select_slot+0x7a>
sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_INIT;
502: 2302 movs r3, #2
504: 76a3 strb r3, [r4, #26]
sd_mmc_cards[slot].clock = SDMMC_CLOCK_INIT;
506: 4b17 ldr r3, [pc, #92] ; (564 <sd_mmc_select_slot+0x9c>)
508: 6123 str r3, [r4, #16]
sd_mmc_cards[slot].bus_width = 1;
50a: 2301 movs r3, #1
50c: 7763 strb r3, [r4, #29]
sd_mmc_cards[slot].high_speed = 0;
50e: 2300 movs r3, #0
510: f884 302e strb.w r3, [r4, #46] ; 0x2e
assert(!(sd_mmc_slot_sel != slot && sd_mmc_nb_block_remaining != 0), ">>>");
514: 7923 ldrb r3, [r4, #4]
516: b1e3 cbz r3, 552 <sd_mmc_select_slot+0x8a>
518: 8e20 ldrh r0, [r4, #48] ; 0x30
51a: fab0 f080 clz r0, r0
51e: 0940 lsrs r0, r0, #5
520: 4a11 ldr r2, [pc, #68] ; (568 <sd_mmc_select_slot+0xa0>)
522: 4912 ldr r1, [pc, #72] ; (56c <sd_mmc_select_slot+0xa4>)
524: 4d12 ldr r5, [pc, #72] ; (570 <sd_mmc_select_slot+0xa8>)
526: f240 532c movw r3, #1324 ; 0x52c
52a: 47a8 blx r5
sd_mmc_slot_sel = slot;
52c: 2300 movs r3, #0
52e: 7123 strb r3, [r4, #4]
sd_mmc_card = &sd_mmc_cards[slot];
530: 4b10 ldr r3, [pc, #64] ; (574 <sd_mmc_select_slot+0xac>)
532: 6023 str r3, [r4, #0]
sd_mmc_configure_slot();
534: 4b10 ldr r3, [pc, #64] ; (578 <sd_mmc_select_slot+0xb0>)
536: 4798 blx r3
return (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_INIT) ? SD_MMC_INIT_ONGOING : SD_MMC_OK;
538: 7ea0 ldrb r0, [r4, #26]
53a: 1e83 subs r3, r0, #2
53c: 4258 negs r0, r3
53e: 4158 adcs r0, r3
540: e7d7 b.n 4f2 <sd_mmc_select_slot+0x2a>
if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE) {
542: 2803 cmp r0, #3
544: d1e6 bne.n 514 <sd_mmc_select_slot+0x4c>
546: e7d4 b.n 4f2 <sd_mmc_select_slot+0x2a>
|| (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE)) {
548: 7ea3 ldrb r3, [r4, #26]
if ((sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD)
54a: 3b03 subs r3, #3
54c: 2b01 cmp r3, #1
54e: d8e1 bhi.n 514 <sd_mmc_select_slot+0x4c>
550: e7d7 b.n 502 <sd_mmc_select_slot+0x3a>
assert(!(sd_mmc_slot_sel != slot && sd_mmc_nb_block_remaining != 0), ">>>");
552: 2001 movs r0, #1
554: e7e4 b.n 520 <sd_mmc_select_slot+0x58>
return SD_MMC_ERR_SLOT;
556: 2004 movs r0, #4
558: e7cb b.n 4f2 <sd_mmc_select_slot+0x2a>
55a: bf00 nop
55c: 20000290 .word 0x20000290
560: 00000459 .word 0x00000459
564: 00061a80 .word 0x00061a80
568: 00002b12 .word 0x00002b12
56c: 00002b25 .word 0x00002b25
570: 00002169 .word 0x00002169
574: 200002a0 .word 0x200002a0
578: 000004a1 .word 0x000004a1
0000057c <sd_mmc_cmd13>:
{
57c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
580: 4d0b ldr r5, [pc, #44] ; (5b0 <sd_mmc_cmd13+0x34>)
if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD13_SEND_STATUS, (uint32_t)sd_mmc_card->rca << 16)) {
582: 4e0c ldr r6, [pc, #48] ; (5b4 <sd_mmc_cmd13+0x38>)
584: 4f0c ldr r7, [pc, #48] ; (5b8 <sd_mmc_cmd13+0x3c>)
if (driver_get_response(sd_mmc_hal) & CARD_STATUS_READY_FOR_DATA) {
586: f8df 8034 ldr.w r8, [pc, #52] ; 5bc <sd_mmc_cmd13+0x40>
if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD13_SEND_STATUS, (uint32_t)sd_mmc_card->rca << 16)) {
58a: 6833 ldr r3, [r6, #0]
58c: 68b0 ldr r0, [r6, #8]
58e: 891a ldrh r2, [r3, #8]
590: f241 110d movw r1, #4365 ; 0x110d
594: 0412 lsls r2, r2, #16
596: 47b8 blx r7
598: 4604 mov r4, r0
59a: b128 cbz r0, 5a8 <sd_mmc_cmd13+0x2c>
if (driver_get_response(sd_mmc_hal) & CARD_STATUS_READY_FOR_DATA) {
59c: 68b0 ldr r0, [r6, #8]
59e: 47c0 blx r8
5a0: 05c3 lsls r3, r0, #23
5a2: d402 bmi.n 5aa <sd_mmc_cmd13+0x2e>
if (nec_timeout-- == 0) {
5a4: 3d01 subs r5, #1
5a6: d1f0 bne.n 58a <sd_mmc_cmd13+0xe>
return false;
5a8: 2400 movs r4, #0
}
5aa: 4620 mov r0, r4
5ac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
5b0: 00030d41 .word 0x00030d41
5b4: 20000290 .word 0x20000290
5b8: 00001249 .word 0x00001249
5bc: 000013b9 .word 0x000013b9
000005c0 <sd_mmc_cmd9_spi>:
* data (CSD) on the CMD line spi.
*
* \return true if success, otherwise false
*/
static bool sd_mmc_cmd9_spi(void)
{
5c0: b573 push {r0, r1, r4, r5, r6, lr}
if (!driver_adtc_start(sd_mmc_hal, SDMMC_SPI_CMD9_SEND_CSD, (uint32_t)sd_mmc_card->rca << 16,
5c2: 4c0e ldr r4, [pc, #56] ; (5fc <sd_mmc_cmd9_spi+0x3c>)
5c4: 490e ldr r1, [pc, #56] ; (600 <sd_mmc_cmd9_spi+0x40>)
5c6: 6823 ldr r3, [r4, #0]
5c8: 68a0 ldr r0, [r4, #8]
5ca: 891a ldrh r2, [r3, #8]
5cc: 4e0d ldr r6, [pc, #52] ; (604 <sd_mmc_cmd9_spi+0x44>)
5ce: 2501 movs r5, #1
5d0: 2310 movs r3, #16
5d2: e9cd 5500 strd r5, r5, [sp]
5d6: 409a lsls r2, r3
5d8: 47b0 blx r6
5da: b160 cbz r0, 5f6 <sd_mmc_cmd9_spi+0x36>
CSD_REG_BSIZE, 1, true)) {
return false;
}
if (!driver_start_read_blocks(sd_mmc_hal, sd_mmc_card->csd, 1)) {
5dc: 6821 ldr r1, [r4, #0]
5de: 68a0 ldr r0, [r4, #8]
5e0: 4b09 ldr r3, [pc, #36] ; (608 <sd_mmc_cmd9_spi+0x48>)
5e2: 462a mov r2, r5
5e4: 310e adds r1, #14
5e6: 4798 blx r3
5e8: b128 cbz r0, 5f6 <sd_mmc_cmd9_spi+0x36>
return false;
}
return driver_wait_end_of_read_blocks(sd_mmc_hal);
5ea: 68a0 ldr r0, [r4, #8]
5ec: 4b07 ldr r3, [pc, #28] ; (60c <sd_mmc_cmd9_spi+0x4c>)
}
5ee: b002 add sp, #8
5f0: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return driver_wait_end_of_read_blocks(sd_mmc_hal);
5f4: 4718 bx r3
}
5f6: 2000 movs r0, #0
5f8: b002 add sp, #8
5fa: bd70 pop {r4, r5, r6, pc}
5fc: 20000290 .word 0x20000290
600: 00081109 .word 0x00081109
604: 00001061 .word 0x00001061
608: 0000125d .word 0x0000125d
60c: 00001309 .word 0x00001309
00000610 <sd_mmc_deselect_slot>:
if (sd_mmc_slot_sel < CONF_SD_MMC_MEM_CNT) {
610: 4b03 ldr r3, [pc, #12] ; (620 <sd_mmc_deselect_slot+0x10>)
612: 7919 ldrb r1, [r3, #4]
614: b911 cbnz r1, 61c <sd_mmc_deselect_slot+0xc>
driver_deselect_device(sd_mmc_hal, sd_mmc_slot_sel);
616: 6898 ldr r0, [r3, #8]
618: 4b02 ldr r3, [pc, #8] ; (624 <sd_mmc_deselect_slot+0x14>)
61a: 4718 bx r3
}
61c: 4770 bx lr
61e: bf00 nop
620: 20000290 .word 0x20000290
624: 00001411 .word 0x00001411
00000628 <sdio_cmd53.constprop.0>:
static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t inc_addr, uint32_t size,
628: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
62c: 4605 mov r5, r0
assert(size != 0, ">>>");
62e: f8df 9070 ldr.w r9, [pc, #112] ; 6a0 <sdio_cmd53.constprop.0+0x78>
static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t inc_addr, uint32_t size,
632: 9f0a ldr r7, [sp, #40] ; 0x28
634: 460e mov r6, r1
636: 4690 mov r8, r2
638: 461c mov r4, r3
assert(size != 0, ">>>");
63a: 4a13 ldr r2, [pc, #76] ; (688 <sdio_cmd53.constprop.0+0x60>)
63c: 4913 ldr r1, [pc, #76] ; (68c <sdio_cmd53.constprop.0+0x64>)
63e: f240 4395 movw r3, #1173 ; 0x495
642: 2001 movs r0, #1
644: 47c8 blx r9
assert(size <= 512, ">>>");
646: 4a10 ldr r2, [pc, #64] ; (688 <sdio_cmd53.constprop.0+0x60>)
648: 4910 ldr r1, [pc, #64] ; (68c <sdio_cmd53.constprop.0+0x64>)
64a: f240 4396 movw r3, #1174 ; 0x496
64e: 2001 movs r0, #1
650: 47c8 blx r9
| ((uint32_t)inc_addr << SDIO_CMD53_OP_CODE) | ((uint32_t)0 << SDIO_CMD53_BLOCK_MODE)
652: 06a3 lsls r3, r4, #26
| ((uint32_t)func_nb << SDIO_CMD53_FUNCTION_NUM) | ((uint32_t)rw_flag << SDIO_CMD53_RW_FLAG),
654: ea43 2448 orr.w r4, r3, r8, lsl #9
658: ea44 7206 orr.w r2, r4, r6, lsl #28
((size % 512) << SDIO_CMD53_COUNT) | ((uint32_t)reg_addr << SDIO_CMD53_REG_ADDR)
65c: f3c7 0108 ubfx r1, r7, #0, #9
return driver_adtc_start(
660: 480b ldr r0, [pc, #44] ; (690 <sdio_cmd53.constprop.0+0x68>)
662: 4c0c ldr r4, [pc, #48] ; (694 <sdio_cmd53.constprop.0+0x6c>)
| ((uint32_t)func_nb << SDIO_CMD53_FUNCTION_NUM) | ((uint32_t)rw_flag << SDIO_CMD53_RW_FLAG),
664: 430a orrs r2, r1
return driver_adtc_start(
666: 2301 movs r3, #1
668: 490b ldr r1, [pc, #44] ; (698 <sdio_cmd53.constprop.0+0x70>)
66a: e9cd 3300 strd r3, r3, [sp]
66e: 2d00 cmp r5, #0
670: bf08 it eq
672: 4601 moveq r1, r0
674: 4809 ldr r0, [pc, #36] ; (69c <sdio_cmd53.constprop.0+0x74>)
676: b2bb uxth r3, r7
678: ea42 72c5 orr.w r2, r2, r5, lsl #31
67c: 6880 ldr r0, [r0, #8]
67e: 47a0 blx r4
}
680: b003 add sp, #12
682: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
686: bf00 nop
688: 00002b12 .word 0x00002b12
68c: 00002b25 .word 0x00002b25
690: 00011335 .word 0x00011335
694: 00001061 .word 0x00001061
698: 00019335 .word 0x00019335
69c: 20000290 .word 0x20000290
6a0: 00002169 .word 0x00002169
000006a4 <sdio_cmd52.constprop.0>:
static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data)
6a4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
assert(io_data != NULL, ">>>");
6a8: 461d mov r5, r3
static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data)
6aa: 4606 mov r6, r0
6ac: 4614 mov r4, r2
assert(io_data != NULL, ">>>");
6ae: 1e28 subs r0, r5, #0
6b0: bf18 it ne
6b2: 2001 movne r0, #1
6b4: 4a0e ldr r2, [pc, #56] ; (6f0 <sdio_cmd52.constprop.0+0x4c>)
6b6: f8df 804c ldr.w r8, [pc, #76] ; 704 <sdio_cmd52.constprop.0+0x60>
static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data)
6ba: 460f mov r7, r1
assert(io_data != NULL, ">>>");
6bc: f240 4376 movw r3, #1142 ; 0x476
6c0: 490c ldr r1, [pc, #48] ; (6f4 <sdio_cmd52.constprop.0+0x50>)
| ((uint32_t)reg_addr << SDIO_CMD52_REG_ADRR))) {
6c2: 0264 lsls r4, r4, #9
assert(io_data != NULL, ">>>");
6c4: 47c0 blx r8
if (!driver_send_cmd(sd_mmc_hal,
6c6: ea44 7207 orr.w r2, r4, r7, lsl #28
6ca: ea42 70c6 orr.w r0, r2, r6, lsl #31
((uint32_t)*io_data << SDIO_CMD52_WR_DATA) | ((uint32_t)rw_flag << SDIO_CMD52_RW_FLAG)
6ce: 782a ldrb r2, [r5, #0]
if (!driver_send_cmd(sd_mmc_hal,
6d0: 4e09 ldr r6, [pc, #36] ; (6f8 <sdio_cmd52.constprop.0+0x54>)
6d2: 4b0a ldr r3, [pc, #40] ; (6fc <sdio_cmd52.constprop.0+0x58>)
6d4: 4302 orrs r2, r0
6d6: f241 3134 movw r1, #4916 ; 0x1334
6da: 68b0 ldr r0, [r6, #8]
6dc: 4798 blx r3
6de: 4604 mov r4, r0
6e0: b118 cbz r0, 6ea <sdio_cmd52.constprop.0+0x46>
*io_data = driver_get_response(sd_mmc_hal) & 0xFF;
6e2: 68b0 ldr r0, [r6, #8]
6e4: 4b06 ldr r3, [pc, #24] ; (700 <sdio_cmd52.constprop.0+0x5c>)
6e6: 4798 blx r3
6e8: 7028 strb r0, [r5, #0]
}
6ea: 4620 mov r0, r4
6ec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
6f0: 00002b12 .word 0x00002b12
6f4: 00002b25 .word 0x00002b25
6f8: 20000290 .word 0x20000290
6fc: 00001249 .word 0x00001249
700: 000013b9 .word 0x000013b9
704: 00002169 .word 0x00002169
00000708 <sd_mmc_init>:
#endif
/*--------------------- PUBLIC FUNCTIONS ----------------------------*/
void sd_mmc_init(void *hal, sd_mmc_detect_t *card_detects, sd_mmc_detect_t *wp_detects)
{
708: b510 push {r4, lr}
/* GPIO will be used to detect card and write protect.
* The related clocks and pinmux must be configurated in good
* condition. */
for (uint8_t slot = 0; slot < CONF_SD_MMC_MEM_CNT; slot++) {
sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD;
70a: 4b04 ldr r3, [pc, #16] ; (71c <sd_mmc_init+0x14>)
70c: 2404 movs r4, #4
70e: 769c strb r4, [r3, #26]
}
sd_mmc_slot_sel = 0xFF; /* No slot configurated */
710: 24ff movs r4, #255 ; 0xff
712: 711c strb r4, [r3, #4]
sd_mmc_hal = hal;
_cd = card_detects;
714: e9c3 0102 strd r0, r1, [r3, #8]
_wp = wp_detects;
718: 635a str r2, [r3, #52] ; 0x34
}
71a: bd10 pop {r4, pc}
71c: 20000290 .word 0x20000290
00000720 <sd_mmc_check>:
{
return CONF_SD_MMC_MEM_CNT;
}
sd_mmc_err_t sd_mmc_check(uint8_t slot)
{
720: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
sd_mmc_err_t sd_mmc_err;
sd_mmc_err = sd_mmc_select_slot(slot);
724: 4b84 ldr r3, [pc, #528] ; (938 <sd_mmc_check+0x218>)
{
726: b089 sub sp, #36 ; 0x24
sd_mmc_err = sd_mmc_select_slot(slot);
728: 4798 blx r3
if (sd_mmc_err != SD_MMC_INIT_ONGOING) {
72a: 2801 cmp r0, #1
sd_mmc_err = sd_mmc_select_slot(slot);
72c: 4680 mov r8, r0
if (sd_mmc_err != SD_MMC_INIT_ONGOING) {
72e: d005 beq.n 73c <sd_mmc_check+0x1c>
// To notify that the card has been just initialized
// It is necessary for USB Device MSC
return SD_MMC_INIT_ONGOING;
}
sd_mmc_card->state = SD_MMC_CARD_STATE_UNUSABLE;
sd_mmc_deselect_slot();
730: 4b82 ldr r3, [pc, #520] ; (93c <sd_mmc_check+0x21c>)
732: 4798 blx r3
return SD_MMC_ERR_UNUSABLE;
}
734: 4640 mov r0, r8
736: b009 add sp, #36 ; 0x24
738: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
sd_mmc_card->type = CARD_TYPE_SD;
73c: 4c80 ldr r4, [pc, #512] ; (940 <sd_mmc_check+0x220>)
sd_mmc_spi_debug("Start SD card install\n\r");
73e: 4f81 ldr r7, [pc, #516] ; (944 <sd_mmc_check+0x224>)
sd_mmc_card->type = CARD_TYPE_SD;
740: 6823 ldr r3, [r4, #0]
sd_mmc_card->version = CARD_VER_UNKNOWN;
742: 2500 movs r5, #0
sd_mmc_card->type = CARD_TYPE_SD;
744: 72d8 strb r0, [r3, #11]
sd_mmc_card->version = CARD_VER_UNKNOWN;
746: 731d strb r5, [r3, #12]
sd_mmc_card->rca = 0;
748: 811d strh r5, [r3, #8]
sd_mmc_spi_debug("Start SD card install\n\r");
74a: 487f ldr r0, [pc, #508] ; (948 <sd_mmc_check+0x228>)
74c: 47b8 blx r7
driver_send_clock(sd_mmc_hal);
74e: 68a0 ldr r0, [r4, #8]
750: 4b7e ldr r3, [pc, #504] ; (94c <sd_mmc_check+0x22c>)
752: 4798 blx r3
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
754: 462a mov r2, r5
756: 68a0 ldr r0, [r4, #8]
758: 4d7d ldr r5, [pc, #500] ; (950 <sd_mmc_check+0x230>)
75a: f44f 5188 mov.w r1, #4352 ; 0x1100
75e: 47a8 blx r5
760: b338 cbz r0, 7b2 <sd_mmc_check+0x92>
if (!driver_send_cmd(sd_mmc_hal, SD_CMD8_SEND_IF_COND, SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) {
762: 68a0 ldr r0, [r4, #8]
764: f44f 72d5 mov.w r2, #426 ; 0x1aa
768: f245 5108 movw r1, #21768 ; 0x5508
76c: 47a8 blx r5
76e: bb30 cbnz r0, 7be <sd_mmc_check+0x9e>
*v2 = 0;
770: 2600 movs r6, #0
if (!driver_send_cmd(sd_mmc_hal, SDIO_CMD5_SEND_OP_COND, 0)) {
772: 68a0 ldr r0, [r4, #8]
774: 2200 movs r2, #0
776: f244 5105 movw r1, #17669 ; 0x4505
77a: 47a8 blx r5
77c: 2800 cmp r0, #0
77e: f000 80a6 beq.w 8ce <sd_mmc_check+0x1ae>
resp = driver_get_response(sd_mmc_hal);
782: 68a0 ldr r0, [r4, #8]
784: f8df 91cc ldr.w r9, [pc, #460] ; 954 <sd_mmc_check+0x234>
788: 47c8 blx r9
if ((resp & OCR_SDIO_NF) == 0) {
78a: f010 4fe0 tst.w r0, #1879048192 ; 0x70000000
78e: f000 809e beq.w 8ce <sd_mmc_check+0x1ae>
792: f241 3a89 movw sl, #5001 ; 0x1389
if (!driver_send_cmd(sd_mmc_hal, SDIO_CMD5_SEND_OP_COND, resp & SD_MMC_VOLTAGE_SUPPORT)) {
796: f400 12fc and.w r2, r0, #2064384 ; 0x1f8000
79a: f244 5105 movw r1, #17669 ; 0x4505
79e: 68a0 ldr r0, [r4, #8]
7a0: 47a8 blx r5
7a2: b130 cbz r0, 7b2 <sd_mmc_check+0x92>
resp = driver_get_response(sd_mmc_hal);
7a4: 68a0 ldr r0, [r4, #8]
7a6: 47c8 blx r9
if ((resp & OCR_POWER_UP_BUSY) == OCR_POWER_UP_BUSY) {
7a8: 2800 cmp r0, #0
7aa: db14 blt.n 7d6 <sd_mmc_check+0xb6>
if (cmd5_retry-- == 0) {
7ac: f1ba 0a01 subs.w sl, sl, #1
7b0: d1f1 bne.n 796 <sd_mmc_check+0x76>
sd_mmc_card->state = SD_MMC_CARD_STATE_UNUSABLE;
7b2: 6823 ldr r3, [r4, #0]
7b4: f04f 0803 mov.w r8, #3
7b8: f883 800a strb.w r8, [r3, #10]
7bc: e7b8 b.n 730 <sd_mmc_check+0x10>
resp = driver_get_response(sd_mmc_hal);
7be: 68a0 ldr r0, [r4, #8]
7c0: 4b64 ldr r3, [pc, #400] ; (954 <sd_mmc_check+0x234>)
7c2: 4798 blx r3
if (resp == 0xFFFFFFFF) {
7c4: 1c41 adds r1, r0, #1
7c6: d0d3 beq.n 770 <sd_mmc_check+0x50>
if ((resp & (SD_CMD8_MASK_PATTERN | SD_CMD8_MASK_VOLTAGE)) != (SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) {
7c8: f3c0 000b ubfx r0, r0, #0, #12
7cc: f5b0 7fd5 cmp.w r0, #426 ; 0x1aa
7d0: d1ef bne.n 7b2 <sd_mmc_check+0x92>
*v2 = 1;
7d2: 4646 mov r6, r8
7d4: e7cd b.n 772 <sd_mmc_check+0x52>
if ((resp & OCR_SDIO_MP) > 0) {
7d6: 0102 lsls r2, r0, #4
sd_mmc_card->type = CARD_TYPE_SD_COMBO;
7d8: 6823 ldr r3, [r4, #0]
if ((resp & OCR_SDIO_MP) > 0) {
7da: d52f bpl.n 83c <sd_mmc_check+0x11c>
sd_mmc_card->type = CARD_TYPE_SD_COMBO;
7dc: 2205 movs r2, #5
7de: 72da strb r2, [r3, #11]
if (sd_mmc_card->type & CARD_TYPE_SD) {
7e0: ea4f 7a86 mov.w sl, r6, lsl #30
resp = driver_get_response(sd_mmc_hal);
7e4: 4e5b ldr r6, [pc, #364] ; (954 <sd_mmc_check+0x234>)
7e6: f641 39ef movw r9, #7151 ; 0x1bef
if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, 0)) {
7ea: 68a0 ldr r0, [r4, #8]
7ec: 2200 movs r2, #0
7ee: f241 1137 movw r1, #4407 ; 0x1137
7f2: 47a8 blx r5
7f4: 2800 cmp r0, #0
7f6: d17f bne.n 8f8 <sd_mmc_check+0x1d8>
sd_mmc_spi_debug("%s: CMD55 Fail\n\r", __func__);
7f8: 4957 ldr r1, [pc, #348] ; (958 <sd_mmc_check+0x238>)
7fa: 4858 ldr r0, [pc, #352] ; (95c <sd_mmc_check+0x23c>)
sd_mmc_spi_debug("%s: ACMD41 Fail\n\r", __func__);
7fc: 47b8 blx r7
sd_mmc_spi_debug("Start MMC Install\n\r");
7fe: 4858 ldr r0, [pc, #352] ; (960 <sd_mmc_check+0x240>)
800: 47b8 blx r7
sd_mmc_card->type = CARD_TYPE_MMC;
802: 6823 ldr r3, [r4, #0]
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
804: 68a0 ldr r0, [r4, #8]
sd_mmc_card->type = CARD_TYPE_MMC;
806: 2202 movs r2, #2
808: 72da strb r2, [r3, #11]
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
80a: f44f 5188 mov.w r1, #4352 ; 0x1100
80e: 2200 movs r2, #0
810: 47a8 blx r5
812: 2800 cmp r0, #0
814: d0cd beq.n 7b2 <sd_mmc_check+0x92>
resp = driver_get_response(sd_mmc_hal);
816: f8df 913c ldr.w r9, [pc, #316] ; 954 <sd_mmc_check+0x234>
retry = 7150;
81a: f641 36ee movw r6, #7150 ; 0x1bee
if (!driver_send_cmd(sd_mmc_hal, MMC_SPI_CMD1_SEND_OP_COND, 0)) {
81e: 68a0 ldr r0, [r4, #8]
820: 2200 movs r2, #0
822: f241 1101 movw r1, #4353 ; 0x1101
826: 47a8 blx r5
828: 2800 cmp r0, #0
82a: f040 812a bne.w a82 <sd_mmc_check+0x362>
sd_mmc_spi_debug("%s: CMD1 SPI Fail - Busy retry %d\n\r",
82e: f5c6 52df rsb r2, r6, #7136 ; 0x1be0
832: 494c ldr r1, [pc, #304] ; (964 <sd_mmc_check+0x244>)
834: 484c ldr r0, [pc, #304] ; (968 <sd_mmc_check+0x248>)
836: 320e adds r2, #14
838: 47b8 blx r7
return false;
83a: e7ba b.n 7b2 <sd_mmc_check+0x92>
sd_mmc_card->type = CARD_TYPE_SDIO;
83c: 2204 movs r2, #4
83e: 72da strb r2, [r3, #11]
sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]);
840: f8df a134 ldr.w sl, [pc, #308] ; 978 <sd_mmc_check+0x258>
844: f10d 0914 add.w r9, sp, #20
addr_old = SDIO_CCCR_CIS_PTR;
848: 2609 movs r6, #9
84a: 46d3 mov fp, sl
sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]);
84c: 2100 movs r1, #0
84e: 464b mov r3, r9
850: 4632 mov r2, r6
852: 4608 mov r0, r1
addr_old++;
854: 3601 adds r6, #1
sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]);
856: 47d0 blx sl
for (i = 0; i < 4; i++) {
858: 2e0d cmp r6, #13
85a: f109 0901 add.w r9, r9, #1
85e: d1f5 bne.n 84c <sd_mmc_check+0x12c>
addr_old = addr_cis[0] + (addr_cis[1] << 8) + (addr_cis[2] << 16) + (addr_cis[3] << 24);
860: f89d 3015 ldrb.w r3, [sp, #21]
864: f89d 6014 ldrb.w r6, [sp, #20]
868: eb06 2603 add.w r6, r6, r3, lsl #8
86c: f89d 3016 ldrb.w r3, [sp, #22]
870: eb06 4603 add.w r6, r6, r3, lsl #16
874: f89d 3017 ldrb.w r3, [sp, #23]
878: eb06 6603 add.w r6, r6, r3, lsl #24
if (addr_new > (addr_old + 256)) {
87c: f506 7380 add.w r3, r6, #256 ; 0x100
880: 9303 str r3, [sp, #12]
addr_new = addr_old;
882: f04f 0900 mov.w r9, #0
sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
886: 2100 movs r1, #0
888: f10d 0a18 add.w sl, sp, #24
88c: eb0a 0309 add.w r3, sl, r9
890: eb06 0209 add.w r2, r6, r9
894: 4608 mov r0, r1
for (i = 0; i < 3; i++) {
896: f109 0901 add.w r9, r9, #1
sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
89a: 47d8 blx fp
for (i = 0; i < 3; i++) {
89c: f1b9 0f03 cmp.w r9, #3
8a0: d1f1 bne.n 886 <sd_mmc_check+0x166>
if (buf[0] == SDIO_CISTPL_END) {
8a2: f89d 3018 ldrb.w r3, [sp, #24]
8a6: 2bff cmp r3, #255 ; 0xff
8a8: d083 beq.n 7b2 <sd_mmc_check+0x92>
if (buf[0] == SDIO_CISTPL_FUNCE && buf[2] == 0x00) {
8aa: 2b22 cmp r3, #34 ; 0x22
8ac: d104 bne.n 8b8 <sd_mmc_check+0x198>
8ae: f89d 301a ldrb.w r3, [sp, #26]
8b2: 2b00 cmp r3, #0
8b4: f000 81fa beq.w cac <sd_mmc_check+0x58c>
if (buf[1] == 0) {
8b8: f89d 3019 ldrb.w r3, [sp, #25]
8bc: 2b00 cmp r3, #0
8be: f43f af78 beq.w 7b2 <sd_mmc_check+0x92>
addr_new += buf[1] - 1;
8c2: 3302 adds r3, #2
8c4: 441e add r6, r3
if (addr_new > (addr_old + 256)) {
8c6: 9b03 ldr r3, [sp, #12]
8c8: 429e cmp r6, r3
8ca: d9da bls.n 882 <sd_mmc_check+0x162>
8cc: e771 b.n 7b2 <sd_mmc_check+0x92>
if (sd_mmc_card->type & CARD_TYPE_SD) {
8ce: 6823 ldr r3, [r4, #0]
8d0: 7adb ldrb r3, [r3, #11]
8d2: 07db lsls r3, r3, #31
8d4: d484 bmi.n 7e0 <sd_mmc_check+0xc0>
if (IS_SDIO()) {
8d6: 6823 ldr r3, [r4, #0]
8d8: 7adb ldrb r3, [r3, #11]
8da: 075a lsls r2, r3, #29
8dc: d4b0 bmi.n 840 <sd_mmc_check+0x120>
if ((sd_mmc_card->type & CARD_TYPE_SD) &&
8de: 6823 ldr r3, [r4, #0]
8e0: 7adb ldrb r3, [r3, #11]
8e2: f003 0309 and.w r3, r3, #9
8e6: 2b01 cmp r3, #1
8e8: f000 8202 beq.w cf0 <sd_mmc_check+0x5d0>
if (sd_mmc_card->type & CARD_TYPE_SD) {
8ec: 6823 ldr r3, [r4, #0]
8ee: 7adb ldrb r3, [r3, #11]
8f0: 07db lsls r3, r3, #31
8f2: f100 8188 bmi.w c06 <sd_mmc_check+0x4e6>
8f6: e18b b.n c10 <sd_mmc_check+0x4f0>
if (!driver_send_cmd(sd_mmc_hal, SD_SPI_ACMD41_SD_SEND_OP_COND, arg)) {
8f8: 68a0 ldr r0, [r4, #8]
8fa: 4652 mov r2, sl
8fc: f241 1129 movw r1, #4393 ; 0x1129
900: 47a8 blx r5
902: b910 cbnz r0, 90a <sd_mmc_check+0x1ea>
sd_mmc_spi_debug("%s: ACMD41 Fail\n\r", __func__);
904: 4914 ldr r1, [pc, #80] ; (958 <sd_mmc_check+0x238>)
906: 4819 ldr r0, [pc, #100] ; (96c <sd_mmc_check+0x24c>)
908: e778 b.n 7fc <sd_mmc_check+0xdc>
resp = driver_get_response(sd_mmc_hal);
90a: 68a0 ldr r0, [r4, #8]
90c: 47b0 blx r6
if (!(resp & R1_SPI_IDLE)) {
90e: f010 0201 ands.w r2, r0, #1
912: d008 beq.n 926 <sd_mmc_check+0x206>
if (retry-- == 0) {
914: f1b9 0901 subs.w r9, r9, #1
918: f47f af67 bne.w 7ea <sd_mmc_check+0xca>
sd_mmc_spi_debug("%s: ACMD41 Timeout on busy, resp32 0x%08x \n\r",
91c: 4602 mov r2, r0
91e: 490e ldr r1, [pc, #56] ; (958 <sd_mmc_check+0x238>)
920: 4813 ldr r0, [pc, #76] ; (970 <sd_mmc_check+0x250>)
922: 47b8 blx r7
return false;
924: e76b b.n 7fe <sd_mmc_check+0xde>
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD58_READ_OCR, 0)) {
926: 68a0 ldr r0, [r4, #8]
928: f240 513a movw r1, #1338 ; 0x53a
92c: 47a8 blx r5
92e: bb28 cbnz r0, 97c <sd_mmc_check+0x25c>
sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
930: 4909 ldr r1, [pc, #36] ; (958 <sd_mmc_check+0x238>)
932: 4810 ldr r0, [pc, #64] ; (974 <sd_mmc_check+0x254>)
934: e762 b.n 7fc <sd_mmc_check+0xdc>
936: bf00 nop
938: 000004c9 .word 0x000004c9
93c: 00000611 .word 0x00000611
940: 20000290 .word 0x20000290
944: 000020d5 .word 0x000020d5
948: 00002b29 .word 0x00002b29
94c: 000013c5 .word 0x000013c5
950: 00001249 .word 0x00001249
954: 000013b9 .word 0x000013b9
958: 00002c0c .word 0x00002c0c
95c: 00002b41 .word 0x00002b41
960: 00002ba2 .word 0x00002ba2
964: 00002c1b .word 0x00002c1b
968: 00002bb6 .word 0x00002bb6
96c: 00002b52 .word 0x00002b52
970: 00002b64 .word 0x00002b64
974: 00002b91 .word 0x00002b91
978: 000006a5 .word 0x000006a5
if ((driver_get_response(sd_mmc_hal) & OCR_CCS) != 0) {
97c: 68a0 ldr r0, [r4, #8]
97e: 47b0 blx r6
980: 0040 lsls r0, r0, #1
982: d504 bpl.n 98e <sd_mmc_check+0x26e>
sd_mmc_card->type |= CARD_TYPE_HC;
984: 6822 ldr r2, [r4, #0]
986: 7ad3 ldrb r3, [r2, #11]
988: f043 0308 orr.w r3, r3, #8
98c: 72d3 strb r3, [r2, #11]
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
98e: 68a0 ldr r0, [r4, #8]
990: 2200 movs r2, #0
992: f241 113b movw r1, #4411 ; 0x113b
996: 47a8 blx r5
998: 2800 cmp r0, #0
99a: f43f af0a beq.w 7b2 <sd_mmc_check+0x92>
if (sd_mmc_card->type & CARD_TYPE_SD) {
99e: 6823 ldr r3, [r4, #0]
9a0: 7adb ldrb r3, [r3, #11]
9a2: 07d9 lsls r1, r3, #31
9a4: d597 bpl.n 8d6 <sd_mmc_check+0x1b6>
if (!sd_mmc_cmd9_spi()) {
9a6: 4bb2 ldr r3, [pc, #712] ; (c70 <sd_mmc_check+0x550>)
9a8: 4798 blx r3
9aa: 2800 cmp r0, #0
9ac: f43f af01 beq.w 7b2 <sd_mmc_check+0x92>
tran_speed = CSD_TRAN_SPEED(sd_mmc_card->csd);
9b0: f8d4 a000 ldr.w sl, [r4]
9b4: 4eaf ldr r6, [pc, #700] ; (c74 <sd_mmc_check+0x554>)
9b6: f10a 0b0e add.w fp, sl, #14
9ba: 2308 movs r3, #8
9bc: 2260 movs r2, #96 ; 0x60
9be: 2180 movs r1, #128 ; 0x80
9c0: 4658 mov r0, fp
9c2: 47b0 blx r6
mul = sd_trans_multipliers[(tran_speed >> 3) & 0xF];
9c4: 4bac ldr r3, [pc, #688] ; (c78 <sd_mmc_check+0x558>)
9c6: f3c0 02c3 ubfx r2, r0, #3, #4
unit = sd_mmc_trans_units[tran_speed & 0x7];
9ca: f000 0007 and.w r0, r0, #7
9ce: eb03 0080 add.w r0, r3, r0, lsl #2
mul = sd_trans_multipliers[(tran_speed >> 3) & 0xF];
9d2: eb03 0282 add.w r2, r3, r2, lsl #2
if (CSD_STRUCTURE_VERSION(sd_mmc_card->csd) >= SD_CSD_VER_2_0) {
9d6: 2180 movs r1, #128 ; 0x80
sd_mmc_card->clock = unit * mul * 1000;
9d8: 6fd3 ldr r3, [r2, #124] ; 0x7c
9da: 6e02 ldr r2, [r0, #96] ; 0x60
9dc: 4353 muls r3, r2
9de: f44f 727a mov.w r2, #1000 ; 0x3e8
9e2: 4353 muls r3, r2
9e4: f8ca 3000 str.w r3, [sl]
if (CSD_STRUCTURE_VERSION(sd_mmc_card->csd) >= SD_CSD_VER_2_0) {
9e8: 227e movs r2, #126 ; 0x7e
9ea: 2302 movs r3, #2
9ec: 4658 mov r0, fp
9ee: 47b0 blx r6
9f0: 46b1 mov r9, r6
9f2: 2800 cmp r0, #0
9f4: f000 811e beq.w c34 <sd_mmc_check+0x514>
sd_mmc_card->capacity = (SD_CSD_2_0_C_SIZE(sd_mmc_card->csd) + 1) * 512;
9f8: 2316 movs r3, #22
9fa: 2230 movs r2, #48 ; 0x30
9fc: 2180 movs r1, #128 ; 0x80
9fe: 4658 mov r0, fp
a00: 47b0 blx r6
a02: 3001 adds r0, #1
a04: 0240 lsls r0, r0, #9
if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, (uint32_t)sd_mmc_card->rca << 16)) {
a06: f8ba 2008 ldrh.w r2, [sl, #8]
a0a: f8ca 0004 str.w r0, [sl, #4]
a0e: 0412 lsls r2, r2, #16
a10: 68a0 ldr r0, [r4, #8]
a12: f241 1137 movw r1, #4407 ; 0x1137
a16: 47a8 blx r5
a18: 2800 cmp r0, #0
a1a: f43f aeca beq.w 7b2 <sd_mmc_check+0x92>
if (!driver_adtc_start(sd_mmc_hal, SD_ACMD51_SEND_SCR, 0, SD_SCR_REG_BSIZE, 1, true)) {
a1e: 2601 movs r6, #1
a20: e9cd 6600 strd r6, r6, [sp]
a24: 4995 ldr r1, [pc, #596] ; (c7c <sd_mmc_check+0x55c>)
a26: 68a0 ldr r0, [r4, #8]
a28: f8df a26c ldr.w sl, [pc, #620] ; c98 <sd_mmc_check+0x578>
a2c: 2308 movs r3, #8
a2e: 2200 movs r2, #0
a30: 47d0 blx sl
a32: 2800 cmp r0, #0
a34: f43f aebd beq.w 7b2 <sd_mmc_check+0x92>
if (!driver_start_read_blocks(sd_mmc_hal, scr, 1)) {
a38: 68a0 ldr r0, [r4, #8]
a3a: 4b91 ldr r3, [pc, #580] ; (c80 <sd_mmc_check+0x560>)
a3c: 4632 mov r2, r6
a3e: a906 add r1, sp, #24
a40: 4798 blx r3
a42: 2800 cmp r0, #0
a44: f43f aeb5 beq.w 7b2 <sd_mmc_check+0x92>
if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
a48: 68a0 ldr r0, [r4, #8]
a4a: 4b8e ldr r3, [pc, #568] ; (c84 <sd_mmc_check+0x564>)
a4c: 4798 blx r3
a4e: 2800 cmp r0, #0
a50: f43f aeaf beq.w 7b2 <sd_mmc_check+0x92>
switch (SD_SCR_SD_SPEC(scr)) {
a54: 2304 movs r3, #4
a56: 2238 movs r2, #56 ; 0x38
a58: 2140 movs r1, #64 ; 0x40
a5a: a806 add r0, sp, #24
a5c: 47c8 blx r9
a5e: 42b0 cmp r0, r6
sd_mmc_card->version = CARD_VER_SD_1_0;
a60: f8d4 a000 ldr.w sl, [r4]
switch (SD_SCR_SD_SPEC(scr)) {
a64: f000 80fd beq.w c62 <sd_mmc_check+0x542>
a68: 2802 cmp r0, #2
a6a: f040 80fe bne.w c6a <sd_mmc_check+0x54a>
if (SD_SCR_SD_SPEC3(scr) == SD_SCR_SD_SPEC_3_00) {
a6e: 4633 mov r3, r6
a70: 222f movs r2, #47 ; 0x2f
a72: 2140 movs r1, #64 ; 0x40
a74: a806 add r0, sp, #24
a76: 47c8 blx r9
a78: 2801 cmp r0, #1
sd_mmc_card->version = CARD_VER_SD_3_0;
a7a: bf0c ite eq
a7c: 2330 moveq r3, #48 ; 0x30
sd_mmc_card->version = CARD_VER_SD_2_0;
a7e: 2320 movne r3, #32
a80: e0f0 b.n c64 <sd_mmc_check+0x544>
resp = driver_get_response(sd_mmc_hal);
a82: 68a0 ldr r0, [r4, #8]
a84: 47c8 blx r9
if (!(resp & R1_SPI_IDLE)) {
a86: f010 0201 ands.w r2, r0, #1
a8a: d006 beq.n a9a <sd_mmc_check+0x37a>
if (retry-- == 0) {
a8c: 3e01 subs r6, #1
a8e: f4bf aec6 bcs.w 81e <sd_mmc_check+0xfe>
sd_mmc_spi_debug("%s: CMD1 Timeout on busy\n\r", __func__);
a92: 497d ldr r1, [pc, #500] ; (c88 <sd_mmc_check+0x568>)
a94: 487d ldr r0, [pc, #500] ; (c8c <sd_mmc_check+0x56c>)
sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
a96: 47b8 blx r7
return false;
a98: e68b b.n 7b2 <sd_mmc_check+0x92>
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD58_READ_OCR, 0)) {
a9a: 68a0 ldr r0, [r4, #8]
a9c: f240 513a movw r1, #1338 ; 0x53a
aa0: 47a8 blx r5
aa2: b910 cbnz r0, aaa <sd_mmc_check+0x38a>
sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
aa4: 4978 ldr r1, [pc, #480] ; (c88 <sd_mmc_check+0x568>)
aa6: 487a ldr r0, [pc, #488] ; (c90 <sd_mmc_check+0x570>)
aa8: e7f5 b.n a96 <sd_mmc_check+0x376>
if ((driver_get_response(sd_mmc_hal) & OCR_ACCESS_MODE_MASK)
aaa: 68a0 ldr r0, [r4, #8]
aac: 47c8 blx r9
aae: f000 40c0 and.w r0, r0, #1610612736 ; 0x60000000
ab2: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000
sd_mmc_card->type |= CARD_TYPE_HC;
ab6: bf08 it eq
ab8: 6822 ldreq r2, [r4, #0]
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
aba: 68a0 ldr r0, [r4, #8]
sd_mmc_card->type |= CARD_TYPE_HC;
abc: bf02 ittt eq
abe: 7ad3 ldrbeq r3, [r2, #11]
ac0: f043 0308 orreq.w r3, r3, #8
ac4: 72d3 strbeq r3, [r2, #11]
if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
ac6: f241 113b movw r1, #4411 ; 0x113b
aca: 2200 movs r2, #0
acc: 47a8 blx r5
ace: 2800 cmp r0, #0
ad0: f43f ae6f beq.w 7b2 <sd_mmc_check+0x92>
if (!sd_mmc_cmd9_spi()) {
ad4: 4b66 ldr r3, [pc, #408] ; (c70 <sd_mmc_check+0x550>)
ad6: 4798 blx r3
ad8: 2800 cmp r0, #0
ada: f43f ae6a beq.w 7b2 <sd_mmc_check+0x92>
switch (MMC_CSD_SPEC_VERS(sd_mmc_card->csd)) {
ade: f8d4 9000 ldr.w r9, [r4]
ae2: 4e64 ldr r6, [pc, #400] ; (c74 <sd_mmc_check+0x554>)
ae4: f109 0b0e add.w fp, r9, #14
ae8: 2304 movs r3, #4
aea: 227a movs r2, #122 ; 0x7a
aec: 2180 movs r1, #128 ; 0x80
aee: 4658 mov r0, fp
af0: 47b0 blx r6
af2: 3801 subs r0, #1
af4: 46b2 mov sl, r6
af6: 2803 cmp r0, #3
af8: d803 bhi.n b02 <sd_mmc_check+0x3e2>
afa: e8df f000 tbb [pc, r0]
afe: 9391 .short 0x9391
b00: 9795 .short 0x9795
sd_mmc_card->version = CARD_VER_MMC_1_2;
b02: 2312 movs r3, #18
sd_mmc_card->version = CARD_VER_MMC_4;
b04: f889 300c strb.w r3, [r9, #12]
tran_speed = CSD_TRAN_SPEED(sd_mmc_card->csd);
b08: 2260 movs r2, #96 ; 0x60
b0a: 2308 movs r3, #8
b0c: 2180 movs r1, #128 ; 0x80
b0e: 4658 mov r0, fp
b10: 47d0 blx sl
mul = mmc_trans_multipliers[(tran_speed >> 3) & 0xF];
b12: 4b59 ldr r3, [pc, #356] ; (c78 <sd_mmc_check+0x558>)
b14: f3c0 02c3 ubfx r2, r0, #3, #4
unit = sd_mmc_trans_units[tran_speed & 0x7];
b18: f000 0007 and.w r0, r0, #7
b1c: eb03 0080 add.w r0, r3, r0, lsl #2
mul = mmc_trans_multipliers[(tran_speed >> 3) & 0xF];
b20: eb03 0282 add.w r2, r3, r2, lsl #2
if (MMC_CSD_C_SIZE(sd_mmc_card->csd) != 0xFFF) {
b24: 2180 movs r1, #128 ; 0x80
sd_mmc_card->clock = unit * mul * 1000;
b26: 6a13 ldr r3, [r2, #32]
b28: 6e02 ldr r2, [r0, #96] ; 0x60
b2a: 4353 muls r3, r2
b2c: f44f 727a mov.w r2, #1000 ; 0x3e8
b30: 4353 muls r3, r2
b32: f8c9 3000 str.w r3, [r9]
if (MMC_CSD_C_SIZE(sd_mmc_card->csd) != 0xFFF) {
b36: 223e movs r2, #62 ; 0x3e
b38: 230c movs r3, #12
b3a: 4658 mov r0, fp
b3c: 47d0 blx sl
b3e: f640 73ff movw r3, #4095 ; 0xfff
b42: 4298 cmp r0, r3
b44: 4606 mov r6, r0
b46: d012 beq.n b6e <sd_mmc_check+0x44e>
= ((MMC_CSD_C_SIZE(sd_mmc_card->csd) + 1) * (1 << (MMC_CSD_C_SIZE_MULT(sd_mmc_card->csd) + 2)));
b48: 2303 movs r3, #3
b4a: 222f movs r2, #47 ; 0x2f
b4c: 2180 movs r1, #128 ; 0x80
b4e: 4658 mov r0, fp
b50: 47d0 blx sl
b52: 1c73 adds r3, r6, #1
b54: 3002 adds r0, #2
uint32_t blocknr
b56: fa03 f600 lsl.w r6, r3, r0
sd_mmc_card->capacity = blocknr * (1 << MMC_CSD_READ_BL_LEN(sd_mmc_card->csd)) / 1024;
b5a: 2250 movs r2, #80 ; 0x50
b5c: 2304 movs r3, #4
b5e: 2180 movs r1, #128 ; 0x80
b60: 4658 mov r0, fp
b62: 47d0 blx sl
b64: fa06 f000 lsl.w r0, r6, r0
b68: 0a80 lsrs r0, r0, #10
b6a: f8c9 0004 str.w r0, [r9, #4]
if (sd_mmc_card->version >= CARD_VER_MMC_4) {
b6e: f899 300c ldrb.w r3, [r9, #12]
b72: 2b3f cmp r3, #63 ; 0x3f
b74: d93e bls.n bf4 <sd_mmc_check+0x4d4>
if (!driver_adtc_start(sd_mmc_hal, MMC_CMD8_SEND_EXT_CSD, 0, EXT_CSD_BSIZE, 1, false)) {
b76: 2301 movs r3, #1
b78: 2200 movs r2, #0
b7a: e9cd 3200 strd r3, r2, [sp]
b7e: 4945 ldr r1, [pc, #276] ; (c94 <sd_mmc_check+0x574>)
b80: 68a0 ldr r0, [r4, #8]
b82: 4e45 ldr r6, [pc, #276] ; (c98 <sd_mmc_check+0x578>)
b84: f44f 7300 mov.w r3, #512 ; 0x200
b88: 47b0 blx r6
b8a: 2800 cmp r0, #0
b8c: f43f ae11 beq.w 7b2 <sd_mmc_check+0x92>
if (!driver_read_word(sd_mmc_hal, &ext_csd)) {
b90: f8df b114 ldr.w fp, [pc, #276] ; ca8 <sd_mmc_check+0x588>
b94: 2632 movs r6, #50 ; 0x32
b96: 46d9 mov r9, fp
b98: 68a0 ldr r0, [r4, #8]
b9a: a905 add r1, sp, #20
b9c: 47d8 blx fp
b9e: 2800 cmp r0, #0
ba0: f43f ae07 beq.w 7b2 <sd_mmc_check+0x92>
for (i = 0; i < (EXT_CSD_CARD_TYPE_INDEX + 4) / 4; i++) {
ba4: 3e01 subs r6, #1
ba6: b2b6 uxth r6, r6
ba8: 2e00 cmp r6, #0
baa: d1f5 bne.n b98 <sd_mmc_check+0x478>
if (MMC_CSD_C_SIZE(sd_mmc_card->csd) == 0xFFF) {
bac: 6820 ldr r0, [r4, #0]
bae: 230c movs r3, #12
bb0: 223e movs r2, #62 ; 0x3e
bb2: 2180 movs r1, #128 ; 0x80
bb4: 300e adds r0, #14
bb6: 47d0 blx sl
bb8: f640 73ff movw r3, #4095 ; 0xfff
bbc: 4298 cmp r0, r3
bbe: d137 bne.n c30 <sd_mmc_check+0x510>
bc0: 2604 movs r6, #4
if (!driver_read_word(sd_mmc_hal, &sec_count)) {
bc2: 68a0 ldr r0, [r4, #8]
bc4: a906 add r1, sp, #24
bc6: 47c8 blx r9
bc8: 2800 cmp r0, #0
bca: f43f adf2 beq.w 7b2 <sd_mmc_check+0x92>
for (; i < (EXT_CSD_SEC_COUNT_INDEX + 4) / 4; i++) {
bce: 3e01 subs r6, #1
bd0: b2b6 uxth r6, r6
bd2: 2e00 cmp r6, #0
bd4: d1f5 bne.n bc2 <sd_mmc_check+0x4a2>
sd_mmc_card->capacity = sec_count / 2;
bd6: 9b06 ldr r3, [sp, #24]
bd8: 6822 ldr r2, [r4, #0]
bda: 085b lsrs r3, r3, #1
bdc: 6053 str r3, [r2, #4]
bde: 2636 movs r6, #54 ; 0x36
if (!driver_read_word(sd_mmc_hal, &sec_count)) {
be0: 68a0 ldr r0, [r4, #8]
be2: a906 add r1, sp, #24
be4: 47c8 blx r9
be6: 2800 cmp r0, #0
be8: f43f ade3 beq.w 7b2 <sd_mmc_check+0x92>
for (; i < EXT_CSD_BSIZE / 4; i++) {
bec: 3601 adds r6, #1
bee: b2b6 uxth r6, r6
bf0: 2e80 cmp r6, #128 ; 0x80
bf2: d1f5 bne.n be0 <sd_mmc_check+0x4c0>
if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
bf4: 68a0 ldr r0, [r4, #8]
bf6: f44f 7200 mov.w r2, #512 ; 0x200
bfa: f241 1110 movw r1, #4368 ; 0x1110
bfe: 47a8 blx r5
c00: 2800 cmp r0, #0
c02: f43f add6 beq.w 7b2 <sd_mmc_check+0x92>
if (!sd_mmc_cmd13()) {
c06: 4b25 ldr r3, [pc, #148] ; (c9c <sd_mmc_check+0x57c>)
c08: 4798 blx r3
c0a: 2800 cmp r0, #0
c0c: f43f add1 beq.w 7b2 <sd_mmc_check+0x92>
sd_mmc_configure_slot();
c10: 4b23 ldr r3, [pc, #140] ; (ca0 <sd_mmc_check+0x580>)
c12: 4798 blx r3
sd_mmc_spi_debug("SD/MMC card ready\n\r");
c14: 4823 ldr r0, [pc, #140] ; (ca4 <sd_mmc_check+0x584>)
c16: 47b8 blx r7
sd_mmc_card->state = SD_MMC_CARD_STATE_READY;
c18: 6823 ldr r3, [r4, #0]
c1a: 2200 movs r2, #0
c1c: 729a strb r2, [r3, #10]
sd_mmc_deselect_slot();
c1e: e587 b.n 730 <sd_mmc_check+0x10>
sd_mmc_card->version = CARD_VER_MMC_1_4;
c20: 2314 movs r3, #20
c22: e76f b.n b04 <sd_mmc_check+0x3e4>
sd_mmc_card->version = CARD_VER_MMC_2_2;
c24: 2322 movs r3, #34 ; 0x22
c26: e76d b.n b04 <sd_mmc_check+0x3e4>
sd_mmc_card->version = CARD_VER_MMC_3;
c28: 2330 movs r3, #48 ; 0x30
c2a: e76b b.n b04 <sd_mmc_check+0x3e4>
sd_mmc_card->version = CARD_VER_MMC_4;
c2c: 2340 movs r3, #64 ; 0x40
c2e: e769 b.n b04 <sd_mmc_check+0x3e4>
c30: 2632 movs r6, #50 ; 0x32
c32: e7d5 b.n be0 <sd_mmc_check+0x4c0>
= ((SD_CSD_1_0_C_SIZE(sd_mmc_card->csd) + 1) * (1 << (SD_CSD_1_0_C_SIZE_MULT(sd_mmc_card->csd) + 2)));
c34: 230c movs r3, #12
c36: 223e movs r2, #62 ; 0x3e
c38: 2180 movs r1, #128 ; 0x80
c3a: 4658 mov r0, fp
c3c: 47b0 blx r6
c3e: 2303 movs r3, #3
c40: 4606 mov r6, r0
c42: 222f movs r2, #47 ; 0x2f
c44: 2180 movs r1, #128 ; 0x80
c46: 4658 mov r0, fp
c48: 47c8 blx r9
c4a: 3601 adds r6, #1
c4c: 3002 adds r0, #2
uint32_t blocknr
c4e: 4086 lsls r6, r0
sd_mmc_card->capacity = blocknr * (1 << SD_CSD_1_0_READ_BL_LEN(sd_mmc_card->csd)) / 1024;
c50: 2304 movs r3, #4
c52: 2250 movs r2, #80 ; 0x50
c54: 2180 movs r1, #128 ; 0x80
c56: 4658 mov r0, fp
c58: 47c8 blx r9
c5a: fa06 f000 lsl.w r0, r6, r0
c5e: 0a80 lsrs r0, r0, #10
c60: e6d1 b.n a06 <sd_mmc_check+0x2e6>
sd_mmc_card->version = CARD_VER_SD_1_10;
c62: 231a movs r3, #26
sd_mmc_card->version = CARD_VER_SD_1_0;
c64: f88a 300c strb.w r3, [sl, #12]
break;
c68: e635 b.n 8d6 <sd_mmc_check+0x1b6>
sd_mmc_card->version = CARD_VER_SD_1_0;
c6a: 2310 movs r3, #16
c6c: e7fa b.n c64 <sd_mmc_check+0x544>
c6e: bf00 nop
c70: 000005c1 .word 0x000005c1
c74: 000003f9 .word 0x000003f9
c78: 00002c0c .word 0x00002c0c
c7c: 00081133 .word 0x00081133
c80: 0000125d .word 0x0000125d
c84: 00001309 .word 0x00001309
c88: 00002c1b .word 0x00002c1b
c8c: 00002bda .word 0x00002bda
c90: 00002b91 .word 0x00002b91
c94: 00081108 .word 0x00081108
c98: 00001061 .word 0x00001061
c9c: 0000057d .word 0x0000057d
ca0: 000004a1 .word 0x000004a1
ca4: 00002bf5 .word 0x00002bf5
ca8: 0000130d .word 0x0000130d
for (i = 0; i < 6; i++) {
cac: f106 0906 add.w r9, r6, #6
sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
cb0: 2100 movs r1, #0
cb2: 4653 mov r3, sl
cb4: 4632 mov r2, r6
cb6: 4608 mov r0, r1
addr_new++;
cb8: 3601 adds r6, #1
sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
cba: 47d8 blx fp
for (i = 0; i < 6; i++) {
cbc: 454e cmp r6, r9
cbe: f10a 0a01 add.w sl, sl, #1
cc2: d1f5 bne.n cb0 <sd_mmc_check+0x590>
tplfe_max_tran_speed = buf[5];
cc4: f89d 301d ldrb.w r3, [sp, #29]
unit = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7];
cc8: 490e ldr r1, [pc, #56] ; (d04 <sd_mmc_check+0x5e4>)
sd_mmc_card->clock = unit * mul * 1000;
cca: 6822 ldr r2, [r4, #0]
ccc: 2b32 cmp r3, #50 ; 0x32
cce: bf28 it cs
cd0: 2332 movcs r3, #50 ; 0x32
unit = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7];
cd2: f003 0007 and.w r0, r3, #7
mul = sd_trans_multipliers[(tplfe_max_tran_speed >> 3) & 0xF];
cd6: 08db lsrs r3, r3, #3
unit = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7];
cd8: eb01 0080 add.w r0, r1, r0, lsl #2
mul = sd_trans_multipliers[(tplfe_max_tran_speed >> 3) & 0xF];
cdc: eb01 0183 add.w r1, r1, r3, lsl #2
sd_mmc_card->clock = unit * mul * 1000;
ce0: 6e03 ldr r3, [r0, #96] ; 0x60
ce2: 6fc9 ldr r1, [r1, #124] ; 0x7c
ce4: 434b muls r3, r1
ce6: f44f 717a mov.w r1, #1000 ; 0x3e8
cea: 434b muls r3, r1
cec: 6013 str r3, [r2, #0]
return true;
cee: e5f6 b.n 8de <sd_mmc_check+0x1be>
if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
cf0: 68a0 ldr r0, [r4, #8]
cf2: f44f 7200 mov.w r2, #512 ; 0x200
cf6: f241 1110 movw r1, #4368 ; 0x1110
cfa: 47a8 blx r5
cfc: 2800 cmp r0, #0
cfe: f47f adf5 bne.w 8ec <sd_mmc_check+0x1cc>
d02: e556 b.n 7b2 <sd_mmc_check+0x92>
d04: 00002c0c .word 0x00002c0c
00000d08 <sd_mmc_get_type>:
card_type_t sd_mmc_get_type(uint8_t slot)
{
d08: b508 push {r3, lr}
if (SD_MMC_OK != sd_mmc_select_slot(slot)) {
d0a: 4b05 ldr r3, [pc, #20] ; (d20 <sd_mmc_get_type+0x18>)
d0c: 4798 blx r3
d0e: b928 cbnz r0, d1c <sd_mmc_get_type+0x14>
return CARD_TYPE_UNKNOWN;
}
sd_mmc_deselect_slot();
d10: 4b04 ldr r3, [pc, #16] ; (d24 <sd_mmc_get_type+0x1c>)
d12: 4798 blx r3
return sd_mmc_card->type;
d14: 4b04 ldr r3, [pc, #16] ; (d28 <sd_mmc_get_type+0x20>)
d16: 681b ldr r3, [r3, #0]
d18: 7ad8 ldrb r0, [r3, #11]
}
d1a: bd08 pop {r3, pc}
return CARD_TYPE_UNKNOWN;
d1c: 2000 movs r0, #0
d1e: e7fc b.n d1a <sd_mmc_get_type+0x12>
d20: 000004c9 .word 0x000004c9
d24: 00000611 .word 0x00000611
d28: 20000290 .word 0x20000290
00000d2c <sd_mmc_init_read_blocks>:
}
return false;
}
sd_mmc_err_t sd_mmc_init_read_blocks(uint8_t slot, uint32_t start, uint16_t nb_block)
{
d2c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
sd_mmc_err_t sd_mmc_err;
uint32_t cmd, arg, resp;
sd_mmc_err = sd_mmc_select_slot(slot);
d2e: 4b17 ldr r3, [pc, #92] ; (d8c <sd_mmc_init_read_blocks+0x60>)
{
d30: 460f mov r7, r1
d32: 4614 mov r4, r2
sd_mmc_err = sd_mmc_select_slot(slot);
d34: 4798 blx r3
if (sd_mmc_err != SD_MMC_OK) {
d36: 4605 mov r5, r0
d38: b928 cbnz r0, d46 <sd_mmc_init_read_blocks+0x1a>
return sd_mmc_err;
}
/* Wait for data ready status */
if (!sd_mmc_cmd13()) {
d3a: 4b15 ldr r3, [pc, #84] ; (d90 <sd_mmc_init_read_blocks+0x64>)
d3c: 4798 blx r3
d3e: b928 cbnz r0, d4c <sd_mmc_init_read_blocks+0x20>
sd_mmc_deselect_slot();
d40: 4b14 ldr r3, [pc, #80] ; (d94 <sd_mmc_init_read_blocks+0x68>)
d42: 4798 blx r3
return SD_MMC_ERR_COMM;
d44: 2505 movs r5, #5
}
sd_mmc_nb_block_remaining = nb_block;
sd_mmc_nb_block_to_tranfer = nb_block;
return SD_MMC_OK;
}
d46: 4628 mov r0, r5
d48: b003 add sp, #12
d4a: bdf0 pop {r4, r5, r6, r7, pc}
cmd = SDMMC_CMD17_READ_SINGLE_BLOCK;
d4c: 4b12 ldr r3, [pc, #72] ; (d98 <sd_mmc_init_read_blocks+0x6c>)
if (sd_mmc_card->type & CARD_TYPE_HC) {
d4e: 4e13 ldr r6, [pc, #76] ; (d9c <sd_mmc_init_read_blocks+0x70>)
cmd = SDMMC_CMD17_READ_SINGLE_BLOCK;
d50: 4913 ldr r1, [pc, #76] ; (da0 <sd_mmc_init_read_blocks+0x74>)
if (!driver_adtc_start(sd_mmc_hal, cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) {
d52: 68b0 ldr r0, [r6, #8]
cmd = SDMMC_CMD17_READ_SINGLE_BLOCK;
d54: 2c01 cmp r4, #1
d56: bf98 it ls
d58: 4619 movls r1, r3
if (sd_mmc_card->type & CARD_TYPE_HC) {
d5a: 6833 ldr r3, [r6, #0]
d5c: 7adb ldrb r3, [r3, #11]
d5e: 071b lsls r3, r3, #28
arg = (start * SD_MMC_BLOCK_SIZE);
d60: bf58 it pl
d62: 027f lslpl r7, r7, #9
if (!driver_adtc_start(sd_mmc_hal, cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) {
d64: 2301 movs r3, #1
d66: e9cd 4300 strd r4, r3, [sp]
d6a: 463a mov r2, r7
d6c: f44f 7300 mov.w r3, #512 ; 0x200
d70: 4f0c ldr r7, [pc, #48] ; (da4 <sd_mmc_init_read_blocks+0x78>)
d72: 47b8 blx r7
d74: 2800 cmp r0, #0
d76: d0e3 beq.n d40 <sd_mmc_init_read_blocks+0x14>
resp = driver_get_response(sd_mmc_hal);
d78: 4b0b ldr r3, [pc, #44] ; (da8 <sd_mmc_init_read_blocks+0x7c>)
d7a: 68b0 ldr r0, [r6, #8]
d7c: 4798 blx r3
if (resp & CARD_STATUS_ERR_RD_WR) {
d7e: 4b0b ldr r3, [pc, #44] ; (dac <sd_mmc_init_read_blocks+0x80>)
d80: 4003 ands r3, r0
d82: 2b00 cmp r3, #0
d84: d1dc bne.n d40 <sd_mmc_init_read_blocks+0x14>
sd_mmc_nb_block_remaining = nb_block;
d86: 8634 strh r4, [r6, #48] ; 0x30
sd_mmc_nb_block_to_tranfer = nb_block;
d88: 8734 strh r4, [r6, #56] ; 0x38
return SD_MMC_OK;
d8a: e7dc b.n d46 <sd_mmc_init_read_blocks+0x1a>
d8c: 000004c9 .word 0x000004c9
d90: 0000057d .word 0x0000057d
d94: 00000611 .word 0x00000611
d98: 00081111 .word 0x00081111
d9c: 20000290 .word 0x20000290
da0: 00101112 .word 0x00101112
da4: 00001061 .word 0x00001061
da8: 000013b9 .word 0x000013b9
dac: e4580000 .word 0xe4580000
00000db0 <sd_mmc_start_read_blocks>:
sd_mmc_err_t sd_mmc_start_read_blocks(void *dest, uint16_t nb_block)
{
db0: b5f8 push {r3, r4, r5, r6, r7, lr}
assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
db2: 4d0e ldr r5, [pc, #56] ; (dec <sd_mmc_start_read_blocks+0x3c>)
db4: 4a0e ldr r2, [pc, #56] ; (df0 <sd_mmc_start_read_blocks+0x40>)
db6: 4f0f ldr r7, [pc, #60] ; (df4 <sd_mmc_start_read_blocks+0x44>)
{
db8: 4606 mov r6, r0
assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
dba: 8e28 ldrh r0, [r5, #48] ; 0x30
{
dbc: 460c mov r4, r1
assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
dbe: 42a0 cmp r0, r4
dc0: bf34 ite cc
dc2: 2000 movcc r0, #0
dc4: 2001 movcs r0, #1
dc6: 490c ldr r1, [pc, #48] ; (df8 <sd_mmc_start_read_blocks+0x48>)
dc8: f44f 63d9 mov.w r3, #1736 ; 0x6c8
dcc: 47b8 blx r7
if (!driver_start_read_blocks(sd_mmc_hal, dest, nb_block)) {
dce: 68a8 ldr r0, [r5, #8]
dd0: 4b0a ldr r3, [pc, #40] ; (dfc <sd_mmc_start_read_blocks+0x4c>)
dd2: 4622 mov r2, r4
dd4: 4631 mov r1, r6
dd6: 4798 blx r3
dd8: b128 cbz r0, de6 <sd_mmc_start_read_blocks+0x36>
sd_mmc_nb_block_remaining = 0;
return SD_MMC_ERR_COMM;
}
sd_mmc_nb_block_remaining -= nb_block;
dda: 8e28 ldrh r0, [r5, #48] ; 0x30
ddc: 1b01 subs r1, r0, r4
dde: b289 uxth r1, r1
return SD_MMC_OK;
de0: 2000 movs r0, #0
de2: 8629 strh r1, [r5, #48] ; 0x30
}
de4: bdf8 pop {r3, r4, r5, r6, r7, pc}
sd_mmc_nb_block_remaining = 0;
de6: 4601 mov r1, r0
return SD_MMC_ERR_COMM;
de8: 2005 movs r0, #5
dea: e7fa b.n de2 <sd_mmc_start_read_blocks+0x32>
dec: 20000290 .word 0x20000290
df0: 00002b12 .word 0x00002b12
df4: 00002169 .word 0x00002169
df8: 00002b25 .word 0x00002b25
dfc: 0000125d .word 0x0000125d
00000e00 <sd_mmc_wait_end_of_read_blocks>:
sd_mmc_err_t sd_mmc_wait_end_of_read_blocks(bool abort)
{
e00: b538 push {r3, r4, r5, lr}
if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
e02: 4d12 ldr r5, [pc, #72] ; (e4c <sd_mmc_wait_end_of_read_blocks+0x4c>)
e04: 4b12 ldr r3, [pc, #72] ; (e50 <sd_mmc_wait_end_of_read_blocks+0x50>)
{
e06: 4604 mov r4, r0
if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
e08: 68a8 ldr r0, [r5, #8]
e0a: 4798 blx r3
e0c: b1e0 cbz r0, e48 <sd_mmc_wait_end_of_read_blocks+0x48>
return SD_MMC_ERR_COMM;
}
if (abort) {
e0e: b144 cbz r4, e22 <sd_mmc_wait_end_of_read_blocks+0x22>
sd_mmc_nb_block_remaining = 0;
e10: 2300 movs r3, #0
e12: 862b strh r3, [r5, #48] ; 0x30
} else if (sd_mmc_nb_block_remaining) {
return SD_MMC_OK;
}
/* All blocks are transfered then stop read operation */
if (sd_mmc_nb_block_to_tranfer == 1) {
e14: 8f2b ldrh r3, [r5, #56] ; 0x38
e16: 2b01 cmp r3, #1
e18: d108 bne.n e2c <sd_mmc_wait_end_of_read_blocks+0x2c>
/* Single block transfer, then nothing to do */
sd_mmc_deselect_slot();
e1a: 4b0e ldr r3, [pc, #56] ; (e54 <sd_mmc_wait_end_of_read_blocks+0x54>)
e1c: 4798 blx r3
return SD_MMC_OK;
e1e: 2000 movs r0, #0
if (!driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0)) {
driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0);
}
sd_mmc_deselect_slot();
return SD_MMC_OK;
}
e20: bd38 pop {r3, r4, r5, pc}
} else if (sd_mmc_nb_block_remaining) {
e22: 8e2b ldrh r3, [r5, #48] ; 0x30
e24: 2b00 cmp r3, #0
e26: d0f5 beq.n e14 <sd_mmc_wait_end_of_read_blocks+0x14>
return SD_MMC_OK;
e28: 4620 mov r0, r4
e2a: e7f9 b.n e20 <sd_mmc_wait_end_of_read_blocks+0x20>
if (!driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0)) {
e2c: 2200 movs r2, #0
e2e: 68a8 ldr r0, [r5, #8]
e30: 4c09 ldr r4, [pc, #36] ; (e58 <sd_mmc_wait_end_of_read_blocks+0x58>)
e32: f243 110c movw r1, #12556 ; 0x310c
e36: 47a0 blx r4
e38: 4602 mov r2, r0
e3a: 2800 cmp r0, #0
e3c: d1ed bne.n e1a <sd_mmc_wait_end_of_read_blocks+0x1a>
driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0);
e3e: 68a8 ldr r0, [r5, #8]
e40: f243 110c movw r1, #12556 ; 0x310c
e44: 47a0 blx r4
e46: e7e8 b.n e1a <sd_mmc_wait_end_of_read_blocks+0x1a>
return SD_MMC_ERR_COMM;
e48: 2005 movs r0, #5
e4a: e7e9 b.n e20 <sd_mmc_wait_end_of_read_blocks+0x20>
e4c: 20000290 .word 0x20000290
e50: 00001309 .word 0x00001309
e54: 00000611 .word 0x00000611
e58: 00001249 .word 0x00001249
00000e5c <sdio_read_extended>:
return SD_MMC_OK;
}
sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *dest,
uint16_t size)
{
e5c: b570 push {r4, r5, r6, lr}
e5e: b086 sub sp, #24
e60: e9cd 2104 strd r2, r1, [sp, #16]
e64: f8bd 502c ldrh.w r5, [sp, #44] ; 0x2c
e68: 9303 str r3, [sp, #12]
sd_mmc_err_t sd_mmc_err;
if ((size == 0) || (size > 512)) {
e6a: 1e6c subs r4, r5, #1
e6c: f5b4 7f00 cmp.w r4, #512 ; 0x200
e70: d21f bcs.n eb2 <sdio_read_extended+0x56>
return SD_MMC_ERR_PARAM;
}
sd_mmc_err = sd_mmc_select_slot(slot);
e72: 4c11 ldr r4, [pc, #68] ; (eb8 <sdio_read_extended+0x5c>)
e74: 47a0 blx r4
if (sd_mmc_err != SD_MMC_OK) {
e76: 4604 mov r4, r0
e78: b948 cbnz r0, e8e <sdio_read_extended+0x32>
return sd_mmc_err;
}
if (!sdio_cmd53(SDIO_CMD53_READ_FLAG, func_num, addr, inc_addr, size, true)) {
e7a: 9500 str r5, [sp, #0]
e7c: e9dd 3203 ldrd r3, r2, [sp, #12]
e80: 4d0e ldr r5, [pc, #56] ; (ebc <sdio_read_extended+0x60>)
e82: 9905 ldr r1, [sp, #20]
e84: 47a8 blx r5
e86: 4d0e ldr r5, [pc, #56] ; (ec0 <sdio_read_extended+0x64>)
e88: b920 cbnz r0, e94 <sdio_read_extended+0x38>
sd_mmc_deselect_slot();
e8a: 47a8 blx r5
return SD_MMC_ERR_COMM;
e8c: 2405 movs r4, #5
return SD_MMC_ERR_COMM;
}
sd_mmc_deselect_slot();
return SD_MMC_OK;
}
e8e: 4620 mov r0, r4
e90: b006 add sp, #24
e92: bd70 pop {r4, r5, r6, pc}
if (!driver_start_read_blocks(sd_mmc_hal, dest, 1)) {
e94: 4e0b ldr r6, [pc, #44] ; (ec4 <sdio_read_extended+0x68>)
e96: 990a ldr r1, [sp, #40] ; 0x28
e98: 68b0 ldr r0, [r6, #8]
e9a: 4b0b ldr r3, [pc, #44] ; (ec8 <sdio_read_extended+0x6c>)
e9c: 2201 movs r2, #1
e9e: 4798 blx r3
ea0: 2800 cmp r0, #0
ea2: d0f2 beq.n e8a <sdio_read_extended+0x2e>
if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
ea4: 68b0 ldr r0, [r6, #8]
ea6: 4b09 ldr r3, [pc, #36] ; (ecc <sdio_read_extended+0x70>)
ea8: 4798 blx r3
eaa: 2800 cmp r0, #0
eac: d0ed beq.n e8a <sdio_read_extended+0x2e>
sd_mmc_deselect_slot();
eae: 47a8 blx r5
return SD_MMC_OK;
eb0: e7ed b.n e8e <sdio_read_extended+0x32>
return SD_MMC_ERR_PARAM;
eb2: 2406 movs r4, #6
eb4: e7eb b.n e8e <sdio_read_extended+0x32>
eb6: bf00 nop
eb8: 000004c9 .word 0x000004c9
ebc: 00000629 .word 0x00000629
ec0: 00000611 .word 0x00000611
ec4: 20000290 .word 0x20000290
ec8: 0000125d .word 0x0000125d
ecc: 00001309 .word 0x00001309
00000ed0 <spi_m_sync_wait_busy>:
crc = (crc << 1) | 1;
return crc;
}
static bool spi_m_sync_wait_busy(struct spi_m_sync_descriptor* spi)
{
ed0: b573 push {r0, r1, r4, r5, r6, lr}
uint8_t line = 0xFF;
ed2: 23ff movs r3, #255 ; 0xff
ed4: f88d 3002 strb.w r3, [sp, #2]
uint8_t dummy = 0xFF;
ed8: f88d 3003 strb.w r3, [sp, #3]
/* Delay before check busy
* Nbr timing minimum = 8 cylces
*/
struct io_descriptor* spi_inst = NULL;
edc: 2300 movs r3, #0
ede: 9301 str r3, [sp, #4]
spi_m_sync_get_io_descriptor(spi, &spi_inst);
ee0: a901 add r1, sp, #4
ee2: 4b17 ldr r3, [pc, #92] ; (f40 <spi_m_sync_wait_busy+0x70>)
io_write(spi_inst, &dummy, 1);
ee4: 4d17 ldr r5, [pc, #92] ; (f44 <spi_m_sync_wait_busy+0x74>)
io_read(spi_inst, &line, 1);
ee6: 4e18 ldr r6, [pc, #96] ; (f48 <spi_m_sync_wait_busy+0x78>)
* However a timeout is used.
* 200 000 * 8 cycles
*/
uint32_t nec_timeout = 200000;
io_write(spi_inst, &dummy, 1);
io_read(spi_inst, &line, 1);
ee8: 4c18 ldr r4, [pc, #96] ; (f4c <spi_m_sync_wait_busy+0x7c>)
spi_m_sync_get_io_descriptor(spi, &spi_inst);
eea: 4798 blx r3
io_write(spi_inst, &dummy, 1);
eec: 2201 movs r2, #1
eee: f10d 0103 add.w r1, sp, #3
ef2: 9801 ldr r0, [sp, #4]
ef4: 47a8 blx r5
io_read(spi_inst, &line, 1);
ef6: 2201 movs r2, #1
ef8: f10d 0102 add.w r1, sp, #2
efc: 9801 ldr r0, [sp, #4]
efe: 47b0 blx r6
io_write(spi_inst, &dummy, 1);
f00: 2201 movs r2, #1
f02: f10d 0103 add.w r1, sp, #3
f06: 9801 ldr r0, [sp, #4]
f08: 47a8 blx r5
io_read(spi_inst, &line, 1);
f0a: 9801 ldr r0, [sp, #4]
f0c: 2201 movs r2, #1
f0e: f10d 0102 add.w r1, sp, #2
f12: 47b0 blx r6
do {
io_write(spi_inst, &dummy, 1);
f14: 2201 movs r2, #1
f16: f10d 0103 add.w r1, sp, #3
f1a: 9801 ldr r0, [sp, #4]
f1c: 47a8 blx r5
io_read(spi_inst, &line, 1);
f1e: 9801 ldr r0, [sp, #4]
f20: 2201 movs r2, #1
f22: f10d 0102 add.w r1, sp, #2
f26: 47b0 blx r6
if (!(nec_timeout--)) {
f28: 3c01 subs r4, #1
f2a: d006 beq.n f3a <spi_m_sync_wait_busy+0x6a>
return false;
}
} while (line != 0xFF);
f2c: f89d 3002 ldrb.w r3, [sp, #2]
f30: 2bff cmp r3, #255 ; 0xff
f32: d1ef bne.n f14 <spi_m_sync_wait_busy+0x44>
return true;
f34: 2001 movs r0, #1
}
f36: b002 add sp, #8
f38: bd70 pop {r4, r5, r6, pc}
return false;
f3a: 4620 mov r0, r4
f3c: e7fb b.n f36 <spi_m_sync_wait_busy+0x66>
f3e: bf00 nop
f40: 00001521 .word 0x00001521
f44: 000002a5 .word 0x000002a5
f48: 000002d5 .word 0x000002d5
f4c: 00030d41 .word 0x00030d41
00000f50 <spi_m_sync_stop_read_block>:
return true;
}
static void spi_m_sync_stop_read_block(struct spi_m_sync_descriptor* spi)
{
f50: b51f push {r0, r1, r2, r3, r4, lr}
struct io_descriptor* spi_inst = NULL;
f52: 2300 movs r3, #0
f54: 9303 str r3, [sp, #12]
spi_m_sync_get_io_descriptor(spi, &spi_inst);
f56: a903 add r1, sp, #12
f58: 4b09 ldr r3, [pc, #36] ; (f80 <spi_m_sync_stop_read_block+0x30>)
f5a: 4798 blx r3
uint8_t crc[2];
uint8_t dummy = 0xFF;
f5c: 23ff movs r3, #255 ; 0xff
f5e: f88d 3007 strb.w r3, [sp, #7]
// Read 16-bit CRC (not cheked)
io_write(spi_inst, &dummy, 1);
f62: f10d 0107 add.w r1, sp, #7
f66: 9803 ldr r0, [sp, #12]
f68: 4b06 ldr r3, [pc, #24] ; (f84 <spi_m_sync_stop_read_block+0x34>)
f6a: 2201 movs r2, #1
f6c: 4798 blx r3
io_read(spi_inst, crc, 2);
f6e: 9803 ldr r0, [sp, #12]
f70: 4b05 ldr r3, [pc, #20] ; (f88 <spi_m_sync_stop_read_block+0x38>)
f72: 2202 movs r2, #2
f74: a902 add r1, sp, #8
f76: 4798 blx r3
}
f78: b005 add sp, #20
f7a: f85d fb04 ldr.w pc, [sp], #4
f7e: bf00 nop
f80: 00001521 .word 0x00001521
f84: 000002a5 .word 0x000002a5
f88: 000002d5 .word 0x000002d5
00000f8c <spi_m_sync_start_read_block>:
{
f8c: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
spi_m_sync_get_io_descriptor(spi, &spi_inst);
f90: 4b26 ldr r3, [pc, #152] ; (102c <spi_m_sync_start_read_block+0xa0>)
assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
f92: 4d27 ldr r5, [pc, #156] ; (1030 <spi_m_sync_start_read_block+0xa4>)
io_write(spi_inst, &dummy, 1);
f94: 4e27 ldr r6, [pc, #156] ; (1034 <spi_m_sync_start_read_block+0xa8>)
io_read(spi_inst, &token, 1);
f96: f8df 80c4 ldr.w r8, [pc, #196] ; 105c <spi_m_sync_start_read_block+0xd0>
struct io_descriptor* spi_inst = NULL;
f9a: 2400 movs r4, #0
spi_m_sync_get_io_descriptor(spi, &spi_inst);
f9c: a901 add r1, sp, #4
struct io_descriptor* spi_inst = NULL;
f9e: 9401 str r4, [sp, #4]
spi_m_sync_get_io_descriptor(spi, &spi_inst);
fa0: 4798 blx r3
assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
fa2: 4a25 ldr r2, [pc, #148] ; (1038 <spi_m_sync_start_read_block+0xac>)
fa4: 4925 ldr r1, [pc, #148] ; (103c <spi_m_sync_start_read_block+0xb0>)
fa6: 6810 ldr r0, [r2, #0]
uint8_t dummy = 0xFF;
fa8: 23ff movs r3, #255 ; 0xff
faa: f88d 3003 strb.w r3, [sp, #3]
assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
fae: 8893 ldrh r3, [r2, #4]
fb0: fbb0 f2f3 udiv r2, r0, r3
fb4: fb03 0012 mls r0, r3, r2, r0
fb8: fab0 f080 clz r0, r0
fbc: 4a20 ldr r2, [pc, #128] ; (1040 <spi_m_sync_start_read_block+0xb4>)
fbe: 23b3 movs r3, #179 ; 0xb3
fc0: 0940 lsrs r0, r0, #5
fc2: 47a8 blx r5
token = 0;
fc4: f88d 4002 strb.w r4, [sp, #2]
fc8: 4c1e ldr r4, [pc, #120] ; (1044 <spi_m_sync_start_read_block+0xb8>)
if (i-- == 0) {
fca: 3c01 subs r4, #1
fcc: d105 bne.n fda <spi_m_sync_start_read_block+0x4e>
sd_mmc_spi_debug("%s: Read blocks timeout\n\r", __func__);
fce: 491e ldr r1, [pc, #120] ; (1048 <spi_m_sync_start_read_block+0xbc>)
fd0: 481e ldr r0, [pc, #120] ; (104c <spi_m_sync_start_read_block+0xc0>)
fd2: 4b1f ldr r3, [pc, #124] ; (1050 <spi_m_sync_start_read_block+0xc4>)
sd_mmc_spi_debug("%s: Out of range data error token\n\r", __func__);
fd4: 4798 blx r3
return false;
fd6: 4620 mov r0, r4
fd8: e01f b.n 101a <spi_m_sync_start_read_block+0x8e>
io_write(spi_inst, &dummy, 1);
fda: 2201 movs r2, #1
fdc: f10d 0103 add.w r1, sp, #3
fe0: 9801 ldr r0, [sp, #4]
fe2: 47b0 blx r6
io_read(spi_inst, &token, 1);
fe4: 9801 ldr r0, [sp, #4]
fe6: 2201 movs r2, #1
fe8: f10d 0102 add.w r1, sp, #2
fec: 47c0 blx r8
if (SPI_TOKEN_DATA_ERROR_VALID(token)) {
fee: f89d 0002 ldrb.w r0, [sp, #2]
ff2: f010 07f0 ands.w r7, r0, #240 ; 0xf0
ff6: d115 bne.n 1024 <spi_m_sync_start_read_block+0x98>
assert(SPI_TOKEN_DATA_ERROR_ERRORS & token, ">>>");
ff8: 3800 subs r0, #0
ffa: bf18 it ne
ffc: 2001 movne r0, #1
ffe: 490f ldr r1, [pc, #60] ; (103c <spi_m_sync_start_read_block+0xb0>)
1000: 4a0f ldr r2, [pc, #60] ; (1040 <spi_m_sync_start_read_block+0xb4>)
1002: 23c9 movs r3, #201 ; 0xc9
1004: 47a8 blx r5
if (token & (SPI_TOKEN_DATA_ERROR_ERROR
1006: f89d 0002 ldrb.w r0, [sp, #2]
sd_mmc_spi_debug("%s: CRC data error token\n\r", __func__);
100a: 490f ldr r1, [pc, #60] ; (1048 <spi_m_sync_start_read_block+0xbc>)
100c: 4b10 ldr r3, [pc, #64] ; (1050 <spi_m_sync_start_read_block+0xc4>)
if (token & (SPI_TOKEN_DATA_ERROR_ERROR
100e: f010 0407 ands.w r4, r0, #7
1012: d005 beq.n 1020 <spi_m_sync_start_read_block+0x94>
sd_mmc_spi_debug("%s: CRC data error token\n\r", __func__);
1014: 480f ldr r0, [pc, #60] ; (1054 <spi_m_sync_start_read_block+0xc8>)
1016: 4798 blx r3
return false;
1018: 4638 mov r0, r7
}
101a: b002 add sp, #8
101c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
sd_mmc_spi_debug("%s: Out of range data error token\n\r", __func__);
1020: 480d ldr r0, [pc, #52] ; (1058 <spi_m_sync_start_read_block+0xcc>)
1022: e7d7 b.n fd4 <spi_m_sync_start_read_block+0x48>
} while (token != SPI_TOKEN_SINGLE_MULTI_READ);
1024: 28fe cmp r0, #254 ; 0xfe
1026: d1d0 bne.n fca <spi_m_sync_start_read_block+0x3e>
return true;
1028: 2001 movs r0, #1
102a: e7f6 b.n 101a <spi_m_sync_start_read_block+0x8e>
102c: 00001521 .word 0x00001521
1030: 00002169 .word 0x00002169
1034: 000002a5 .word 0x000002a5
1038: 200002cc .word 0x200002cc
103c: 00002b25 .word 0x00002b25
1040: 00002cc8 .word 0x00002cc8
1044: 0007a121 .word 0x0007a121
1048: 00002f1f .word 0x00002f1f
104c: 00002cdf .word 0x00002cdf
1050: 000020d5 .word 0x000020d5
1054: 00002cf9 .word 0x00002cf9
1058: 00002d14 .word 0x00002d14
105c: 000002d5 .word 0x000002d5
00001060 <spi_m_sync_adtc_start>:
return spi_m_sync_adtc_start(spi, cmd, arg, 0, 0, false);
}
bool spi_m_sync_adtc_start(struct spi_m_sync_descriptor* spi,
uint32_t cmd, uint32_t arg, uint16_t block_size,
uint16_t nb_block, bool access_block)
{
1060: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
1064: b089 sub sp, #36 ; 0x24
1066: 460e mov r6, r1
struct io_descriptor* spi_inst = NULL;
1068: 2400 movs r4, #0
{
106a: 9302 str r3, [sp, #8]
spi_m_sync_get_io_descriptor(spi, &spi_inst);
106c: a905 add r1, sp, #20
106e: 4b66 ldr r3, [pc, #408] ; (1208 <spi_m_sync_adtc_start+0x1a8>)
struct io_descriptor* spi_inst = NULL;
1070: 9405 str r4, [sp, #20]
{
1072: 4615 mov r5, r2
1074: 4682 mov sl, r0
spi_m_sync_get_io_descriptor(spi, &spi_inst);
1076: 4798 blx r3
uint8_t dummy = 0xFF;
1078: 23ff movs r3, #255 ; 0xff
uint8_t ncr_timeout;
uint8_t r1;
uint8_t dummy2 = 0xFF;
(void)access_block;
assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
107a: 4a64 ldr r2, [pc, #400] ; (120c <spi_m_sync_adtc_start+0x1ac>)
107c: 4f64 ldr r7, [pc, #400] ; (1210 <spi_m_sync_adtc_start+0x1b0>)
uint8_t dummy = 0xFF;
107e: f88d 3011 strb.w r3, [sp, #17]
uint8_t dummy2 = 0xFF;
1082: f88d 3013 strb.w r3, [sp, #19]
assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
1086: 4963 ldr r1, [pc, #396] ; (1214 <spi_m_sync_adtc_start+0x1b4>)
1088: 23f7 movs r3, #247 ; 0xf7
108a: f3c6 2000 ubfx r0, r6, #8, #1
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
108e: f006 093f and.w r9, r6, #63 ; 0x3f
assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
1092: 47b8 blx r7
cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
1094: f049 0340 orr.w r3, r9, #64 ; 0x40
1098: f88d 3018 strb.w r3, [sp, #24]
cmd_token[1] = arg >> 24;
109c: 0e2b lsrs r3, r5, #24
109e: f88d 3019 strb.w r3, [sp, #25]
cmd_token[2] = arg >> 16;
10a2: 0c2b lsrs r3, r5, #16
10a4: f88d 301a strb.w r3, [sp, #26]
cmd_token[3] = arg >> 8;
cmd_token[4] = arg;
10a8: af06 add r7, sp, #24
cmd_token[3] = arg >> 8;
10aa: 0a2b lsrs r3, r5, #8
10ac: f88d 301b strb.w r3, [sp, #27]
cmd_token[4] = arg;
10b0: f88d 501c strb.w r5, [sp, #28]
crc = 0;
10b4: 4623 mov r3, r4
cmd_token[4] = arg;
10b6: 2206 movs r2, #6
10b8: 463c mov r4, r7
while (size--) {
10ba: 3a01 subs r2, #1
10bc: f012 02ff ands.w r2, r2, #255 ; 0xff
10c0: d12f bne.n 1122 <spi_m_sync_adtc_start+0xc2>
crc = (crc << 1) | 1;
10c2: 005b lsls r3, r3, #1
10c4: f043 0301 orr.w r3, r3, #1
cmd_token[5] = spi_m_sync_crc7(cmd_token, 5);
// 8 cycles to respect Ncs timing
io_write(spi_inst, &dummy, 1);
10c8: f8df 8174 ldr.w r8, [pc, #372] ; 1240 <spi_m_sync_adtc_start+0x1e0>
10cc: 9805 ldr r0, [sp, #20]
cmd_token[5] = spi_m_sync_crc7(cmd_token, 5);
10ce: f88d 301d strb.w r3, [sp, #29]
io_write(spi_inst, &dummy, 1);
10d2: 2201 movs r2, #1
10d4: f10d 0111 add.w r1, sp, #17
10d8: 47c0 blx r8
// send command
io_write(spi_inst, cmd_token, sizeof(cmd_token));
10da: 4621 mov r1, r4
10dc: 2206 movs r2, #6
10de: 9805 ldr r0, [sp, #20]
// Two retries will be done to manage the Ncr timing between command and response
// Ncr: Min. 1x8 clock cycle, Max 8x8 clock cycles
// WORKAROUND for no compliance (Atmel Internal ref. SD13)
r1 = 0xFF;
// Ignore first byte because Ncr min. = 8 clock cycles
io_read(spi_inst, &r1, 1);
10e0: 4f4d ldr r7, [pc, #308] ; (1218 <spi_m_sync_adtc_start+0x1b8>)
io_write(spi_inst, cmd_token, sizeof(cmd_token));
10e2: 47c0 blx r8
r1 = 0xFF;
10e4: 23ff movs r3, #255 ; 0xff
io_read(spi_inst, &r1, 1);
10e6: 9805 ldr r0, [sp, #20]
r1 = 0xFF;
10e8: f88d 3012 strb.w r3, [sp, #18]
io_read(spi_inst, &r1, 1);
10ec: 2201 movs r2, #1
10ee: f10d 0112 add.w r1, sp, #18
10f2: 47b8 blx r7
10f4: 2407 movs r4, #7
ncr_timeout = 7;
while(1)
{
io_read(spi_inst, &r1, 1);
10f6: 2201 movs r2, #1
10f8: 9805 ldr r0, [sp, #20]
10fa: f10d 0112 add.w r1, sp, #18
10fe: 47b8 blx r7
if((r1 & R1_SPI_ERROR) == 0)
1100: f99d 3012 ldrsb.w r3, [sp, #18]
1104: f89d 2012 ldrb.w r2, [sp, #18]
1108: 2b00 cmp r3, #0
110a: da1e bge.n 114a <spi_m_sync_adtc_start+0xea>
{
// Valid response
break;
}
if(--ncr_timeout == 0)
110c: 3c01 subs r4, #1
110e: f014 04ff ands.w r4, r4, #255 ; 0xff
1112: d1f0 bne.n 10f6 <spi_m_sync_adtc_start+0x96>
{
// Here valid r1 response received
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lX, R1 timeout\r\n",
1114: 4941 ldr r1, [pc, #260] ; (121c <spi_m_sync_adtc_start+0x1bc>)
1116: 4842 ldr r0, [pc, #264] ; (1220 <spi_m_sync_adtc_start+0x1c0>)
1118: 462b mov r3, r5
111a: 464a mov r2, r9
// Manage other responses
if (cmd & SDMMC_RESP_BUSY) {
if (!spi_m_sync_wait_busy(spi)) {
sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_BUSY_TIMEOUT;
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, Busy signal always high\n\r",
111c: 4d41 ldr r5, [pc, #260] ; (1224 <spi_m_sync_adtc_start+0x1c4>)
111e: 47a8 blx r5
__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
return false;
1120: e023 b.n 116a <spi_m_sync_adtc_start+0x10a>
value = *buf++;
1122: f817 0b01 ldrb.w r0, [r7], #1
1126: 2108 movs r1, #8
crc <<= 1;
1128: 005b lsls r3, r3, #1
112a: b2db uxtb r3, r3
if ((value & 0x80) ^ (crc & 0x80)) {
112c: ea83 0c00 eor.w ip, r3, r0
1130: f01c 0f80 tst.w ip, #128 ; 0x80
for (i = 0; i < 8; i++) {
1134: f101 31ff add.w r1, r1, #4294967295 ; 0xffffffff
crc ^= 0x09;
1138: bf18 it ne
113a: f083 0309 eorne.w r3, r3, #9
value <<= 1;
113e: 0040 lsls r0, r0, #1
for (i = 0; i < 8; i++) {
1140: f011 01ff ands.w r1, r1, #255 ; 0xff
value <<= 1;
1144: b2c0 uxtb r0, r0
for (i = 0; i < 8; i++) {
1146: d1ef bne.n 1128 <spi_m_sync_adtc_start+0xc8>
1148: e7b7 b.n 10ba <spi_m_sync_adtc_start+0x5a>
sd_mmc_spi_response_32 = r1;
114a: f8df b0f8 ldr.w fp, [pc, #248] ; 1244 <spi_m_sync_adtc_start+0x1e4>
if (r1 & R1_SPI_COM_CRC)
114e: f012 0308 ands.w r3, r2, #8
sd_mmc_spi_response_32 = r1;
1152: f8cb 2008 str.w r2, [fp, #8]
if (r1 & R1_SPI_COM_CRC)
1156: 9303 str r3, [sp, #12]
1158: d00b beq.n 1172 <spi_m_sync_adtc_start+0x112>
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%02x, R1_SPI_COM_CRC\n\r",
115a: 4930 ldr r1, [pc, #192] ; (121c <spi_m_sync_adtc_start+0x1bc>)
115c: 4832 ldr r0, [pc, #200] ; (1228 <spi_m_sync_adtc_start+0x1c8>)
115e: 9200 str r2, [sp, #0]
1160: 462b mov r3, r5
1162: 464a mov r2, r9
1164: 4c2f ldr r4, [pc, #188] ; (1224 <spi_m_sync_adtc_start+0x1c4>)
1166: 47a0 blx r4
return false;
1168: 2400 movs r4, #0
sd_mmc_spi_block_size = block_size;
sd_mmc_spi_nb_block = nb_block;
sd_mmc_spi_transfert_pos = 0;
return true;
}
116a: 4620 mov r0, r4
116c: b009 add sp, #36 ; 0x24
116e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
if (r1 & R1_SPI_ILLEGAL_COMMAND)
1172: f012 0404 ands.w r4, r2, #4
1176: d005 beq.n 1184 <spi_m_sync_adtc_start+0x124>
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 ILLEGAL_COMMAND\n\r",
1178: 9200 str r2, [sp, #0]
117a: 4928 ldr r1, [pc, #160] ; (121c <spi_m_sync_adtc_start+0x1bc>)
117c: 482b ldr r0, [pc, #172] ; (122c <spi_m_sync_adtc_start+0x1cc>)
117e: 462b mov r3, r5
1180: 464a mov r2, r9
1182: e7ef b.n 1164 <spi_m_sync_adtc_start+0x104>
if (r1 & ~R1_SPI_IDLE) {
1184: f012 0ffe tst.w r2, #254 ; 0xfe
1188: d007 beq.n 119a <spi_m_sync_adtc_start+0x13a>
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 error\n\r",
118a: 9200 str r2, [sp, #0]
118c: 462b mov r3, r5
118e: 4923 ldr r1, [pc, #140] ; (121c <spi_m_sync_adtc_start+0x1bc>)
1190: 4d24 ldr r5, [pc, #144] ; (1224 <spi_m_sync_adtc_start+0x1c4>)
1192: 4827 ldr r0, [pc, #156] ; (1230 <spi_m_sync_adtc_start+0x1d0>)
1194: 464a mov r2, r9
1196: 47a8 blx r5
return false;
1198: e7e7 b.n 116a <spi_m_sync_adtc_start+0x10a>
if (cmd & SDMMC_RESP_BUSY) {
119a: 04b1 lsls r1, r6, #18
119c: d509 bpl.n 11b2 <spi_m_sync_adtc_start+0x152>
if (!spi_m_sync_wait_busy(spi)) {
119e: 4a25 ldr r2, [pc, #148] ; (1234 <spi_m_sync_adtc_start+0x1d4>)
11a0: 4650 mov r0, sl
11a2: 4790 blx r2
11a4: 4604 mov r4, r0
11a6: b920 cbnz r0, 11b2 <spi_m_sync_adtc_start+0x152>
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, Busy signal always high\n\r",
11a8: 491c ldr r1, [pc, #112] ; (121c <spi_m_sync_adtc_start+0x1bc>)
11aa: 4823 ldr r0, [pc, #140] ; (1238 <spi_m_sync_adtc_start+0x1d8>)
11ac: 462b mov r3, r5
11ae: 464a mov r2, r9
11b0: e7b4 b.n 111c <spi_m_sync_adtc_start+0xbc>
if (cmd & SDMMC_RESP_8) {
11b2: 05b2 lsls r2, r6, #22
11b4: d50b bpl.n 11ce <spi_m_sync_adtc_start+0x16e>
sd_mmc_spi_response_32 = 0;
11b6: 2200 movs r2, #0
11b8: f8cb 2008 str.w r2, [fp, #8]
io_write(spi_inst, &dummy2, 1);
11bc: f10d 0113 add.w r1, sp, #19
11c0: 2201 movs r2, #1
11c2: 9805 ldr r0, [sp, #20]
11c4: 47c0 blx r8
io_read(spi_inst, (uint8_t*)&sd_mmc_spi_response_32, 1);
11c6: 491d ldr r1, [pc, #116] ; (123c <spi_m_sync_adtc_start+0x1dc>)
11c8: 9805 ldr r0, [sp, #20]
11ca: 2201 movs r2, #1
11cc: 47b8 blx r7
if (cmd & SDMMC_RESP_32) {
11ce: 0573 lsls r3, r6, #21
11d0: d50d bpl.n 11ee <spi_m_sync_adtc_start+0x18e>
io_write(spi_inst, &dummy2, 1);
11d2: 2201 movs r2, #1
11d4: f10d 0113 add.w r1, sp, #19
11d8: 9805 ldr r0, [sp, #20]
11da: 47c0 blx r8
io_read(spi_inst, (uint8_t*)&sd_mmc_spi_response_32, 4);
11dc: 2204 movs r2, #4
11de: 4917 ldr r1, [pc, #92] ; (123c <spi_m_sync_adtc_start+0x1dc>)
11e0: 9805 ldr r0, [sp, #20]
11e2: 47b8 blx r7
sd_mmc_spi_response_32 = BE32(sd_mmc_spi_response_32);
11e4: f8db 2008 ldr.w r2, [fp, #8]
11e8: ba12 rev r2, r2
11ea: f8cb 2008 str.w r2, [fp, #8]
sd_mmc_spi_nb_block = nb_block;
11ee: f8bd 2048 ldrh.w r2, [sp, #72] ; 0x48
sd_mmc_spi_block_size = block_size;
11f2: 9b02 ldr r3, [sp, #8]
sd_mmc_spi_nb_block = nb_block;
11f4: f8ab 2006 strh.w r2, [fp, #6]
sd_mmc_spi_transfert_pos = 0;
11f8: 2200 movs r2, #0
sd_mmc_spi_block_size = block_size;
11fa: f8ab 3004 strh.w r3, [fp, #4]
sd_mmc_spi_transfert_pos = 0;
11fe: f8cb 2000 str.w r2, [fp]
return true;
1202: 2401 movs r4, #1
1204: e7b1 b.n 116a <spi_m_sync_adtc_start+0x10a>
1206: bf00 nop
1208: 00001521 .word 0x00001521
120c: 00002cc8 .word 0x00002cc8
1210: 00002169 .word 0x00002169
1214: 00002de1 .word 0x00002de1
1218: 000002d5 .word 0x000002d5
121c: 00002f78 .word 0x00002f78
1220: 00002e04 .word 0x00002e04
1224: 000020d5 .word 0x000020d5
1228: 00002e2c .word 0x00002e2c
122c: 00002e63 .word 0x00002e63
1230: 00002e9c .word 0x00002e9c
1234: 00000ed1 .word 0x00000ed1
1238: 00002ecb .word 0x00002ecb
123c: 200002d4 .word 0x200002d4
1240: 000002a5 .word 0x000002a5
1244: 200002cc .word 0x200002cc
00001248 <spi_m_sync_send_cmd>:
{
1248: b513 push {r0, r1, r4, lr}
return spi_m_sync_adtc_start(spi, cmd, arg, 0, 0, false);
124a: 2300 movs r3, #0
124c: e9cd 3300 strd r3, r3, [sp]
1250: 4c01 ldr r4, [pc, #4] ; (1258 <spi_m_sync_send_cmd+0x10>)
1252: 47a0 blx r4
}
1254: b002 add sp, #8
1256: bd10 pop {r4, pc}
1258: 00001061 .word 0x00001061
0000125c <spi_m_sync_start_read_blocks>:
bool spi_m_sync_start_read_blocks(struct spi_m_sync_descriptor* spi,
void *dst, uint16_t nb_block)
{
125c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
struct io_descriptor* spi_inst = NULL;
spi_m_sync_get_io_descriptor(spi, &spi_inst);
1260: 4b20 ldr r3, [pc, #128] ; (12e4 <spi_m_sync_start_read_blocks+0x88>)
uint8_t dummy = 0xFF;
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
pos = 0;
while (nb_block--) {
assert(sd_mmc_spi_nb_block >
1262: 4d21 ldr r5, [pc, #132] ; (12e8 <spi_m_sync_start_read_blocks+0x8c>)
1264: f8df 9094 ldr.w r9, [pc, #148] ; 12fc <spi_m_sync_start_read_blocks+0xa0>
1268: f8df a094 ldr.w sl, [pc, #148] ; 1300 <spi_m_sync_start_read_blocks+0xa4>
{
126c: 4688 mov r8, r1
struct io_descriptor* spi_inst = NULL;
126e: 2600 movs r6, #0
spi_m_sync_get_io_descriptor(spi, &spi_inst);
1270: a901 add r1, sp, #4
{
1272: 4607 mov r7, r0
1274: 4614 mov r4, r2
struct io_descriptor* spi_inst = NULL;
1276: 9601 str r6, [sp, #4]
spi_m_sync_get_io_descriptor(spi, &spi_inst);
1278: 4798 blx r3
uint8_t dummy = 0xFF;
127a: 23ff movs r3, #255 ; 0xff
127c: f88d 3003 strb.w r3, [sp, #3]
while (nb_block--) {
1280: b91c cbnz r4, 128a <spi_m_sync_start_read_blocks+0x2e>
pos += sd_mmc_spi_block_size;
sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
spi_m_sync_stop_read_block(spi);
}
return true;
1282: 2001 movs r0, #1
}
1284: b003 add sp, #12
1286: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
assert(sd_mmc_spi_nb_block >
128a: f8b5 c006 ldrh.w ip, [r5, #6]
128e: 682b ldr r3, [r5, #0]
1290: 88a8 ldrh r0, [r5, #4]
1292: fbb3 f0f0 udiv r0, r3, r0
1296: 4584 cmp ip, r0
1298: bf94 ite ls
129a: 2000 movls r0, #0
129c: 2001 movhi r0, #1
129e: f44f 73b2 mov.w r3, #356 ; 0x164
12a2: 464a mov r2, r9
12a4: 4651 mov r1, sl
12a6: f8df b05c ldr.w fp, [pc, #92] ; 1304 <spi_m_sync_start_read_blocks+0xa8>
12aa: 47d8 blx fp
if (!spi_m_sync_start_read_block(spi)) {
12ac: 4b0f ldr r3, [pc, #60] ; (12ec <spi_m_sync_start_read_blocks+0x90>)
12ae: 4638 mov r0, r7
12b0: 4798 blx r3
12b2: 3c01 subs r4, #1
12b4: b2a4 uxth r4, r4
12b6: 2800 cmp r0, #0
12b8: d0e4 beq.n 1284 <spi_m_sync_start_read_blocks+0x28>
io_write(spi_inst, &dummy, 1);
12ba: f10d 0103 add.w r1, sp, #3
12be: 9801 ldr r0, [sp, #4]
12c0: 4b0b ldr r3, [pc, #44] ; (12f0 <spi_m_sync_start_read_blocks+0x94>)
12c2: 2201 movs r2, #1
12c4: 4798 blx r3
io_read(spi_inst, &((uint8_t*)dst)[pos], sd_mmc_spi_block_size);
12c6: 88aa ldrh r2, [r5, #4]
12c8: 9801 ldr r0, [sp, #4]
12ca: 4b0a ldr r3, [pc, #40] ; (12f4 <spi_m_sync_start_read_blocks+0x98>)
12cc: eb08 0106 add.w r1, r8, r6
12d0: 4798 blx r3
pos += sd_mmc_spi_block_size;
12d2: 88aa ldrh r2, [r5, #4]
sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
12d4: 682b ldr r3, [r5, #0]
12d6: 4413 add r3, r2
12d8: 602b str r3, [r5, #0]
spi_m_sync_stop_read_block(spi);
12da: 4638 mov r0, r7
12dc: 4b06 ldr r3, [pc, #24] ; (12f8 <spi_m_sync_start_read_blocks+0x9c>)
pos += sd_mmc_spi_block_size;
12de: 4416 add r6, r2
spi_m_sync_stop_read_block(spi);
12e0: 4798 blx r3
12e2: e7cd b.n 1280 <spi_m_sync_start_read_blocks+0x24>
12e4: 00001521 .word 0x00001521
12e8: 200002cc .word 0x200002cc
12ec: 00000f8d .word 0x00000f8d
12f0: 000002a5 .word 0x000002a5
12f4: 000002d5 .word 0x000002d5
12f8: 00000f51 .word 0x00000f51
12fc: 00002cc8 .word 0x00002cc8
1300: 00002b25 .word 0x00002b25
1304: 00002169 .word 0x00002169
00001308 <spi_m_sync_wait_end_of_read_blocks>:
}
bool spi_m_sync_wait_end_of_read_blocks(struct spi_m_sync_descriptor* spi)
{
return true;
}
1308: 2001 movs r0, #1
130a: 4770 bx lr
0000130c <spi_m_sync_read_word>:
}
return spi_m_sync_stop_multiwrite_block(spi);
}
bool spi_m_sync_read_word(struct spi_m_sync_descriptor* spi, uint32_t* value)
{
130c: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
struct io_descriptor* spi_inst = NULL;
spi_m_sync_get_io_descriptor(spi, &spi_inst);
uint8_t dummy = 0xFF;
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
assert(sd_mmc_spi_nb_block >
130e: 4c21 ldr r4, [pc, #132] ; (1394 <spi_m_sync_read_word+0x88>)
{
1310: 9101 str r1, [sp, #4]
struct io_descriptor* spi_inst = NULL;
1312: 2300 movs r3, #0
1314: 9303 str r3, [sp, #12]
spi_m_sync_get_io_descriptor(spi, &spi_inst);
1316: a903 add r1, sp, #12
1318: 4b1f ldr r3, [pc, #124] ; (1398 <spi_m_sync_read_word+0x8c>)
{
131a: 4605 mov r5, r0
spi_m_sync_get_io_descriptor(spi, &spi_inst);
131c: 4798 blx r3
assert(sd_mmc_spi_nb_block >
131e: 88e6 ldrh r6, [r4, #6]
1320: 88a0 ldrh r0, [r4, #4]
1322: 4a1e ldr r2, [pc, #120] ; (139c <spi_m_sync_read_word+0x90>)
1324: 491e ldr r1, [pc, #120] ; (13a0 <spi_m_sync_read_word+0x94>)
uint8_t dummy = 0xFF;
1326: 23ff movs r3, #255 ; 0xff
1328: f88d 300b strb.w r3, [sp, #11]
assert(sd_mmc_spi_nb_block >
132c: 6823 ldr r3, [r4, #0]
132e: fbb3 f0f0 udiv r0, r3, r0
1332: 4286 cmp r6, r0
1334: f44f 73e7 mov.w r3, #462 ; 0x1ce
1338: 4e1a ldr r6, [pc, #104] ; (13a4 <spi_m_sync_read_word+0x98>)
133a: bf94 ite ls
133c: 2000 movls r0, #0
133e: 2001 movhi r0, #1
1340: 47b0 blx r6
(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size),
">>>");
if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
1342: 88a2 ldrh r2, [r4, #4]
1344: 6823 ldr r3, [r4, #0]
1346: fbb3 f1f2 udiv r1, r3, r2
134a: fb02 3311 mls r3, r2, r1, r3
134e: b1b3 cbz r3, 137e <spi_m_sync_read_word+0x72>
if (!spi_m_sync_start_read_block(spi)) {
return false;
}
}
// Read data
io_write(spi_inst, &dummy, 1);
1350: 4b15 ldr r3, [pc, #84] ; (13a8 <spi_m_sync_read_word+0x9c>)
1352: 9803 ldr r0, [sp, #12]
1354: 2201 movs r2, #1
1356: f10d 010b add.w r1, sp, #11
135a: 4798 blx r3
io_read(spi_inst, (uint8_t*)&value, 4);
135c: 2204 movs r2, #4
135e: eb0d 0102 add.w r1, sp, r2
1362: 4b12 ldr r3, [pc, #72] ; (13ac <spi_m_sync_read_word+0xa0>)
1364: 9803 ldr r0, [sp, #12]
1366: 4798 blx r3
*value = LE32(*value);
sd_mmc_spi_transfert_pos += 4;
1368: 6823 ldr r3, [r4, #0]
if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
136a: 88a2 ldrh r2, [r4, #4]
sd_mmc_spi_transfert_pos += 4;
136c: 3304 adds r3, #4
136e: 6023 str r3, [r4, #0]
if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
1370: fbb3 f1f2 udiv r1, r3, r2
1374: fb02 3311 mls r3, r2, r1, r3
1378: b143 cbz r3, 138c <spi_m_sync_read_word+0x80>
// End of block
spi_m_sync_stop_read_block(spi);
}
return true;}
137a: 2001 movs r0, #1
137c: e004 b.n 1388 <spi_m_sync_read_word+0x7c>
if (!spi_m_sync_start_read_block(spi)) {
137e: 4b0c ldr r3, [pc, #48] ; (13b0 <spi_m_sync_read_word+0xa4>)
1380: 4628 mov r0, r5
1382: 4798 blx r3
1384: 2800 cmp r0, #0
1386: d1e3 bne.n 1350 <spi_m_sync_read_word+0x44>
return true;}
1388: b004 add sp, #16
138a: bd70 pop {r4, r5, r6, pc}
spi_m_sync_stop_read_block(spi);
138c: 4b09 ldr r3, [pc, #36] ; (13b4 <spi_m_sync_read_word+0xa8>)
138e: 4628 mov r0, r5
1390: 4798 blx r3
1392: e7f2 b.n 137a <spi_m_sync_read_word+0x6e>
1394: 200002cc .word 0x200002cc
1398: 00001521 .word 0x00001521
139c: 00002cc8 .word 0x00002cc8
13a0: 00002b25 .word 0x00002b25
13a4: 00002169 .word 0x00002169
13a8: 000002a5 .word 0x000002a5
13ac: 000002d5 .word 0x000002d5
13b0: 00000f8d .word 0x00000f8d
13b4: 00000f51 .word 0x00000f51
000013b8 <spi_m_sync_get_response>:
uint32_t spi_m_sync_get_response(struct spi_m_sync_descriptor* spi)
{
return sd_mmc_spi_response_32;
}
13b8: 4b01 ldr r3, [pc, #4] ; (13c0 <spi_m_sync_get_response+0x8>)
13ba: 6898 ldr r0, [r3, #8]
13bc: 4770 bx lr
13be: bf00 nop
13c0: 200002cc .word 0x200002cc
000013c4 <spi_m_sync_send_clock>:
void spi_m_sync_send_clock(struct spi_m_sync_descriptor* spi)
{
13c4: b537 push {r0, r1, r2, r4, r5, lr}
struct io_descriptor* spi_inst = NULL;
13c6: 2300 movs r3, #0
13c8: 9301 str r3, [sp, #4]
spi_m_sync_get_io_descriptor(spi, &spi_inst);
13ca: a901 add r1, sp, #4
13cc: 4b08 ldr r3, [pc, #32] ; (13f0 <spi_m_sync_send_clock+0x2c>)
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
// Send 80 cycles
for(i = 0; i < 10; i++)
{
io_write(spi_inst, &dummy, 1); // 8 cycles
13ce: 4d09 ldr r5, [pc, #36] ; (13f4 <spi_m_sync_send_clock+0x30>)
spi_m_sync_get_io_descriptor(spi, &spi_inst);
13d0: 4798 blx r3
uint8_t dummy = 0xFF;
13d2: 23ff movs r3, #255 ; 0xff
13d4: f88d 3003 strb.w r3, [sp, #3]
13d8: 240a movs r4, #10
io_write(spi_inst, &dummy, 1); // 8 cycles
13da: 9801 ldr r0, [sp, #4]
13dc: 2201 movs r2, #1
13de: f10d 0103 add.w r1, sp, #3
for(i = 0; i < 10; i++)
13e2: 3c01 subs r4, #1
io_write(spi_inst, &dummy, 1); // 8 cycles
13e4: 47a8 blx r5
for(i = 0; i < 10; i++)
13e6: f014 04ff ands.w r4, r4, #255 ; 0xff
13ea: d1f6 bne.n 13da <spi_m_sync_send_clock+0x16>
}
}
13ec: b003 add sp, #12
13ee: bd30 pop {r4, r5, pc}
13f0: 00001521 .word 0x00001521
13f4: 000002a5 .word 0x000002a5
000013f8 <spi_m_sync_select_device>:
int32_t spi_m_sync_select_device(struct spi_m_sync_descriptor* spi, uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed)
{
UNUSED(bus_width);
UNUSED(high_speed);
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
PORT->Group[SPI_CS_PORT].OUT.reg &= ~(1 << SPI_CS_PIN);
13f8: 4a04 ldr r2, [pc, #16] ; (140c <spi_m_sync_select_device+0x14>)
13fa: f8d2 3090 ldr.w r3, [r2, #144] ; 0x90
13fe: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
1402: f8c2 3090 str.w r3, [r2, #144] ; 0x90
return 0;
}
1406: 2000 movs r0, #0
1408: 4770 bx lr
140a: bf00 nop
140c: 41008000 .word 0x41008000
00001410 <spi_m_sync_deselect_device>:
int32_t spi_m_sync_deselect_device(struct spi_m_sync_descriptor* spi, uint8_t slot)
{
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
PORT->Group[1].OUT.reg |= (1 << SPI_CS_PIN);
1410: 4a04 ldr r2, [pc, #16] ; (1424 <spi_m_sync_deselect_device+0x14>)
1412: f8d2 3090 ldr.w r3, [r2, #144] ; 0x90
1416: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
141a: f8c2 3090 str.w r3, [r2, #144] ; 0x90
return 0;
}
141e: 2000 movs r0, #0
1420: 4770 bx lr
1422: bf00 nop
1424: 41008000 .word 0x41008000
00001428 <spi_m_sync_init>:
ASSERT(spi);
spi->func = (struct _spi_m_sync_hpl_interface *)func;
}
int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw)
{
1428: b538 push {r3, r4, r5, lr}
142a: 460d mov r5, r1
int32_t rc = 0;
ASSERT(spi && hw);
142c: 4604 mov r4, r0
142e: b110 cbz r0, 1436 <spi_m_sync_init+0xe>
1430: 1e08 subs r0, r1, #0
1432: bf18 it ne
1434: 2001 movne r0, #1
1436: 490a ldr r1, [pc, #40] ; (1460 <spi_m_sync_init+0x38>)
1438: 4b0a ldr r3, [pc, #40] ; (1464 <spi_m_sync_init+0x3c>)
143a: 2240 movs r2, #64 ; 0x40
143c: 4798 blx r3
spi->dev.prvt = (void *)hw;
143e: 4620 mov r0, r4
rc = _spi_m_sync_init(&spi->dev, hw);
1440: 4b09 ldr r3, [pc, #36] ; (1468 <spi_m_sync_init+0x40>)
spi->dev.prvt = (void *)hw;
1442: f840 5f04 str.w r5, [r0, #4]!
rc = _spi_m_sync_init(&spi->dev, hw);
1446: 4629 mov r1, r5
1448: 4798 blx r3
if (rc < 0) {
144a: 2800 cmp r0, #0
144c: db07 blt.n 145e <spi_m_sync_init+0x36>
return rc;
}
spi->flags = SPI_DEACTIVATE_NEXT;
144e: f44f 4300 mov.w r3, #32768 ; 0x8000
1452: 82a3 strh r3, [r4, #20]
spi->io.read = _spi_m_sync_io_read;
1454: 4b05 ldr r3, [pc, #20] ; (146c <spi_m_sync_init+0x44>)
1456: 6123 str r3, [r4, #16]
spi->io.write = _spi_m_sync_io_write;
1458: 4b05 ldr r3, [pc, #20] ; (1470 <spi_m_sync_init+0x48>)
145a: 60e3 str r3, [r4, #12]
return ERR_NONE;
145c: 2000 movs r0, #0
}
145e: bd38 pop {r3, r4, r5, pc}
1460: 00002fe6 .word 0x00002fe6
1464: 00001605 .word 0x00001605
1468: 00001ea5 .word 0x00001ea5
146c: 000014e9 .word 0x000014e9
1470: 000014b1 .word 0x000014b1
00001474 <spi_m_sync_transfer>:
return spi_m_sync_transfer(spi, &xfer);
}
int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer)
{
1474: b530 push {r4, r5, lr}
1476: 460c mov r4, r1
1478: b085 sub sp, #20
struct spi_msg msg;
ASSERT(spi && p_xfer);
147a: 4605 mov r5, r0
147c: b110 cbz r0, 1484 <spi_m_sync_transfer+0x10>
147e: 1e08 subs r0, r1, #0
1480: bf18 it ne
1482: 2001 movne r0, #1
1484: 22b3 movs r2, #179 ; 0xb3
1486: 4907 ldr r1, [pc, #28] ; (14a4 <spi_m_sync_transfer+0x30>)
1488: 4b07 ldr r3, [pc, #28] ; (14a8 <spi_m_sync_transfer+0x34>)
148a: 4798 blx r3
msg.txbuf = p_xfer->txbuf;
148c: 6823 ldr r3, [r4, #0]
148e: 9301 str r3, [sp, #4]
msg.rxbuf = p_xfer->rxbuf;
1490: 6863 ldr r3, [r4, #4]
1492: 9302 str r3, [sp, #8]
msg.size = p_xfer->size;
1494: 68a3 ldr r3, [r4, #8]
1496: 9303 str r3, [sp, #12]
return _spi_m_sync_trans(&spi->dev, &msg);
1498: a901 add r1, sp, #4
149a: 4b04 ldr r3, [pc, #16] ; (14ac <spi_m_sync_transfer+0x38>)
149c: 1d28 adds r0, r5, #4
149e: 4798 blx r3
}
14a0: b005 add sp, #20
14a2: bd30 pop {r4, r5, pc}
14a4: 00002fe6 .word 0x00002fe6
14a8: 00001605 .word 0x00001605
14ac: 00001fd9 .word 0x00001fd9
000014b0 <_spi_m_sync_io_write>:
{
14b0: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
ASSERT(io);
14b2: 4604 mov r4, r0
14b4: 3800 subs r0, #0
14b6: bf18 it ne
14b8: 2001 movne r0, #1
{
14ba: 460e mov r6, r1
14bc: 4615 mov r5, r2
ASSERT(io);
14be: 4907 ldr r1, [pc, #28] ; (14dc <_spi_m_sync_io_write+0x2c>)
14c0: 4b07 ldr r3, [pc, #28] ; (14e0 <_spi_m_sync_io_write+0x30>)
14c2: 22a3 movs r2, #163 ; 0xa3
14c4: 4798 blx r3
xfer.rxbuf = 0;
14c6: 2300 movs r3, #0
xfer.txbuf = (uint8_t *)buf;
14c8: e9cd 6301 strd r6, r3, [sp, #4]
return spi_m_sync_transfer(spi, &xfer);
14cc: a901 add r1, sp, #4
14ce: 4b05 ldr r3, [pc, #20] ; (14e4 <_spi_m_sync_io_write+0x34>)
xfer.size = length;
14d0: 9503 str r5, [sp, #12]
return spi_m_sync_transfer(spi, &xfer);
14d2: f1a4 000c sub.w r0, r4, #12
14d6: 4798 blx r3
}
14d8: b004 add sp, #16
14da: bd70 pop {r4, r5, r6, pc}
14dc: 00002fe6 .word 0x00002fe6
14e0: 00001605 .word 0x00001605
14e4: 00001475 .word 0x00001475
000014e8 <_spi_m_sync_io_read>:
{
14e8: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
ASSERT(io);
14ea: 4604 mov r4, r0
14ec: 3800 subs r0, #0
14ee: bf18 it ne
14f0: 2001 movne r0, #1
{
14f2: 460e mov r6, r1
14f4: 4615 mov r5, r2
ASSERT(io);
14f6: 4907 ldr r1, [pc, #28] ; (1514 <_spi_m_sync_io_read+0x2c>)
14f8: 4b07 ldr r3, [pc, #28] ; (1518 <_spi_m_sync_io_read+0x30>)
14fa: 2287 movs r2, #135 ; 0x87
14fc: 4798 blx r3
xfer.txbuf = 0;
14fe: 2300 movs r3, #0
1500: 9301 str r3, [sp, #4]
return spi_m_sync_transfer(spi, &xfer);
1502: a901 add r1, sp, #4
1504: 4b05 ldr r3, [pc, #20] ; (151c <_spi_m_sync_io_read+0x34>)
xfer.rxbuf = buf;
1506: 9602 str r6, [sp, #8]
return spi_m_sync_transfer(spi, &xfer);
1508: f1a4 000c sub.w r0, r4, #12
xfer.size = length;
150c: 9503 str r5, [sp, #12]
return spi_m_sync_transfer(spi, &xfer);
150e: 4798 blx r3
}
1510: b004 add sp, #16
1512: bd70 pop {r4, r5, r6, pc}
1514: 00002fe6 .word 0x00002fe6
1518: 00001605 .word 0x00001605
151c: 00001475 .word 0x00001475
00001520 <spi_m_sync_get_io_descriptor>:
int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io)
{
1520: b538 push {r3, r4, r5, lr}
1522: 460d mov r5, r1
ASSERT(spi && io);
1524: 4604 mov r4, r0
1526: b110 cbz r0, 152e <spi_m_sync_get_io_descriptor+0xe>
1528: 1e08 subs r0, r1, #0
152a: bf18 it ne
152c: 2001 movne r0, #1
152e: 4904 ldr r1, [pc, #16] ; (1540 <spi_m_sync_get_io_descriptor+0x20>)
1530: 4b04 ldr r3, [pc, #16] ; (1544 <spi_m_sync_get_io_descriptor+0x24>)
1532: 22bd movs r2, #189 ; 0xbd
*io = &spi->io;
1534: 340c adds r4, #12
ASSERT(spi && io);
1536: 4798 blx r3
*io = &spi->io;
1538: 602c str r4, [r5, #0]
return 0;
}
153a: 2000 movs r0, #0
153c: bd38 pop {r3, r4, r5, pc}
153e: bf00 nop
1540: 00002fe6 .word 0x00002fe6
1544: 00001605 .word 0x00001605
00001548 <mci_sync_init>:
/**
* \brief Initialize MCI low level driver.
*/
int32_t mci_sync_init(struct mci_sync_desc *mci, void *hw)
{
1548: b570 push {r4, r5, r6, lr}
154a: 460d mov r5, r1
ASSERT(mci && hw);
154c: 4604 mov r4, r0
154e: b110 cbz r0, 1556 <mci_sync_init+0xe>
1550: 1e08 subs r0, r1, #0
1552: bf18 it ne
1554: 2001 movne r0, #1
1556: 4905 ldr r1, [pc, #20] ; (156c <mci_sync_init+0x24>)
1558: 4b05 ldr r3, [pc, #20] ; (1570 <mci_sync_init+0x28>)
155a: 2231 movs r2, #49 ; 0x31
155c: 4798 blx r3
return _mci_sync_init(&mci->device, hw);
155e: 4629 mov r1, r5
1560: 4620 mov r0, r4
1562: 4b04 ldr r3, [pc, #16] ; (1574 <mci_sync_init+0x2c>)
}
1564: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return _mci_sync_init(&mci->device, hw);
1568: 4718 bx r3
156a: bf00 nop
156c: 00003002 .word 0x00003002
1570: 00001605 .word 0x00001605
1574: 00001649 .word 0x00001649
00001578 <delay_init>:
/**
* \brief Initialize Delay driver
*/
void delay_init(void *const hw)
{
_delay_init(hardware = hw);
1578: 4b01 ldr r3, [pc, #4] ; (1580 <delay_init+0x8>)
157a: 6018 str r0, [r3, #0]
157c: 4b01 ldr r3, [pc, #4] ; (1584 <delay_init+0xc>)
157e: 4718 bx r3
1580: 200002d8 .word 0x200002d8
1584: 00000305 .word 0x00000305
00001588 <_init_chip>:
}
static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
{
NVMCTRL_CRITICAL_SECTION_ENTER();
((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
1588: 4a0a ldr r2, [pc, #40] ; (15b4 <_init_chip+0x2c>)
158a: 8813 ldrh r3, [r2, #0]
158c: b29b uxth r3, r3
/**
* \brief Initialize the hardware abstraction layer
*/
void _init_chip(void)
{
158e: b510 push {r4, lr}
1590: f443 63a0 orr.w r3, r3, #1280 ; 0x500
1594: 8013 strh r3, [r2, #0]
hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
_osc32kctrl_init_sources();
1596: 4b08 ldr r3, [pc, #32] ; (15b8 <_init_chip+0x30>)
1598: 4798 blx r3
_oscctrl_init_sources();
159a: 4b08 ldr r3, [pc, #32] ; (15bc <_init_chip+0x34>)
159c: 4798 blx r3
_mclk_init();
159e: 4b08 ldr r3, [pc, #32] ; (15c0 <_init_chip+0x38>)
15a0: 4798 blx r3
#if _GCLK_INIT_1ST
_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
#endif
_oscctrl_init_referenced_generators();
15a2: 4b08 ldr r3, [pc, #32] ; (15c4 <_init_chip+0x3c>)
15a4: 4798 blx r3
#endif
#if CONF_CMCC_ENABLE
cache_init();
#endif
}
15a6: e8bd 4010 ldmia.w sp!, {r4, lr}
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
15aa: 4b07 ldr r3, [pc, #28] ; (15c8 <_init_chip+0x40>)
15ac: f640 70ff movw r0, #4095 ; 0xfff
15b0: 4718 bx r3
15b2: bf00 nop
15b4: 41004000 .word 0x41004000
15b8: 00001911 .word 0x00001911
15bc: 0000160b .word 0x0000160b
15c0: 0000180d .word 0x0000180d
15c4: 0000160d .word 0x0000160d
15c8: 000015cd .word 0x000015cd
000015cc <_gclk_init_generators_by_fref>:
void _gclk_init_generators_by_fref(uint32_t bm)
{
#if CONF_GCLK_GENERATOR_0_CONFIG == 1
if (bm & (1ul << 0)) {
15cc: 07c2 lsls r2, r0, #31
15ce: d507 bpl.n 15e0 <_gclk_init_generators_by_fref+0x14>
}
static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg = data;
15d0: 4b09 ldr r3, [pc, #36] ; (15f8 <_gclk_init_generators_by_fref+0x2c>)
15d2: 4a0a ldr r2, [pc, #40] ; (15fc <_gclk_init_generators_by_fref+0x30>)
15d4: 621a str r2, [r3, #32]
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
15d6: f643 72fd movw r2, #16381 ; 0x3ffd
15da: 6859 ldr r1, [r3, #4]
15dc: 4211 tst r1, r2
15de: d1fc bne.n 15da <_gclk_init_generators_by_fref+0xe>
| (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_3_CONFIG == 1
if (bm & (1ul << 3)) {
15e0: 0703 lsls r3, r0, #28
15e2: d507 bpl.n 15f4 <_gclk_init_generators_by_fref+0x28>
((Gclk *)hw)->GENCTRL[index].reg = data;
15e4: 4b04 ldr r3, [pc, #16] ; (15f8 <_gclk_init_generators_by_fref+0x2c>)
15e6: 4a06 ldr r2, [pc, #24] ; (1600 <_gclk_init_generators_by_fref+0x34>)
15e8: 62da str r2, [r3, #44] ; 0x2c
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
15ea: f643 72fd movw r2, #16381 ; 0x3ffd
15ee: 6859 ldr r1, [r3, #4]
15f0: 4211 tst r1, r2
15f2: d1fc bne.n 15ee <_gclk_init_generators_by_fref+0x22>
| (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
}
#endif
}
15f4: 4770 bx lr
15f6: bf00 nop
15f8: 40001c00 .word 0x40001c00
15fc: 00010107 .word 0x00010107
1600: 00010105 .word 0x00010105
00001604 <assert>:
/**
* \brief Assert function
*/
void assert(const bool condition, const char *const file, const int line)
{
if (!(condition)) {
1604: b900 cbnz r0, 1608 <assert+0x4>
__asm("BKPT #0");
1606: be00 bkpt 0x0000
}
(void)file;
(void)line;
}
1608: 4770 bx lr
0000160a <_oscctrl_init_sources>:
hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1);
#endif
#endif
(void)hw;
}
160a: 4770 bx lr
0000160c <_oscctrl_init_referenced_generators>:
static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
hri_oscctrl_dpllratio_reg_t data)
{
OSCCTRL_CRITICAL_SECTION_ENTER();
((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data;
160c: 4b0c ldr r3, [pc, #48] ; (1640 <_oscctrl_init_referenced_generators+0x34>)
160e: 4a0d ldr r2, [pc, #52] ; (1644 <_oscctrl_init_referenced_generators+0x38>)
1610: 635a str r2, [r3, #52] ; 0x34
while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
1612: 6bda ldr r2, [r3, #60] ; 0x3c
1614: f012 0f06 tst.w r2, #6
1618: d1fb bne.n 1612 <_oscctrl_init_referenced_generators+0x6>
static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
hri_oscctrl_dpllctrlb_reg_t data)
{
OSCCTRL_CRITICAL_SECTION_ENTER();
((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data;
161a: f44f 6202 mov.w r2, #2080 ; 0x820
161e: 639a str r2, [r3, #56] ; 0x38
((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data;
1620: 2202 movs r2, #2
1622: f883 2030 strb.w r2, [r3, #48] ; 0x30
while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
1626: 4a06 ldr r2, [pc, #24] ; (1640 <_oscctrl_init_referenced_generators+0x34>)
1628: 6bd3 ldr r3, [r2, #60] ; 0x3c
162a: 0798 lsls r0, r3, #30
162c: d4fc bmi.n 1628 <_oscctrl_init_referenced_generators+0x1c>
return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
162e: 4b04 ldr r3, [pc, #16] ; (1640 <_oscctrl_init_referenced_generators+0x34>)
1630: 6c1a ldr r2, [r3, #64] ; 0x40
#endif
#endif
#if CONF_FDPLL0_CONFIG == 1
#if CONF_FDPLL0_ENABLE == 1
while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0)))
1632: 07d1 lsls r1, r2, #31
1634: d402 bmi.n 163c <_oscctrl_init_referenced_generators+0x30>
return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
1636: 6c1a ldr r2, [r3, #64] ; 0x40
1638: 0792 lsls r2, r2, #30
163a: d5f9 bpl.n 1630 <_oscctrl_init_referenced_generators+0x24>
hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE);
while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
;
#endif
(void)hw;
}
163c: 4770 bx lr
163e: bf00 nop
1640: 40001000 .word 0x40001000
1644: 00010e4d .word 0x00010e4d
00001648 <_mci_sync_init>:
/**
* \brief Initialize MCI low level driver.
*/
int32_t _mci_sync_init(struct _mci_sync_device *const mci_dev, void *const hw)
{
1648: b538 push {r3, r4, r5, lr}
164a: 460c mov r4, r1
ASSERT(mci_dev && hw);
164c: 4605 mov r5, r0
164e: b110 cbz r0, 1656 <_mci_sync_init+0xe>
1650: 1e08 subs r0, r1, #0
1652: bf18 it ne
1654: 2001 movne r0, #1
1656: 4b12 ldr r3, [pc, #72] ; (16a0 <_mci_sync_init+0x58>)
1658: 4912 ldr r1, [pc, #72] ; (16a4 <_mci_sync_init+0x5c>)
165a: 22d8 movs r2, #216 ; 0xd8
165c: 4798 blx r3
}
static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw)
{
SDHC_CRITICAL_SECTION_ENTER();
((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL;
165e: f894 302f ldrb.w r3, [r4, #47] ; 0x2f
mci_dev->hw = hw;
1662: 602c str r4, [r5, #0]
1664: f043 0301 orr.w r3, r3, #1
1668: f884 302f strb.w r3, [r4, #47] ; 0x2f
}
static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Sdhc *)hw)->SRR.reg;
166c: f894 002f ldrb.w r0, [r4, #47] ; 0x2f
hri_sdhc_set_SRR_SWRSTALL_bit(hw);
while (hri_sdhc_get_SRR_SWRSTALL_bit(hw))
1670: f010 0001 ands.w r0, r0, #1
1674: d1fa bne.n 166c <_mci_sync_init+0x24>
((Sdhc *)hw)->TCR.reg = data;
1676: 230e movs r3, #14
1678: f884 302e strb.w r3, [r4, #46] ; 0x2e
((Sdhc *)hw)->PCR.reg = data;
167c: 230f movs r3, #15
167e: f884 3029 strb.w r3, [r4, #41] ; 0x29
}
static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
{
SDHC_CRITICAL_SECTION_ENTER();
((Sdhc *)hw)->NISTER.reg |= mask;
1682: 8ea3 ldrh r3, [r4, #52] ; 0x34
1684: b29b uxth r3, r3
1686: ea6f 2353 mvn.w r3, r3, lsr #9
168a: ea6f 2343 mvn.w r3, r3, lsl #9
168e: 86a3 strh r3, [r4, #52] ; 0x34
}
static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
{
SDHC_CRITICAL_SECTION_ENTER();
((Sdhc *)hw)->EISTER.reg |= mask;
1690: 8ee3 ldrh r3, [r4, #54] ; 0x36
1692: b29b uxth r3, r3
1694: ea6f 2393 mvn.w r3, r3, lsr #10
1698: ea6f 2383 mvn.w r3, r3, lsl #10
169c: 86e3 strh r3, [r4, #54] ; 0x36
hri_sdhc_set_NISTER_reg(hw, SDHC_NISTER_MASK);
hri_sdhc_set_EISTER_reg(hw, SDHC_EISTER_MASK);
return ERR_NONE;
}
169e: bd38 pop {r3, r4, r5, pc}
16a0: 00001605 .word 0x00001605
16a4: 0000301c .word 0x0000301c
000016a8 <usart_sync_write>:
* \param[in] length The number of bytes to write
*
* \return The number of bytes written.
*/
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
16a8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
16ac: 460e mov r6, r1
16ae: 4615 mov r5, r2
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
16b0: 4604 mov r4, r0
16b2: b118 cbz r0, 16bc <usart_sync_write+0x14>
16b4: b329 cbz r1, 1702 <usart_sync_write+0x5a>
16b6: 1e10 subs r0, r2, #0
16b8: bf18 it ne
16ba: 2001 movne r0, #1
16bc: 4912 ldr r1, [pc, #72] ; (1708 <usart_sync_write+0x60>)
16be: 4b13 ldr r3, [pc, #76] ; (170c <usart_sync_write+0x64>)
while (!_usart_sync_is_ready_to_send(&descr->device))
16c0: 4f13 ldr r7, [pc, #76] ; (1710 <usart_sync_write+0x68>)
ASSERT(io_descr && buf && length);
16c2: 22f1 movs r2, #241 ; 0xf1
16c4: 4798 blx r3
while (!_usart_sync_is_ready_to_send(&descr->device))
16c6: 3408 adds r4, #8
16c8: 46b9 mov r9, r7
16ca: 4620 mov r0, r4
16cc: 47b8 blx r7
16ce: 2800 cmp r0, #0
16d0: d0fb beq.n 16ca <usart_sync_write+0x22>
;
do {
_usart_sync_write_byte(&descr->device, buf[offset]);
16d2: f8df 8044 ldr.w r8, [pc, #68] ; 1718 <usart_sync_write+0x70>
uint32_t offset = 0;
16d6: 2700 movs r7, #0
_usart_sync_write_byte(&descr->device, buf[offset]);
16d8: 5df1 ldrb r1, [r6, r7]
16da: 4620 mov r0, r4
16dc: 47c0 blx r8
while (!_usart_sync_is_ready_to_send(&descr->device))
16de: 4620 mov r0, r4
16e0: 47c8 blx r9
16e2: 2800 cmp r0, #0
16e4: d0fb beq.n 16de <usart_sync_write+0x36>
;
} while (++offset < length);
16e6: 3701 adds r7, #1
16e8: 42bd cmp r5, r7
16ea: d8f5 bhi.n 16d8 <usart_sync_write+0x30>
16ec: 2d00 cmp r5, #0
while (!_usart_sync_is_transmit_done(&descr->device))
16ee: 4e09 ldr r6, [pc, #36] ; (1714 <usart_sync_write+0x6c>)
} while (++offset < length);
16f0: bf08 it eq
16f2: 2501 moveq r5, #1
while (!_usart_sync_is_transmit_done(&descr->device))
16f4: 4620 mov r0, r4
16f6: 47b0 blx r6
16f8: 2800 cmp r0, #0
16fa: d0fb beq.n 16f4 <usart_sync_write+0x4c>
;
return (int32_t)offset;
}
16fc: 4628 mov r0, r5
16fe: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(io_descr && buf && length);
1702: 4608 mov r0, r1
1704: e7da b.n 16bc <usart_sync_write+0x14>
1706: bf00 nop
1708: 00003033 .word 0x00003033
170c: 00001605 .word 0x00001605
1710: 00001e87 .word 0x00001e87
1714: 00001e91 .word 0x00001e91
1718: 00001e79 .word 0x00001e79
0000171c <usart_sync_read>:
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
{
171c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
1720: 460e mov r6, r1
1722: 4615 mov r5, r2
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
1724: 4604 mov r4, r0
1726: b118 cbz r0, 1730 <usart_sync_read+0x14>
1728: b1e9 cbz r1, 1766 <usart_sync_read+0x4a>
172a: 1e10 subs r0, r2, #0
172c: bf18 it ne
172e: 2001 movne r0, #1
1730: 490e ldr r1, [pc, #56] ; (176c <usart_sync_read+0x50>)
1732: 4b0f ldr r3, [pc, #60] ; (1770 <usart_sync_read+0x54>)
do {
while (!_usart_sync_is_byte_received(&descr->device))
1734: f8df 903c ldr.w r9, [pc, #60] ; 1774 <usart_sync_read+0x58>
;
buf[offset] = _usart_sync_read_byte(&descr->device);
1738: f8df 803c ldr.w r8, [pc, #60] ; 1778 <usart_sync_read+0x5c>
ASSERT(io_descr && buf && length);
173c: f44f 7286 mov.w r2, #268 ; 0x10c
1740: 4798 blx r3
uint32_t offset = 0;
1742: 2700 movs r7, #0
while (!_usart_sync_is_byte_received(&descr->device))
1744: 3408 adds r4, #8
1746: 4620 mov r0, r4
1748: 47c8 blx r9
174a: 2800 cmp r0, #0
174c: d0fb beq.n 1746 <usart_sync_read+0x2a>
buf[offset] = _usart_sync_read_byte(&descr->device);
174e: 4620 mov r0, r4
1750: 47c0 blx r8
1752: 55f0 strb r0, [r6, r7]
} while (++offset < length);
1754: 3701 adds r7, #1
1756: 42bd cmp r5, r7
1758: d8f5 bhi.n 1746 <usart_sync_read+0x2a>
175a: 2d00 cmp r5, #0
return (int32_t)offset;
}
175c: bf14 ite ne
175e: 4628 movne r0, r5
1760: 2001 moveq r0, #1
1762: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(io_descr && buf && length);
1766: 4608 mov r0, r1
1768: e7e2 b.n 1730 <usart_sync_read+0x14>
176a: bf00 nop
176c: 00003033 .word 0x00003033
1770: 00001605 .word 0x00001605
1774: 00001e9b .word 0x00001e9b
1778: 00001e7f .word 0x00001e7f
0000177c <usart_sync_init>:
{
177c: b538 push {r3, r4, r5, lr}
177e: 460d mov r5, r1
ASSERT(descr && hw);
1780: 4604 mov r4, r0
1782: b110 cbz r0, 178a <usart_sync_init+0xe>
1784: 1e08 subs r0, r1, #0
1786: bf18 it ne
1788: 2001 movne r0, #1
178a: 4907 ldr r1, [pc, #28] ; (17a8 <usart_sync_init+0x2c>)
178c: 4b07 ldr r3, [pc, #28] ; (17ac <usart_sync_init+0x30>)
178e: 2234 movs r2, #52 ; 0x34
1790: 4798 blx r3
init_status = _usart_sync_init(&descr->device, hw);
1792: 4b07 ldr r3, [pc, #28] ; (17b0 <usart_sync_init+0x34>)
1794: 4629 mov r1, r5
1796: f104 0008 add.w r0, r4, #8
179a: 4798 blx r3
if (init_status) {
179c: b918 cbnz r0, 17a6 <usart_sync_init+0x2a>
descr->io.read = usart_sync_read;
179e: 4b05 ldr r3, [pc, #20] ; (17b4 <usart_sync_init+0x38>)
17a0: 6063 str r3, [r4, #4]
descr->io.write = usart_sync_write;
17a2: 4b05 ldr r3, [pc, #20] ; (17b8 <usart_sync_init+0x3c>)
17a4: 6023 str r3, [r4, #0]
}
17a6: bd38 pop {r3, r4, r5, pc}
17a8: 00003033 .word 0x00003033
17ac: 00001605 .word 0x00001605
17b0: 00001e39 .word 0x00001e39
17b4: 0000171d .word 0x0000171d
17b8: 000016a9 .word 0x000016a9
000017bc <usart_sync_enable>:
{
17bc: b510 push {r4, lr}
ASSERT(descr);
17be: 4604 mov r4, r0
17c0: 3800 subs r0, #0
17c2: bf18 it ne
17c4: 2001 movne r0, #1
17c6: 4905 ldr r1, [pc, #20] ; (17dc <usart_sync_enable+0x20>)
17c8: 4b05 ldr r3, [pc, #20] ; (17e0 <usart_sync_enable+0x24>)
17ca: 2253 movs r2, #83 ; 0x53
17cc: 4798 blx r3
_usart_sync_enable(&descr->device);
17ce: f104 0008 add.w r0, r4, #8
17d2: 4b04 ldr r3, [pc, #16] ; (17e4 <usart_sync_enable+0x28>)
17d4: 4798 blx r3
}
17d6: 2000 movs r0, #0
17d8: bd10 pop {r4, pc}
17da: bf00 nop
17dc: 00003033 .word 0x00003033
17e0: 00001605 .word 0x00001605
17e4: 00001e65 .word 0x00001e65
000017e8 <usart_sync_get_io_descriptor>:
{
17e8: b538 push {r3, r4, r5, lr}
17ea: 460d mov r5, r1
ASSERT(descr && io);
17ec: 4604 mov r4, r0
17ee: b110 cbz r0, 17f6 <usart_sync_get_io_descriptor+0xe>
17f0: 1e08 subs r0, r1, #0
17f2: bf18 it ne
17f4: 2001 movne r0, #1
17f6: 4903 ldr r1, [pc, #12] ; (1804 <usart_sync_get_io_descriptor+0x1c>)
17f8: 4b03 ldr r3, [pc, #12] ; (1808 <usart_sync_get_io_descriptor+0x20>)
17fa: 2269 movs r2, #105 ; 0x69
17fc: 4798 blx r3
*io = &descr->io;
17fe: 602c str r4, [r5, #0]
}
1800: 2000 movs r0, #0
1802: bd38 pop {r3, r4, r5, pc}
1804: 00003033 .word 0x00003033
1808: 00001605 .word 0x00001605
0000180c <_mclk_init>:
}
static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->CPUDIV.reg = data;
180c: 4b01 ldr r3, [pc, #4] ; (1814 <_mclk_init+0x8>)
180e: 2201 movs r2, #1
1810: 715a strb r2, [r3, #5]
*/
void _mclk_init(void)
{
void *hw = (void *)MCLK;
hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV));
}
1812: 4770 bx lr
1814: 40000800 .word 0x40000800
00001818 <RAMECC_Handler>:
return tmp;
}
static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
{
return ((Ramecc *)hw)->INTFLAG.reg;
1818: 4a0b ldr r2, [pc, #44] ; (1848 <RAMECC_Handler+0x30>)
181a: 7893 ldrb r3, [r2, #2]
/**
* \internal RAMECC interrupt handler
*/
void RAMECC_Handler(void)
{
181c: b082 sub sp, #8
181e: b2db uxtb r3, r3
struct _ramecc_device *dev = (struct _ramecc_device *)&device;
volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
1820: 9301 str r3, [sp, #4]
if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
1822: 9b01 ldr r3, [sp, #4]
1824: 0799 lsls r1, r3, #30
1826: d505 bpl.n 1834 <RAMECC_Handler+0x1c>
1828: 4b08 ldr r3, [pc, #32] ; (184c <RAMECC_Handler+0x34>)
182a: 681b ldr r3, [r3, #0]
182c: b113 cbz r3, 1834 <RAMECC_Handler+0x1c>
return tmp;
}
static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
{
return ((Ramecc *)hw)->ERRADDR.reg;
182e: 6850 ldr r0, [r2, #4]
} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
} else {
return;
}
}
1830: b002 add sp, #8
dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
1832: 4718 bx r3
} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
1834: 9b01 ldr r3, [sp, #4]
1836: 07db lsls r3, r3, #31
1838: d504 bpl.n 1844 <RAMECC_Handler+0x2c>
183a: 4b04 ldr r3, [pc, #16] ; (184c <RAMECC_Handler+0x34>)
183c: 685b ldr r3, [r3, #4]
183e: b10b cbz r3, 1844 <RAMECC_Handler+0x2c>
1840: 4a01 ldr r2, [pc, #4] ; (1848 <RAMECC_Handler+0x30>)
1842: e7f4 b.n 182e <RAMECC_Handler+0x16>
}
1844: b002 add sp, #8
1846: 4770 bx lr
1848: 41020000 .word 0x41020000
184c: 200002dc .word 0x200002dc
00001850 <diskio_init>:
#include "diskio_start.h"
void diskio_init(void)
{
}
1850: 4770 bx lr
00001852 <Dummy_Handler>:
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
1852: e7fe b.n 1852 <Dummy_Handler>
00001854 <Reset_Handler>:
if (pSrc != pDest) {
1854: 4918 ldr r1, [pc, #96] ; (18b8 <Reset_Handler+0x64>)
1856: 4819 ldr r0, [pc, #100] ; (18bc <Reset_Handler+0x68>)
1858: 4281 cmp r1, r0
{
185a: b510 push {r4, lr}
if (pSrc != pDest) {
185c: d00a beq.n 1874 <Reset_Handler+0x20>
*pDest++ = *pSrc++;
185e: 4b18 ldr r3, [pc, #96] ; (18c0 <Reset_Handler+0x6c>)
1860: 1cda adds r2, r3, #3
1862: 1a12 subs r2, r2, r0
1864: f022 0203 bic.w r2, r2, #3
1868: 1ec4 subs r4, r0, #3
186a: 42a3 cmp r3, r4
186c: bf38 it cc
186e: 2200 movcc r2, #0
1870: 4b14 ldr r3, [pc, #80] ; (18c4 <Reset_Handler+0x70>)
1872: 4798 blx r3
*pDest++ = 0;
1874: 4b14 ldr r3, [pc, #80] ; (18c8 <Reset_Handler+0x74>)
1876: 4815 ldr r0, [pc, #84] ; (18cc <Reset_Handler+0x78>)
1878: 1cda adds r2, r3, #3
187a: 1a12 subs r2, r2, r0
187c: 1ec1 subs r1, r0, #3
187e: f022 0203 bic.w r2, r2, #3
1882: 4299 cmp r1, r3
1884: bf88 it hi
1886: 2200 movhi r2, #0
1888: 4b11 ldr r3, [pc, #68] ; (18d0 <Reset_Handler+0x7c>)
188a: 2100 movs r1, #0
188c: 4798 blx r3
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
188e: 4a11 ldr r2, [pc, #68] ; (18d4 <Reset_Handler+0x80>)
1890: 4b11 ldr r3, [pc, #68] ; (18d8 <Reset_Handler+0x84>)
1892: f022 027f bic.w r2, r2, #127 ; 0x7f
1896: 609a str r2, [r3, #8]
SCB->CPACR |= (0xFu << 20);
1898: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88
189c: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000
18a0: f8c3 2088 str.w r2, [r3, #136] ; 0x88
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
18a4: f3bf 8f4f dsb sy
__ASM volatile ("isb 0xF":::"memory");
18a8: f3bf 8f6f isb sy
__libc_init_array();
18ac: 4b0b ldr r3, [pc, #44] ; (18dc <Reset_Handler+0x88>)
18ae: 4798 blx r3
main();
18b0: 4b0b ldr r3, [pc, #44] ; (18e0 <Reset_Handler+0x8c>)
18b2: 4798 blx r3
while (1)
18b4: e7fe b.n 18b4 <Reset_Handler+0x60>
18b6: bf00 nop
18b8: 000031c0 .word 0x000031c0
18bc: 20000000 .word 0x20000000
18c0: 2000006c .word 0x2000006c
18c4: 000021cd .word 0x000021cd
18c8: 2000036c .word 0x2000036c
18cc: 20000070 .word 0x20000070
18d0: 000021e9 .word 0x000021e9
18d4: 00000000 .word 0x00000000
18d8: e000ed00 .word 0xe000ed00
18dc: 00002185 .word 0x00002185
18e0: 000018e5 .word 0x000018e5
000018e4 <main>:
#include <atmel_start.h>
#include "pdebug.h"
#include "sd_mmc_start.h"
int main(void)
{
18e4: b508 push {r3, lr}
/* Initializes MCU, drivers and middleware */
atmel_start_init();
18e6: 4b05 ldr r3, [pc, #20] ; (18fc <main+0x18>)
18e8: 4798 blx r3
pdebug_init();
18ea: 4b05 ldr r3, [pc, #20] ; (1900 <main+0x1c>)
18ec: 4798 blx r3
printf("Hello world\n");
18ee: 4b05 ldr r3, [pc, #20] ; (1904 <main+0x20>)
18f0: 4805 ldr r0, [pc, #20] ; (1908 <main+0x24>)
18f2: 4798 blx r3
SDMMC_example();
18f4: 4b05 ldr r3, [pc, #20] ; (190c <main+0x28>)
18f6: 4798 blx r3
/* Replace with your application code */
while (1) {
18f8: e7fe b.n 18f8 <main+0x14>
18fa: bf00 nop
18fc: 000020b5 .word 0x000020b5
1900: 00002135 .word 0x00002135
1904: 000020d5 .word 0x000020d5
1908: 0000304f .word 0x0000304f
190c: 00000359 .word 0x00000359
00001910 <_osc32kctrl_init_sources>:
}
static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->XOSC32K.reg = data;
1910: 4b06 ldr r3, [pc, #24] ; (192c <_osc32kctrl_init_sources+0x1c>)
1912: f242 328e movw r2, #9102 ; 0x238e
1916: 829a strh r2, [r3, #20]
}
static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->CFDCTRL.reg = data;
1918: 2200 movs r2, #0
191a: 759a strb r2, [r3, #22]
}
static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->EVCTRL.reg = data;
191c: 75da strb r2, [r3, #23]
}
static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
{
uint32_t tmp;
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
191e: 69da ldr r2, [r3, #28]
calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
hri_osc32kctrl_write_OSCULP32K_reg(hw,
#if CONF_OSCULP32K_CALIB_ENABLE == 1
OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
#else
OSC32KCTRL_OSCULP32K_CALIB(calib)
1920: f402 527c and.w r2, r2, #16128 ; 0x3f00
}
static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->OSCULP32K.reg = data;
1924: 61da str r2, [r3, #28]
((Osc32kctrl *)hw)->RTCCTRL.reg = data;
1926: 2201 movs r2, #1
1928: 741a strb r2, [r3, #16]
#endif
#endif
hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
(void)calib;
}
192a: 4770 bx lr
192c: 40001400 .word 0x40001400
00001930 <hri_rtcmode0_wait_for_sync>:
typedef uint8_t hri_rtcalarm_mask_reg_t;
typedef uint8_t hri_rtcmode2_mask_reg_t;
static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
{
while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
1930: 6903 ldr r3, [r0, #16]
1932: 420b tst r3, r1
1934: d1fc bne.n 1930 <hri_rtcmode0_wait_for_sync>
};
}
1936: 4770 bx lr
00001938 <_calendar_init>:
/**
* \brief Initializes the RTC module with given configurations.
*/
int32_t _calendar_init(struct calendar_dev *const dev)
{
1938: b510 push {r4, lr}
ASSERT(dev && dev->hw);
193a: 4604 mov r4, r0
193c: b118 cbz r0, 1946 <_calendar_init+0xe>
193e: 6800 ldr r0, [r0, #0]
1940: 3800 subs r0, #0
1942: bf18 it ne
1944: 2001 movne r0, #1
1946: 4917 ldr r1, [pc, #92] ; (19a4 <_calendar_init+0x6c>)
1948: 4b17 ldr r3, [pc, #92] ; (19a8 <_calendar_init+0x70>)
194a: 222f movs r2, #47 ; 0x2f
194c: 4798 blx r3
_rtc_dev = dev;
194e: 4b17 ldr r3, [pc, #92] ; (19ac <_calendar_init+0x74>)
}
static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
{
uint16_t tmp;
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
1950: 6820 ldr r0, [r4, #0]
1952: 4a17 ldr r2, [pc, #92] ; (19b0 <_calendar_init+0x78>)
1954: 601c str r4, [r3, #0]
1956: f248 0103 movw r1, #32771 ; 0x8003
195a: 4790 blx r2
tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
195c: 8803 ldrh r3, [r0, #0]
if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) {
195e: 079b lsls r3, r3, #30
1960: d50a bpl.n 1978 <_calendar_init+0x40>
#if !CONF_RTC_INIT_RESET
return ERR_DENIED;
#else
hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
1962: 6820 ldr r0, [r4, #0]
}
static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
{
RTC_CRITICAL_SECTION_ENTER();
((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
1964: 8803 ldrh r3, [r0, #0]
1966: f023 0302 bic.w r3, r3, #2
196a: 041b lsls r3, r3, #16
196c: 0c1b lsrs r3, r3, #16
196e: 8003 strh r3, [r0, #0]
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
1970: 4790 blx r2
hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE);
1972: 6820 ldr r0, [r4, #0]
1974: 2102 movs r1, #2
1976: 4790 blx r2
#endif
}
hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
1978: 6820 ldr r0, [r4, #0]
((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
197a: 8803 ldrh r3, [r0, #0]
197c: b29b uxth r3, r3
197e: f043 0301 orr.w r3, r3, #1
1982: 8003 strh r3, [r0, #0]
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
1984: 2101 movs r1, #1
1986: 4790 blx r2
hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
1988: 6820 ldr r0, [r4, #0]
198a: 4790 blx r2
| (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos)
| (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
| (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos));
#endif
hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC);
198c: 6820 ldr r0, [r4, #0]
}
static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
{
RTC_CRITICAL_SECTION_ENTER();
((Rtc *)hw)->MODE0.CTRLA.reg = data;
198e: f44f 4301 mov.w r3, #33024 ; 0x8100
1992: 8003 strh r3, [r0, #0]
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
1994: f248 0103 movw r1, #32771 ; 0x8003
1998: 4790 blx r2
hri_rtc_write_TAMPCTRL_reg(
dev->hw,
199a: 6823 ldr r3, [r4, #0]
}
static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
{
RTC_CRITICAL_SECTION_ENTER();
((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
199c: 2000 movs r0, #0
199e: 6618 str r0, [r3, #96] ; 0x60
| (CONF_RTC_TAMPER_INACT_2 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_3 == TAMPER_MODE_ACTL)
| (CONF_RTC_TAMPER_INACT_4 == TAMPER_MODE_ACTL)) {
hri_rtcmode0_set_CTRLB_RTCOUT_bit(dev->hw);
}
return ERR_NONE;
}
19a0: bd10 pop {r4, pc}
19a2: bf00 nop
19a4: 0000305c .word 0x0000305c
19a8: 00001605 .word 0x00001605
19ac: 200002ec .word 0x200002ec
19b0: 00001931 .word 0x00001931
000019b4 <RTC_Handler>:
/**
* \brief Rtc interrupt handler
*/
void RTC_Handler(void)
{
_rtc_interrupt_handler(_rtc_dev);
19b4: 4b0d ldr r3, [pc, #52] ; (19ec <RTC_Handler+0x38>)
{
19b6: b510 push {r4, lr}
_rtc_interrupt_handler(_rtc_dev);
19b8: 681c ldr r4, [r3, #0]
uint16_t interrupt_status = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
19ba: 6822 ldr r2, [r4, #0]
return ((Rtc *)hw)->MODE0.INTFLAG.reg;
19bc: 8991 ldrh r1, [r2, #12]
return ((Rtc *)hw)->MODE0.INTENSET.reg;
19be: 8953 ldrh r3, [r2, #10]
19c0: b29b uxth r3, r3
if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) {
19c2: 400b ands r3, r1
19c4: 05da lsls r2, r3, #23
19c6: d507 bpl.n 19d8 <RTC_Handler+0x24>
dev->callback(dev);
19c8: 6863 ldr r3, [r4, #4]
19ca: 4620 mov r0, r4
19cc: 4798 blx r3
hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
19ce: 6823 ldr r3, [r4, #0]
((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
19d0: f44f 7280 mov.w r2, #256 ; 0x100
((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
19d4: 819a strh r2, [r3, #12]
}
19d6: bd10 pop {r4, pc}
} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
19d8: 045b lsls r3, r3, #17
19da: d5fc bpl.n 19d6 <RTC_Handler+0x22>
dev->callback_tamper(dev);
19dc: 68a3 ldr r3, [r4, #8]
19de: 4620 mov r0, r4
19e0: 4798 blx r3
hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
19e2: 6823 ldr r3, [r4, #0]
19e4: f44f 4280 mov.w r2, #16384 ; 0x4000
19e8: e7f4 b.n 19d4 <RTC_Handler+0x20>
19ea: bf00 nop
19ec: 200002ec .word 0x200002ec
000019f0 <gpio_set_pin_direction>:
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
19f0: f000 031f and.w r3, r0, #31
{
19f4: b530 push {r4, r5, lr}
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
19f6: 2501 movs r5, #1
19f8: 409d lsls r5, r3
((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
19fa: 0940 lsrs r0, r0, #5
19fc: 4b0d ldr r3, [pc, #52] ; (1a34 <gpio_set_pin_direction+0x44>)
19fe: 01c0 lsls r0, r0, #7
switch (direction) {
1a00: 2902 cmp r1, #2
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
1a02: b2ac uxth r4, r5
| ((mask & 0xffff0000) >> 16));
1a04: ea4f 4215 mov.w r2, r5, lsr #16
((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
1a08: 4403 add r3, r0
switch (direction) {
1a0a: d00b beq.n 1a24 <gpio_set_pin_direction+0x34>
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
1a0c: f044 4480 orr.w r4, r4, #1073741824 ; 0x40000000
1a10: f444 3400 orr.w r4, r4, #131072 ; 0x20000
hri_port_write_WRCONFIG_reg(PORT,
1a14: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000
((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
1a18: 605d str r5, [r3, #4]
1a1a: f442 3200 orr.w r2, r2, #131072 ; 0x20000
static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
hri_port_wrconfig_reg_t data)
{
PORT_CRITICAL_SECTION_ENTER();
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
1a1e: 629c str r4, [r3, #40] ; 0x28
1a20: 629a str r2, [r3, #40] ; 0x28
}
1a22: bd30 pop {r4, r5, pc}
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
1a24: f044 4480 orr.w r4, r4, #1073741824 ; 0x40000000
((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
1a28: 609d str r5, [r3, #8]
hri_port_write_WRCONFIG_reg(
1a2a: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
1a2e: 629c str r4, [r3, #40] ; 0x28
1a30: e7f6 b.n 1a20 <gpio_set_pin_direction+0x30>
1a32: bf00 nop
1a34: 41008000 .word 0x41008000
00001a38 <gpio_set_pin_pull_mode.constprop.0>:
((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
1a38: 0942 lsrs r2, r0, #5
1a3a: f000 031f and.w r3, r0, #31
1a3e: eb03 13c2 add.w r3, r3, r2, lsl #7
1a42: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000
1a46: f503 4300 add.w r3, r3, #32768 ; 0x8000
1a4a: f893 2040 ldrb.w r2, [r3, #64] ; 0x40
1a4e: f002 02fb and.w r2, r2, #251 ; 0xfb
1a52: f883 2040 strb.w r2, [r3, #64] ; 0x40
}
1a56: 4770 bx lr
00001a58 <_gpio_set_pin_function>:
/**
* \brief Set gpio pin function
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
{
uint8_t port = GPIO_PORT(gpio);
1a58: 0943 lsrs r3, r0, #5
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
1a5a: 01db lsls r3, r3, #7
1a5c: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000
{
1a60: b530 push {r4, r5, lr}
1a62: f503 4300 add.w r3, r3, #32768 ; 0x8000
uint8_t pin = GPIO_PIN(gpio);
1a66: f000 041f and.w r4, r0, #31
1a6a: 191d adds r5, r3, r4
1a6c: eb03 0354 add.w r3, r3, r4, lsr #1
1a70: f895 2040 ldrb.w r2, [r5, #64] ; 0x40
tmp &= ~PORT_PINCFG_PMUXEN;
1a74: f002 02fe and.w r2, r2, #254 ; 0xfe
tmp |= value << PORT_PINCFG_PMUXEN_Pos;
1a78: f042 0201 orr.w r2, r2, #1
((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
1a7c: f885 2040 strb.w r2, [r5, #64] ; 0x40
} else {
hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
if (pin & 1) {
// Odd numbered pin
hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
1a80: b2ca uxtb r2, r1
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
1a82: f893 1030 ldrb.w r1, [r3, #48] ; 0x30
if (pin & 1) {
1a86: f010 0f01 tst.w r0, #1
tmp &= ~PORT_PMUX_PMUXO_Msk;
1a8a: bf1b ittet ne
1a8c: f001 010f andne.w r1, r1, #15
tmp |= PORT_PMUX_PMUXO(data);
1a90: ea41 1102 orrne.w r1, r1, r2, lsl #4
tmp &= ~PORT_PMUX_PMUXE_Msk;
1a94: f001 01f0 andeq.w r1, r1, #240 ; 0xf0
tmp |= PORT_PMUX_PMUXO(data);
1a98: b2c9 uxtbne r1, r1
tmp |= PORT_PMUX_PMUXE(data);
1a9a: bf08 it eq
1a9c: 4311 orreq r1, r2
((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
1a9e: f883 1030 strb.w r1, [r3, #48] ; 0x30
} else {
// Even numbered pin
hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
}
}
}
1aa2: bd30 pop {r4, r5, pc}
00001aa4 <CALENDER_INTERFACE_CLOCK_init>:
}
static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
1aa4: 4a02 ldr r2, [pc, #8] ; (1ab0 <CALENDER_INTERFACE_CLOCK_init+0xc>)
1aa6: 6953 ldr r3, [r2, #20]
1aa8: f443 7300 orr.w r3, r3, #512 ; 0x200
1aac: 6153 str r3, [r2, #20]
struct mci_sync_desc IO_BUS;
void CALENDER_INTERFACE_CLOCK_init(void)
{
hri_mclk_set_APBAMASK_RTC_bit(MCLK);
}
1aae: 4770 bx lr
1ab0: 40000800 .word 0x40000800
00001ab4 <CALENDER_INTERFACE_init>:
void CALENDER_INTERFACE_init(void)
{
1ab4: b510 push {r4, lr}
CALENDER_INTERFACE_CLOCK_init();
1ab6: 4b04 ldr r3, [pc, #16] ; (1ac8 <CALENDER_INTERFACE_init+0x14>)
calendar_init(&CALENDER_INTERFACE, RTC);
1ab8: 4904 ldr r1, [pc, #16] ; (1acc <CALENDER_INTERFACE_init+0x18>)
1aba: 4805 ldr r0, [pc, #20] ; (1ad0 <CALENDER_INTERFACE_init+0x1c>)
CALENDER_INTERFACE_CLOCK_init();
1abc: 4798 blx r3
}
1abe: e8bd 4010 ldmia.w sp!, {r4, lr}
calendar_init(&CALENDER_INTERFACE, RTC);
1ac2: 4b04 ldr r3, [pc, #16] ; (1ad4 <CALENDER_INTERFACE_init+0x20>)
1ac4: 4718 bx r3
1ac6: bf00 nop
1ac8: 00001aa5 .word 0x00001aa5
1acc: 40002400 .word 0x40002400
1ad0: 200002f0 .word 0x200002f0
1ad4: 00000315 .word 0x00000315
00001ad8 <USART_DBG_PORT_init>:
void USART_DBG_PORT_init(void)
{
1ad8: b510 push {r4, lr}
_gpio_set_pin_function(pin, function);
1ada: 4c05 ldr r4, [pc, #20] ; (1af0 <USART_DBG_PORT_init+0x18>)
1adc: 4905 ldr r1, [pc, #20] ; (1af4 <USART_DBG_PORT_init+0x1c>)
1ade: 2039 movs r0, #57 ; 0x39
1ae0: 47a0 blx r4
1ae2: 4623 mov r3, r4
1ae4: 4904 ldr r1, [pc, #16] ; (1af8 <USART_DBG_PORT_init+0x20>)
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
1ae6: e8bd 4010 ldmia.w sp!, {r4, lr}
1aea: 2038 movs r0, #56 ; 0x38
1aec: 4718 bx r3
1aee: bf00 nop
1af0: 00001a59 .word 0x00001a59
1af4: 00390003 .word 0x00390003
1af8: 00380003 .word 0x00380003
00001afc <USART_DBG_CLOCK_init>:
}
static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg = data;
1afc: 4b06 ldr r3, [pc, #24] ; (1b18 <USART_DBG_CLOCK_init+0x1c>)
1afe: 2240 movs r2, #64 ; 0x40
1b00: f8c3 20dc str.w r2, [r3, #220] ; 0xdc
1b04: 2243 movs r2, #67 ; 0x43
1b06: f8c3 208c str.w r2, [r3, #140] ; 0x8c
}
static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
1b0a: 4a04 ldr r2, [pc, #16] ; (1b1c <USART_DBG_CLOCK_init+0x20>)
1b0c: 6993 ldr r3, [r2, #24]
1b0e: f443 7300 orr.w r3, r3, #512 ; 0x200
1b12: 6193 str r3, [r2, #24]
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
1b14: 4770 bx lr
1b16: bf00 nop
1b18: 40001c00 .word 0x40001c00
1b1c: 40000800 .word 0x40000800
00001b20 <USART_DBG_init>:
void USART_DBG_init(void)
{
1b20: b510 push {r4, lr}
USART_DBG_CLOCK_init();
1b22: 4b05 ldr r3, [pc, #20] ; (1b38 <USART_DBG_init+0x18>)
usart_sync_init(&USART_DBG, SERCOM2, (void *)NULL);
1b24: 4905 ldr r1, [pc, #20] ; (1b3c <USART_DBG_init+0x1c>)
1b26: 4806 ldr r0, [pc, #24] ; (1b40 <USART_DBG_init+0x20>)
USART_DBG_CLOCK_init();
1b28: 4798 blx r3
usart_sync_init(&USART_DBG, SERCOM2, (void *)NULL);
1b2a: 4b06 ldr r3, [pc, #24] ; (1b44 <USART_DBG_init+0x24>)
1b2c: 2200 movs r2, #0
1b2e: 4798 blx r3
USART_DBG_PORT_init();
}
1b30: e8bd 4010 ldmia.w sp!, {r4, lr}
USART_DBG_PORT_init();
1b34: 4b04 ldr r3, [pc, #16] ; (1b48 <USART_DBG_init+0x28>)
1b36: 4718 bx r3
1b38: 00001afd .word 0x00001afd
1b3c: 41012000 .word 0x41012000
1b40: 20000310 .word 0x20000310
1b44: 0000177d .word 0x0000177d
1b48: 00001ad9 .word 0x00001ad9
00001b4c <SPI_SD_MMC_PORT_init>:
void SPI_SD_MMC_PORT_init(void)
{
1b4c: b570 push {r4, r5, r6, lr}
((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
1b4e: 4e11 ldr r6, [pc, #68] ; (1b94 <SPI_SD_MMC_PORT_init+0x48>)
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(PB27, GPIO_DIRECTION_OUT);
1b50: 4d11 ldr r5, [pc, #68] ; (1b98 <SPI_SD_MMC_PORT_init+0x4c>)
1b52: 4c12 ldr r4, [pc, #72] ; (1b9c <SPI_SD_MMC_PORT_init+0x50>)
1b54: f04f 6300 mov.w r3, #134217728 ; 0x8000000
1b58: f8c6 3094 str.w r3, [r6, #148] ; 0x94
1b5c: 2102 movs r1, #2
1b5e: 203b movs r0, #59 ; 0x3b
1b60: 47a8 blx r5
1b62: 490f ldr r1, [pc, #60] ; (1ba0 <SPI_SD_MMC_PORT_init+0x54>)
1b64: 203b movs r0, #59 ; 0x3b
1b66: 47a0 blx r4
1b68: f04f 6380 mov.w r3, #67108864 ; 0x4000000
1b6c: f8c6 3094 str.w r3, [r6, #148] ; 0x94
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(PB26, GPIO_DIRECTION_OUT);
1b70: 2102 movs r1, #2
1b72: 203a movs r0, #58 ; 0x3a
1b74: 47a8 blx r5
1b76: 490b ldr r1, [pc, #44] ; (1ba4 <SPI_SD_MMC_PORT_init+0x58>)
1b78: 203a movs r0, #58 ; 0x3a
1b7a: 47a0 blx r4
gpio_set_pin_function(PB26, PINMUX_PB26D_SERCOM4_PAD1);
// Set pin direction to input
gpio_set_pin_direction(PB29, GPIO_DIRECTION_IN);
1b7c: 2101 movs r1, #1
1b7e: 203d movs r0, #61 ; 0x3d
1b80: 47a8 blx r5
gpio_set_pin_pull_mode(PB29,
1b82: 4b09 ldr r3, [pc, #36] ; (1ba8 <SPI_SD_MMC_PORT_init+0x5c>)
1b84: 4909 ldr r1, [pc, #36] ; (1bac <SPI_SD_MMC_PORT_init+0x60>)
1b86: 203d movs r0, #61 ; 0x3d
1b88: 4798 blx r3
1b8a: 4623 mov r3, r4
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB29, PINMUX_PB29D_SERCOM4_PAD3);
}
1b8c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
1b90: 4718 bx r3
1b92: bf00 nop
1b94: 41008000 .word 0x41008000
1b98: 000019f1 .word 0x000019f1
1b9c: 00001a59 .word 0x00001a59
1ba0: 003b0003 .word 0x003b0003
1ba4: 003a0003 .word 0x003a0003
1ba8: 00001a39 .word 0x00001a39
1bac: 003d0003 .word 0x003d0003
00001bb0 <SPI_SD_MMC_CLOCK_init>:
1bb0: 4b06 ldr r3, [pc, #24] ; (1bcc <SPI_SD_MMC_CLOCK_init+0x1c>)
1bb2: 2240 movs r2, #64 ; 0x40
1bb4: f8c3 2108 str.w r2, [r3, #264] ; 0x108
1bb8: 2243 movs r2, #67 ; 0x43
1bba: f8c3 208c str.w r2, [r3, #140] ; 0x8c
}
static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
1bbe: 4a04 ldr r2, [pc, #16] ; (1bd0 <SPI_SD_MMC_CLOCK_init+0x20>)
1bc0: 6a13 ldr r3, [r2, #32]
1bc2: f043 0301 orr.w r3, r3, #1
1bc6: 6213 str r3, [r2, #32]
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
}
1bc8: 4770 bx lr
1bca: bf00 nop
1bcc: 40001c00 .word 0x40001c00
1bd0: 40000800 .word 0x40000800
00001bd4 <SPI_SD_MMC_init>:
void SPI_SD_MMC_init(void)
{
1bd4: b510 push {r4, lr}
SPI_SD_MMC_CLOCK_init();
1bd6: 4b05 ldr r3, [pc, #20] ; (1bec <SPI_SD_MMC_init+0x18>)
spi_m_sync_init(&SPI_SD_MMC, SERCOM4);
1bd8: 4805 ldr r0, [pc, #20] ; (1bf0 <SPI_SD_MMC_init+0x1c>)
SPI_SD_MMC_CLOCK_init();
1bda: 4798 blx r3
spi_m_sync_init(&SPI_SD_MMC, SERCOM4);
1bdc: f04f 4186 mov.w r1, #1124073472 ; 0x43000000
1be0: 4b04 ldr r3, [pc, #16] ; (1bf4 <SPI_SD_MMC_init+0x20>)
1be2: 4798 blx r3
SPI_SD_MMC_PORT_init();
}
1be4: e8bd 4010 ldmia.w sp!, {r4, lr}
SPI_SD_MMC_PORT_init();
1be8: 4b03 ldr r3, [pc, #12] ; (1bf8 <SPI_SD_MMC_init+0x24>)
1bea: 4718 bx r3
1bec: 00001bb1 .word 0x00001bb1
1bf0: 2000031c .word 0x2000031c
1bf4: 00001429 .word 0x00001429
1bf8: 00001b4d .word 0x00001b4d
00001bfc <IO_BUS_PORT_init>:
void IO_BUS_PORT_init(void)
{
1bfc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
1c00: 4e21 ldr r6, [pc, #132] ; (1c88 <IO_BUS_PORT_init+0x8c>)
gpio_set_pin_direction(PB11,
1c02: 4f22 ldr r7, [pc, #136] ; (1c8c <IO_BUS_PORT_init+0x90>)
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PB11,
1c04: 4d22 ldr r5, [pc, #136] ; (1c90 <IO_BUS_PORT_init+0x94>)
1c06: 4c23 ldr r4, [pc, #140] ; (1c94 <IO_BUS_PORT_init+0x98>)
1c08: f44f 6900 mov.w r9, #2048 ; 0x800
gpio_set_pin_direction(PB11,
1c0c: 2102 movs r1, #2
1c0e: 202b movs r0, #43 ; 0x2b
1c10: 47b8 blx r7
gpio_set_pin_pull_mode(PB11,
1c12: 202b movs r0, #43 ; 0x2b
1c14: 4920 ldr r1, [pc, #128] ; (1c98 <IO_BUS_PORT_init+0x9c>)
1c16: f8c6 9094 str.w r9, [r6, #148] ; 0x94
1c1a: 47a8 blx r5
1c1c: 47a0 blx r4
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PB11I_SDHC0_SDCK);
gpio_set_pin_direction(PA08,
1c1e: 2102 movs r1, #2
1c20: 2008 movs r0, #8
1c22: 47b8 blx r7
1c24: f44f 7380 mov.w r3, #256 ; 0x100
1c28: 6173 str r3, [r6, #20]
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA08,
1c2a: 2008 movs r0, #8
1c2c: f04f 1108 mov.w r1, #524296 ; 0x80008
1c30: 47a8 blx r5
1c32: 47a0 blx r4
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA08I_SDHC0_SDCMD);
gpio_set_pin_direction(PA09,
1c34: 2102 movs r1, #2
1c36: 2009 movs r0, #9
1c38: 47b8 blx r7
1c3a: f44f 7300 mov.w r3, #512 ; 0x200
1c3e: 6173 str r3, [r6, #20]
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA09,
1c40: 2009 movs r0, #9
1c42: 4916 ldr r1, [pc, #88] ; (1c9c <IO_BUS_PORT_init+0xa0>)
1c44: 47a8 blx r5
1c46: f44f 6880 mov.w r8, #1024 ; 0x400
1c4a: 47a0 blx r4
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA09I_SDHC0_SDDAT0);
gpio_set_pin_direction(PA10,
1c4c: 2102 movs r1, #2
1c4e: 200a movs r0, #10
1c50: 47b8 blx r7
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA10,
1c52: 200a movs r0, #10
1c54: 4912 ldr r1, [pc, #72] ; (1ca0 <IO_BUS_PORT_init+0xa4>)
1c56: f8c6 8014 str.w r8, [r6, #20]
1c5a: 47a8 blx r5
1c5c: 47a0 blx r4
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA10I_SDHC0_SDDAT1);
gpio_set_pin_direction(PA11,
1c5e: 2102 movs r1, #2
1c60: 200b movs r0, #11
1c62: 47b8 blx r7
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA11,
1c64: 200b movs r0, #11
1c66: 490f ldr r1, [pc, #60] ; (1ca4 <IO_BUS_PORT_init+0xa8>)
1c68: f8c6 9014 str.w r9, [r6, #20]
1c6c: 47a8 blx r5
1c6e: 47a0 blx r4
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA11I_SDHC0_SDDAT2);
gpio_set_pin_direction(PB10,
1c70: 2102 movs r1, #2
1c72: 202a movs r0, #42 ; 0x2a
1c74: 47b8 blx r7
1c76: f8c6 8094 str.w r8, [r6, #148] ; 0x94
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PB10,
1c7a: 202a movs r0, #42 ; 0x2a
1c7c: 47a8 blx r5
1c7e: 490a ldr r1, [pc, #40] ; (1ca8 <IO_BUS_PORT_init+0xac>)
1c80: 4623 mov r3, r4
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PB10I_SDHC0_SDDAT3);
}
1c82: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
1c86: 4718 bx r3
1c88: 41008000 .word 0x41008000
1c8c: 000019f1 .word 0x000019f1
1c90: 00001a39 .word 0x00001a39
1c94: 00001a59 .word 0x00001a59
1c98: 002b0008 .word 0x002b0008
1c9c: 00090008 .word 0x00090008
1ca0: 000a0008 .word 0x000a0008
1ca4: 000b0008 .word 0x000b0008
1ca8: 002a0008 .word 0x002a0008
00001cac <IO_BUS_CLOCK_init>:
((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
1cac: 4a05 ldr r2, [pc, #20] ; (1cc4 <IO_BUS_CLOCK_init+0x18>)
1cae: 6913 ldr r3, [r2, #16]
1cb0: f443 4300 orr.w r3, r3, #32768 ; 0x8000
1cb4: 6113 str r3, [r2, #16]
1cb6: 4b04 ldr r3, [pc, #16] ; (1cc8 <IO_BUS_CLOCK_init+0x1c>)
1cb8: 2240 movs r2, #64 ; 0x40
1cba: f8c3 2134 str.w r2, [r3, #308] ; 0x134
1cbe: f8c3 208c str.w r2, [r3, #140] ; 0x8c
void IO_BUS_CLOCK_init(void)
{
hri_mclk_set_AHBMASK_SDHC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, CONF_GCLK_SDHC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, CONF_GCLK_SDHC0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
1cc2: 4770 bx lr
1cc4: 40000800 .word 0x40000800
1cc8: 40001c00 .word 0x40001c00
00001ccc <IO_BUS_init>:
void IO_BUS_init(void)
{
1ccc: b510 push {r4, lr}
IO_BUS_CLOCK_init();
1cce: 4b05 ldr r3, [pc, #20] ; (1ce4 <IO_BUS_init+0x18>)
mci_sync_init(&IO_BUS, SDHC0);
1cd0: 4805 ldr r0, [pc, #20] ; (1ce8 <IO_BUS_init+0x1c>)
IO_BUS_CLOCK_init();
1cd2: 4798 blx r3
mci_sync_init(&IO_BUS, SDHC0);
1cd4: f04f 418a mov.w r1, #1157627904 ; 0x45000000
1cd8: 4b04 ldr r3, [pc, #16] ; (1cec <IO_BUS_init+0x20>)
1cda: 4798 blx r3
IO_BUS_PORT_init();
}
1cdc: e8bd 4010 ldmia.w sp!, {r4, lr}
IO_BUS_PORT_init();
1ce0: 4b03 ldr r3, [pc, #12] ; (1cf0 <IO_BUS_init+0x24>)
1ce2: 4718 bx r3
1ce4: 00001cad .word 0x00001cad
1ce8: 20000338 .word 0x20000338
1cec: 00001549 .word 0x00001549
1cf0: 00001bfd .word 0x00001bfd
00001cf4 <delay_driver_init>:
void delay_driver_init(void)
{
delay_init(SysTick);
1cf4: 4801 ldr r0, [pc, #4] ; (1cfc <delay_driver_init+0x8>)
1cf6: 4b02 ldr r3, [pc, #8] ; (1d00 <delay_driver_init+0xc>)
1cf8: 4718 bx r3
1cfa: bf00 nop
1cfc: e000e010 .word 0xe000e010
1d00: 00001579 .word 0x00001579
00001d04 <system_init>:
}
void system_init(void)
{
1d04: b510 push {r4, lr}
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
1d06: 4b07 ldr r3, [pc, #28] ; (1d24 <system_init+0x20>)
1d08: 4798 blx r3
init_mcu();
CALENDER_INTERFACE_init();
1d0a: 4b07 ldr r3, [pc, #28] ; (1d28 <system_init+0x24>)
1d0c: 4798 blx r3
USART_DBG_init();
1d0e: 4b07 ldr r3, [pc, #28] ; (1d2c <system_init+0x28>)
1d10: 4798 blx r3
SPI_SD_MMC_init();
1d12: 4b07 ldr r3, [pc, #28] ; (1d30 <system_init+0x2c>)
1d14: 4798 blx r3
IO_BUS_init();
1d16: 4b07 ldr r3, [pc, #28] ; (1d34 <system_init+0x30>)
1d18: 4798 blx r3
delay_driver_init();
}
1d1a: e8bd 4010 ldmia.w sp!, {r4, lr}
delay_driver_init();
1d1e: 4b06 ldr r3, [pc, #24] ; (1d38 <system_init+0x34>)
1d20: 4718 bx r3
1d22: bf00 nop
1d24: 00001589 .word 0x00001589
1d28: 00001ab5 .word 0x00001ab5
1d2c: 00001b21 .word 0x00001b21
1d30: 00001bd5 .word 0x00001bd5
1d34: 00001ccd .word 0x00001ccd
1d38: 00001cf5 .word 0x00001cf5
00001d3c <hri_sercomspi_wait_for_sync>:
return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
}
static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
{
while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
1d3c: 69c3 ldr r3, [r0, #28]
1d3e: 420b tst r3, r1
1d40: d1fc bne.n 1d3c <hri_sercomspi_wait_for_sync>
};
}
1d42: 4770 bx lr
00001d44 <hri_sercomusart_wait_for_sync>:
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
}
static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
{
while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
1d44: 69c3 ldr r3, [r0, #28]
1d46: 420b tst r3, r1
1d48: d1fc bne.n 1d44 <hri_sercomusart_wait_for_sync>
};
}
1d4a: 4770 bx lr
00001d4c <hri_sercomspi_clear_CTRLA_ENABLE_bit>:
}
static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
1d4c: 6802 ldr r2, [r0, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
1d4e: 4b03 ldr r3, [pc, #12] ; (1d5c <hri_sercomspi_clear_CTRLA_ENABLE_bit+0x10>)
((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
1d50: f022 0202 bic.w r2, r2, #2
1d54: 6002 str r2, [r0, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
1d56: 2103 movs r1, #3
1d58: 4718 bx r3
1d5a: bf00 nop
1d5c: 00001d3d .word 0x00001d3d
00001d60 <hri_sercomusart_clear_CTRLA_ENABLE_bit>:
}
static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
1d60: 6802 ldr r2, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
1d62: 4b03 ldr r3, [pc, #12] ; (1d70 <hri_sercomusart_clear_CTRLA_ENABLE_bit+0x10>)
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
1d64: f022 0202 bic.w r2, r2, #2
1d68: 6002 str r2, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
1d6a: 2103 movs r1, #3
1d6c: 4718 bx r3
1d6e: bf00 nop
1d70: 00001d45 .word 0x00001d45
00001d74 <_sercom_get_hardware_index>:
/**
* \brief Retrieve ordinal number of the given sercom hardware instance
*/
static uint8_t _sercom_get_hardware_index(const void *const hw)
{
1d74: b570 push {r4, r5, r6, lr}
Sercom *const sercom_modules[] = SERCOM_INSTS;
1d76: 4d0c ldr r5, [pc, #48] ; (1da8 <_sercom_get_hardware_index+0x34>)
{
1d78: 4606 mov r6, r0
Sercom *const sercom_modules[] = SERCOM_INSTS;
1d7a: cd0f ldmia r5!, {r0, r1, r2, r3}
{
1d7c: b088 sub sp, #32
Sercom *const sercom_modules[] = SERCOM_INSTS;
1d7e: 466c mov r4, sp
1d80: c40f stmia r4!, {r0, r1, r2, r3}
1d82: e895 000f ldmia.w r5, {r0, r1, r2, r3}
1d86: e884 000f stmia.w r4, {r0, r1, r2, r3}
/* Find index for SERCOM instance. */
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
1d8a: 466a mov r2, sp
1d8c: 2300 movs r3, #0
if ((uint32_t)hw == (uint32_t)sercom_modules[i]) {
1d8e: f852 1b04 ldr.w r1, [r2], #4
1d92: 42b1 cmp r1, r6
1d94: d102 bne.n 1d9c <_sercom_get_hardware_index+0x28>
return i;
1d96: b2d8 uxtb r0, r3
}
}
return 0;
}
1d98: b008 add sp, #32
1d9a: bd70 pop {r4, r5, r6, pc}
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
1d9c: 3301 adds r3, #1
1d9e: 2b08 cmp r3, #8
1da0: d1f5 bne.n 1d8e <_sercom_get_hardware_index+0x1a>
return 0;
1da2: 2000 movs r0, #0
1da4: e7f8 b.n 1d98 <_sercom_get_hardware_index+0x24>
1da6: bf00 nop
1da8: 0000308c .word 0x0000308c
00001dac <_usart_init>:
* \param[in] hw The pointer to hardware instance
*
* \return The status of initialization
*/
static int32_t _usart_init(void *const hw)
{
1dac: b538 push {r3, r4, r5, lr}
uint8_t sercom_offset = _sercom_get_hardware_index(hw);
1dae: 4b1b ldr r3, [pc, #108] ; (1e1c <_usart_init+0x70>)
{
1db0: 4604 mov r4, r0
uint8_t sercom_offset = _sercom_get_hardware_index(hw);
1db2: 4798 blx r3
if (_usarts[i].number == sercom_offset) {
1db4: 2802 cmp r0, #2
1db6: d005 beq.n 1dc4 <_usart_init+0x18>
ASSERT(false);
1db8: 4919 ldr r1, [pc, #100] ; (1e20 <_usart_init+0x74>)
1dba: 4b1a ldr r3, [pc, #104] ; (1e24 <_usart_init+0x78>)
1dbc: f240 2247 movw r2, #583 ; 0x247
1dc0: 2000 movs r0, #0
1dc2: 4798 blx r3
return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
1dc4: 69e3 ldr r3, [r4, #28]
1dc6: 4d18 ldr r5, [pc, #96] ; (1e28 <_usart_init+0x7c>)
uint8_t i = _get_sercom_index(hw);
if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
1dc8: f013 0f01 tst.w r3, #1
1dcc: d10e bne.n 1dec <_usart_init+0x40>
static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw,
hri_sercomusart_ctrla_reg_t mask)
{
uint32_t tmp;
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
1dce: 2103 movs r1, #3
1dd0: 4620 mov r0, r4
1dd2: 47a8 blx r5
tmp = ((Sercom *)hw)->USART.CTRLA.reg;
1dd4: 6823 ldr r3, [r4, #0]
uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk;
if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
1dd6: 079b lsls r3, r3, #30
1dd8: d503 bpl.n 1de2 <_usart_init+0x36>
hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
1dda: 4b14 ldr r3, [pc, #80] ; (1e2c <_usart_init+0x80>)
1ddc: 4798 blx r3
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
1dde: 2102 movs r1, #2
1de0: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg = data;
1de2: 2305 movs r3, #5
1de4: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
1de6: 2103 movs r1, #3
1de8: 4620 mov r0, r4
1dea: 47a8 blx r5
}
hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
}
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
1dec: 4620 mov r0, r4
1dee: 2101 movs r1, #1
1df0: 47a8 blx r5
((Sercom *)hw)->USART.CTRLA.reg = data;
1df2: 4b0f ldr r3, [pc, #60] ; (1e30 <_usart_init+0x84>)
1df4: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
1df6: 2103 movs r1, #3
1df8: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLB.reg = data;
1dfa: f44f 3340 mov.w r3, #196608 ; 0x30000
1dfe: 6063 str r3, [r4, #4]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
1e00: 211f movs r1, #31
1e02: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLC.reg = data;
1e04: 4b0b ldr r3, [pc, #44] ; (1e34 <_usart_init+0x88>)
1e06: 60a3 str r3, [r4, #8]
}
static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.BAUD.reg = data;
1e08: f64f 4311 movw r3, #64529 ; 0xfc11
1e0c: 81a3 strh r3, [r4, #12]
}
static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.RXPL.reg = data;
1e0e: 2300 movs r3, #0
1e10: 73a3 strb r3, [r4, #14]
hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl);
hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl);
return ERR_NONE;
}
1e12: 4618 mov r0, r3
}
static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.DBGCTRL.reg = data;
1e14: f884 3030 strb.w r3, [r4, #48] ; 0x30
1e18: bd38 pop {r3, r4, r5, pc}
1e1a: bf00 nop
1e1c: 00001d75 .word 0x00001d75
1e20: 00003071 .word 0x00003071
1e24: 00001605 .word 0x00001605
1e28: 00001d45 .word 0x00001d45
1e2c: 00001d61 .word 0x00001d61
1e30: 40100004 .word 0x40100004
1e34: 00700002 .word 0x00700002
00001e38 <_usart_sync_init>:
{
1e38: b570 push {r4, r5, r6, lr}
ASSERT(device);
1e3a: 4605 mov r5, r0
1e3c: 3800 subs r0, #0
{
1e3e: 460c mov r4, r1
ASSERT(device);
1e40: 4b05 ldr r3, [pc, #20] ; (1e58 <_usart_sync_init+0x20>)
1e42: 4906 ldr r1, [pc, #24] ; (1e5c <_usart_sync_init+0x24>)
1e44: bf18 it ne
1e46: 2001 movne r0, #1
1e48: 22bb movs r2, #187 ; 0xbb
1e4a: 4798 blx r3
device->hw = hw;
1e4c: 602c str r4, [r5, #0]
return _usart_init(hw);
1e4e: 4620 mov r0, r4
1e50: 4b03 ldr r3, [pc, #12] ; (1e60 <_usart_sync_init+0x28>)
}
1e52: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return _usart_init(hw);
1e56: 4718 bx r3
1e58: 00001605 .word 0x00001605
1e5c: 00003071 .word 0x00003071
1e60: 00001dad .word 0x00001dad
00001e64 <_usart_sync_enable>:
hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw);
1e64: 6800 ldr r0, [r0, #0]
((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
1e66: 6803 ldr r3, [r0, #0]
1e68: f043 0302 orr.w r3, r3, #2
1e6c: 6003 str r3, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
1e6e: 2103 movs r1, #3
1e70: 4b00 ldr r3, [pc, #0] ; (1e74 <_usart_sync_enable+0x10>)
1e72: 4718 bx r3
1e74: 00001d45 .word 0x00001d45
00001e78 <_usart_sync_write_byte>:
hri_sercomusart_write_DATA_reg(device->hw, data);
1e78: 6803 ldr r3, [r0, #0]
((Sercom *)hw)->USART.DATA.reg = data;
1e7a: 6299 str r1, [r3, #40] ; 0x28
}
1e7c: 4770 bx lr
00001e7e <_usart_sync_read_byte>:
return hri_sercomusart_read_DATA_reg(device->hw);
1e7e: 6803 ldr r3, [r0, #0]
return ((Sercom *)hw)->USART.DATA.reg;
1e80: 6a98 ldr r0, [r3, #40] ; 0x28
}
1e82: b2c0 uxtb r0, r0
1e84: 4770 bx lr
00001e86 <_usart_sync_is_ready_to_send>:
return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
1e86: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
1e88: 7e18 ldrb r0, [r3, #24]
}
1e8a: f000 0001 and.w r0, r0, #1
1e8e: 4770 bx lr
00001e90 <_usart_sync_is_transmit_done>:
return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
1e90: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
1e92: 7e18 ldrb r0, [r3, #24]
}
1e94: f3c0 0040 ubfx r0, r0, #1, #1
1e98: 4770 bx lr
00001e9a <_usart_sync_is_byte_received>:
return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
1e9a: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
1e9c: 7e18 ldrb r0, [r3, #24]
}
1e9e: f3c0 0080 ubfx r0, r0, #2, #1
1ea2: 4770 bx lr
00001ea4 <_spi_m_sync_init>:
return NULL;
}
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
{
1ea4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
1ea8: 4b44 ldr r3, [pc, #272] ; (1fbc <_spi_m_sync_init+0x118>)
return NULL;
1eaa: 4d45 ldr r5, [pc, #276] ; (1fc0 <_spi_m_sync_init+0x11c>)
{
1eac: 4607 mov r7, r0
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
1eae: 4608 mov r0, r1
{
1eb0: 460c mov r4, r1
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
1eb2: 4798 blx r3
return NULL;
1eb4: 2804 cmp r0, #4
1eb6: bf18 it ne
1eb8: 2500 movne r5, #0
const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
ASSERT(dev && hw);
1eba: 2f00 cmp r7, #0
1ebc: d05d beq.n 1f7a <_spi_m_sync_init+0xd6>
1ebe: 1e20 subs r0, r4, #0
1ec0: bf18 it ne
1ec2: 2001 movne r0, #1
1ec4: 4e3f ldr r6, [pc, #252] ; (1fc4 <_spi_m_sync_init+0x120>)
1ec6: 4940 ldr r1, [pc, #256] ; (1fc8 <_spi_m_sync_init+0x124>)
1ec8: f640 123f movw r2, #2367 ; 0x93f
1ecc: 47b0 blx r6
if (regs == NULL) {
1ece: 46b0 mov r8, r6
1ed0: 2d00 cmp r5, #0
1ed2: d070 beq.n 1fb6 <_spi_m_sync_init+0x112>
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
1ed4: 69e3 ldr r3, [r4, #28]
1ed6: 4e3d ldr r6, [pc, #244] ; (1fcc <_spi_m_sync_init+0x128>)
return ERR_INVALID_ARG;
}
if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
1ed8: f013 0f01 tst.w r3, #1
1edc: d113 bne.n 1f06 <_spi_m_sync_init+0x62>
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
1ede: 2103 movs r1, #3
1ee0: 4620 mov r0, r4
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
1ee2: f8d5 9000 ldr.w r9, [r5]
1ee6: 47b0 blx r6
tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
1ee8: 6823 ldr r3, [r4, #0]
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
1eea: 079b lsls r3, r3, #30
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
1eec: f009 091c and.w r9, r9, #28
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
1ef0: d503 bpl.n 1efa <_spi_m_sync_init+0x56>
hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
1ef2: 4b37 ldr r3, [pc, #220] ; (1fd0 <_spi_m_sync_init+0x12c>)
1ef4: 4798 blx r3
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
1ef6: 2102 movs r1, #2
1ef8: 47b0 blx r6
}
hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
1efa: f049 0301 orr.w r3, r9, #1
((Sercom *)hw)->SPI.CTRLA.reg = data;
1efe: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
1f00: 2103 movs r1, #3
1f02: 4620 mov r0, r4
1f04: 47b0 blx r6
}
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
1f06: 2101 movs r1, #1
1f08: 4620 mov r0, r4
1f0a: 47b0 blx r6
dev->prvt = hw;
if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
1f0c: 682b ldr r3, [r5, #0]
1f0e: f8df 90c4 ldr.w r9, [pc, #196] ; 1fd4 <_spi_m_sync_init+0x130>
dev->prvt = hw;
1f12: 603c str r4, [r7, #0]
if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
1f14: f003 031c and.w r3, r3, #28
1f18: 2b08 cmp r3, #8
1f1a: d130 bne.n 1f7e <_spi_m_sync_init+0xda>
ASSERT(hw && regs);
1f1c: 492a ldr r1, [pc, #168] ; (1fc8 <_spi_m_sync_init+0x124>)
1f1e: 2001 movs r0, #1
1f20: f640 121d movw r2, #2333 ; 0x91d
1f24: 47c0 blx r8
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
1f26: 682b ldr r3, [r5, #0]
hri_sercomspi_write_CTRLA_reg(
1f28: ea03 0309 and.w r3, r3, r9
((Sercom *)hw)->SPI.CTRLA.reg = data;
1f2c: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
1f2e: 2103 movs r1, #3
1f30: 4620 mov r0, r4
1f32: 47b0 blx r6
(regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN))
1f34: 686b ldr r3, [r5, #4]
| (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN));
1f36: f423 3308 bic.w r3, r3, #139264 ; 0x22000
1f3a: f423 7310 bic.w r3, r3, #576 ; 0x240
hri_sercomspi_write_CTRLB_reg(hw,
1f3e: f443 3300 orr.w r3, r3, #131072 ; 0x20000
1f42: f443 7310 orr.w r3, r3, #576 ; 0x240
((Sercom *)hw)->SPI.CTRLB.reg = data;
1f46: 6063 str r3, [r4, #4]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
1f48: 2117 movs r1, #23
1f4a: 47b0 blx r6
hri_sercomspi_write_ADDR_reg(hw, regs->addr);
1f4c: 68ab ldr r3, [r5, #8]
((Sercom *)hw)->SPI.ADDR.reg = data;
1f4e: 6263 str r3, [r4, #36] ; 0x24
hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
1f50: 7b6b ldrb r3, [r5, #13]
((Sercom *)hw)->SPI.DBGCTRL.reg = data;
1f52: f884 3030 strb.w r3, [r4, #48] ; 0x30
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
1f56: 69e3 ldr r3, [r4, #28]
while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF))
1f58: 2b00 cmp r3, #0
1f5a: d1fc bne.n 1f56 <_spi_m_sync_init+0xb2>
} else {
_spi_load_regs_master(hw, regs);
}
/* Load character size from default hardware configuration */
dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
1f5c: 686b ldr r3, [r5, #4]
1f5e: f013 0f07 tst.w r3, #7
1f62: bf0c ite eq
1f64: 2301 moveq r3, #1
1f66: 2302 movne r3, #2
1f68: 713b strb r3, [r7, #4]
dev->dummy_byte = regs->dummy_byte;
1f6a: 7bab ldrb r3, [r5, #14]
1f6c: 7bea ldrb r2, [r5, #15]
1f6e: ea43 2302 orr.w r3, r3, r2, lsl #8
1f72: 80fb strh r3, [r7, #6]
return ERR_NONE;
1f74: 2000 movs r0, #0
}
1f76: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(dev && hw);
1f7a: 4638 mov r0, r7
1f7c: e7a2 b.n 1ec4 <_spi_m_sync_init+0x20>
ASSERT(hw && regs);
1f7e: 4912 ldr r1, [pc, #72] ; (1fc8 <_spi_m_sync_init+0x124>)
1f80: 2001 movs r0, #1
1f82: f640 1209 movw r2, #2313 ; 0x909
1f86: 47c0 blx r8
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
1f88: 682b ldr r3, [r5, #0]
hri_sercomspi_write_CTRLA_reg(
1f8a: ea03 0309 and.w r3, r3, r9
((Sercom *)hw)->SPI.CTRLA.reg = data;
1f8e: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
1f90: 2103 movs r1, #3
1f92: 4620 mov r0, r4
1f94: 47b0 blx r6
(regs->ctrlb
1f96: 686b ldr r3, [r5, #4]
| (SERCOM_SPI_CTRLB_RXEN));
1f98: f423 3338 bic.w r3, r3, #188416 ; 0x2e000
1f9c: f423 7310 bic.w r3, r3, #576 ; 0x240
hri_sercomspi_write_CTRLB_reg(
1fa0: f443 3300 orr.w r3, r3, #131072 ; 0x20000
((Sercom *)hw)->SPI.CTRLB.reg = data;
1fa4: 6063 str r3, [r4, #4]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
1fa6: 2117 movs r1, #23
1fa8: 47b0 blx r6
hri_sercomspi_write_BAUD_reg(hw, regs->baud);
1faa: 7b2b ldrb r3, [r5, #12]
((Sercom *)hw)->SPI.BAUD.reg = data;
1fac: 7323 strb r3, [r4, #12]
hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
1fae: 7b6b ldrb r3, [r5, #13]
((Sercom *)hw)->SPI.DBGCTRL.reg = data;
1fb0: f884 3030 strb.w r3, [r4, #48] ; 0x30
}
1fb4: e7d2 b.n 1f5c <_spi_m_sync_init+0xb8>
return ERR_INVALID_ARG;
1fb6: f06f 000c mvn.w r0, #12
1fba: e7dc b.n 1f76 <_spi_m_sync_init+0xd2>
1fbc: 00001d75 .word 0x00001d75
1fc0: 000030c4 .word 0x000030c4
1fc4: 00001605 .word 0x00001605
1fc8: 00003071 .word 0x00003071
1fcc: 00001d3d .word 0x00001d3d
1fd0: 00001d4d .word 0x00001d4d
1fd4: fffffefc .word 0xfffffefc
00001fd8 <_spi_m_sync_trans>:
return ERR_NONE;
}
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg)
{
1fd8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
void * hw = dev->prvt;
1fdc: 6804 ldr r4, [r0, #0]
int32_t rc = 0;
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
1fde: f890 8004 ldrb.w r8, [r0, #4]
ASSERT(dev && hw);
1fe2: 4b2a ldr r3, [pc, #168] ; (208c <_spi_m_sync_trans+0xb4>)
{
1fe4: 4607 mov r7, r0
ASSERT(dev && hw);
1fe6: 1e20 subs r0, r4, #0
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
1fe8: e9d1 6500 ldrd r6, r5, [r1]
ASSERT(dev && hw);
1fec: f640 22a3 movw r2, #2723 ; 0xaa3
1ff0: bf18 it ne
1ff2: 2001 movne r0, #1
{
1ff4: 4689 mov r9, r1
ASSERT(dev && hw);
1ff6: 4926 ldr r1, [pc, #152] ; (2090 <_spi_m_sync_trans+0xb8>)
1ff8: 4798 blx r3
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
1ffa: 69e2 ldr r2, [r4, #28]
/* If settings are not applied (pending), we can not go on */
if (hri_sercomspi_is_syncing(
1ffc: f012 0207 ands.w r2, r2, #7
2000: d13e bne.n 2080 <_spi_m_sync_trans+0xa8>
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
2002: 4b24 ldr r3, [pc, #144] ; (2094 <_spi_m_sync_trans+0xbc>)
2004: 2103 movs r1, #3
2006: 4620 mov r0, r4
2008: 4798 blx r3
tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
200a: 6823 ldr r3, [r4, #0]
hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) {
return ERR_BUSY;
}
/* SPI must be enabled to start synchronous transfer */
if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) {
200c: 0799 lsls r1, r3, #30
200e: d53a bpl.n 2086 <_spi_m_sync_trans+0xae>
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
2010: 4611 mov r1, r2
return ((Sercom *)hw)->SPI.INTFLAG.reg;
2012: 7e23 ldrb r3, [r4, #24]
2014: b2d8 uxtb r0, r3
if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) {
2016: 075b lsls r3, r3, #29
2018: d40f bmi.n 203a <_spi_m_sync_trans+0x62>
uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw);
if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) {
/* In master mode, do not start next byte before previous byte received
* to make better output waveform */
if (ctrl.rxcnt >= ctrl.txcnt) {
201a: 428a cmp r2, r1
201c: d818 bhi.n 2050 <_spi_m_sync_trans+0x78>
if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) {
201e: 07c3 lsls r3, r0, #31
2020: d516 bpl.n 2050 <_spi_m_sync_trans+0x78>
_spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte);
2022: 88fb ldrh r3, [r7, #6]
if (ctrl->txbuf) {
2024: b136 cbz r6, 2034 <_spi_m_sync_trans+0x5c>
if (ctrl->char_size > 1) {
2026: f1b8 0f01 cmp.w r8, #1
data = *ctrl->txbuf++;
202a: 7833 ldrb r3, [r6, #0]
data |= (*ctrl->txbuf) << 8;
202c: bf8c ite hi
202e: f836 3b02 ldrhhi.w r3, [r6], #2
data = *ctrl->txbuf++;
2032: 3601 addls r6, #1
ctrl->txcnt++;
2034: 3201 adds r2, #1
((Sercom *)hw)->SPI.DATA.reg = data;
2036: 62a3 str r3, [r4, #40] ; 0x28
}
2038: e00a b.n 2050 <_spi_m_sync_trans+0x78>
return ((Sercom *)hw)->SPI.DATA.reg;
203a: 6aa3 ldr r3, [r4, #40] ; 0x28
if (ctrl->rxbuf) {
203c: b13d cbz r5, 204e <_spi_m_sync_trans+0x76>
if (ctrl->char_size > 1) {
203e: f1b8 0f01 cmp.w r8, #1
*ctrl->rxbuf++ = (uint8_t)data;
2042: 702b strb r3, [r5, #0]
*ctrl->rxbuf++ = (uint8_t)(data >> 8);
2044: bf85 ittet hi
2046: 0a1b lsrhi r3, r3, #8
2048: 706b strbhi r3, [r5, #1]
*ctrl->rxbuf++ = (uint8_t)data;
204a: 3501 addls r5, #1
*ctrl->rxbuf++ = (uint8_t)(data >> 8);
204c: 3502 addhi r5, #2
ctrl->rxcnt++;
204e: 3101 adds r1, #1
if (SERCOM_SPI_INTFLAG_ERROR & iflag) {
2050: 0600 lsls r0, r0, #24
2052: d407 bmi.n 2064 <_spi_m_sync_trans+0x8c>
rc = _spi_err_check(iflag, hw);
if (rc < 0) {
break;
}
if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) {
2054: f8d9 3008 ldr.w r3, [r9, #8]
2058: 4293 cmp r3, r2
205a: d8da bhi.n 2012 <_spi_m_sync_trans+0x3a>
205c: 428b cmp r3, r1
205e: d8d8 bhi.n 2012 <_spi_m_sync_trans+0x3a>
rc = ctrl.txcnt;
2060: 4610 mov r0, r2
while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
2062: e006 b.n 2072 <_spi_m_sync_trans+0x9a>
}
static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.STATUS.reg = mask;
2064: f64f 73ff movw r3, #65535 ; 0xffff
2068: 8363 strh r3, [r4, #26]
((Sercom *)hw)->SPI.INTFLAG.reg = mask;
206a: 2380 movs r3, #128 ; 0x80
206c: 7623 strb r3, [r4, #24]
return ERR_OVERFLOW;
206e: f06f 0012 mvn.w r0, #18
tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
2072: 7e23 ldrb r3, [r4, #24]
while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
2074: 079b lsls r3, r3, #30
2076: d0fc beq.n 2072 <_spi_m_sync_trans+0x9a>
((Sercom *)hw)->SPI.INTFLAG.reg = mask;
2078: 2303 movs r3, #3
207a: 7623 strb r3, [r4, #24]
}
/* Wait until SPI bus idle */
_spi_wait_bus_idle(hw);
return rc;
}
207c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
return ERR_BUSY;
2080: f06f 0003 mvn.w r0, #3
2084: e7fa b.n 207c <_spi_m_sync_trans+0xa4>
return ERR_NOT_INITIALIZED;
2086: f06f 0013 mvn.w r0, #19
208a: e7f7 b.n 207c <_spi_m_sync_trans+0xa4>
208c: 00001605 .word 0x00001605
2090: 00003071 .word 0x00003071
2094: 00001d3d .word 0x00001d3d
00002098 <atomic_enter_critical>:
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
2098: f3ef 8310 mrs r3, PRIMASK
/**
* \brief Disable interrupts, enter critical section
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic)
{
*atomic = __get_PRIMASK();
209c: 6003 str r3, [r0, #0]
__ASM volatile ("cpsid i" : : : "memory");
209e: b672 cpsid i
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
20a0: f3bf 8f5f dmb sy
__disable_irq();
__DMB();
}
20a4: 4770 bx lr
000020a6 <atomic_leave_critical>:
20a6: f3bf 8f5f dmb sy
* \brief Exit atomic section
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic)
{
__DMB();
__set_PRIMASK(*atomic);
20aa: 6803 ldr r3, [r0, #0]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
20ac: f383 8810 msr PRIMASK, r3
}
20b0: 4770 bx lr
...
000020b4 <atmel_start_init>:
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
20b4: b510 push {r4, lr}
system_init();
20b6: 4b04 ldr r3, [pc, #16] ; (20c8 <atmel_start_init+0x14>)
20b8: 4798 blx r3
sd_mmc_stack_init();
20ba: 4b04 ldr r3, [pc, #16] ; (20cc <atmel_start_init+0x18>)
20bc: 4798 blx r3
diskio_init();
}
20be: e8bd 4010 ldmia.w sp!, {r4, lr}
diskio_init();
20c2: 4b03 ldr r3, [pc, #12] ; (20d0 <atmel_start_init+0x1c>)
20c4: 4718 bx r3
20c6: bf00 nop
20c8: 00001d05 .word 0x00001d05
20cc: 000003c5 .word 0x000003c5
20d0: 00001851 .word 0x00001851
000020d4 <pprintf>:
return 0;
}
int pprintf(const char* fmt, ...)
{
20d4: b40f push {r0, r1, r2, r3}
20d6: b530 push {r4, r5, lr}
20d8: b0c3 sub sp, #268 ; 0x10c
size_t size_str = strlen(fmt);
20da: 4c11 ldr r4, [pc, #68] ; (2120 <pprintf+0x4c>)
{
20dc: 9d46 ldr r5, [sp, #280] ; 0x118
size_t size_str = strlen(fmt);
20de: 4628 mov r0, r5
20e0: 47a0 blx r4
if (size_str >= MAX_PRINTF_BUFFER)
20e2: 28ff cmp r0, #255 ; 0xff
20e4: d818 bhi.n 2118 <pprintf+0x44>
{
return -1;
}
uint8_t printf_buffer[MAX_PRINTF_BUFFER];
memset(printf_buffer, '\0', MAX_PRINTF_BUFFER);
20e6: 4b0f ldr r3, [pc, #60] ; (2124 <pprintf+0x50>)
20e8: f44f 7280 mov.w r2, #256 ; 0x100
20ec: 2100 movs r1, #0
20ee: a802 add r0, sp, #8
20f0: 4798 blx r3
va_list args;
va_start(args, fmt);
20f2: aa47 add r2, sp, #284 ; 0x11c
vsprintf((char*)printf_buffer, fmt, args);
20f4: 4b0c ldr r3, [pc, #48] ; (2128 <pprintf+0x54>)
va_start(args, fmt);
20f6: 9201 str r2, [sp, #4]
vsprintf((char*)printf_buffer, fmt, args);
20f8: 4629 mov r1, r5
20fa: a802 add r0, sp, #8
20fc: 4798 blx r3
va_end(args);
return io_write(debug_io, (const uint8_t*)printf_buffer, strlen((const char*)printf_buffer));
20fe: a802 add r0, sp, #8
2100: 47a0 blx r4
2102: 4b0a ldr r3, [pc, #40] ; (212c <pprintf+0x58>)
2104: b282 uxth r2, r0
2106: a902 add r1, sp, #8
2108: 6818 ldr r0, [r3, #0]
210a: 4b09 ldr r3, [pc, #36] ; (2130 <pprintf+0x5c>)
210c: 4798 blx r3
}
210e: b043 add sp, #268 ; 0x10c
2110: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
2114: b004 add sp, #16
2116: 4770 bx lr
return -1;
2118: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
211c: e7f7 b.n 210e <pprintf+0x3a>
211e: bf00 nop
2120: 000021f9 .word 0x000021f9
2124: 000021e9 .word 0x000021e9
2128: 00002235 .word 0x00002235
212c: 20000350 .word 0x20000350
2130: 000002a5 .word 0x000002a5
00002134 <pdebug_init>:
{
2134: b510 push {r4, lr}
usart_sync_get_io_descriptor(&USART_DBG, &debug_io);
2136: 4c06 ldr r4, [pc, #24] ; (2150 <pdebug_init+0x1c>)
2138: 4906 ldr r1, [pc, #24] ; (2154 <pdebug_init+0x20>)
213a: 4b07 ldr r3, [pc, #28] ; (2158 <pdebug_init+0x24>)
213c: 4620 mov r0, r4
213e: 4798 blx r3
usart_sync_enable(&USART_DBG);
2140: 4b06 ldr r3, [pc, #24] ; (215c <pdebug_init+0x28>)
2142: 4620 mov r0, r4
2144: 4798 blx r3
printf("Debug Initialized\n");
2146: 4b06 ldr r3, [pc, #24] ; (2160 <pdebug_init+0x2c>)
2148: 4806 ldr r0, [pc, #24] ; (2164 <pdebug_init+0x30>)
214a: 4798 blx r3
}
214c: 2000 movs r0, #0
214e: bd10 pop {r4, pc}
2150: 20000310 .word 0x20000310
2154: 20000350 .word 0x20000350
2158: 000017e9 .word 0x000017e9
215c: 000017bd .word 0x000017bd
2160: 000020d5 .word 0x000020d5
2164: 000030d5 .word 0x000030d5
00002168 <passert>:
void passert(const bool cond, const char* msg_failure, const char* file, const int line)
{
2168: b510 push {r4, lr}
216a: 460c mov r4, r1
216c: 4619 mov r1, r3
if(!cond)
216e: b920 cbnz r0, 217a <passert+0x12>
{
printf("Assert Failure at line %d, %s: %s\n",
2170: 4623 mov r3, r4
2172: 4802 ldr r0, [pc, #8] ; (217c <passert+0x14>)
2174: 4c02 ldr r4, [pc, #8] ; (2180 <passert+0x18>)
2176: 47a0 blx r4
line,
file,
msg_failure);
for(;;){}
2178: e7fe b.n 2178 <passert+0x10>
}
}
217a: bd10 pop {r4, pc}
217c: 000030e8 .word 0x000030e8
2180: 000020d5 .word 0x000020d5
00002184 <__libc_init_array>:
2184: b570 push {r4, r5, r6, lr}
2186: 4d0d ldr r5, [pc, #52] ; (21bc <__libc_init_array+0x38>)
2188: 4c0d ldr r4, [pc, #52] ; (21c0 <__libc_init_array+0x3c>)
218a: 1b64 subs r4, r4, r5
218c: 10a4 asrs r4, r4, #2
218e: 2600 movs r6, #0
2190: 42a6 cmp r6, r4
2192: d109 bne.n 21a8 <__libc_init_array+0x24>
2194: 4d0b ldr r5, [pc, #44] ; (21c4 <__libc_init_array+0x40>)
2196: 4c0c ldr r4, [pc, #48] ; (21c8 <__libc_init_array+0x44>)
2198: f001 f802 bl 31a0 <_init>
219c: 1b64 subs r4, r4, r5
219e: 10a4 asrs r4, r4, #2
21a0: 2600 movs r6, #0
21a2: 42a6 cmp r6, r4
21a4: d105 bne.n 21b2 <__libc_init_array+0x2e>
21a6: bd70 pop {r4, r5, r6, pc}
21a8: f855 3b04 ldr.w r3, [r5], #4
21ac: 4798 blx r3
21ae: 3601 adds r6, #1
21b0: e7ee b.n 2190 <__libc_init_array+0xc>
21b2: f855 3b04 ldr.w r3, [r5], #4
21b6: 4798 blx r3
21b8: 3601 adds r6, #1
21ba: e7f2 b.n 21a2 <__libc_init_array+0x1e>
21bc: 000031ac .word 0x000031ac
21c0: 000031ac .word 0x000031ac
21c4: 000031ac .word 0x000031ac
21c8: 000031b0 .word 0x000031b0
000021cc <memcpy>:
21cc: 440a add r2, r1
21ce: 4291 cmp r1, r2
21d0: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
21d4: d100 bne.n 21d8 <memcpy+0xc>
21d6: 4770 bx lr
21d8: b510 push {r4, lr}
21da: f811 4b01 ldrb.w r4, [r1], #1
21de: f803 4f01 strb.w r4, [r3, #1]!
21e2: 4291 cmp r1, r2
21e4: d1f9 bne.n 21da <memcpy+0xe>
21e6: bd10 pop {r4, pc}
000021e8 <memset>:
21e8: 4402 add r2, r0
21ea: 4603 mov r3, r0
21ec: 4293 cmp r3, r2
21ee: d100 bne.n 21f2 <memset+0xa>
21f0: 4770 bx lr
21f2: f803 1b01 strb.w r1, [r3], #1
21f6: e7f9 b.n 21ec <memset+0x4>
000021f8 <strlen>:
21f8: 4603 mov r3, r0
21fa: f813 2b01 ldrb.w r2, [r3], #1
21fe: 2a00 cmp r2, #0
2200: d1fb bne.n 21fa <strlen+0x2>
2202: 1a18 subs r0, r3, r0
2204: 3801 subs r0, #1
2206: 4770 bx lr
00002208 <_vsiprintf_r>:
2208: b500 push {lr}
220a: b09b sub sp, #108 ; 0x6c
220c: 9100 str r1, [sp, #0]
220e: 9104 str r1, [sp, #16]
2210: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
2214: 9105 str r1, [sp, #20]
2216: 9102 str r1, [sp, #8]
2218: 4905 ldr r1, [pc, #20] ; (2230 <_vsiprintf_r+0x28>)
221a: 9103 str r1, [sp, #12]
221c: 4669 mov r1, sp
221e: f000 f8cb bl 23b8 <_svfiprintf_r>
2222: 9b00 ldr r3, [sp, #0]
2224: 2200 movs r2, #0
2226: 701a strb r2, [r3, #0]
2228: b01b add sp, #108 ; 0x6c
222a: f85d fb04 ldr.w pc, [sp], #4
222e: bf00 nop
2230: ffff0208 .word 0xffff0208
00002234 <vsiprintf>:
2234: 4613 mov r3, r2
2236: 460a mov r2, r1
2238: 4601 mov r1, r0
223a: 4802 ldr r0, [pc, #8] ; (2244 <vsiprintf+0x10>)
223c: 6800 ldr r0, [r0, #0]
223e: f7ff bfe3 b.w 2208 <_vsiprintf_r>
2242: bf00 nop
2244: 20000008 .word 0x20000008
00002248 <__retarget_lock_acquire_recursive>:
2248: 4770 bx lr
0000224a <__retarget_lock_release_recursive>:
224a: 4770 bx lr
0000224c <_malloc_r>:
224c: b5f8 push {r3, r4, r5, r6, r7, lr}
224e: 1ccd adds r5, r1, #3
2250: f025 0503 bic.w r5, r5, #3
2254: 3508 adds r5, #8
2256: 2d0c cmp r5, #12
2258: bf38 it cc
225a: 250c movcc r5, #12
225c: 2d00 cmp r5, #0
225e: 4606 mov r6, r0
2260: db01 blt.n 2266 <_malloc_r+0x1a>
2262: 42a9 cmp r1, r5
2264: d903 bls.n 226e <_malloc_r+0x22>
2266: 230c movs r3, #12
2268: 6033 str r3, [r6, #0]
226a: 2000 movs r0, #0
226c: bdf8 pop {r3, r4, r5, r6, r7, pc}
226e: f000 fbb1 bl 29d4 <__malloc_lock>
2272: 4921 ldr r1, [pc, #132] ; (22f8 <_malloc_r+0xac>)
2274: 680a ldr r2, [r1, #0]
2276: 4614 mov r4, r2
2278: b99c cbnz r4, 22a2 <_malloc_r+0x56>
227a: 4f20 ldr r7, [pc, #128] ; (22fc <_malloc_r+0xb0>)
227c: 683b ldr r3, [r7, #0]
227e: b923 cbnz r3, 228a <_malloc_r+0x3e>
2280: 4621 mov r1, r4
2282: 4630 mov r0, r6
2284: f000 fb2c bl 28e0 <_sbrk_r>
2288: 6038 str r0, [r7, #0]
228a: 4629 mov r1, r5
228c: 4630 mov r0, r6
228e: f000 fb27 bl 28e0 <_sbrk_r>
2292: 1c43 adds r3, r0, #1
2294: d123 bne.n 22de <_malloc_r+0x92>
2296: 230c movs r3, #12
2298: 6033 str r3, [r6, #0]
229a: 4630 mov r0, r6
229c: f000 fba0 bl 29e0 <__malloc_unlock>
22a0: e7e3 b.n 226a <_malloc_r+0x1e>
22a2: 6823 ldr r3, [r4, #0]
22a4: 1b5b subs r3, r3, r5
22a6: d417 bmi.n 22d8 <_malloc_r+0x8c>
22a8: 2b0b cmp r3, #11
22aa: d903 bls.n 22b4 <_malloc_r+0x68>
22ac: 6023 str r3, [r4, #0]
22ae: 441c add r4, r3
22b0: 6025 str r5, [r4, #0]
22b2: e004 b.n 22be <_malloc_r+0x72>
22b4: 6863 ldr r3, [r4, #4]
22b6: 42a2 cmp r2, r4
22b8: bf0c ite eq
22ba: 600b streq r3, [r1, #0]
22bc: 6053 strne r3, [r2, #4]
22be: 4630 mov r0, r6
22c0: f000 fb8e bl 29e0 <__malloc_unlock>
22c4: f104 000b add.w r0, r4, #11
22c8: 1d23 adds r3, r4, #4
22ca: f020 0007 bic.w r0, r0, #7
22ce: 1ac2 subs r2, r0, r3
22d0: d0cc beq.n 226c <_malloc_r+0x20>
22d2: 1a1b subs r3, r3, r0
22d4: 50a3 str r3, [r4, r2]
22d6: e7c9 b.n 226c <_malloc_r+0x20>
22d8: 4622 mov r2, r4
22da: 6864 ldr r4, [r4, #4]
22dc: e7cc b.n 2278 <_malloc_r+0x2c>
22de: 1cc4 adds r4, r0, #3
22e0: f024 0403 bic.w r4, r4, #3
22e4: 42a0 cmp r0, r4
22e6: d0e3 beq.n 22b0 <_malloc_r+0x64>
22e8: 1a21 subs r1, r4, r0
22ea: 4630 mov r0, r6
22ec: f000 faf8 bl 28e0 <_sbrk_r>
22f0: 3001 adds r0, #1
22f2: d1dd bne.n 22b0 <_malloc_r+0x64>
22f4: e7cf b.n 2296 <_malloc_r+0x4a>
22f6: bf00 nop
22f8: 20000354 .word 0x20000354
22fc: 20000358 .word 0x20000358
00002300 <__ssputs_r>:
2300: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
2304: 688e ldr r6, [r1, #8]
2306: 429e cmp r6, r3
2308: 4682 mov sl, r0
230a: 460c mov r4, r1
230c: 4690 mov r8, r2
230e: 461f mov r7, r3
2310: d838 bhi.n 2384 <__ssputs_r+0x84>
2312: 898a ldrh r2, [r1, #12]
2314: f412 6f90 tst.w r2, #1152 ; 0x480
2318: d032 beq.n 2380 <__ssputs_r+0x80>
231a: 6825 ldr r5, [r4, #0]
231c: 6909 ldr r1, [r1, #16]
231e: eba5 0901 sub.w r9, r5, r1
2322: 6965 ldr r5, [r4, #20]
2324: eb05 0545 add.w r5, r5, r5, lsl #1
2328: eb05 75d5 add.w r5, r5, r5, lsr #31
232c: 3301 adds r3, #1
232e: 444b add r3, r9
2330: 106d asrs r5, r5, #1
2332: 429d cmp r5, r3
2334: bf38 it cc
2336: 461d movcc r5, r3
2338: 0553 lsls r3, r2, #21
233a: d531 bpl.n 23a0 <__ssputs_r+0xa0>
233c: 4629 mov r1, r5
233e: f7ff ff85 bl 224c <_malloc_r>
2342: 4606 mov r6, r0
2344: b950 cbnz r0, 235c <__ssputs_r+0x5c>
2346: 230c movs r3, #12
2348: f8ca 3000 str.w r3, [sl]
234c: 89a3 ldrh r3, [r4, #12]
234e: f043 0340 orr.w r3, r3, #64 ; 0x40
2352: 81a3 strh r3, [r4, #12]
2354: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
2358: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
235c: 6921 ldr r1, [r4, #16]
235e: 464a mov r2, r9
2360: f7ff ff34 bl 21cc <memcpy>
2364: 89a3 ldrh r3, [r4, #12]
2366: f423 6390 bic.w r3, r3, #1152 ; 0x480
236a: f043 0380 orr.w r3, r3, #128 ; 0x80
236e: 81a3 strh r3, [r4, #12]
2370: 6126 str r6, [r4, #16]
2372: 6165 str r5, [r4, #20]
2374: 444e add r6, r9
2376: eba5 0509 sub.w r5, r5, r9
237a: 6026 str r6, [r4, #0]
237c: 60a5 str r5, [r4, #8]
237e: 463e mov r6, r7
2380: 42be cmp r6, r7
2382: d900 bls.n 2386 <__ssputs_r+0x86>
2384: 463e mov r6, r7
2386: 4632 mov r2, r6
2388: 6820 ldr r0, [r4, #0]
238a: 4641 mov r1, r8
238c: f000 fb08 bl 29a0 <memmove>
2390: 68a3 ldr r3, [r4, #8]
2392: 6822 ldr r2, [r4, #0]
2394: 1b9b subs r3, r3, r6
2396: 4432 add r2, r6
2398: 60a3 str r3, [r4, #8]
239a: 6022 str r2, [r4, #0]
239c: 2000 movs r0, #0
239e: e7db b.n 2358 <__ssputs_r+0x58>
23a0: 462a mov r2, r5
23a2: f000 fb71 bl 2a88 <_realloc_r>
23a6: 4606 mov r6, r0
23a8: 2800 cmp r0, #0
23aa: d1e1 bne.n 2370 <__ssputs_r+0x70>
23ac: 6921 ldr r1, [r4, #16]
23ae: 4650 mov r0, sl
23b0: f000 fb1c bl 29ec <_free_r>
23b4: e7c7 b.n 2346 <__ssputs_r+0x46>
...
000023b8 <_svfiprintf_r>:
23b8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
23bc: 4698 mov r8, r3
23be: 898b ldrh r3, [r1, #12]
23c0: 061b lsls r3, r3, #24
23c2: b09d sub sp, #116 ; 0x74
23c4: 4607 mov r7, r0
23c6: 460d mov r5, r1
23c8: 4614 mov r4, r2
23ca: d50e bpl.n 23ea <_svfiprintf_r+0x32>
23cc: 690b ldr r3, [r1, #16]
23ce: b963 cbnz r3, 23ea <_svfiprintf_r+0x32>
23d0: 2140 movs r1, #64 ; 0x40
23d2: f7ff ff3b bl 224c <_malloc_r>
23d6: 6028 str r0, [r5, #0]
23d8: 6128 str r0, [r5, #16]
23da: b920 cbnz r0, 23e6 <_svfiprintf_r+0x2e>
23dc: 230c movs r3, #12
23de: 603b str r3, [r7, #0]
23e0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
23e4: e0d1 b.n 258a <_svfiprintf_r+0x1d2>
23e6: 2340 movs r3, #64 ; 0x40
23e8: 616b str r3, [r5, #20]
23ea: 2300 movs r3, #0
23ec: 9309 str r3, [sp, #36] ; 0x24
23ee: 2320 movs r3, #32
23f0: f88d 3029 strb.w r3, [sp, #41] ; 0x29
23f4: f8cd 800c str.w r8, [sp, #12]
23f8: 2330 movs r3, #48 ; 0x30
23fa: f8df 81a8 ldr.w r8, [pc, #424] ; 25a4 <_svfiprintf_r+0x1ec>
23fe: f88d 302a strb.w r3, [sp, #42] ; 0x2a
2402: f04f 0901 mov.w r9, #1
2406: 4623 mov r3, r4
2408: 469a mov sl, r3
240a: f813 2b01 ldrb.w r2, [r3], #1
240e: b10a cbz r2, 2414 <_svfiprintf_r+0x5c>
2410: 2a25 cmp r2, #37 ; 0x25
2412: d1f9 bne.n 2408 <_svfiprintf_r+0x50>
2414: ebba 0b04 subs.w fp, sl, r4
2418: d00b beq.n 2432 <_svfiprintf_r+0x7a>
241a: 465b mov r3, fp
241c: 4622 mov r2, r4
241e: 4629 mov r1, r5
2420: 4638 mov r0, r7
2422: f7ff ff6d bl 2300 <__ssputs_r>
2426: 3001 adds r0, #1
2428: f000 80aa beq.w 2580 <_svfiprintf_r+0x1c8>
242c: 9a09 ldr r2, [sp, #36] ; 0x24
242e: 445a add r2, fp
2430: 9209 str r2, [sp, #36] ; 0x24
2432: f89a 3000 ldrb.w r3, [sl]
2436: 2b00 cmp r3, #0
2438: f000 80a2 beq.w 2580 <_svfiprintf_r+0x1c8>
243c: 2300 movs r3, #0
243e: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
2442: e9cd 2305 strd r2, r3, [sp, #20]
2446: f10a 0a01 add.w sl, sl, #1
244a: 9304 str r3, [sp, #16]
244c: 9307 str r3, [sp, #28]
244e: f88d 3053 strb.w r3, [sp, #83] ; 0x53
2452: 931a str r3, [sp, #104] ; 0x68
2454: 4654 mov r4, sl
2456: 2205 movs r2, #5
2458: f814 1b01 ldrb.w r1, [r4], #1
245c: 4851 ldr r0, [pc, #324] ; (25a4 <_svfiprintf_r+0x1ec>)
245e: f000 fa4f bl 2900 <memchr>
2462: 9a04 ldr r2, [sp, #16]
2464: b9d8 cbnz r0, 249e <_svfiprintf_r+0xe6>
2466: 06d0 lsls r0, r2, #27
2468: bf44 itt mi
246a: 2320 movmi r3, #32
246c: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
2470: 0711 lsls r1, r2, #28
2472: bf44 itt mi
2474: 232b movmi r3, #43 ; 0x2b
2476: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
247a: f89a 3000 ldrb.w r3, [sl]
247e: 2b2a cmp r3, #42 ; 0x2a
2480: d015 beq.n 24ae <_svfiprintf_r+0xf6>
2482: 9a07 ldr r2, [sp, #28]
2484: 4654 mov r4, sl
2486: 2000 movs r0, #0
2488: f04f 0c0a mov.w ip, #10
248c: 4621 mov r1, r4
248e: f811 3b01 ldrb.w r3, [r1], #1
2492: 3b30 subs r3, #48 ; 0x30
2494: 2b09 cmp r3, #9
2496: d94e bls.n 2536 <_svfiprintf_r+0x17e>
2498: b1b0 cbz r0, 24c8 <_svfiprintf_r+0x110>
249a: 9207 str r2, [sp, #28]
249c: e014 b.n 24c8 <_svfiprintf_r+0x110>
249e: eba0 0308 sub.w r3, r0, r8
24a2: fa09 f303 lsl.w r3, r9, r3
24a6: 4313 orrs r3, r2
24a8: 9304 str r3, [sp, #16]
24aa: 46a2 mov sl, r4
24ac: e7d2 b.n 2454 <_svfiprintf_r+0x9c>
24ae: 9b03 ldr r3, [sp, #12]
24b0: 1d19 adds r1, r3, #4
24b2: 681b ldr r3, [r3, #0]
24b4: 9103 str r1, [sp, #12]
24b6: 2b00 cmp r3, #0
24b8: bfbb ittet lt
24ba: 425b neglt r3, r3
24bc: f042 0202 orrlt.w r2, r2, #2
24c0: 9307 strge r3, [sp, #28]
24c2: 9307 strlt r3, [sp, #28]
24c4: bfb8 it lt
24c6: 9204 strlt r2, [sp, #16]
24c8: 7823 ldrb r3, [r4, #0]
24ca: 2b2e cmp r3, #46 ; 0x2e
24cc: d10c bne.n 24e8 <_svfiprintf_r+0x130>
24ce: 7863 ldrb r3, [r4, #1]
24d0: 2b2a cmp r3, #42 ; 0x2a
24d2: d135 bne.n 2540 <_svfiprintf_r+0x188>
24d4: 9b03 ldr r3, [sp, #12]
24d6: 1d1a adds r2, r3, #4
24d8: 681b ldr r3, [r3, #0]
24da: 9203 str r2, [sp, #12]
24dc: 2b00 cmp r3, #0
24de: bfb8 it lt
24e0: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff
24e4: 3402 adds r4, #2
24e6: 9305 str r3, [sp, #20]
24e8: f8df a0c8 ldr.w sl, [pc, #200] ; 25b4 <_svfiprintf_r+0x1fc>
24ec: 7821 ldrb r1, [r4, #0]
24ee: 2203 movs r2, #3
24f0: 4650 mov r0, sl
24f2: f000 fa05 bl 2900 <memchr>
24f6: b140 cbz r0, 250a <_svfiprintf_r+0x152>
24f8: 2340 movs r3, #64 ; 0x40
24fa: eba0 000a sub.w r0, r0, sl
24fe: fa03 f000 lsl.w r0, r3, r0
2502: 9b04 ldr r3, [sp, #16]
2504: 4303 orrs r3, r0
2506: 3401 adds r4, #1
2508: 9304 str r3, [sp, #16]
250a: f814 1b01 ldrb.w r1, [r4], #1
250e: 4826 ldr r0, [pc, #152] ; (25a8 <_svfiprintf_r+0x1f0>)
2510: f88d 1028 strb.w r1, [sp, #40] ; 0x28
2514: 2206 movs r2, #6
2516: f000 f9f3 bl 2900 <memchr>
251a: 2800 cmp r0, #0
251c: d038 beq.n 2590 <_svfiprintf_r+0x1d8>
251e: 4b23 ldr r3, [pc, #140] ; (25ac <_svfiprintf_r+0x1f4>)
2520: bb1b cbnz r3, 256a <_svfiprintf_r+0x1b2>
2522: 9b03 ldr r3, [sp, #12]
2524: 3307 adds r3, #7
2526: f023 0307 bic.w r3, r3, #7
252a: 3308 adds r3, #8
252c: 9303 str r3, [sp, #12]
252e: 9b09 ldr r3, [sp, #36] ; 0x24
2530: 4433 add r3, r6
2532: 9309 str r3, [sp, #36] ; 0x24
2534: e767 b.n 2406 <_svfiprintf_r+0x4e>
2536: fb0c 3202 mla r2, ip, r2, r3
253a: 460c mov r4, r1
253c: 2001 movs r0, #1
253e: e7a5 b.n 248c <_svfiprintf_r+0xd4>
2540: 2300 movs r3, #0
2542: 3401 adds r4, #1
2544: 9305 str r3, [sp, #20]
2546: 4619 mov r1, r3
2548: f04f 0c0a mov.w ip, #10
254c: 4620 mov r0, r4
254e: f810 2b01 ldrb.w r2, [r0], #1
2552: 3a30 subs r2, #48 ; 0x30
2554: 2a09 cmp r2, #9
2556: d903 bls.n 2560 <_svfiprintf_r+0x1a8>
2558: 2b00 cmp r3, #0
255a: d0c5 beq.n 24e8 <_svfiprintf_r+0x130>
255c: 9105 str r1, [sp, #20]
255e: e7c3 b.n 24e8 <_svfiprintf_r+0x130>
2560: fb0c 2101 mla r1, ip, r1, r2
2564: 4604 mov r4, r0
2566: 2301 movs r3, #1
2568: e7f0 b.n 254c <_svfiprintf_r+0x194>
256a: ab03 add r3, sp, #12
256c: 9300 str r3, [sp, #0]
256e: 462a mov r2, r5
2570: 4b0f ldr r3, [pc, #60] ; (25b0 <_svfiprintf_r+0x1f8>)
2572: a904 add r1, sp, #16
2574: 4638 mov r0, r7
2576: f3af 8000 nop.w
257a: 1c42 adds r2, r0, #1
257c: 4606 mov r6, r0
257e: d1d6 bne.n 252e <_svfiprintf_r+0x176>
2580: 89ab ldrh r3, [r5, #12]
2582: 065b lsls r3, r3, #25
2584: f53f af2c bmi.w 23e0 <_svfiprintf_r+0x28>
2588: 9809 ldr r0, [sp, #36] ; 0x24
258a: b01d add sp, #116 ; 0x74
258c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
2590: ab03 add r3, sp, #12
2592: 9300 str r3, [sp, #0]
2594: 462a mov r2, r5
2596: 4b06 ldr r3, [pc, #24] ; (25b0 <_svfiprintf_r+0x1f8>)
2598: a904 add r1, sp, #16
259a: 4638 mov r0, r7
259c: f000 f87a bl 2694 <_printf_i>
25a0: e7eb b.n 257a <_svfiprintf_r+0x1c2>
25a2: bf00 nop
25a4: 0000316c .word 0x0000316c
25a8: 00003176 .word 0x00003176
25ac: 00000000 .word 0x00000000
25b0: 00002301 .word 0x00002301
25b4: 00003172 .word 0x00003172
000025b8 <_printf_common>:
25b8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
25bc: 4616 mov r6, r2
25be: 4699 mov r9, r3
25c0: 688a ldr r2, [r1, #8]
25c2: 690b ldr r3, [r1, #16]
25c4: f8dd 8020 ldr.w r8, [sp, #32]
25c8: 4293 cmp r3, r2
25ca: bfb8 it lt
25cc: 4613 movlt r3, r2
25ce: 6033 str r3, [r6, #0]
25d0: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
25d4: 4607 mov r7, r0
25d6: 460c mov r4, r1
25d8: b10a cbz r2, 25de <_printf_common+0x26>
25da: 3301 adds r3, #1
25dc: 6033 str r3, [r6, #0]
25de: 6823 ldr r3, [r4, #0]
25e0: 0699 lsls r1, r3, #26
25e2: bf42 ittt mi
25e4: 6833 ldrmi r3, [r6, #0]
25e6: 3302 addmi r3, #2
25e8: 6033 strmi r3, [r6, #0]
25ea: 6825 ldr r5, [r4, #0]
25ec: f015 0506 ands.w r5, r5, #6
25f0: d106 bne.n 2600 <_printf_common+0x48>
25f2: f104 0a19 add.w sl, r4, #25
25f6: 68e3 ldr r3, [r4, #12]
25f8: 6832 ldr r2, [r6, #0]
25fa: 1a9b subs r3, r3, r2
25fc: 42ab cmp r3, r5
25fe: dc26 bgt.n 264e <_printf_common+0x96>
2600: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
2604: 1e13 subs r3, r2, #0
2606: 6822 ldr r2, [r4, #0]
2608: bf18 it ne
260a: 2301 movne r3, #1
260c: 0692 lsls r2, r2, #26
260e: d42b bmi.n 2668 <_printf_common+0xb0>
2610: f104 0243 add.w r2, r4, #67 ; 0x43
2614: 4649 mov r1, r9
2616: 4638 mov r0, r7
2618: 47c0 blx r8
261a: 3001 adds r0, #1
261c: d01e beq.n 265c <_printf_common+0xa4>
261e: 6823 ldr r3, [r4, #0]
2620: 68e5 ldr r5, [r4, #12]
2622: 6832 ldr r2, [r6, #0]
2624: f003 0306 and.w r3, r3, #6
2628: 2b04 cmp r3, #4
262a: bf08 it eq
262c: 1aad subeq r5, r5, r2
262e: 68a3 ldr r3, [r4, #8]
2630: 6922 ldr r2, [r4, #16]
2632: bf0c ite eq
2634: ea25 75e5 biceq.w r5, r5, r5, asr #31
2638: 2500 movne r5, #0
263a: 4293 cmp r3, r2
263c: bfc4 itt gt
263e: 1a9b subgt r3, r3, r2
2640: 18ed addgt r5, r5, r3
2642: 2600 movs r6, #0
2644: 341a adds r4, #26
2646: 42b5 cmp r5, r6
2648: d11a bne.n 2680 <_printf_common+0xc8>
264a: 2000 movs r0, #0
264c: e008 b.n 2660 <_printf_common+0xa8>
264e: 2301 movs r3, #1
2650: 4652 mov r2, sl
2652: 4649 mov r1, r9
2654: 4638 mov r0, r7
2656: 47c0 blx r8
2658: 3001 adds r0, #1
265a: d103 bne.n 2664 <_printf_common+0xac>
265c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
2660: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
2664: 3501 adds r5, #1
2666: e7c6 b.n 25f6 <_printf_common+0x3e>
2668: 18e1 adds r1, r4, r3
266a: 1c5a adds r2, r3, #1
266c: 2030 movs r0, #48 ; 0x30
266e: f881 0043 strb.w r0, [r1, #67] ; 0x43
2672: 4422 add r2, r4
2674: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
2678: f882 1043 strb.w r1, [r2, #67] ; 0x43
267c: 3302 adds r3, #2
267e: e7c7 b.n 2610 <_printf_common+0x58>
2680: 2301 movs r3, #1
2682: 4622 mov r2, r4
2684: 4649 mov r1, r9
2686: 4638 mov r0, r7
2688: 47c0 blx r8
268a: 3001 adds r0, #1
268c: d0e6 beq.n 265c <_printf_common+0xa4>
268e: 3601 adds r6, #1
2690: e7d9 b.n 2646 <_printf_common+0x8e>
...
00002694 <_printf_i>:
2694: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
2698: 460c mov r4, r1
269a: 4691 mov r9, r2
269c: 7e27 ldrb r7, [r4, #24]
269e: 990c ldr r1, [sp, #48] ; 0x30
26a0: 2f78 cmp r7, #120 ; 0x78
26a2: 4680 mov r8, r0
26a4: 469a mov sl, r3
26a6: f104 0243 add.w r2, r4, #67 ; 0x43
26aa: d807 bhi.n 26bc <_printf_i+0x28>
26ac: 2f62 cmp r7, #98 ; 0x62
26ae: d80a bhi.n 26c6 <_printf_i+0x32>
26b0: 2f00 cmp r7, #0
26b2: f000 80d8 beq.w 2866 <_printf_i+0x1d2>
26b6: 2f58 cmp r7, #88 ; 0x58
26b8: f000 80a3 beq.w 2802 <_printf_i+0x16e>
26bc: f104 0642 add.w r6, r4, #66 ; 0x42
26c0: f884 7042 strb.w r7, [r4, #66] ; 0x42
26c4: e03a b.n 273c <_printf_i+0xa8>
26c6: f1a7 0363 sub.w r3, r7, #99 ; 0x63
26ca: 2b15 cmp r3, #21
26cc: d8f6 bhi.n 26bc <_printf_i+0x28>
26ce: a001 add r0, pc, #4 ; (adr r0, 26d4 <_printf_i+0x40>)
26d0: f850 f023 ldr.w pc, [r0, r3, lsl #2]
26d4: 0000272d .word 0x0000272d
26d8: 00002741 .word 0x00002741
26dc: 000026bd .word 0x000026bd
26e0: 000026bd .word 0x000026bd
26e4: 000026bd .word 0x000026bd
26e8: 000026bd .word 0x000026bd
26ec: 00002741 .word 0x00002741
26f0: 000026bd .word 0x000026bd
26f4: 000026bd .word 0x000026bd
26f8: 000026bd .word 0x000026bd
26fc: 000026bd .word 0x000026bd
2700: 0000284d .word 0x0000284d
2704: 00002771 .word 0x00002771
2708: 0000282f .word 0x0000282f
270c: 000026bd .word 0x000026bd
2710: 000026bd .word 0x000026bd
2714: 0000286f .word 0x0000286f
2718: 000026bd .word 0x000026bd
271c: 00002771 .word 0x00002771
2720: 000026bd .word 0x000026bd
2724: 000026bd .word 0x000026bd
2728: 00002837 .word 0x00002837
272c: 680b ldr r3, [r1, #0]
272e: 1d1a adds r2, r3, #4
2730: 681b ldr r3, [r3, #0]
2732: 600a str r2, [r1, #0]
2734: f104 0642 add.w r6, r4, #66 ; 0x42
2738: f884 3042 strb.w r3, [r4, #66] ; 0x42
273c: 2301 movs r3, #1
273e: e0a3 b.n 2888 <_printf_i+0x1f4>
2740: 6825 ldr r5, [r4, #0]
2742: 6808 ldr r0, [r1, #0]
2744: 062e lsls r6, r5, #24
2746: f100 0304 add.w r3, r0, #4
274a: d50a bpl.n 2762 <_printf_i+0xce>
274c: 6805 ldr r5, [r0, #0]
274e: 600b str r3, [r1, #0]
2750: 2d00 cmp r5, #0
2752: da03 bge.n 275c <_printf_i+0xc8>
2754: 232d movs r3, #45 ; 0x2d
2756: 426d negs r5, r5
2758: f884 3043 strb.w r3, [r4, #67] ; 0x43
275c: 485e ldr r0, [pc, #376] ; (28d8 <_printf_i+0x244>)
275e: 230a movs r3, #10
2760: e019 b.n 2796 <_printf_i+0x102>
2762: f015 0f40 tst.w r5, #64 ; 0x40
2766: 6805 ldr r5, [r0, #0]
2768: 600b str r3, [r1, #0]
276a: bf18 it ne
276c: b22d sxthne r5, r5
276e: e7ef b.n 2750 <_printf_i+0xbc>
2770: 680b ldr r3, [r1, #0]
2772: 6825 ldr r5, [r4, #0]
2774: 1d18 adds r0, r3, #4
2776: 6008 str r0, [r1, #0]
2778: 0628 lsls r0, r5, #24
277a: d501 bpl.n 2780 <_printf_i+0xec>
277c: 681d ldr r5, [r3, #0]
277e: e002 b.n 2786 <_printf_i+0xf2>
2780: 0669 lsls r1, r5, #25
2782: d5fb bpl.n 277c <_printf_i+0xe8>
2784: 881d ldrh r5, [r3, #0]
2786: 4854 ldr r0, [pc, #336] ; (28d8 <_printf_i+0x244>)
2788: 2f6f cmp r7, #111 ; 0x6f
278a: bf0c ite eq
278c: 2308 moveq r3, #8
278e: 230a movne r3, #10
2790: 2100 movs r1, #0
2792: f884 1043 strb.w r1, [r4, #67] ; 0x43
2796: 6866 ldr r6, [r4, #4]
2798: 60a6 str r6, [r4, #8]
279a: 2e00 cmp r6, #0
279c: bfa2 ittt ge
279e: 6821 ldrge r1, [r4, #0]
27a0: f021 0104 bicge.w r1, r1, #4
27a4: 6021 strge r1, [r4, #0]
27a6: b90d cbnz r5, 27ac <_printf_i+0x118>
27a8: 2e00 cmp r6, #0
27aa: d04d beq.n 2848 <_printf_i+0x1b4>
27ac: 4616 mov r6, r2
27ae: fbb5 f1f3 udiv r1, r5, r3
27b2: fb03 5711 mls r7, r3, r1, r5
27b6: 5dc7 ldrb r7, [r0, r7]
27b8: f806 7d01 strb.w r7, [r6, #-1]!
27bc: 462f mov r7, r5
27be: 42bb cmp r3, r7
27c0: 460d mov r5, r1
27c2: d9f4 bls.n 27ae <_printf_i+0x11a>
27c4: 2b08 cmp r3, #8
27c6: d10b bne.n 27e0 <_printf_i+0x14c>
27c8: 6823 ldr r3, [r4, #0]
27ca: 07df lsls r7, r3, #31
27cc: d508 bpl.n 27e0 <_printf_i+0x14c>
27ce: 6923 ldr r3, [r4, #16]
27d0: 6861 ldr r1, [r4, #4]
27d2: 4299 cmp r1, r3
27d4: bfde ittt le
27d6: 2330 movle r3, #48 ; 0x30
27d8: f806 3c01 strble.w r3, [r6, #-1]
27dc: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff
27e0: 1b92 subs r2, r2, r6
27e2: 6122 str r2, [r4, #16]
27e4: f8cd a000 str.w sl, [sp]
27e8: 464b mov r3, r9
27ea: aa03 add r2, sp, #12
27ec: 4621 mov r1, r4
27ee: 4640 mov r0, r8
27f0: f7ff fee2 bl 25b8 <_printf_common>
27f4: 3001 adds r0, #1
27f6: d14c bne.n 2892 <_printf_i+0x1fe>
27f8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
27fc: b004 add sp, #16
27fe: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
2802: 4835 ldr r0, [pc, #212] ; (28d8 <_printf_i+0x244>)
2804: f884 7045 strb.w r7, [r4, #69] ; 0x45
2808: 6823 ldr r3, [r4, #0]
280a: 680e ldr r6, [r1, #0]
280c: 061f lsls r7, r3, #24
280e: f856 5b04 ldr.w r5, [r6], #4
2812: 600e str r6, [r1, #0]
2814: d514 bpl.n 2840 <_printf_i+0x1ac>
2816: 07d9 lsls r1, r3, #31
2818: bf44 itt mi
281a: f043 0320 orrmi.w r3, r3, #32
281e: 6023 strmi r3, [r4, #0]
2820: b91d cbnz r5, 282a <_printf_i+0x196>
2822: 6823 ldr r3, [r4, #0]
2824: f023 0320 bic.w r3, r3, #32
2828: 6023 str r3, [r4, #0]
282a: 2310 movs r3, #16
282c: e7b0 b.n 2790 <_printf_i+0xfc>
282e: 6823 ldr r3, [r4, #0]
2830: f043 0320 orr.w r3, r3, #32
2834: 6023 str r3, [r4, #0]
2836: 2378 movs r3, #120 ; 0x78
2838: 4828 ldr r0, [pc, #160] ; (28dc <_printf_i+0x248>)
283a: f884 3045 strb.w r3, [r4, #69] ; 0x45
283e: e7e3 b.n 2808 <_printf_i+0x174>
2840: 065e lsls r6, r3, #25
2842: bf48 it mi
2844: b2ad uxthmi r5, r5
2846: e7e6 b.n 2816 <_printf_i+0x182>
2848: 4616 mov r6, r2
284a: e7bb b.n 27c4 <_printf_i+0x130>
284c: 680b ldr r3, [r1, #0]
284e: 6826 ldr r6, [r4, #0]
2850: 6960 ldr r0, [r4, #20]
2852: 1d1d adds r5, r3, #4
2854: 600d str r5, [r1, #0]
2856: 0635 lsls r5, r6, #24
2858: 681b ldr r3, [r3, #0]
285a: d501 bpl.n 2860 <_printf_i+0x1cc>
285c: 6018 str r0, [r3, #0]
285e: e002 b.n 2866 <_printf_i+0x1d2>
2860: 0671 lsls r1, r6, #25
2862: d5fb bpl.n 285c <_printf_i+0x1c8>
2864: 8018 strh r0, [r3, #0]
2866: 2300 movs r3, #0
2868: 6123 str r3, [r4, #16]
286a: 4616 mov r6, r2
286c: e7ba b.n 27e4 <_printf_i+0x150>
286e: 680b ldr r3, [r1, #0]
2870: 1d1a adds r2, r3, #4
2872: 600a str r2, [r1, #0]
2874: 681e ldr r6, [r3, #0]
2876: 6862 ldr r2, [r4, #4]
2878: 2100 movs r1, #0
287a: 4630 mov r0, r6
287c: f000 f840 bl 2900 <memchr>
2880: b108 cbz r0, 2886 <_printf_i+0x1f2>
2882: 1b80 subs r0, r0, r6
2884: 6060 str r0, [r4, #4]
2886: 6863 ldr r3, [r4, #4]
2888: 6123 str r3, [r4, #16]
288a: 2300 movs r3, #0
288c: f884 3043 strb.w r3, [r4, #67] ; 0x43
2890: e7a8 b.n 27e4 <_printf_i+0x150>
2892: 6923 ldr r3, [r4, #16]
2894: 4632 mov r2, r6
2896: 4649 mov r1, r9
2898: 4640 mov r0, r8
289a: 47d0 blx sl
289c: 3001 adds r0, #1
289e: d0ab beq.n 27f8 <_printf_i+0x164>
28a0: 6823 ldr r3, [r4, #0]
28a2: 079b lsls r3, r3, #30
28a4: d413 bmi.n 28ce <_printf_i+0x23a>
28a6: 68e0 ldr r0, [r4, #12]
28a8: 9b03 ldr r3, [sp, #12]
28aa: 4298 cmp r0, r3
28ac: bfb8 it lt
28ae: 4618 movlt r0, r3
28b0: e7a4 b.n 27fc <_printf_i+0x168>
28b2: 2301 movs r3, #1
28b4: 4632 mov r2, r6
28b6: 4649 mov r1, r9
28b8: 4640 mov r0, r8
28ba: 47d0 blx sl
28bc: 3001 adds r0, #1
28be: d09b beq.n 27f8 <_printf_i+0x164>
28c0: 3501 adds r5, #1
28c2: 68e3 ldr r3, [r4, #12]
28c4: 9903 ldr r1, [sp, #12]
28c6: 1a5b subs r3, r3, r1
28c8: 42ab cmp r3, r5
28ca: dcf2 bgt.n 28b2 <_printf_i+0x21e>
28cc: e7eb b.n 28a6 <_printf_i+0x212>
28ce: 2500 movs r5, #0
28d0: f104 0619 add.w r6, r4, #25
28d4: e7f5 b.n 28c2 <_printf_i+0x22e>
28d6: bf00 nop
28d8: 0000317d .word 0x0000317d
28dc: 0000318e .word 0x0000318e
000028e0 <_sbrk_r>:
28e0: b538 push {r3, r4, r5, lr}
28e2: 4d06 ldr r5, [pc, #24] ; (28fc <_sbrk_r+0x1c>)
28e4: 2300 movs r3, #0
28e6: 4604 mov r4, r0
28e8: 4608 mov r0, r1
28ea: 602b str r3, [r5, #0]
28ec: f7fd fd76 bl 3dc <_sbrk>
28f0: 1c43 adds r3, r0, #1
28f2: d102 bne.n 28fa <_sbrk_r+0x1a>
28f4: 682b ldr r3, [r5, #0]
28f6: b103 cbz r3, 28fa <_sbrk_r+0x1a>
28f8: 6023 str r3, [r4, #0]
28fa: bd38 pop {r3, r4, r5, pc}
28fc: 20000368 .word 0x20000368
00002900 <memchr>:
2900: f001 01ff and.w r1, r1, #255 ; 0xff
2904: 2a10 cmp r2, #16
2906: db2b blt.n 2960 <memchr+0x60>
2908: f010 0f07 tst.w r0, #7
290c: d008 beq.n 2920 <memchr+0x20>
290e: f810 3b01 ldrb.w r3, [r0], #1
2912: 3a01 subs r2, #1
2914: 428b cmp r3, r1
2916: d02d beq.n 2974 <memchr+0x74>
2918: f010 0f07 tst.w r0, #7
291c: b342 cbz r2, 2970 <memchr+0x70>
291e: d1f6 bne.n 290e <memchr+0xe>
2920: b4f0 push {r4, r5, r6, r7}
2922: ea41 2101 orr.w r1, r1, r1, lsl #8
2926: ea41 4101 orr.w r1, r1, r1, lsl #16
292a: f022 0407 bic.w r4, r2, #7
292e: f07f 0700 mvns.w r7, #0
2932: 2300 movs r3, #0
2934: e8f0 5602 ldrd r5, r6, [r0], #8
2938: 3c08 subs r4, #8
293a: ea85 0501 eor.w r5, r5, r1
293e: ea86 0601 eor.w r6, r6, r1
2942: fa85 f547 uadd8 r5, r5, r7
2946: faa3 f587 sel r5, r3, r7
294a: fa86 f647 uadd8 r6, r6, r7
294e: faa5 f687 sel r6, r5, r7
2952: b98e cbnz r6, 2978 <memchr+0x78>
2954: d1ee bne.n 2934 <memchr+0x34>
2956: bcf0 pop {r4, r5, r6, r7}
2958: f001 01ff and.w r1, r1, #255 ; 0xff
295c: f002 0207 and.w r2, r2, #7
2960: b132 cbz r2, 2970 <memchr+0x70>
2962: f810 3b01 ldrb.w r3, [r0], #1
2966: 3a01 subs r2, #1
2968: ea83 0301 eor.w r3, r3, r1
296c: b113 cbz r3, 2974 <memchr+0x74>
296e: d1f8 bne.n 2962 <memchr+0x62>
2970: 2000 movs r0, #0
2972: 4770 bx lr
2974: 3801 subs r0, #1
2976: 4770 bx lr
2978: 2d00 cmp r5, #0
297a: bf06 itte eq
297c: 4635 moveq r5, r6
297e: 3803 subeq r0, #3
2980: 3807 subne r0, #7
2982: f015 0f01 tst.w r5, #1
2986: d107 bne.n 2998 <memchr+0x98>
2988: 3001 adds r0, #1
298a: f415 7f80 tst.w r5, #256 ; 0x100
298e: bf02 ittt eq
2990: 3001 addeq r0, #1
2992: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
2996: 3001 addeq r0, #1
2998: bcf0 pop {r4, r5, r6, r7}
299a: 3801 subs r0, #1
299c: 4770 bx lr
299e: bf00 nop
000029a0 <memmove>:
29a0: 4288 cmp r0, r1
29a2: b510 push {r4, lr}
29a4: eb01 0402 add.w r4, r1, r2
29a8: d902 bls.n 29b0 <memmove+0x10>
29aa: 4284 cmp r4, r0
29ac: 4623 mov r3, r4
29ae: d807 bhi.n 29c0 <memmove+0x20>
29b0: 1e43 subs r3, r0, #1
29b2: 42a1 cmp r1, r4
29b4: d008 beq.n 29c8 <memmove+0x28>
29b6: f811 2b01 ldrb.w r2, [r1], #1
29ba: f803 2f01 strb.w r2, [r3, #1]!
29be: e7f8 b.n 29b2 <memmove+0x12>
29c0: 4402 add r2, r0
29c2: 4601 mov r1, r0
29c4: 428a cmp r2, r1
29c6: d100 bne.n 29ca <memmove+0x2a>
29c8: bd10 pop {r4, pc}
29ca: f813 4d01 ldrb.w r4, [r3, #-1]!
29ce: f802 4d01 strb.w r4, [r2, #-1]!
29d2: e7f7 b.n 29c4 <memmove+0x24>
000029d4 <__malloc_lock>:
29d4: 4801 ldr r0, [pc, #4] ; (29dc <__malloc_lock+0x8>)
29d6: f7ff bc37 b.w 2248 <__retarget_lock_acquire_recursive>
29da: bf00 nop
29dc: 20000360 .word 0x20000360
000029e0 <__malloc_unlock>:
29e0: 4801 ldr r0, [pc, #4] ; (29e8 <__malloc_unlock+0x8>)
29e2: f7ff bc32 b.w 224a <__retarget_lock_release_recursive>
29e6: bf00 nop
29e8: 20000360 .word 0x20000360
000029ec <_free_r>:
29ec: b538 push {r3, r4, r5, lr}
29ee: 4605 mov r5, r0
29f0: 2900 cmp r1, #0
29f2: d045 beq.n 2a80 <_free_r+0x94>
29f4: f851 3c04 ldr.w r3, [r1, #-4]
29f8: 1f0c subs r4, r1, #4
29fa: 2b00 cmp r3, #0
29fc: bfb8 it lt
29fe: 18e4 addlt r4, r4, r3
2a00: f7ff ffe8 bl 29d4 <__malloc_lock>
2a04: 4a1f ldr r2, [pc, #124] ; (2a84 <_free_r+0x98>)
2a06: 6813 ldr r3, [r2, #0]
2a08: 4610 mov r0, r2
2a0a: b933 cbnz r3, 2a1a <_free_r+0x2e>
2a0c: 6063 str r3, [r4, #4]
2a0e: 6014 str r4, [r2, #0]
2a10: 4628 mov r0, r5
2a12: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
2a16: f7ff bfe3 b.w 29e0 <__malloc_unlock>
2a1a: 42a3 cmp r3, r4
2a1c: d90b bls.n 2a36 <_free_r+0x4a>
2a1e: 6821 ldr r1, [r4, #0]
2a20: 1862 adds r2, r4, r1
2a22: 4293 cmp r3, r2
2a24: bf04 itt eq
2a26: 681a ldreq r2, [r3, #0]
2a28: 685b ldreq r3, [r3, #4]
2a2a: 6063 str r3, [r4, #4]
2a2c: bf04 itt eq
2a2e: 1852 addeq r2, r2, r1
2a30: 6022 streq r2, [r4, #0]
2a32: 6004 str r4, [r0, #0]
2a34: e7ec b.n 2a10 <_free_r+0x24>
2a36: 461a mov r2, r3
2a38: 685b ldr r3, [r3, #4]
2a3a: b10b cbz r3, 2a40 <_free_r+0x54>
2a3c: 42a3 cmp r3, r4
2a3e: d9fa bls.n 2a36 <_free_r+0x4a>
2a40: 6811 ldr r1, [r2, #0]
2a42: 1850 adds r0, r2, r1
2a44: 42a0 cmp r0, r4
2a46: d10b bne.n 2a60 <_free_r+0x74>
2a48: 6820 ldr r0, [r4, #0]
2a4a: 4401 add r1, r0
2a4c: 1850 adds r0, r2, r1
2a4e: 4283 cmp r3, r0
2a50: 6011 str r1, [r2, #0]
2a52: d1dd bne.n 2a10 <_free_r+0x24>
2a54: 6818 ldr r0, [r3, #0]
2a56: 685b ldr r3, [r3, #4]
2a58: 6053 str r3, [r2, #4]
2a5a: 4401 add r1, r0
2a5c: 6011 str r1, [r2, #0]
2a5e: e7d7 b.n 2a10 <_free_r+0x24>
2a60: d902 bls.n 2a68 <_free_r+0x7c>
2a62: 230c movs r3, #12
2a64: 602b str r3, [r5, #0]
2a66: e7d3 b.n 2a10 <_free_r+0x24>
2a68: 6820 ldr r0, [r4, #0]
2a6a: 1821 adds r1, r4, r0
2a6c: 428b cmp r3, r1
2a6e: bf04 itt eq
2a70: 6819 ldreq r1, [r3, #0]
2a72: 685b ldreq r3, [r3, #4]
2a74: 6063 str r3, [r4, #4]
2a76: bf04 itt eq
2a78: 1809 addeq r1, r1, r0
2a7a: 6021 streq r1, [r4, #0]
2a7c: 6054 str r4, [r2, #4]
2a7e: e7c7 b.n 2a10 <_free_r+0x24>
2a80: bd38 pop {r3, r4, r5, pc}
2a82: bf00 nop
2a84: 20000354 .word 0x20000354
00002a88 <_realloc_r>:
2a88: b5f8 push {r3, r4, r5, r6, r7, lr}
2a8a: 4607 mov r7, r0
2a8c: 4614 mov r4, r2
2a8e: 460e mov r6, r1
2a90: b921 cbnz r1, 2a9c <_realloc_r+0x14>
2a92: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
2a96: 4611 mov r1, r2
2a98: f7ff bbd8 b.w 224c <_malloc_r>
2a9c: b922 cbnz r2, 2aa8 <_realloc_r+0x20>
2a9e: f7ff ffa5 bl 29ec <_free_r>
2aa2: 4625 mov r5, r4
2aa4: 4628 mov r0, r5
2aa6: bdf8 pop {r3, r4, r5, r6, r7, pc}
2aa8: f000 f814 bl 2ad4 <_malloc_usable_size_r>
2aac: 42a0 cmp r0, r4
2aae: d20f bcs.n 2ad0 <_realloc_r+0x48>
2ab0: 4621 mov r1, r4
2ab2: 4638 mov r0, r7
2ab4: f7ff fbca bl 224c <_malloc_r>
2ab8: 4605 mov r5, r0
2aba: 2800 cmp r0, #0
2abc: d0f2 beq.n 2aa4 <_realloc_r+0x1c>
2abe: 4631 mov r1, r6
2ac0: 4622 mov r2, r4
2ac2: f7ff fb83 bl 21cc <memcpy>
2ac6: 4631 mov r1, r6
2ac8: 4638 mov r0, r7
2aca: f7ff ff8f bl 29ec <_free_r>
2ace: e7e9 b.n 2aa4 <_realloc_r+0x1c>
2ad0: 4635 mov r5, r6
2ad2: e7e7 b.n 2aa4 <_realloc_r+0x1c>
00002ad4 <_malloc_usable_size_r>:
2ad4: f851 3c04 ldr.w r3, [r1, #-4]
2ad8: 1f18 subs r0, r3, #4
2ada: 2b00 cmp r3, #0
2adc: bfbc itt lt
2ade: 580b ldrlt r3, [r1, r0]
2ae0: 18c0 addlt r0, r0, r3
2ae2: 4770 bx lr
2ae4: 682f2e2e .word 0x682f2e2e
2ae8: 732f6c61 .word 0x732f6c61
2aec: 682f6372 .word 0x682f6372
2af0: 695f6c61 .word 0x695f6c61
2af4: 00632e6f .word 0x00632e6f
2af8: 682f2e2e .word 0x682f2e2e
2afc: 732f6c61 .word 0x732f6c61
2b00: 682f6372 .word 0x682f6372
2b04: 635f6c61 .word 0x635f6c61
2b08: 6e656c61 .word 0x6e656c61
2b0c: 2e726164 .word 0x2e726164
2b10: 0063 .short 0x0063
2b12: 2e2e .short 0x2e2e
2b14: 5f64732f .word 0x5f64732f
2b18: 2f636d6d .word 0x2f636d6d
2b1c: 6d5f6473 .word 0x6d5f6473
2b20: 632e636d .word 0x632e636d
2b24: 3e3e3e00 .word 0x3e3e3e00
2b28: 61745300 .word 0x61745300
2b2c: 53207472 .word 0x53207472
2b30: 61632044 .word 0x61632044
2b34: 69206472 .word 0x69206472
2b38: 6174736e .word 0x6174736e
2b3c: 0d0a6c6c .word 0x0d0a6c6c
2b40: 3a732500 .word 0x3a732500
2b44: 444d4320 .word 0x444d4320
2b48: 46203535 .word 0x46203535
2b4c: 0a6c6961 .word 0x0a6c6961
2b50: 7325000d .word 0x7325000d
2b54: 4341203a .word 0x4341203a
2b58: 3134444d .word 0x3134444d
2b5c: 69614620 .word 0x69614620
2b60: 000d0a6c .word 0x000d0a6c
2b64: 203a7325 .word 0x203a7325
2b68: 444d4341 .word 0x444d4341
2b6c: 54203134 .word 0x54203134
2b70: 6f656d69 .word 0x6f656d69
2b74: 6f207475 .word 0x6f207475
2b78: 7562206e .word 0x7562206e
2b7c: 202c7973 .word 0x202c7973
2b80: 70736572 .word 0x70736572
2b84: 30203233 .word 0x30203233
2b88: 38302578 .word 0x38302578
2b8c: 0d0a2078 .word 0x0d0a2078
2b90: 3a732500 .word 0x3a732500
2b94: 444d4320 .word 0x444d4320
2b98: 46203835 .word 0x46203835
2b9c: 0a6c6961 .word 0x0a6c6961
2ba0: 7453000d .word 0x7453000d
2ba4: 20747261 .word 0x20747261
2ba8: 20434d4d .word 0x20434d4d
2bac: 74736e49 .word 0x74736e49
2bb0: 0a6c6c61 .word 0x0a6c6c61
2bb4: 7325000d .word 0x7325000d
2bb8: 4d43203a .word 0x4d43203a
2bbc: 53203144 .word 0x53203144
2bc0: 46204950 .word 0x46204950
2bc4: 206c6961 .word 0x206c6961
2bc8: 7542202d .word 0x7542202d
2bcc: 72207973 .word 0x72207973
2bd0: 79727465 .word 0x79727465
2bd4: 0a642520 .word 0x0a642520
2bd8: 7325000d .word 0x7325000d
2bdc: 4d43203a .word 0x4d43203a
2be0: 54203144 .word 0x54203144
2be4: 6f656d69 .word 0x6f656d69
2be8: 6f207475 .word 0x6f207475
2bec: 7562206e .word 0x7562206e
2bf0: 0d0a7973 .word 0x0d0a7973
2bf4: 2f445300 .word 0x2f445300
2bf8: 20434d4d .word 0x20434d4d
2bfc: 64726163 .word 0x64726163
2c00: 61657220 .word 0x61657220
2c04: 0d0a7964 .word 0x0d0a7964
2c08: 00000000 .word 0x00000000
00002c0c <__func__.1>:
2c0c: 735f6473 6f5f6970 6f635f70 sd_spi_op_cond.
00002c1b <__func__.0>:
2c1b: 5f636d6d 5f697073 635f706f 00646e6f mmc_spi_op_cond.
...
00002c2c <mmc_trans_multipliers>:
2c2c: 00000000 0000000a 0000000c 0000000d ................
2c3c: 0000000f 00000014 0000001a 0000001e ................
2c4c: 00000023 00000028 0000002d 00000034 #...(...-...4...
2c5c: 00000037 0000003c 00000046 00000050 7...<...F...P...
00002c6c <sd_mmc_trans_units>:
2c6c: 0000000a 00000064 000003e8 00002710 ....d........'..
...
00002c88 <sd_trans_multipliers>:
2c88: 00000000 0000000a 0000000c 0000000d ................
2c98: 0000000f 00000014 00000019 0000001e ................
2ca8: 00000023 00000028 0000002d 00000032 #...(...-...2...
2cb8: 00000037 0000003c 00000046 00000050 7...<...F...P...
2cc8: 732f2e2e 6d6d5f64 64732f63 636d6d5f ../sd_mmc/sd_mmc
2cd8: 6970735f 2500632e 52203a73 20646165 _spi.c.%s: Read
2ce8: 636f6c62 7420736b 6f656d69 0d0a7475 blocks timeout..
2cf8: 3a732500 43524320 74616420 72652061 .%s: CRC data er
2d08: 20726f72 656b6f74 000d0a6e 203a7325 ror token...%s:
2d18: 2074754f 7220666f 65676e61 74616420 Out of range dat
2d28: 72652061 20726f72 656b6f74 000d0a6e a error token...
2d38: 203a7325 61766e49 2064696c 61746144 %s: Invalid Data
2d48: 73655220 736e6f70 6f542065 206e656b Response Token
2d58: 78257830 25000d0a 57203a73 65746972 0x%x...%s: Write
2d68: 6f6c6220 2c736b63 5f445320 5f434d4d blocks, SD_MMC_
2d78: 5f495053 5f525245 2c435243 73657220 SPI_ERR_CRC, res
2d88: 78302070 0d0a7825 3a732500 69725720 p 0x%x...%s: Wri
2d98: 62206574 6b636f6c 44532073 434d4d5f te blocks SD_MMC
2da8: 4950535f 5252455f 2c52575f 73657220 _SPI_ERR_WR, res
2db8: 78302070 0d0a7825 3a732500 6f745320 p 0x%x...%s: Sto
2dc8: 72772070 20657469 636f6c62 7420736b p write blocks t
2dd8: 6f656d69 0d0a7475 206f4e00 43204453 imeout...No SD C
2de8: 20647261 70736572 65736e6f 73617720 ard response was
2df8: 65727020 746e6573 002e2e2e 203a7325 present....%s:
2e08: 20646d63 64323025 7261202c 78302067 cmd %02d, arg 0x
2e18: 6c383025 52202c58 69742031 756f656d %08lX, R1 timeou
2e28: 000a0d74 203a7325 20646d63 64323025 t...%s: cmd %02d
2e38: 7261202c 78302067 6c383025 72202c78 , arg 0x%08lx, r
2e48: 78302031 78323025 3152202c 4950535f 1 0x%02x, R1_SPI
2e58: 4d4f435f 4352435f 25000d0a 63203a73 _COM_CRC...%s: c
2e68: 2520646d 2c643230 67726120 25783020 md %02d, arg 0x%
2e78: 786c3830 3172202c 25783020 52202c78 08lx, r1 0x%x, R
2e88: 4c492031 4147454c 4f435f4c 4e414d4d 1 ILLEGAL_COMMAN
2e98: 000d0a44 203a7325 20646d63 64323025 D...%s: cmd %02d
2ea8: 7261202c 78302067 6c383025 72202c78 , arg 0x%08lx, r
2eb8: 78302031 202c7825 65203152 726f7272 1 0x%x, R1 error
2ec8: 25000d0a 63203a73 2520646d 2c643230 ...%s: cmd %02d,
2ed8: 67726120 25783020 786c3830 7542202c arg 0x%08lx, Bu
2ee8: 73207973 616e6769 6c61206c 73796177 sy signal always
2ef8: 67696820 000d0a68 203a7325 74697257 high...%s: Writ
2f08: 6c622065 736b636f 6d697420 74756f65 e blocks timeout
2f18: 3c000d0a ...<<<.
00002f1f <__func__.5>:
2f1f: 5f697073 79735f6d 735f636e 74726174 spi_m_sync_start
2f2f: 6165725f 6c625f64 006b636f _read_block.
00002f3b <__func__.3>:
2f3b: 5f697073 79735f6d 735f636e 5f706f74 spi_m_sync_stop_
2f4b: 74697277 6c625f65 006b636f write_block.
00002f57 <__func__.1>:
2f57: 5f697073 79735f6d 735f636e 5f706f74 spi_m_sync_stop_
2f67: 746c756d 69727769 625f6574 6b636f6c multiwrite_block
...
00002f78 <__func__.6>:
2f78: 5f697073 79735f6d 615f636e 5f637464 spi_m_sync_adtc_
2f88: 72617473 start.
00002f8e <__func__.4>:
2f8e: 5f697073 79735f6d 735f636e 74726174 spi_m_sync_start
2f9e: 6972775f 625f6574 6b636f6c _write_blocks.
00002fac <__func__.2>:
2fac: 5f697073 79735f6d 775f636e 5f746961 spi_m_sync_wait_
2fbc: 5f646e65 775f666f 65746972 6f6c625f end_of_write_blo
2fcc: 00736b63 cks.
00002fd0 <__func__.0>:
2fd0: 5f697073 79735f6d 775f636e 65746972 spi_m_sync_write
2fe0: 726f775f 2e2e0064 6c61682f 6372732f _word.../hal/src
2ff0: 6c61682f 6970735f 735f6d5f 2e636e79 /hal_spi_m_sync.
3000: 2e2e0063 6c61682f 6372732f 6c61682f c.../hal/src/hal
3010: 69636d5f 6e79735f 00632e63 682f2e2e _mci_sync.c.../h
3020: 732f6c70 2f636864 5f6c7068 63686473 pl/sdhc/hpl_sdhc
3030: 2e00632e 61682f2e 72732f6c 61682f63 .c.../hal/src/ha
3040: 73755f6c 5f747261 636e7973 4800632e l_usart_sync.c.H
3050: 6f6c6c65 726f7720 000a646c 682f2e2e ello world..../h
3060: 722f6c70 682f6374 725f6c70 632e6374 pl/rtc/hpl_rtc.c
3070: 2f2e2e00 2f6c7068 63726573 682f6d6f .../hpl/sercom/h
3080: 735f6c70 6f637265 00632e6d 40003000 pl_sercom.c..0.@
3090: 40003400 41012000 41014000 43000000 .4.@. .A.@.A...C
30a0: 43000400 43000800 43000c00 ...C...C...C
000030ac <_i2cms>:
...
000030c4 <sercomspi_regs>:
30c4: 0030000c 00020000 00000000 01ff00fe ..0.............
30d4: 62654404 49206775 6974696e 7a696c61 .Debug Initializ
30e4: 000a6465 65737341 46207472 756c6961 ed..Assert Failu
30f4: 61206572 696c2074 2520656e 25202c64 re at line %d, %
3104: 25203a73 00000a73 s: %s...
0000310c <__sf_fake_stderr>:
...
0000312c <__sf_fake_stdin>:
...
0000314c <__sf_fake_stdout>:
...
316c: 2b302d23 6c680020 6665004c 47464567 #-0+ .hlL.efgEFG
317c: 32313000 36353433 41393837 45444342 .0123456789ABCDE
318c: 31300046 35343332 39383736 64636261 F.0123456789abcd
319c: 00006665 ef..
000031a0 <_init>:
31a0: b5f8 push {r3, r4, r5, r6, r7, lr}
31a2: bf00 nop
31a4: bcf8 pop {r3, r4, r5, r6, r7}
31a6: bc08 pop {r3}
31a8: 469e mov lr, r3
31aa: 4770 bx lr
000031ac <__frame_dummy_init_array_entry>:
31ac: 0289 0000 ....
000031b0 <_fini>:
31b0: b5f8 push {r3, r4, r5, r6, r7, lr}
31b2: bf00 nop
31b4: bcf8 pop {r3, r4, r5, r6, r7}
31b6: bc08 pop {r3}
31b8: 469e mov lr, r3
31ba: 4770 bx lr
000031bc <__do_global_dtors_aux_fini_array_entry>:
31bc: 0265 0000 e...
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