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100 lines
6.3 KiB
C
100 lines
6.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for TCC4
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAME54_TCC4_INSTANCE_
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#define _SAME54_TCC4_INSTANCE_
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/* ========== Register definition for TCC4 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TCC4_CTRLA (0x43001000) /**< \brief (TCC4) Control A */
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#define REG_TCC4_CTRLBCLR (0x43001004) /**< \brief (TCC4) Control B Clear */
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#define REG_TCC4_CTRLBSET (0x43001005) /**< \brief (TCC4) Control B Set */
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#define REG_TCC4_SYNCBUSY (0x43001008) /**< \brief (TCC4) Synchronization Busy */
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#define REG_TCC4_FCTRLA (0x4300100C) /**< \brief (TCC4) Recoverable Fault A Configuration */
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#define REG_TCC4_FCTRLB (0x43001010) /**< \brief (TCC4) Recoverable Fault B Configuration */
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#define REG_TCC4_DRVCTRL (0x43001018) /**< \brief (TCC4) Driver Control */
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#define REG_TCC4_DBGCTRL (0x4300101E) /**< \brief (TCC4) Debug Control */
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#define REG_TCC4_EVCTRL (0x43001020) /**< \brief (TCC4) Event Control */
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#define REG_TCC4_INTENCLR (0x43001024) /**< \brief (TCC4) Interrupt Enable Clear */
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#define REG_TCC4_INTENSET (0x43001028) /**< \brief (TCC4) Interrupt Enable Set */
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#define REG_TCC4_INTFLAG (0x4300102C) /**< \brief (TCC4) Interrupt Flag Status and Clear */
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#define REG_TCC4_STATUS (0x43001030) /**< \brief (TCC4) Status */
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#define REG_TCC4_COUNT (0x43001034) /**< \brief (TCC4) Count */
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#define REG_TCC4_WAVE (0x4300103C) /**< \brief (TCC4) Waveform Control */
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#define REG_TCC4_PER (0x43001040) /**< \brief (TCC4) Period */
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#define REG_TCC4_CC0 (0x43001044) /**< \brief (TCC4) Compare and Capture 0 */
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#define REG_TCC4_CC1 (0x43001048) /**< \brief (TCC4) Compare and Capture 1 */
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#define REG_TCC4_PERBUF (0x4300106C) /**< \brief (TCC4) Period Buffer */
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#define REG_TCC4_CCBUF0 (0x43001070) /**< \brief (TCC4) Compare and Capture Buffer 0 */
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#define REG_TCC4_CCBUF1 (0x43001074) /**< \brief (TCC4) Compare and Capture Buffer 1 */
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#else
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#define REG_TCC4_CTRLA (*(RwReg *)0x43001000UL) /**< \brief (TCC4) Control A */
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#define REG_TCC4_CTRLBCLR (*(RwReg8 *)0x43001004UL) /**< \brief (TCC4) Control B Clear */
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#define REG_TCC4_CTRLBSET (*(RwReg8 *)0x43001005UL) /**< \brief (TCC4) Control B Set */
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#define REG_TCC4_SYNCBUSY (*(RoReg *)0x43001008UL) /**< \brief (TCC4) Synchronization Busy */
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#define REG_TCC4_FCTRLA (*(RwReg *)0x4300100CUL) /**< \brief (TCC4) Recoverable Fault A Configuration */
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#define REG_TCC4_FCTRLB (*(RwReg *)0x43001010UL) /**< \brief (TCC4) Recoverable Fault B Configuration */
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#define REG_TCC4_DRVCTRL (*(RwReg *)0x43001018UL) /**< \brief (TCC4) Driver Control */
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#define REG_TCC4_DBGCTRL (*(RwReg8 *)0x4300101EUL) /**< \brief (TCC4) Debug Control */
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#define REG_TCC4_EVCTRL (*(RwReg *)0x43001020UL) /**< \brief (TCC4) Event Control */
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#define REG_TCC4_INTENCLR (*(RwReg *)0x43001024UL) /**< \brief (TCC4) Interrupt Enable Clear */
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#define REG_TCC4_INTENSET (*(RwReg *)0x43001028UL) /**< \brief (TCC4) Interrupt Enable Set */
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#define REG_TCC4_INTFLAG (*(RwReg *)0x4300102CUL) /**< \brief (TCC4) Interrupt Flag Status and Clear */
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#define REG_TCC4_STATUS (*(RwReg *)0x43001030UL) /**< \brief (TCC4) Status */
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#define REG_TCC4_COUNT (*(RwReg *)0x43001034UL) /**< \brief (TCC4) Count */
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#define REG_TCC4_WAVE (*(RwReg *)0x4300103CUL) /**< \brief (TCC4) Waveform Control */
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#define REG_TCC4_PER (*(RwReg *)0x43001040UL) /**< \brief (TCC4) Period */
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#define REG_TCC4_CC0 (*(RwReg *)0x43001044UL) /**< \brief (TCC4) Compare and Capture 0 */
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#define REG_TCC4_CC1 (*(RwReg *)0x43001048UL) /**< \brief (TCC4) Compare and Capture 1 */
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#define REG_TCC4_PERBUF (*(RwReg *)0x4300106CUL) /**< \brief (TCC4) Period Buffer */
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#define REG_TCC4_CCBUF0 (*(RwReg *)0x43001070UL) /**< \brief (TCC4) Compare and Capture Buffer 0 */
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#define REG_TCC4_CCBUF1 (*(RwReg *)0x43001074UL) /**< \brief (TCC4) Compare and Capture Buffer 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TCC4 peripheral ========== */
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#define TCC4_CC_NUM 2 // Number of Compare/Capture units
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#define TCC4_DITHERING 0 // Dithering feature implemented
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#define TCC4_DMAC_ID_MC_0 42
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#define TCC4_DMAC_ID_MC_1 43
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#define TCC4_DMAC_ID_MC_LSB 42
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#define TCC4_DMAC_ID_MC_MSB 43
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#define TCC4_DMAC_ID_MC_SIZE 2
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#define TCC4_DMAC_ID_OVF 41 // DMA overflow/underflow/retrigger trigger
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#define TCC4_DTI 0 // Dead-Time-Insertion feature implemented
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#define TCC4_EXT 0 // Coding of implemented extended features
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#define TCC4_GCLK_ID 38 // Index of Generic Clock
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#define TCC4_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
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#define TCC4_OTMX 0 // Output Matrix feature implemented
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#define TCC4_OW_NUM 2 // Number of Output Waveforms
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#define TCC4_PG 0 // Pattern Generation feature implemented
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#define TCC4_SIZE 16
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#define TCC4_SWAP 0 // DTI outputs swap feature implemented
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#endif /* _SAME54_TCC4_INSTANCE_ */
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