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78 lines
3.7 KiB
C
78 lines
3.7 KiB
C
/**
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* \file
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*
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* \brief Instance description for NVMCTRL
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_NVMCTRL_INSTANCE_
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#define _SAMD21_NVMCTRL_INSTANCE_
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/* ========== Register definition for NVMCTRL peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */
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#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */
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#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
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#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
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#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */
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#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
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#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */
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#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */
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#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */
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#else
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#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
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#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */
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#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
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#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
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#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */
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#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
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#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */
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#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */
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#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for NVMCTRL peripheral ========== */
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#define NVMCTRL_AUX0_ADDRESS 0x00804000
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#define NVMCTRL_AUX1_ADDRESS 0x00806000
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#define NVMCTRL_AUX2_ADDRESS 0x00808000
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#define NVMCTRL_AUX3_ADDRESS 0x0080A000
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#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
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#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
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#define NVMCTRL_FLASH_SIZE 262144
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#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
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#define NVMCTRL_PAGE_HW 32
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#define NVMCTRL_PAGE_SIZE 64
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#define NVMCTRL_PAGE_W 16
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#define NVMCTRL_PMSB 3
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#define NVMCTRL_PSZ_BITS 6
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#define NVMCTRL_ROW_PAGES 4
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#define NVMCTRL_ROW_SIZE 256
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#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030
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#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
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#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
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#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
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#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
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