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762 lines
21 KiB
C
762 lines
21 KiB
C
/**
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* \file
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*
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* \brief SAM ICM
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAME54_ICM_COMPONENT_
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#ifndef _HRI_ICM_E54_H_INCLUDED_
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#define _HRI_ICM_E54_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_ICM_CRITICAL_SECTIONS)
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#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define ICM_CRITICAL_SECTION_ENTER()
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#define ICM_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_icm_cfg_reg_t;
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typedef uint32_t hri_icm_ctrl_reg_t;
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typedef uint32_t hri_icm_dscr_reg_t;
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typedef uint32_t hri_icm_hash_reg_t;
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typedef uint32_t hri_icm_imr_reg_t;
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typedef uint32_t hri_icm_isr_reg_t;
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typedef uint32_t hri_icm_sr_reg_t;
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typedef uint32_t hri_icm_uasr_reg_t;
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typedef uint32_t hri_icm_uihval_reg_t;
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typedef uint32_t hri_icmdescriptor_raddr_reg_t;
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typedef uint32_t hri_icmdescriptor_rcfg_reg_t;
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typedef uint32_t hri_icmdescriptor_rctrl_reg_t;
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typedef uint32_t hri_icmdescriptor_rnext_reg_t;
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static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RADDR.reg |= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw,
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hri_icmdescriptor_raddr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((IcmDescriptor *)hw)->RADDR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RADDR.reg = data;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RADDR.reg &= ~mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RADDR.reg ^= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw)
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{
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return ((IcmDescriptor *)hw)->RADDR.reg;
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}
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static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCFG.reg |= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw,
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hri_icmdescriptor_rcfg_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((IcmDescriptor *)hw)->RCFG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCFG.reg = data;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCFG.reg &= ~mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCFG.reg ^= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw)
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{
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return ((IcmDescriptor *)hw)->RCFG.reg;
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}
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static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCTRL.reg |= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw,
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hri_icmdescriptor_rctrl_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((IcmDescriptor *)hw)->RCTRL.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCTRL.reg = data;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCTRL.reg &= ~mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RCTRL.reg ^= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw)
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{
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return ((IcmDescriptor *)hw)->RCTRL.reg;
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}
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static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RNEXT.reg |= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw,
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hri_icmdescriptor_rnext_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((IcmDescriptor *)hw)->RNEXT.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RNEXT.reg = data;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RNEXT.reg &= ~mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
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{
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ICM_CRITICAL_SECTION_ENTER();
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((IcmDescriptor *)hw)->RNEXT.reg ^= mask;
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ICM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw)
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{
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return ((IcmDescriptor *)hw)->RNEXT.reg;
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}
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static inline void hri_icm_set_IMR_URAD_bit(const void *const hw)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_URAD;
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}
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static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw)
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{
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return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos;
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}
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static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
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} else {
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((Icm *)hw)->IER.reg = ICM_IMR_URAD;
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}
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}
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static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw)
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{
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((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
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}
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static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask);
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}
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static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos;
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return tmp;
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}
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static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos;
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return tmp;
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}
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static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RHC(data);
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((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data);
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}
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static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask);
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}
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static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask);
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}
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static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos;
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return tmp;
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}
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static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos;
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return tmp;
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}
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static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RDM(data);
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((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data);
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}
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static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask);
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}
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static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask);
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}
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static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos;
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return tmp;
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}
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static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos;
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return tmp;
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}
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static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RBE(data);
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((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data);
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}
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static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask);
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}
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static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask);
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}
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static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos;
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return tmp;
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}
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static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos;
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return tmp;
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}
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static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RWC(data);
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((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data);
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}
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static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask);
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}
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static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_REC(mask);
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}
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static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos;
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return tmp;
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}
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static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Icm *)hw)->IMR.reg;
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tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos;
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return tmp;
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}
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static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_REC(data);
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((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data);
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}
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static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask);
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}
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static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
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{
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((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask);
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}
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static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->IMR.reg;
|
|
tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->IMR.reg;
|
|
tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data)
|
|
{
|
|
((Icm *)hw)->IER.reg = ICM_IMR_RSU(data);
|
|
((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data);
|
|
}
|
|
|
|
static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
|
|
{
|
|
((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask);
|
|
}
|
|
|
|
static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
|
|
{
|
|
((Icm *)hw)->IER.reg = mask;
|
|
}
|
|
|
|
static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->IMR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw)
|
|
{
|
|
return ((Icm *)hw)->IMR.reg;
|
|
}
|
|
|
|
static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data)
|
|
{
|
|
((Icm *)hw)->IER.reg = data;
|
|
((Icm *)hw)->IDR.reg = ~data;
|
|
}
|
|
|
|
static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
|
|
{
|
|
((Icm *)hw)->IDR.reg = mask;
|
|
}
|
|
|
|
static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos;
|
|
}
|
|
|
|
static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos;
|
|
}
|
|
|
|
static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos;
|
|
}
|
|
|
|
static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos;
|
|
}
|
|
|
|
static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos;
|
|
}
|
|
|
|
static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->SR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw)
|
|
{
|
|
return ((Icm *)hw)->SR.reg;
|
|
}
|
|
|
|
static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->ISR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw)
|
|
{
|
|
return ((Icm *)hw)->ISR.reg;
|
|
}
|
|
|
|
static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask)
|
|
{
|
|
return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos;
|
|
}
|
|
|
|
static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw)
|
|
{
|
|
return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos;
|
|
}
|
|
|
|
static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->UASR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw)
|
|
{
|
|
return ((Icm *)hw)->UASR.reg;
|
|
}
|
|
|
|
static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->CFG.reg |= mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->CFG.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->CFG.reg = data;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->CFG.reg &= ~mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->CFG.reg ^= mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw)
|
|
{
|
|
return ((Icm *)hw)->CFG.reg;
|
|
}
|
|
|
|
static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->DSCR.reg |= mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->DSCR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->DSCR.reg = data;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->DSCR.reg &= ~mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->DSCR.reg ^= mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw)
|
|
{
|
|
return ((Icm *)hw)->DSCR.reg;
|
|
}
|
|
|
|
static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->HASH.reg |= mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Icm *)hw)->HASH.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->HASH.reg = data;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->HASH.reg &= ~mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->HASH.reg ^= mask;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw)
|
|
{
|
|
return ((Icm *)hw)->HASH.reg;
|
|
}
|
|
|
|
static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->CTRL.reg = data;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data)
|
|
{
|
|
ICM_CRITICAL_SECTION_ENTER();
|
|
((Icm *)hw)->UIHVAL[index].reg = data;
|
|
ICM_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _HRI_ICM_E54_H_INCLUDED */
|
|
#endif /* _SAME54_ICM_COMPONENT_ */
|