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98 lines
5.9 KiB
C
98 lines
5.9 KiB
C
/**
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* \file
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*
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* \brief Instance description for TC6
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_TC6_INSTANCE_
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#define _SAMD21_TC6_INSTANCE_
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/* ========== Register definition for TC6 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TC6_CTRLA (0x42003800) /**< \brief (TC6) Control A */
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#define REG_TC6_READREQ (0x42003802) /**< \brief (TC6) Read Request */
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#define REG_TC6_CTRLBCLR (0x42003804) /**< \brief (TC6) Control B Clear */
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#define REG_TC6_CTRLBSET (0x42003805) /**< \brief (TC6) Control B Set */
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#define REG_TC6_CTRLC (0x42003806) /**< \brief (TC6) Control C */
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#define REG_TC6_DBGCTRL (0x42003808) /**< \brief (TC6) Debug Control */
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#define REG_TC6_EVCTRL (0x4200380A) /**< \brief (TC6) Event Control */
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#define REG_TC6_INTENCLR (0x4200380C) /**< \brief (TC6) Interrupt Enable Clear */
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#define REG_TC6_INTENSET (0x4200380D) /**< \brief (TC6) Interrupt Enable Set */
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#define REG_TC6_INTFLAG (0x4200380E) /**< \brief (TC6) Interrupt Flag Status and Clear */
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#define REG_TC6_STATUS (0x4200380F) /**< \brief (TC6) Status */
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#define REG_TC6_COUNT16_COUNT (0x42003810) /**< \brief (TC6) COUNT16 Counter Value */
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#define REG_TC6_COUNT16_CC0 (0x42003818) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
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#define REG_TC6_COUNT16_CC1 (0x4200381A) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
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#define REG_TC6_COUNT32_COUNT (0x42003810) /**< \brief (TC6) COUNT32 Counter Value */
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#define REG_TC6_COUNT32_CC0 (0x42003818) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
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#define REG_TC6_COUNT32_CC1 (0x4200381C) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
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#define REG_TC6_COUNT8_COUNT (0x42003810) /**< \brief (TC6) COUNT8 Counter Value */
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#define REG_TC6_COUNT8_PER (0x42003814) /**< \brief (TC6) COUNT8 Period Value */
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#define REG_TC6_COUNT8_CC0 (0x42003818) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
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#define REG_TC6_COUNT8_CC1 (0x42003819) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
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#else
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#define REG_TC6_CTRLA (*(RwReg16*)0x42003800UL) /**< \brief (TC6) Control A */
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#define REG_TC6_READREQ (*(RwReg16*)0x42003802UL) /**< \brief (TC6) Read Request */
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#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC6) Control B Clear */
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#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC6) Control B Set */
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#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806UL) /**< \brief (TC6) Control C */
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#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808UL) /**< \brief (TC6) Debug Control */
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#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AUL) /**< \brief (TC6) Event Control */
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#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CUL) /**< \brief (TC6) Interrupt Enable Clear */
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#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DUL) /**< \brief (TC6) Interrupt Enable Set */
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#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EUL) /**< \brief (TC6) Interrupt Flag Status and Clear */
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#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FUL) /**< \brief (TC6) Status */
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#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810UL) /**< \brief (TC6) COUNT16 Counter Value */
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#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818UL) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
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#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AUL) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
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#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810UL) /**< \brief (TC6) COUNT32 Counter Value */
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#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818UL) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
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#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CUL) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
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#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810UL) /**< \brief (TC6) COUNT8 Counter Value */
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#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814UL) /**< \brief (TC6) COUNT8 Period Value */
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#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818UL) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
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#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819UL) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TC6 peripheral ========== */
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#define TC6_CC8_NUM 2 // Number of 8-bit Counters
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#define TC6_CC16_NUM 2 // Number of 16-bit Counters
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#define TC6_CC32_NUM 2 // Number of 32-bit Counters
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#define TC6_DITHERING_EXT 0 // Dithering feature implemented
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#define TC6_DMAC_ID_MC_0 34
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#define TC6_DMAC_ID_MC_1 35
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#define TC6_DMAC_ID_MC_LSB 34
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#define TC6_DMAC_ID_MC_MSB 35
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#define TC6_DMAC_ID_MC_SIZE 2
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#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
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#define TC6_GCLK_ID 29 // Index of Generic Clock
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#define TC6_MASTER 1
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#define TC6_OW_NUM 2 // Number of Output Waveforms
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#define TC6_PERIOD_EXT 0 // Period feature implemented
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#define TC6_SHADOW_EXT 0 // Shadow feature implemented
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#endif /* _SAMD21_TC6_INSTANCE_ */
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